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Merge pull request #233 from bcostm/master 

[NUCLEO_F302R8] Fix issue with SystemCoreClock variable update.
pull/234/head
Bogdan Marinescu 2014-03-25 13:33:05 +00:00
parent cb306a57ce 575f9f9269
commit 8b4f07882b
3 changed files with 15 additions and 11 deletions
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3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct
View File

@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
} }
; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188) ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data ; + 4 more bytes reserved for the SystemCoreClock variable
RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }

3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f302x8.sct
View File

@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
} }
; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188) ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data ; + 4 more bytes reserved for the SystemCoreClock variable
RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }

18
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c
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@ -141,7 +141,10 @@
* @{ * @{
*/ */
uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */ // [TODO] Do the same for other compilers
// Warning: the RAM is initialized AFTER the SetSysClock function is called.
// This variable must be placed outside the initialized section (see scatter file).
uint32_t SystemCoreClock __attribute__((at(0x20000188))) = 64000000; /* Default with HSI. Will be updated if HSE is used */
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@ -208,16 +211,16 @@ void SystemInit(void)
/* Disable all interrupts */ /* Disable all interrupts */
RCC->CIR = 0x00000000; RCC->CIR = 0x00000000;
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif #endif
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
} }
/** /**
@ -331,9 +334,6 @@ void SetSysClock(void)
} }
} }
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Output SYSCLK on MCO pin(PA8) for debugging purpose */ /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
/* /*
// Enable GPIOA clock // Enable GPIOA clock
@ -412,6 +412,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{ {
} }
SystemCoreClock = 72000000;
return 1; // OK return 1; // OK
} }
else else
@ -459,6 +460,7 @@ uint8_t SetSysClock_PLL_HSI(void)
{ {
} }
SystemCoreClock = 64000000;
return 1; // OK return 1; // OK
} }