mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #233 from bcostm/master
[NUCLEO_F302R8] Fix issue with SystemCoreClock variable update.pull/234/head
commit
8b4f07882b
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@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
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}
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; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
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RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
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; + 4 more bytes reserved for the SystemCoreClock variable
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RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
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.ANY (+RW +ZI)
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}
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@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
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}
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; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
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RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
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; + 4 more bytes reserved for the SystemCoreClock variable
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RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
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.ANY (+RW +ZI)
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}
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@ -141,7 +141,10 @@
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* @{
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*/
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uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
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// [TODO] Do the same for other compilers
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// Warning: the RAM is initialized AFTER the SetSysClock function is called.
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// This variable must be placed outside the initialized section (see scatter file).
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uint32_t SystemCoreClock __attribute__((at(0x20000188))) = 64000000; /* Default with HSI. Will be updated if HSE is used */
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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@ -208,16 +211,16 @@ void SystemInit(void)
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings */
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SetSysClock();
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings */
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SetSysClock();
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}
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/**
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@ -330,9 +333,6 @@ void SetSysClock(void)
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}
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}
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}
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/* Update SystemCoreClock variable */
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SystemCoreClockUpdate();
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/* Output SYSCLK on MCO pin(PA8) for debugging purpose */
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/*
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@ -411,7 +411,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
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{
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}
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SystemCoreClock = 72000000;
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return 1; // OK
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}
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else
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@ -459,6 +460,7 @@ uint8_t SetSysClock_PLL_HSI(void)
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{
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}
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SystemCoreClock = 64000000;
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return 1; // OK
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}
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