diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/PeripheralNames.h b/libraries/mbed/vendor/Freescale/KL05Z/hal/PeripheralNames.h index 2918835c8c..be8f0f506e 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/PeripheralNames.h +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/PeripheralNames.h @@ -33,10 +33,10 @@ typedef enum { typedef enum { ADC0_SE2 = 2, ADC0_SE3 = 3, - ADC0_SE10 = 4, - ADC0_SE11 = 5, - ADC0_SE12 = 6, - ADC0_SE13 = 7 + ADC0_SE10 = 10, + ADC0_SE11 = 11, + ADC0_SE12 = 12, + ADC0_SE13 = 13 } ADCName; typedef enum { diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/PinNames.h b/libraries/mbed/vendor/Freescale/KL05Z/hal/PinNames.h index 3729d331d1..bd5d018a36 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/PinNames.h +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/PinNames.h @@ -27,6 +27,7 @@ typedef enum { PIN_OUTPUT } PinDirection; +/* PCR - 0x1000 */ #define PORT_SHIFT 12 typedef enum { diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/analogout_api.c b/libraries/mbed/vendor/Freescale/KL05Z/hal/analogout_api.c index f5148f48b6..d6b713d999 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/analogout_api.c +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/analogout_api.c @@ -23,7 +23,7 @@ static const PinMap PinMap_DAC[] = { {PTB1, DAC_0, 0}, - {NC , NC , 0} + {NC , NC , 0} }; void analogout_init(dac_t *obj, PinName pin) { @@ -50,7 +50,9 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) {} +void analogout_free(dac_t *obj) { + +} static inline void dac_write(dac_t *obj, int value) { DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF); diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_api.c b/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_api.c index 523151fd87..cb771d7c89 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_api.c +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_api.c @@ -18,16 +18,16 @@ uint32_t gpio_set(PinName pin) { pin_function(pin, 1); - return 1 << ((pin & 0x7F) >> 2); + return 1 << ((pin & 0x7F) >> 2); // 1 << pin number } void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) { - if(pin == NC) return; + if (pin == NC) return; obj->pin = pin; obj->mask = gpio_set(pin); - unsigned int port = (unsigned int)pin >> PORT_SHIFT; + uint32_t port = (uint32_t)pin >> PORT_SHIFT; FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40); obj->reg_set = ®->PSOR; @@ -37,8 +37,12 @@ void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) { gpio_dir(obj, direction); switch (direction) { - case PIN_OUTPUT: pin_mode(pin, PullNone); break; - case PIN_INPUT : pin_mode(pin, PullDown); break; + case PIN_OUTPUT: + pin_mode(pin, PullNone); + break; + case PIN_INPUT : + pin_mode(pin, PullDown); + break; } } @@ -48,7 +52,11 @@ void gpio_mode(gpio_t *obj, PinMode mode) { void gpio_dir(gpio_t *obj, PinDirection direction) { switch (direction) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + case PIN_INPUT : + *obj->reg_dir &= ~obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir |= obj->mask; + break; } } diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_irq_api.c b/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_irq_api.c index aa05651bd2..15e62fd42f 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_irq_api.c +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/gpio_irq_api.c @@ -19,4 +19,137 @@ #include "gpio_irq_api.h" #include "error.h" +#define CHANNEL_NUM 64 // 31 pins on 2 ports +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +#define IRQ_DISABLED (0) +#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) +#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) +#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) + +static void handle_interrupt_in(PORT_Type *port, int ch_base) { + uint32_t mask = 0, i; + + for (i = 0; i < 32; i++) { + uint32_t pmask = (1 << i); + if (port->ISFR & pmask) { + mask |= pmask; + uint32_t id = channel_ids[ch_base + i]; + if (id == 0) continue; + + FGPIO_Type *gpio; + gpio_irq_event event = IRQ_NONE; + switch (port->PCR[i] & PORT_PCR_IRQC_MASK) { + case IRQ_RAISING_EDGE: + event = IRQ_RISE; + break; + + case IRQ_FALLING_EDGE: + event = IRQ_FALL; + break; + + case IRQ_EITHER_EDGE: + gpio = (port == PORTA) ? (FPTA) : (FPTD); + event = (gpio->PDIR & pmask) ? (IRQ_RISE) : (IRQ_FALL); + break; + } + if (event != IRQ_NONE) + irq_handler(id, event); + } + } + port->ISFR = mask; +} + +/* IRQ only on PORTA and PORTD */ +void gpio_irqA(void) { + handle_interrupt_in(PORTA, 0); +} + +void gpio_irqD(void) { + handle_interrupt_in(PORTD, 32); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) return -1; + + irq_handler = handler; + + obj->port = pin >> PORT_SHIFT; + obj->pin = (pin & 0x7F) >> 2; + + uint32_t ch_base, vector; + IRQn_Type irq_n; + switch (obj->port) { + case PortA: + ch_base = 0; + irq_n = PORTA_IRQn; + vector = (uint32_t)gpio_irqA; + break; + + case PortD: + ch_base = 32; + irq_n = PORTD_IRQn; + vector = (uint32_t)gpio_irqD; + break; + + default: + error("gpio_irq only supported on Port A and D\n"); + break; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + obj->ch = ch_base + obj->pin; + channel_ids[obj->ch] = id; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); + + uint32_t irq_settings = IRQ_DISABLED; + + switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { + case IRQ_DISABLED: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); + } + break; + + case IRQ_RAISING_EDGE: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_FALL) + irq_settings = IRQ_RAISING_EDGE; + } + break; + + case IRQ_FALLING_EDGE: + if (enable) { + irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_RISE) + irq_settings = IRQ_FALLING_EDGE; + } + break; + + case IRQ_EITHER_EDGE: + if (enable) { + irq_settings = IRQ_EITHER_EDGE; + } else { + irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); + } + break; + } + + // Interrupt configuration and clear interrupt + port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; +} diff --git a/libraries/mbed/vendor/Freescale/KL05Z/hal/pinmap.c b/libraries/mbed/vendor/Freescale/KL05Z/hal/pinmap.c index 7b68e497c0..b00b849610 100644 --- a/libraries/mbed/vendor/Freescale/KL05Z/hal/pinmap.c +++ b/libraries/mbed/vendor/Freescale/KL05Z/hal/pinmap.c @@ -23,7 +23,7 @@ void pin_function(PinName pin, int function) { uint32_t pin_n = (uint32_t)(pin & 0x7C) >> 2; SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n); - __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + 0x1000 * port_n)))->PCR[pin_n]; + __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + (1 << PORT_SHIFT) * port_n)))->PCR[pin_n]; // pin mux bits: [10:8] -> 11100000000 = (0x700) *pin_pcr = (*pin_pcr & ~0x700) | (function << 8); diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index fcaab274cb..870a93cd27 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -3,84 +3,96 @@ class Target: def __init__(self): # ARM Core self.core = None - + # The silicon vendor of this chip self.vendor = None - + # How much time (in seconds) it takes to the interface chip to flash a # new image and reset the target chip self.program_cycle_s = 1.5 - + # list of toolchains that are supported by the mbed SDK for this target self.supported_toolchains = None - + self.name = self.__class__.__name__ class LPC2368(Target): def __init__(self): Target.__init__(self) - + self.core = "ARM7TDMI-S" self.vendor = "NXP" - + self.supported_toolchains = ["ARM"] class LPC1768(Target): def __init__(self): Target.__init__(self) - + self.core = "Cortex-M3" self.vendor = "NXP" - + self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"] class LPC11U24(Target): def __init__(self): Target.__init__(self) - + self.core = "Cortex-M0" self.vendor = "NXP" - + self.supported_toolchains = ["ARM", "uARM"] +class KL05Z(Target): + def __init__(self): + Target.__init__(self) + + self.core = "Cortex-M0+" + self.vendor = "Freescale" + + self.supported_toolchains = ["ARM"] + + self.program_cycle_s = 4 + + class KL25Z(Target): def __init__(self): Target.__init__(self) - + self.core = "Cortex-M0+" self.vendor = "Freescale" - + self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB"] - + self.program_cycle_s = 4 class LPC812(Target): def __init__(self): Target.__init__(self) - + self.core = "Cortex-M0+" self.vendor = "NXP" - + self.supported_toolchains = ["uARM"] - + self.program_cycle_s = 4 class LPC4088(Target): def __init__(self): Target.__init__(self) - + self.core = "Cortex-M4" self.vendor = "NXP" - + self.supported_toolchains = ["ARM", "GCC_CR"] - + class MBED_MCU(Target): def __init__(self): Target.__init__(self) @@ -95,6 +107,7 @@ TARGETS = [ LPC2368(), LPC1768(), LPC11U24(), + KL05Z(), KL25Z(), LPC812(), LPC4088(),