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TARGET_NXP: Remove support for LPC11U6X 

Mbed OS no longer supports any LPC11U6X targets.
This commit removes all source files for those targets.
pull/13918/head
Hugues Kamba 2020-11-18 11:39:56 +00:00
parent f2278567d0
commit 8972cde3ab
30 changed files with 0 additions and 5759 deletions
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74
targets/TARGET_NXP/TARGET_LPC11U6X/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART0_BASE,
UART_1 = (int)LPC_USART1_BASE,
UART_2 = (int)LPC_USART2_BASE,
UART_3 = (int)LPC_USART3_BASE,
UART_4 = (int)LPC_USART4_BASE,
} UARTName;
typedef enum {
ADC_0 = 0,
ADC_1,
ADC_2,
ADC_3,
ADC_4,
ADC_5,
ADC_6,
ADC_7,
ADC_8,
ADC_9,
ADC_10,
ADC_11,
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
I2C_0 = (int)LPC_I2C0_BASE,
I2C_1 = (int)LPC_I2C1_BASE
} I2CName;
typedef enum {
SCT0_0 = 0,
SCT0_1,
SCT0_2,
SCT0_3,
SCT1_0,
SCT1_1,
SCT1_2,
SCT1_3,
} PWMName;
#ifdef __cplusplus
}
#endif
#endif

182
targets/TARGET_NXP/TARGET_LPC11U6X/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 16
#define PIN_SHIFT 9
typedef enum {
// LPC11U68 Pin Names (PORT[19:16] + PIN[15:9] + IOCON offset[8:0])
P0_0 = (0 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x000,
P0_1 = (0 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x004,
P0_2 = (0 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x008,
P0_3 = (0 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x00C,
P0_4 = (0 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x010,
P0_5 = (0 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x014,
P0_6 = (0 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x018,
P0_7 = (0 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x01C,
P0_8 = (0 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x020,
P0_9 = (0 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x024,
P0_10= (0 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x028,
P0_11= (0 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x02C,
P0_12= (0 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x030,
P0_13= (0 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x034,
P0_14= (0 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x038,
P0_15= (0 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x03C,
P0_16= (0 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x040,
P0_17= (0 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x044,
P0_18= (0 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x048,
P0_19= (0 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x04C,
P0_20= (0 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x050,
P0_21= (0 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x054,
P0_22= (0 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x058,
P0_23= (0 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x05C,
P1_0 = (1 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x060,
P1_1 = (1 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x064,
P1_2 = (1 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x068,
P1_3 = (1 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x06C,
P1_4 = (1 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x070,
P1_5 = (1 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x074,
P1_6 = (1 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x078,
P1_7 = (1 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x07C,
P1_8 = (1 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x080,
P1_9 = (1 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x084,
P1_10= (1 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x088,
P1_11= (1 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x08C,
P1_12= (1 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x090,
P1_13= (1 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x094,
P1_14= (1 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x098,
P1_15= (1 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x09C,
P1_16= (1 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x0A0,
P1_17= (1 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x0A4,
P1_18= (1 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x0A8,
P1_19= (1 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x0AC,
P1_20= (1 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x0B0,
P1_21= (1 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x0B4,
P1_22= (1 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x0B8,
P1_23= (1 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x0BC,
P1_24= (1 << PORT_SHIFT) | (24<< PIN_SHIFT) | 0x0C0,
P1_25= (1 << PORT_SHIFT) | (25<< PIN_SHIFT) | 0x0C4,
P1_26= (1 << PORT_SHIFT) | (26<< PIN_SHIFT) | 0x0C8,
P1_27= (1 << PORT_SHIFT) | (27<< PIN_SHIFT) | 0x0CC,
P1_28= (1 << PORT_SHIFT) | (28<< PIN_SHIFT) | 0x0D0,
P1_29= (1 << PORT_SHIFT) | (29<< PIN_SHIFT) | 0x0D4,
P1_30= (1 << PORT_SHIFT) | (30<< PIN_SHIFT) | 0x0D8,
P1_31= (1 << PORT_SHIFT) | (31<< PIN_SHIFT) | 0x0DC,
P2_0 = (2 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x0F0,
P2_1 = (2 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x0F4,
P2_2 = (2 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x0FC,
P2_3 = (2 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x100,
P2_4 = (2 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x104,
P2_5 = (2 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x108,
P2_6 = (2 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x10C,
P2_7 = (2 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x110,
P2_8 = (2 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x114,
P2_9 = (2 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x118,
P2_10= (2 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x11C,
P2_11= (2 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x120,
P2_12= (2 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x124,
P2_13= (2 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x128,
P2_14= (2 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x12C,
P2_15= (2 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x130,
P2_16= (2 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x134,
P2_17= (2 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x138,
P2_18= (2 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x13C,
P2_19= (2 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x140,
P2_20= (2 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x144,
P2_21= (2 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x148,
P2_22= (2 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x14C,
P2_23= (2 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x150,
LED_RED = P2_17,
LED_GREEN = P2_16,
LED_BLUE = P2_18,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// Serial to USB pins
USBTX = P0_19,
USBRX = P0_18,
// Arduino Shield Receptacles Names
D0 = P0_18,
D1 = P0_19,
D2 = P1_18,
D3 = P1_24,
D4 = P1_19,
D5 = P1_26,
D6 = P1_27,
D7 = P1_25,
D8 = P1_28,
D9 = P2_3,
D10= P0_2,
D11= P0_9,
D12= P0_8,
D13= P1_29,
D14= P0_5,
D15= P0_4,
A0 = P1_9,
A1 = P0_14,
A2 = P0_13,
A3 = P0_12,
A4 = P0_5, // same port as SDA
A5 = P0_4, // same port as SCL
SDA= P0_5, // same port as A4
SCL= P0_4, // same port as A5
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

33
targets/TARGET_NXP/TARGET_LPC11U6X/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2
} PortName;
#ifdef __cplusplus
}
#endif
#endif

142
targets/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#if DEVICE_ANALOGIN
#define ANALOGIN_MEDIAN_FILTER 1
#define ADC_10BIT_RANGE 0x3FF
#define ADC_12BIT_RANGE 0xFFF
#define PDRUN_VALID_BITS 0x000025FFL
#define PDRUN_RESERVED_ONE 0x0000C800L
#define ADC_RANGE ADC_12BIT_RANGE
static const PinMap PinMap_ADC[] = {
{P1_9 , ADC_0, 3},
{P0_23, ADC_1, 1},
{P0_16, ADC_2, 1},
{P0_15, ADC_3, 3},
{P1_22, ADC_4, 3},
{P1_3 , ADC_5, 4},
{P0_14, ADC_6, 2},
{P0_13, ADC_7, 2},
{P0_12, ADC_8, 2},
{P0_11, ADC_9, 2},
{P1_29, ADC_10,4},
{P0_22, ADC_11,1},
{NC , NC ,0}
};
void analogin_init(analogin_t *obj, PinName pin) {
volatile uint32_t tmp;
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
pinmap_pinout(pin, PinMap_ADC);
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
// set pin to ADC mode
*reg &= ~(1 << 7); // set ADMODE = 0 (analog mode)
// ADC Powered
tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
tmp &= ~((1 << 4) & PDRUN_VALID_BITS);
LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
// Enable clock for ADC
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13);
// Determine the clock divider for a 500kHz ADC clock during calibration
uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
// Perform a self-calibration
LPC_ADC->CTRL = (1UL << 30) | (clkdiv & 0xFF);
while ((LPC_ADC->CTRL & (1UL << 30)) != 0);
// Sampling clock: SystemClock divided by 1
LPC_ADC->CTRL = 0;
}
static inline uint32_t adc_read(analogin_t *obj) {
// select channel
LPC_ADC->SEQA_CTRL &= ~(0xFFF);
LPC_ADC->SEQA_CTRL |= (1UL << obj->adc);
// start conversion, sequence enable with async mode
LPC_ADC->SEQA_CTRL |= ((1UL << 26) | (1UL << 31) | (1UL << 19));
// Repeatedly get the sample data until DONE bit
volatile uint32_t data;
do {
data = LPC_ADC->SEQA_GDAT;
} while ((data & (1UL << 31)) == 0);
data = LPC_ADC->DAT[obj->adc];
// Stop conversion
LPC_ADC->SEQA_CTRL &= ~(1UL << 31);
return ((data >> 4) & ADC_RANGE);
}
static inline void order(uint32_t *a, uint32_t *b) {
if (*a > *b) {
uint32_t t = *a;
*a = *b;
*b = t;
}
}
static inline uint32_t adc_read_u32(analogin_t *obj) {
uint32_t value;
#if ANALOGIN_MEDIAN_FILTER
uint32_t v1 = adc_read(obj);
uint32_t v2 = adc_read(obj);
uint32_t v3 = adc_read(obj);
order(&v1, &v2);
order(&v2, &v3);
order(&v1, &v2);
value = v2;
#else
value = adc_read(obj);
#endif
return value;
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (float)value * (1.0f / (float)ADC_RANGE);
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}
#endif

39
targets/TARGET_NXP/TARGET_LPC11U6X/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

1247
targets/TARGET_NXP/TARGET_LPC11U6X/device/LPC11U6x.h
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52
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct
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#! armcc -E
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; 256k flash
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32kB
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x10000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00008000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
#define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
}
}

216
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.S
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;/**************************************************************************//**
; * @file startup_LPC11U6x.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * NXP LPC11U6x Device Series
; * @version V1.00
; * @date 22. October 2013
; *
; * @note
; * Copyright (C) 2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
DCD USART0_IRQHandler ; 16+21 USART0 interrupt
DCD USB_IRQHandler ; 16+22 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD RTC_IRQHandler ; 16+25 RTC interrupt
DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
DCD DMA_IRQHandler ; 16+28 DMA interrupt
DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
DCD 0 ; 16+31 Reserved
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT USART1_4_IRQHandler [WEAK]
EXPORT USART2_3_IRQHandler [WEAK]
EXPORT SCT0_1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT CT16B0_IRQHandler [WEAK]
EXPORT CT16B1_IRQHandler [WEAK]
EXPORT CT32B0_IRQHandler [WEAK]
EXPORT CT32B1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT ADC_A_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BOD_WDT_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT ADC_B_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
I2C1_IRQHandler
USART1_4_IRQHandler
USART2_3_IRQHandler
SCT0_1_IRQHandler
SSP1_IRQHandler
I2C0_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART0_IRQHandler
USB_IRQHandler
USB_FIQ_IRQHandler
ADC_A_IRQHandler
RTC_IRQHandler
BOD_WDT_IRQHandler
FLASH_IRQHandler
DMA_IRQHandler
ADC_B_IRQHandler
USBWAKEUP_IRQHandler
B .
ENDP
ALIGN
END

26
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct
View File

@ -1,26 +0,0 @@
#! armcc -E
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
; 32kB (0x8000) - 0x100 = 0x7F00
RW_IRAM1 (0x10000000+0x100) (0x8000-0x100-Stack_Size) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x10000000+0x8000) EMPTY -Stack_Size { ; stack
}
}

217
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.S
View File

@ -1,217 +0,0 @@
;/**************************************************************************//**
; * @file startup_LPC11U6x.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * NXP LPC11U6x Device Series
; * @version V1.00
; * @date 22. October 2013
; *
; * @note
; * Copyright (C) 2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
DCD USART0_IRQHandler ; 16+21 USART0 interrupt
DCD USB_IRQHandler ; 16+22 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD RTC_IRQHandler ; 16+25 RTC interrupt
DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
DCD DMA_IRQHandler ; 16+28 DMA interrupt
DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
DCD 0 ; 16+31 Reserved
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT USART1_4_IRQHandler [WEAK]
EXPORT USART2_3_IRQHandler [WEAK]
EXPORT SCT0_1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT CT16B0_IRQHandler [WEAK]
EXPORT CT16B1_IRQHandler [WEAK]
EXPORT CT32B0_IRQHandler [WEAK]
EXPORT CT32B1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT ADC_A_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BOD_WDT_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT ADC_B_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
I2C1_IRQHandler
USART1_4_IRQHandler
USART2_3_IRQHandler
SCT0_1_IRQHandler
SSP1_IRQHandler
I2C0_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART0_IRQHandler
USB_IRQHandler
USB_FIQ_IRQHandler
ADC_A_IRQHandler
RTC_IRQHandler
BOD_WDT_IRQHandler
FLASH_IRQHandler
DMA_IRQHandler
ADC_B_IRQHandler
USBWAKEUP_IRQHandler
B .
ENDP
ALIGN
END

267
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld
View File

@ -1,267 +0,0 @@
/*Based on following file*/
/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2014
* Generated linker script file for LPC11U68
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
*/
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE;
MEMORY
{
/* Define each memory region */
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash256 = 0x0 + 0x40000;
__top_Ram0_32 = 0x10000000 + 0x8000;
__top_Ram1_2 = 0x20000000 + 0x800;
__top_Ram2USB_2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
_etext = .;
/* possible MTB section for Ram1_2 */
.mtb_buffer_RAM2 (NOLOAD) :
{
KEEP(*(.mtb.$RAM2*))
KEEP(*(.mtb.$RAM1_2*))
} > Ram1_2
/* DATA section for Ram1_2 */
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_2)
*(.data.$RAM2*)
*(.data.$Ram1_2*)
. = ALIGN(8) ;
} > Ram1_2 AT>MFlash256
/* possible MTB section for Ram2USB_2 */
.mtb_buffer_RAM3 (NOLOAD) :
{
KEEP(*(.mtb.$RAM3*))
KEEP(*(.mtb.$RAM2USB_2*))
} > Ram2USB_2
/* DATA section for Ram2USB_2 */
.data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2USB_2)
*(.data.$RAM3*)
*(.data.$Ram2USB_2*)
. = ALIGN(8) ;
} > Ram2USB_2 AT>MFlash256
/* MAIN DATA SECTION */
/* Default MTB section */
.mtb_buffer_default (NOLOAD) :
{
KEEP(*(.mtb*))
} > Ram0_32
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > Ram0_32
/* Main DATA section (Ram0_32) */
.data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(8) ;
_edata = . ;
} > Ram0_32 AT>MFlash256
/* BSS section for Ram1_2 */
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_2*)
. = ALIGN(8) ;
} > Ram1_2
/* BSS section for Ram2USB_2 */
.bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$Ram2USB_2*)
. = ALIGN(8) ;
} > Ram2USB_2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_32
/* NOINIT section for Ram1_2 */
.noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
. = ALIGN(8) ;
} > Ram1_2
/* NOINIT section for Ram2USB_2 */
.noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
. = ALIGN(8) ;
} > Ram2USB_2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
. = ALIGN(8) ;
_end_noinit = .;
} > Ram0_32
PROVIDE(_pvHeapStart = .);
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(Ram0_32) + LENGTH(Ram0_32) - STACK_SIZE;
__HeapLimit = .;
} > Ram0_32
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > Ram0_32
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(Ram0_32) + LENGTH(Ram0_32);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
PROVIDE(__stack = __StackTop);
PROVIDE(_vStackTop = __StackTop);
}

171
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp
View File

@ -1,171 +0,0 @@
extern "C" {
#include "LPC11U6x.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM0
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC11U68
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
I2C1_IRQHandler, // 10 - I2C1
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
I2C0_IRQHandler, // 15 - I2C0
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
USART0_IRQHandler, // 21 - USART0
USB_IRQHandler, // 22 - USB IRQ
USB_FIQHandler, // 23 - USB FIQ
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
RTC_IRQHandler, // 25 - Real Time CLock interrpt
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
DMA_IRQHandler, // 28 - DMA interrupt
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
0, // 31 - Reserved
};
/* End Vector */
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
/* Reset entry point*/
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (software_init_hook)
software_init_hook();
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
}

50
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf
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@ -1,50 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x100000FF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000100;
define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;
define symbol __CRP_end__ = 0x000002FF;
define symbol __RAM1_start__ = 0x20000000;
define symbol __RAM1_end__ = 0x200007FF;
define symbol __RAM_USB_start__= 0x20004000;
define symbol __RAM_USB_end__ = 0x200047FF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
define region RAM_USB_region = mem:[from __RAM_USB_start__ to __RAM_USB_end__];
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block HEAP, block CSTACK };
place in CRP_region { section .crp };
place in RAM1_region { section .sram1 };
place in RAM_USB_region { section .sram_usb };

251
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.S
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@ -1,251 +0,0 @@
;/*****************************************************************************
; * @file: startup_LPC11u6x.s
; * @purpose: CMSIS Cortex-M0PLUS Core Device Startup File
; * for the NXP LPC11u6x Device Series (manually edited)
; * @version: V1.00
; * @date: 19. October 2009
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
DCD PIN_INT0_IRQHandler ; Pin interrupt 0
DCD PIN_INT1_IRQHandler ; Pin interrupt 1
DCD PIN_INT2_IRQHandler ; Pin interrupt 2
DCD PIN_INT3_IRQHandler ; Pin interrupt 3
DCD PIN_INT4_IRQHandler ; Pin interrupt 4
DCD PIN_INT5_IRQHandler ; Pin interrupt 5
DCD PIN_INT6_IRQHandler ; Pin interrupt 6
DCD PIN_INT7_IRQHandler ; Pin interrupt 7
DCD GINT0_IRQHandler ; Port interrupt group 0
DCD GINT1_IRQHandler ; Port interrupt group 1
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD USART1_4_IRQHandler ; USARTS 1 and 4 shared interrupt
DCD USART2_3_IRQHandler ; USARTS 2 and 3 shared interrupt
DCD SCT0_1_IRQHandler ; SCT 0 and 1 shared interrupt
DCD SSP1_IRQHandler ; SSP1 interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD CT16B0_IRQHandler ; CT16B0 (16-bit Timer 0)
DCD CT16B1_IRQHandler ; CT16B1 (16-bit Timer 1)
DCD CT32B0_IRQHandler ; CT32B0 (32-bit Timer 0)
DCD CT32B1_IRQHandler ; CT32B0 (32-bit Timer 1)
DCD SSP0_IRQHandler ; SSP0 interrupt interrupt
DCD USART0_IRQHandler ; USART 0 interrupt interrupt
DCD USB_IRQHandler ; USB IRQ interrupt
DCD USB_FIQ_IRQHandler ; USB FIQ interrupt
DCD ADC_A_IRQHandler ; ADC A sequence (A/D Converter) interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD BOD_WDT_IRQHandler ; Shared BOD (Brownout Detect) and WDT interrupts
DCD FLASH_IRQHandler ; Flash Memory Controller interrupt
DCD DMA_IRQHandler ; DMA Controller interrupt
DCD ADC_B_IRQHandler ; ADC B sequence interrupt
DCD USBWakeup_IRQHandler ; USB wake-up interrupt
DCD Reserved_IRQHandler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK Reserved_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
Reserved_IRQHandler
B .
PUBWEAK PIN_INT0_IRQHandler
PUBWEAK PIN_INT1_IRQHandler
PUBWEAK PIN_INT2_IRQHandler
PUBWEAK PIN_INT3_IRQHandler
PUBWEAK PIN_INT4_IRQHandler
PUBWEAK PIN_INT5_IRQHandler
PUBWEAK PIN_INT6_IRQHandler
PUBWEAK PIN_INT7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK USART1_4_IRQHandler
PUBWEAK USART2_3_IRQHandler
PUBWEAK SCT0_1_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK CT16B0_IRQHandler
PUBWEAK CT16B1_IRQHandler
PUBWEAK CT32B0_IRQHandler
PUBWEAK CT32B1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK USART0_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK USB_FIQ_IRQHandler
PUBWEAK ADC_A_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK BOD_WDT_IRQHandler
PUBWEAK FLASH_IRQHandler
PUBWEAK DMA_IRQHandler
PUBWEAK ADC_B_IRQHandler
PUBWEAK USBWakeup_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
THUMB
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
I2C1_IRQHandler
USART1_4_IRQHandler
USART2_3_IRQHandler
SCT0_1_IRQHandler
SSP1_IRQHandler
I2C0_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART0_IRQHandler
USB_IRQHandler
USB_FIQ_IRQHandler
ADC_A_IRQHandler
RTC_IRQHandler
BOD_WDT_IRQHandler
FLASH_IRQHandler
DMA_IRQHandler
ADC_B_IRQHandler
USBWakeup_IRQHandler
Default_Handler
B Default_Handler
SECTION .crp:CODE:ROOT(2)
DATA
/* Code Read Protection
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- Copy RAM to flash command can not write to Sector 0.
- Erase command can erase Sector 0 only when all sectors
are selected for erase.
- Compare command is disabled.
- Read Memory command is disabled.
CRP2 0x87654321 - Read Memory is disabled.
- Write to RAM is disabled.
- "Go" command is disabled.
- Copy RAM to flash is disabled.
- Compare is disabled.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
DCD 0xFFFFFFFF
END

26
targets/TARGET_NXP/TARGET_LPC11U6X/device/cmsis.h
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@ -1,26 +0,0 @@
/*
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* A generic CMSIS include header, pulling in LPC8xx specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC11U6x.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_NXP/TARGET_LPC11U6X/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM
#endif

574
targets/TARGET_NXP/TARGET_LPC11U6X/device/system_LPC11U6x.c
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@ -1,574 +0,0 @@
/**************************************************************************//**
* @file system_LPC11U6x.c
* @brief CMSIS Cortex-M3 Device System Source File for
* NXP LPC11U6x Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC11U6x.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*- SystemCoreClock Configuration -------------------------------------------*/
// <e0> SystemCoreClock Configuration
#define CLOCK_SETUP 1
//
// <h> System Oscillator Control (SYSOSCCTRL)
// <o.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o.1> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
//
// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
// <0=> IRC Oscillator
// <1=> Crystal Oscillator (SYSOSC)
// <3=> RTC Oscillator (32 kHz)
#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <e> Clock Configuration (Manual)
#define CLOCK_SETUP_REG 1
//
// <h> WD Oscillator Setting (WDTOSCCTRL)
// <o.0..4> DIVSEL: Select Divider for Fclkana
// <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
// <0-31>
// <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
// <1=> 0.5 MHz
// <2=> 0.8 MHz
// <3=> 1.1 MHz
// <4=> 1.4 MHz
// <5=> 1.6 MHz
// <6=> 1.8 MHz
// <7=> 2.0 MHz
// <8=> 2.2 MHz
// <9=> 2.4 MHz
// <10=> 2.6 MHz
// <11=> 2.7 MHz
// <12=> 2.9 MHz
// <13=> 3.1 MHz
// <14=> 3.2 MHz
// <15=> 3.4 MHz
// </h>
#define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
//
// <h> System PLL Setting (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.5..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> Main Clock Source Select (MAINCLKSEL)
// <0=> IRC Oscillator
// <1=> PLL Input
// <2=> WD Oscillator
// <3=> PLL Output
#define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
//
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
// </e>
//
// <e> Clock Configuration (via ROM PLL API)
#define CLOCK_SETUP_API 0
//
// <o> PLL API Mode Select
// <0=> Exact
// <1=> Less than or equal
// <2=> Greater than or equal
// <3=> As close as possible
#define PLL_API_MODE_Val 0
//
// <o> CPU Frequency [Hz] <1000000-50000000:1000>
#define PLL_API_FREQ_Val 48000000
// </e>
//
// <e> USB Clock Configuration
#define USB_CLOCK_SETUP 1
// <h> USB PLL Control (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.5..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
// <0=> IRC Oscillator
// <1=> System Oscillator
#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
// <0=> USB PLL out
// <1=> Main clock
#define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
//
// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
// </e>
//
// </e>
//
// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
//
#define XTAL_CLK_Val 12000000
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
#error "WDTOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
#if (CLOCK_SETUP_API == 1)
#error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
#endif
#if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
#error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
#endif
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
#error "MAINCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
#error "You must select either manual or API based Clock Configuration!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
#error "XTAL frequency is out of bounds"
#endif
#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
#error "PLL API Mode Select not valid"
#endif
#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
#error "CPU Frequency (API mode) not valid"
#endif
/*----------------------------------------------------------------------------
Calculate system core clock
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP) /* Clock Setup */
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
#define __SYS_PLLCLKIN (__RTC_OSC_CLK)
#else
#error "Oops"
#endif
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
#if (__FREQSEL == 0)
#error "WDTOSCCTRL.FREQSEL undefined!"
#elif (__FREQSEL == 1)
#define __OSC_CLK ( 500000 / __DIVSEL)
#elif (__FREQSEL == 2)
#define __OSC_CLK ( 800000 / __DIVSEL)
#elif (__FREQSEL == 3)
#define __OSC_CLK (1100000 / __DIVSEL)
#elif (__FREQSEL == 4)
#define __OSC_CLK (1400000 / __DIVSEL)
#elif (__FREQSEL == 5)
#define __OSC_CLK (1600000 / __DIVSEL)
#elif (__FREQSEL == 6)
#define __OSC_CLK (1800000 / __DIVSEL)
#elif (__FREQSEL == 7)
#define __OSC_CLK (2000000 / __DIVSEL)
#elif (__FREQSEL == 8)
#define __OSC_CLK (2200000 / __DIVSEL)
#elif (__FREQSEL == 9)
#define __OSC_CLK (2400000 / __DIVSEL)
#elif (__FREQSEL == 10)
#define __OSC_CLK (2600000 / __DIVSEL)
#elif (__FREQSEL == 11)
#define __OSC_CLK (2700000 / __DIVSEL)
#elif (__FREQSEL == 12)
#define __OSC_CLK (2900000 / __DIVSEL)
#elif (__FREQSEL == 13)
#define __OSC_CLK (3100000 / __DIVSEL)
#elif (__FREQSEL == 14)
#define __OSC_CLK (3200000 / __DIVSEL)
#else
#define __OSC_CLK (3400000 / __DIVSEL)
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSEL_Val & 0x03) == 0)
#define __MAIN_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSEL_Val & 0x03) == 1)
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSEL_Val & 0x03) == 2)
#define __MAIN_CLOCK (__OSC_CLK)
#elif ((MAINCLKSEL_Val & 0x03) == 3)
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
#else
#error "Oops"
#endif
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
#define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
#endif /* Clock Setup via PLL API */
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif /* CLOCK_SETUP */
#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
#include "power_api.h"
typedef struct _ROM {
const unsigned p_dev0;
const unsigned p_dev1;
const unsigned p_dev2;
const PWRD * pPWRD; /* ROM Power Management API */
const unsigned p_dev4;
const unsigned p_dev5;
const unsigned p_dev6;
const unsigned p_dev7;
} ROM;
/*----------------------------------------------------------------------------
PLL API Function
*----------------------------------------------------------------------------*/
static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
{
uint32_t cmd[5], res[5];
ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
cmd[0] = pllInFreq; /* PLL's input freq in KHz */
cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
cmd[2] = pllMode;
cmd[3] = 0; /* no timeout for PLL to lock */
/* Execute API call */
(*rom)->pPWRD->set_pll(cmd, res); /* call API function */
if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
while(1); /* ... stay here */
}
}
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t oscClk = 0;
/* Determine clock frequency according to clock register values */
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
case 0: oscClk = 0; break;
case 1: oscClk = 500000; break;
case 2: oscClk = 800000; break;
case 3: oscClk = 1100000; break;
case 4: oscClk = 1400000; break;
case 5: oscClk = 1600000; break;
case 6: oscClk = 1800000; break;
case 7: oscClk = 2000000; break;
case 8: oscClk = 2200000; break;
case 9: oscClk = 2400000; break;
case 10: oscClk = 2600000; break;
case 11: oscClk = 2700000; break;
case 12: oscClk = 2900000; break;
case 13: oscClk = 3100000; break;
case 14: oscClk = 3200000; break;
case 15: oscClk = 3400000; break;
}
oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* WDT Oscillator */
SystemCoreClock = oscClk;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
#define PDRUN_VALID_BITS 0x000025FFL
#define PDRUN_RESERVED_ONE 0x0000C800L
static void power_down_config(uint32_t val)
{
volatile uint32_t tmp;
tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
tmp |= (val & PDRUN_VALID_BITS);
LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
}
static void power_up_config(uint32_t val)
{
volatile uint32_t tmp;
tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
tmp &= ~(val & PDRUN_VALID_BITS);
LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*/
void SystemInit (void) {
#if (CLOCK_SETUP)
volatile uint32_t i;
#endif
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
// Initialize XTALIN/XTALOUT pins
LPC_IOCON->PIO2_0 = 0x01;
LPC_IOCON->PIO2_1 = 0x01;
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
power_up_config(1<<5); /* Power-up sysosc */
for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if (((MAINCLKSEL_Val & 0x03) == 2) )
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
power_down_config(1<<7); /* Power-down SYSPLL */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
power_up_config(1<<7); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->MAINCLKUEN = 0x01;
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
// LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
// LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
// LPC_SYSCON->SYSPLLCLKUEN = 0x01;
// while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->MAINCLKUEN = 0x01;
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
LPC_SYSCON->SYSAHBCLKDIV = 1;
setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
#endif /* Clock Setup via PLL API */
#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->USBPLLCLKUEN = 0x01;
while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
#endif
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
#endif
#endif /* Clock Setup */
}

64
targets/TARGET_NXP/TARGET_LPC11U6X/device/system_LPC11U6x.h
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@ -1,64 +0,0 @@
/**************************************************************************//**
* @file system_LPC11U6x.h
* @brief CMSIS Cortex-M3 Device System Header File for
* NXP LPC11U6x Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC11U6x_H
#define __SYSTEM_LPC11U6x_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC11U6x_H */

77
targets/TARGET_NXP/TARGET_LPC11U6X/gpio_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
static int gpio_enabled = 0;
static void gpio_enable(void) {
gpio_enabled = 1;
/* Enable AHB clock to the GPIO and IOCON domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 16) | (1 << 6));
}
uint32_t gpio_set(PinName pin) {
MBED_ASSERT(pin != (PinName)NC);
if (!gpio_enabled)
gpio_enable();
int func = ((pin == P0_0) || // reset
(pin == P0_10) || // SWCLK
(pin == P0_11) || // TDI
(pin == P0_12) || // TMS
(pin == P0_13) || // TDO
(pin == P0_14) || // TRST
(pin == P0_15)) ? (1) : (0); // SWDIO
pin_function(pin, func);
return (1UL << ((int)pin >> PIN_SHIFT & 0x1F));
}
void gpio_init(gpio_t *obj, PinName pin) {
obj->pin = pin;
if (pin == (PinName)NC)
return;
obj->mask = gpio_set(pin);
unsigned int port = (unsigned int)(pin >> PORT_SHIFT);
obj->reg_set = &LPC_GPIO_PORT->SET[port];
obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
obj->reg_in = &LPC_GPIO_PORT->PIN[port];
obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
MBED_ASSERT(obj->pin != (PinName)NC);
switch (direction) {
case PIN_INPUT :
*obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
}

163
targets/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c
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@ -1,163 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#if DEVICE_INTERRUPTIN
#define CHANNEL_NUM 8
#define LPC_GPIO_X LPC_PINT
#define PININT_IRQ PIN_INT0_IRQn
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
(channel_ids[channel] == 0 ) ||
(LPC_GPIO_X->ISEL & ch_bit ) ) return;
if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
LPC_GPIO_X->RISE = ch_bit;
}
if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
LPC_GPIO_X->FALL = ch_bit;
}
LPC_GPIO_X->IST = ch_bit;
}
void gpio_irq0(void) {handle_interrupt_in(0);}
void gpio_irq1(void) {handle_interrupt_in(1);}
void gpio_irq2(void) {handle_interrupt_in(2);}
void gpio_irq3(void) {handle_interrupt_in(3);}
void gpio_irq4(void) {handle_interrupt_in(4);}
void gpio_irq5(void) {handle_interrupt_in(5);}
void gpio_irq6(void) {handle_interrupt_in(6);}
void gpio_irq7(void) {handle_interrupt_in(7);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
// PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO2_7 interrupt
if (pin >= P2_8) return -1;
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* Enable AHB clock to the PIN, GPIO and IOCON domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
/* Gets offset value for each port */
uint32_t offset;
switch ((pin >> PORT_SHIFT) & 0x3) {
case 0: offset = 0; // PIO0[23:0]
break;
case 1: offset = 24; // PIO1[31:0]
break;
case 2: offset = 56; // PIO2[7:0]
break;
}
/* Set the INTPIN number : offset + pin_number */
LPC_SYSCON->PINTSEL[obj->ch] = (offset + ((pin >> PIN_SHIFT) & 0x1F));
// Interrupt Wake-Up Enable
LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3] &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F));
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio_irq0;
break;
case 1: channels_irq = &gpio_irq1;
break;
case 2: channels_irq = &gpio_irq2;
break;
case 3: channels_irq = &gpio_irq3;
break;
case 4: channels_irq = &gpio_irq4;
break;
case 5: channels_irq = &gpio_irq5;
break;
case 6: channels_irq = &gpio_irq6;
break;
case 7: channels_irq = &gpio_irq7;
break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (!(LPC_GPIO_X->ISEL & ch_bit))
LPC_GPIO_X->IST = ch_bit;
// Edge trigger
LPC_GPIO_X->ISEL &= ~ch_bit;
if (event == IRQ_RISE) {
if (enable) {
LPC_GPIO_X->IENR |= ch_bit;
} else {
LPC_GPIO_X->IENR &= ~ch_bit;
}
} else {
if (enable) {
LPC_GPIO_X->IENF |= ch_bit;
} else {
LPC_GPIO_X->IENF &= ~ch_bit;
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
#endif

57
targets/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

421
targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c
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@ -1,421 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#if DEVICE_I2C
static const PinMap PinMap_I2C_SDA[] = {
{P0_5 , I2C_0, 1},
{P1_3 , I2C_1, 3},
{P1_14, I2C_1, 1},
{P1_24, I2C_1, 2},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{P0_4 , I2C_0, 1},
{P0_7 , I2C_1, 3},
{P1_11, I2C_1, 1},
{P1_30, I2C_1, 1},
{NC , NC, 0}
};
#define I2C_CONSET(x) (x->i2c->CONSET)
#define I2C_CONCLR(x) (x->i2c->CONCLR)
#define I2C_STAT(x) (x->i2c->STAT)
#define I2C_DAT(x) (x->i2c->DAT)
#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
static const uint32_t I2C_addr_offset[2][4] = {
{0x0C, 0x20, 0x24, 0x28}, // slave address offset
{0x30, 0x34, 0x38, 0x3C} // slave address mask offset
};
static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
I2C_CONCLR(obj) = (start << 5)
| (stop << 4)
| (interrupt << 3)
| (acknowledge << 2);
}
static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
I2C_CONSET(obj) = (start << 5)
| (stop << 4)
| (interrupt << 3)
| (acknowledge << 2);
}
// Clear the Serial Interrupt (SI)
static inline void i2c_clear_SI(i2c_t *obj) {
i2c_conclr(obj, 0, 0, 1, 0);
}
static inline int i2c_status(i2c_t *obj) {
return I2C_STAT(obj);
}
// Wait until the Serial Interrupt (SI) is set
static int i2c_wait_SI(i2c_t *obj) {
volatile int timeout = 0;
while (!(I2C_CONSET(obj) & (1 << 3))) {
timeout++;
if (timeout > 100000) return -1;
}
return 0;
}
static inline void i2c_interface_enable(i2c_t *obj) {
I2C_CONSET(obj) = 0x40;
}
static inline void i2c_power_enable(i2c_t *obj) {
LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 5) | (1 << 25));
LPC_SYSCON->PRESETCTRL |= ((1 << 1) | (1 << 3));
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// determine the SPI to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (LPC_I2C0_Type *)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)obj->i2c != NC);
// enable power
i2c_power_enable(obj);
// set default frequency at 100k
i2c_frequency(obj, 100000);
i2c_conclr(obj, 1, 1, 1, 1);
i2c_interface_enable(obj);
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
}
inline int i2c_start(i2c_t *obj) {
int status = 0;
int isInterrupted = I2C_CONSET(obj) & (1 << 3);
// 8.1 Before master mode can be entered, I2CON must be initialised to:
// - I2EN STA STO SI AA - -
// - 1 0 0 x x - -
// if AA = 0, it can't enter slave mode
i2c_conclr(obj, 1, 1, 0, 1);
// The master mode may now be entered by setting the STA bit
// this will generate a start condition when the bus becomes free
i2c_conset(obj, 1, 0, 0, 1);
// Clearing SI bit when it wasn't set on entry can jump past state
// 0x10 or 0x08 and erroneously send uninitialized slave address.
if (isInterrupted)
i2c_clear_SI(obj);
i2c_wait_SI(obj);
status = i2c_status(obj);
// Clear start bit now that it's transmitted
i2c_conclr(obj, 1, 0, 0, 0);
return status;
}
inline int i2c_stop(i2c_t *obj) {
int timeout = 0;
// write the stop bit
i2c_conset(obj, 0, 1, 0, 0);
i2c_clear_SI(obj);
// wait for STO bit to reset
while(I2C_CONSET(obj) & (1 << 4)) {
timeout ++;
if (timeout > 100000) return 1;
}
return 0;
}
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
I2C_DAT(obj) = value;
// clear SI to init a send
i2c_clear_SI(obj);
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
static inline int i2c_do_read(i2c_t *obj, int last) {
// we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
if (last) {
i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
} else {
i2c_conset(obj, 0, 0, 0, 1); // send a ACK
}
// accept byte
i2c_clear_SI(obj);
// wait for it to arrive
i2c_wait_SI(obj);
// return the data
return (I2C_DAT(obj) & 0xFF);
}
void i2c_frequency(i2c_t *obj, int hz) {
// No peripheral clock divider on the M0
uint32_t PCLK = SystemCoreClock;
uint32_t pulse = PCLK / (hz * 2);
// I2C Rate
I2C_SCLL(obj, pulse);
I2C_SCLH(obj, pulse);
}
// The I2C does a read or a write as a whole operation
// There are two types of error conditions it can encounter
// 1) it can not obtain the bus
// 2) it gets error responses at part of the transmission
//
// We tackle them as follows:
// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
// which basically turns it in to a 2)
// 2) on error, we use the standard error mechanisms to report/debug
//
// Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
status = i2c_start(obj);
if ((status != 0x10) && (status != 0x08)) {
i2c_stop(obj);
return I2C_ERROR_BUS_BUSY;
}
status = i2c_do_write(obj, (address | 0x01), 1);
if (status != 0x40) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
int value = i2c_do_read(obj, 0);
status = i2c_status(obj);
if (status != 0x50) {
i2c_stop(obj);
return count;
}
data[count] = (char) value;
}
// read in last byte
int value = i2c_do_read(obj, 1);
status = i2c_status(obj);
if (status != 0x58) {
i2c_stop(obj);
return length - 1;
}
data[count] = (char) value;
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i, status;
status = i2c_start(obj);
if ((status != 0x10) && (status != 0x08)) {
i2c_stop(obj);
return I2C_ERROR_BUS_BUSY;
}
status = i2c_do_write(obj, (address & 0xFE), 1);
if (status != 0x18) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
for (i=0; i<length; i++) {
status = i2c_do_write(obj, data[i], 0);
if(status != 0x28) {
i2c_stop(obj);
return i;
}
}
// clearing the serial interrupt here might cause an unintended rewrite of the last byte
// see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
// i2c_clear_SI(obj);
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
}
return length;
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
return (i2c_do_read(obj, last) & 0xFF);
}
int i2c_byte_write(i2c_t *obj, int data) {
int ack;
int status = i2c_do_write(obj, (data & 0xFF), 0);
switch(status) {
case 0x18: case 0x28: // Master transmit ACKs
ack = 1;
break;
case 0x40: // Master receive address transmitted ACK
ack = 1;
break;
case 0xB8: // Slave transmit ACK
ack = 1;
break;
default:
ack = 0;
break;
}
return ack;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
if (enable_slave != 0) {
i2c_conclr(obj, 1, 1, 1, 0);
i2c_conset(obj, 0, 0, 0, 1);
} else {
i2c_conclr(obj, 1, 1, 1, 1);
}
}
int i2c_slave_receive(i2c_t *obj) {
int status;
int retval;
status = i2c_status(obj);
switch(status) {
case 0x60: retval = 3; break;
case 0x70: retval = 2; break;
case 0xA8: retval = 1; break;
default : retval = 0; break;
}
return(retval);
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
int status;
do {
i2c_clear_SI(obj);
i2c_wait_SI(obj);
status = i2c_status(obj);
if((status == 0x80) || (status == 0x90)) {
data[count] = I2C_DAT(obj) & 0xFF;
}
count++;
} while (((status == 0x80) || (status == 0x90) ||
(status == 0x060) || (status == 0x70)) && (count < length));
if(status != 0xA0) {
i2c_stop(obj);
}
i2c_clear_SI(obj);
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int count = 0;
int status;
if(length <= 0) {
return(0);
}
do {
status = i2c_do_write(obj, data[count], 0);
count++;
} while ((count < length) && (status == 0xB8));
if((status != 0xC0) && (status != 0xC8)) {
i2c_stop(obj);
}
i2c_clear_SI(obj);
return(count);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
uint32_t addr;
if ((idx >= 0) && (idx <= 3)) {
addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
*((uint32_t *) addr) = address & 0xFF;
}
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}
#endif

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targets/TARGET_NXP/TARGET_LPC11U6X/objects.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#if DEVICE_INTERRUPTIN
struct gpio_irq_s {
uint32_t ch;
};
#endif
#if DEVICE_PWMOUT
struct pwmout_s {
LPC_SCT0_Type* pwm;
uint32_t pwm_ch;
};
#endif
#if DEVICE_SERIAL
struct serial_s {
LPC_USART0_Type *uart;
LPC_USART4_Type *mini_uart;
unsigned char index;
};
#endif
#if DEVICE_ANALOGIN
struct analogin_s {
ADCName adc;
};
#endif
#if DEVICE_ANALOGOUT
struct dac_s {
DACName dac;
};
#endif
#if DEVICE_I2C
struct i2c_s {
LPC_I2C0_Type *i2c;
};
#endif
#if DEVICE_SPI
struct spi_s {
LPC_SSP0_Type *spi;
unsigned char spi_n;
};
#endif
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

46
targets/TARGET_NXP/TARGET_LPC11U6X/pinmap.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function) {
MBED_ASSERT(pin != (PinName)NC);
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
// pin function bits: [2:0] -> 111 = (0x7)
*reg = (*reg & ~0x7) | (function & 0x7);
}
void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
if ((pin == P0_4) || (pin == P0_5)) {
// The true open-drain pins PIO0_4 and PIO0_5 can be configured for different I2C-bus speeds.
return;
}
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
if (mode == OpenDrain) {
*reg |= (1 << 10);
} else {
uint32_t tmp = *reg;
tmp &= ~(0x3 << 3);
tmp |= (mode & 0x3) << 3;
*reg = tmp;
}
}

250
targets/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#if DEVICE_PWMOUT
#define SCT_CHANNELS 2
static const PinMap PinMap_PWM[] = {
{P1_19, SCT0_0, 2},
{P2_2, SCT0_1, 3},
{P2_7, SCT0_2, 2},
{P1_13, SCT0_3, 2},
{P2_16, SCT1_0, 1},
{P2_17, SCT1_1, 1},
{P2_18, SCT1_2, 1},
{P2_19, SCT1_3, 1},
{NC, NC, 0}
};
static LPC_SCT0_Type *SCTs[SCT_CHANNELS] = {
(LPC_SCT0_Type *)LPC_SCT0,
(LPC_SCT0_Type *)LPC_SCT1,
};
// bit flags for used SCTs
static unsigned char sct_used = 0;
static int get_available_sct(void)
{
int i;
for (i = 0; i < SCT_CHANNELS; i++) {
if ((sct_used & (1 << i)) == 0) {
return i;
}
}
return -1;
}
void pwmout_init(pwmout_t *obj, PinName pin)
{
// determine the SPI to use
PWMName pwm_mapped = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
if (pwm_mapped == (PWMName)NC) {
error("PwmOut pin mapping failed");
}
int sct_n = get_available_sct();
if (sct_n == -1) {
error("No available SCT");
}
sct_used |= (1 << sct_n);
obj->pwm = SCTs[sct_n];
obj->pwm_ch = sct_n;
// Enable the SCT clock
LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 31);
// Clear peripheral reset the SCT:
LPC_SYSCON->PRESETCTRL |= (1 << (obj->pwm_ch + 9));
pinmap_pinout(pin, PinMap_PWM);
LPC_SCT0_Type *pwm = obj->pwm;
// Unified 32-bit counter, autolimit
pwm->CONFIG |= ((0x3 << 17) | 0x01);
// halt and clear the counter
pwm->CTRL |= (1 << 2) | (1 << 3);
switch (pwm_mapped) {
case SCT0_0:
case SCT1_0:
pwm->OUT0_SET = (1 << 0); // event 0
pwm->OUT0_CLR = (1 << 1); // event 1
break;
case SCT0_1:
case SCT1_1:
pwm->OUT1_SET = (1 << 0); // event 0
pwm->OUT1_CLR = (1 << 1); // event 1
break;
case SCT0_2:
case SCT1_2:
pwm->OUT2_SET = (1 << 0); // event 0
pwm->OUT2_CLR = (1 << 1); // event 1
break;
case SCT0_3:
case SCT1_3:
pwm->OUT3_SET = (1 << 0); // event 0
pwm->OUT3_CLR = (1 << 1); // event 1
break;
default:
break;
}
// Event 0 : MATCH and MATCHSEL=0
pwm->EV0_CTRL = (1 << 12);
pwm->EV0_STATE = 0xFFFFFFFF;
// Event 1 : MATCH and MATCHSEL=1
pwm->EV1_CTRL = (1 << 12) | (1 << 0);
pwm->EV1_STATE = 0xFFFFFFFF;
// default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write(obj, 0);
}
void pwmout_free(pwmout_t *obj)
{
sct_used &= ~(1 << obj->pwm_ch);
if (sct_used == 0) {
// Disable the SCT clock
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1UL << 31);
}
}
void pwmout_write(pwmout_t *obj, float value)
{
LPC_SCT0_Type *pwm = obj->pwm;
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
if (t_on > 0) {
pwm->MATCHREL1 = t_on - 1;
// Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
}
}
float pwmout_read(pwmout_t *obj)
{
LPC_SCT0_Type *pwm = obj->pwm;
uint32_t t_off = pwm->MATCHREL0 + 1;
uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
float v = (float)t_on / (float)t_off;
return (v > 1.0f) ? (1.0f) : (v);
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
LPC_SCT0_Type *pwm = obj->pwm;
uint32_t t_off = pwm->MATCHREL0 + 1;
uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
float v = (float)t_on / (float)t_off;
uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
uint32_t pulsewidth_ticks = period_ticks * v;
pwm->MATCHREL0 = period_ticks - 1;
if (pulsewidth_ticks > 0) {
pwm->MATCHREL1 = pulsewidth_ticks - 1;
// Un-halt the timer and ensure the new period & pulse-width take immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH0 = pwm->MATCHREL0;
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
// Ensure the new period will take immediate effect when the timer is un-halted
pwm->MATCH0 = pwm->MATCHREL0;
}
}
int pwmout_read_period_us(pwmout_t *obj)
{
return pwm->MATCHREL0 + 1;
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
LPC_SCT0_Type *pwm = obj->pwm;
if (us > 0) {
pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
// Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
}
}
int pwmout_read_pulsewidth_us(pwmout_t *obj)
{
return (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM;
}
#endif

65
targets/TARGET_NXP/TARGET_LPC11U6X/rtc_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#if DEVICE_RTC
void rtc_init(void)
{
// Enables clock for RTC
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 30);
// Software reset
LPC_RTC->CTRL |= 1;
LPC_RTC->COUNT = 0;
// Enabled RTC
LPC_RTC->CTRL |= (1 << 7);
// clear reset
LPC_RTC->CTRL &= ~1;
}
void rtc_free(void)
{
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 30);
LPC_RTC->CTRL &= ~(1 << 7);
}
int rtc_isenabled(void)
{
return (((LPC_RTC->CTRL) & 0x80) != 0);
}
time_t rtc_read(void)
{
return (time_t)LPC_RTC->COUNT;
}
void rtc_write(time_t t)
{
// Disabled RTC
LPC_RTC->CTRL &= ~(1 << 7);
// Set count
LPC_RTC->COUNT = t;
//Enabled RTC
LPC_RTC->CTRL |= (1 << 7);
}
#endif

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targets/TARGET_NXP/TARGET_LPC11U6X/serial_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include "mbed_assert.h"
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#if DEVICE_SERIAL
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 5
// CFG
#define UART_EN (0x01<<0)
// CTL
#define TXBRKEN (0x01<<1)
// STAT
#define RXRDY (0x01<<0)
#define TXRDY (0x01<<2)
#define DELTACTS (0x01<<5)
#define RXBRK (0x01<<10)
#define DELTARXBRK (0x01<<11)
static const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_18, UART_0, 2},
{P1_27, UART_0, 2},
{P1_8 , UART_1, 2},
{P0_14, UART_1, 4},
{P1_0 , UART_2, 3},
{P1_23, UART_2, 3},
{P2_4 , UART_3, 1},
{P2_12, UART_4, 1},
{ NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_17, UART_0, 2},
{P1_26, UART_0, 2},
{P1_2 , UART_1, 3},
{P0_13, UART_1, 4},
{P0_20, UART_2, 2},
{P1_6 , UART_2, 2},
{P2_3 , UART_3, 1},
{P2_11, UART_4, 1},
{NC , NC , 0}
};
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
switch (uart) {
case UART_0:
obj->index = 0;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
break;
case UART_1:
obj->index = 1;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 20);
LPC_SYSCON->PRESETCTRL |= (1 << 5);
break;
case UART_2:
obj->index = 2;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 21);
LPC_SYSCON->PRESETCTRL |= (1 << 6);
break;
case UART_3:
obj->index = 3;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 22);
LPC_SYSCON->PRESETCTRL |= (1 << 7);
break;
case UART_4:
obj->index = 4;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 22);
LPC_SYSCON->PRESETCTRL |= (1 << 8);
break;
}
if (obj->index == 0)
obj->uart = (LPC_USART0_Type *)uart;
else
obj->mini_uart = (LPC_USART4_Type *)uart;
if (obj->index == 0) {
// enable fifos and default rx trigger level
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
| 0 << 1 // Rx Fifo Clear
| 0 << 2 // Tx Fifo Clear
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
// disable irqs
obj->uart->IER = 0 << 0 // Rx Data available irq enable
| 0 << 1 // Tx Fifo empty irq enable
| 0 << 2; // Rx Line Status irq enable
}
else {
// Clear all status bits
obj->mini_uart->STAT = (DELTACTS | DELTARXBRK);
// Enable UART
obj->mini_uart->CFG |= UART_EN;
}
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart && (obj->index == 0)) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
serial_irq_ids[obj->index] = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
LPC_SYSCON->USART0CLKDIV = 1;
LPC_SYSCON->FRGCLKDIV = 1;
if (obj->index == 0) {
uint32_t PCLK = SystemCoreClock;
// First we check to see if the basic divide with no DivAddVal/MulVal
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
// MulVal = 1. Otherwise, we search the valid ratio value range to find
// the closest match. This could be more elegant, using search methods
// and/or lookup tables, but the brute force method is not that much
// slower, and is more maintainable.
uint16_t DL = PCLK / (16 * baudrate);
uint8_t DivAddVal = 0;
uint8_t MulVal = 1;
int hit = 0;
uint16_t dlv;
uint8_t mv, dav;
if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
int err_best = baudrate, b;
for (mv = 1; mv < 16 && !hit; mv++)
{
for (dav = 0; dav < mv; dav++)
{
// baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
// solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
// mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
// for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
// note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
else // 2 bits headroom, use more precision
dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
// datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
if (dlv == 0)
dlv = 1;
// datasheet says if dav > 0 then DL must be >= 2
if ((dav > 0) && (dlv < 2))
dlv = 2;
// integer rearrangement of the baudrate equation (with rounding)
b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
// check to see how we went
b = abs(b - baudrate);
if (b < err_best)
{
err_best = b;
DL = dlv;
MulVal = mv;
DivAddVal = dav;
if (b == baudrate)
{
hit = 1;
break;
}
}
}
}
}
// set LCR[DLAB] to enable writing to divider registers
obj->uart->LCR |= (1 << 7);
// set divider values
obj->uart->DLM = (DL >> 8) & 0xFF;
obj->uart->DLL = (DL >> 0) & 0xFF;
obj->uart->FDR = (uint32_t) DivAddVal << 0
| (uint32_t) MulVal << 4;
// clear LCR[DLAB]
obj->uart->LCR &= ~(1 << 7);
}
else {
uint32_t UARTSysClk = SystemCoreClock / LPC_SYSCON->FRGCLKDIV;
obj->mini_uart->BRG = UARTSysClk / 16 / baudrate - 1;
LPC_SYSCON->UARTFRGDIV = 0xFF;
LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
(baudrate * (obj->mini_uart->BRG + 1))
) - (LPC_SYSCON->UARTFRGDIV + 1);
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
stop_bits -= 1;
if (obj->index == 0) {
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
data_bits -= 5;
int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
case ParityEven: parity_enable = 1; parity_select = 1; break;
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
break;
}
obj->uart->LCR = data_bits << 0
| stop_bits << 2
| parity_enable << 3
| parity_select << 4;
}
else {
// 0: 7 data bits ... 2: 9 data bits
MBED_ASSERT((data_bits > 6) && (data_bits < 10));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
data_bits -= 7;
int paritysel;
switch (parity) {
case ParityNone: paritysel = 0; break;
case ParityEven: paritysel = 2; break;
case ParityOdd : paritysel = 3; break;
default:
return;
}
obj->mini_uart->CFG = (data_bits << 2)
| (paritysel << 4)
| (stop_bits << 6)
| UART_EN;
}
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t iir, uint32_t index) {
SerialIrq irq_type;
switch (iir) {
case 1: irq_type = TxIrq; break;
case 2: irq_type = RxIrq; break;
default: return;
}
if (serial_irq_ids[index] != 0)
irq_handler(serial_irq_ids[index], irq_type);
}
void uart0_irq()
{
uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0);
}
void uart1_irq()
{
if(LPC_USART1->STAT & (1 << 2)){
uart_irq(1, 1);
}
if(LPC_USART1->STAT & (1 << 0)){
uart_irq(2, 1);
}
}
void uart2_irq()
{
if(LPC_USART2->STAT & (1 << 2)){
uart_irq(1, 2);
}
if(LPC_USART2->STAT & (1 << 0)){
uart_irq(2, 2);
}
}
void uart3_irq()
{
if(LPC_USART3->STAT & (1 << 2)){
uart_irq(1, 3);
}
if(LPC_USART3->STAT & (1 << 0)){
uart_irq(2, 3);
}
}
void uart4_irq()
{
if(LPC_USART4->STAT & (1 << 2)){
uart_irq(1, 4);
}
if(LPC_USART4->STAT & (1 << 0)){
uart_irq(2, 4);
}
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
if(obj->index == 0){
irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq;
}
else{
switch ((int)obj->mini_uart) {
case UART_0: irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
case UART_1: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart1_irq; break;
case UART_2: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart2_irq; break;
case UART_3: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart3_irq; break;
case UART_4: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart4_irq; break;
}
}
if (enable) {
if (obj->index == 0) {
obj->uart->IER |= (1 << irq);
}
else {
obj->mini_uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (RxIrq) : (TxIrq);
if (obj->index == 0) {
obj->uart->IER &= ~(1 << irq);
all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
}
else {
obj->mini_uart->INTENCLR = (1 << ((irq == RxIrq) ? 0 : 2));
all_disabled = (obj->mini_uart->INTENSET) == 0;
}
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
if (obj->index == 0) {
return obj->uart->RBR;
}
else {
return obj->mini_uart->RXDAT;
}
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
if (obj->index == 0) {
obj->uart->THR = c;
}
else {
obj->mini_uart->TXDAT = c;
}
}
int serial_readable(serial_t *obj) {
if (obj->index == 0) {
return obj->uart->LSR & 0x01;
}
else {
return obj->mini_uart->STAT & RXRDY;
}
}
int serial_writable(serial_t *obj) {
if (obj->index == 0) {
return obj->uart->LSR & 0x20;
}
else {
return obj->mini_uart->STAT & TXRDY;
}
}
void serial_clear(serial_t *obj) {
if (obj->index == 0) {
obj->uart->FCR = 1 << 1 // rx FIFO reset
| 1 << 2 // tx FIFO reset
| 0 << 6; // interrupt depth
}
else {
obj->mini_uart->STAT = 0;
}
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
if (obj->index == 0) {
obj->uart->LCR |= (1 << 6);
}
else {
obj->mini_uart->CTL |= TXBRKEN;
}
}
void serial_break_clear(serial_t *obj) {
if (obj->index == 0) {
obj->uart->LCR &= ~(1 << 6);
}
else {
obj->mini_uart->CTL &= ~TXBRKEN;
}
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}
#endif

70
targets/TARGET_NXP/TARGET_LPC11U6X/sleep.c
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@ -1,70 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#if DEVICE_SLEEP
void hal_sleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected
mbed_interface_disconnect();
#endif
// PCON[PM] (bits 2:0) set to 0
LPC_PMU->PCON &= ~0x03;
// SRC[SLEEPDEEP] set to 0 = sleep
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
// wait for interrupt
__WFI();
}
void hal_deepsleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected
mbed_interface_disconnect();
#endif
// PCON[PM] (bits 2:0) set to 1
LPC_PMU->PCON &= ~0x03;
LPC_PMU->PCON |= 0x01;
//According to user manual it is kinda picky about reserved bits, so we follow that nicely
//Keep WDOSC and BOD in same state as they are now during deepsleep
LPC_SYSCON->PDSLEEPCFG = 0x00000037 | (LPC_SYSCON->PDRUNCFG & (0x00000048));
// Power up same as before powerdown
LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
// All interrupts can wake
LPC_SYSCON->STARTERP0 = 0xFF;
LPC_SYSCON->STARTERP1 = 0xFFFFFFFF;
// SRC[SLEEPDEEP] set to 1 = deep sleep
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// wait for interrupt
__WFI();
}
#endif

266
targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c
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@ -1,266 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#if DEVICE_SPI
static const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P2_7 , SPI_0, 0x01},
{P1_20, SPI_1, 0x02},
{P1_27, SPI_1, 0x04},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P1_12, SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x01},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P1_16, SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_15, SPI_0, 0x01},
{P0_23, SPI_1, 0x04},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (LPC_SSP0_Type*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
LPC_SYSCON->SSP0CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 0;
break;
case SPI_1:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
LPC_SYSCON->SSP1CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 2;
break;
}
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_disable(obj);
MBED_ASSERT(((bits >= 4) && (bits <= 16)) || ((mode >= 0) && (mode <= 3)));
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int DSS = bits - 1; // DSS (data select size)
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
obj->spi->CR0 = tmp;
tmp = obj->spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
| 0 << 3; // SOD - slave output disable - na
obj->spi->CR1 = tmp;
ssp_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
ssp_disable(obj);
uint32_t PCLK = SystemCoreClock;
int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_hz = PCLK / prescaler;
// calculate the divider
int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
// check we can support the divider
if (divider < 256) {
// prescaler
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;
}
}
error("Couldn't setup requested SPI frequency");
}
static inline int ssp_disable(spi_t *obj) {
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj) {
return obj->spi->CR1 |= (1 << 1);
}
static inline int ssp_readable(spi_t *obj) {
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj) {
return obj->spi->SR & (1 << 1);
}
static inline void ssp_write(spi_t *obj, int value) {
while (!ssp_writeable(obj));
obj->spi->DR = value;
}
static inline int ssp_read(spi_t *obj) {
while (!ssp_readable(obj));
return obj->spi->DR;
}
static inline int ssp_busy(spi_t *obj) {
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);
return ssp_read(obj);
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj) {
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value) {
while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value;
}
int spi_busy(spi_t *obj) {
return ssp_busy(obj);
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
#endif

73
targets/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c
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@ -1,73 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define US_TICKER_TIMER ((LPC_CT32B0_Type *)LPC_CT32B1_BASE)
#define US_TICKER_TIMER_IRQn CT32B1_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock CT32B1
uint32_t PCLK = SystemCoreClock;
US_TICKER_TIMER->TCR = 0x2; // reset
uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
US_TICKER_TIMER->PR = prescale - 1;
US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
if (!us_ticker_inited)
us_ticker_init();
return US_TICKER_TIMER->TC;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
// set match value
US_TICKER_TIMER->MR0 = (uint32_t)timestamp;
// enable match interrupt
US_TICKER_TIMER->MCR |= 1;
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
void us_ticker_free(void)
{
}