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Remove unavailable and EOLed target boards - STM32 (#287) 

* Remove unavailable and EOLed target boards - STM32

* Make CI detect any missing MCU descriptions

* Oops fix CI syntax

* Aaand add those MCUs

* Also remove "orphaned" cellular modem COMPONENTs
pull/15530/head
Jamie Smith 2024-06-20 21:35:53 -07:00 committed by GitHub
parent dfac17ba38
commit 8956a75bd9
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
92 changed files with 55 additions and 9330 deletions
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26
.github/workflows/basic_checks.yml vendored
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@ -163,7 +163,7 @@ jobs:
steps:
-
name: Checkout repo
uses: actions/checkout@v3
uses: actions/checkout@v4
- name: Install python3-venv
run: |
@ -185,6 +185,30 @@ jobs:
cd tools/python
./run_python_tests.sh
check-cmsis-mcu-descriptions-matches-target-list:
runs-on: ubuntu-latest
steps:
- name: Checkout repo
uses: actions/checkout@v4
- name: Install python3-venv
run: |
sudo apt-get update
sudo apt-get install -y python3-venv
- name: install dependencies
run: |
python3 -m venv venv
source venv/bin/activate
pip install -r tools/requirements.txt
- name: Verify that cmsis_mcu_descriptions.json5 is in sync with targets.json5
run: |
source venv/bin/activate
cd tools/python
python -m mbed_tools.cli.main cmsis-mcu-descr find-unused
python -m mbed_tools.cli.main cmsis-mcu-descr check-missing
pin-validation:
runs-on: ubuntu-latest

1
connectivity/drivers/cellular/CMakeLists.txt
View File

@ -9,6 +9,5 @@ add_subdirectory(Altair)
add_subdirectory(GEMALTO)
add_subdirectory(GENERIC)
add_subdirectory(MultiTech)
add_subdirectory(QUECTEL)
add_subdirectory(RiotMicro)
add_subdirectory(TELIT)

23
connectivity/drivers/cellular/QUECTEL/CMakeLists.txt
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@ -1,23 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
if("COMPONENT_QUECTEL_EC2X=1" IN_LIST MBED_TARGET_DEFINITIONS)
add_subdirectory(COMPONENT_QUECTEL_EC2X)
endif()
if("COMPONENT_QUECTEL_BG96=1" IN_LIST MBED_TARGET_DEFINITIONS OR ("COMPONENT_STMOD_CELLULAR=1" IN_LIST MBED_TARGET_DEFINITIONS AND "MBED_CONF_STMOD_CELLULAR_TYPE=STMOD_BG96"))
add_subdirectory(COMPONENT_QUECTEL_BG96)
endif()
if("COMPONENT_QUECTEL_UG96=1" IN_LIST MBED_TARGET_DEFINITIONS OR ("COMPONENT_STMOD_CELLULAR=1" IN_LIST MBED_TARGET_DEFINITIONS AND "MBED_CONF_STMOD_CELLULAR_TYPE=STMOD_UG96"))
add_subdirectory(COMPONENT_QUECTEL_UG96)
endif()
if("COMPONENT_QUECTEL_BC95=1" IN_LIST MBED_TARGET_DEFINITIONS)
add_subdirectory(COMPONENT_QUECTEL_BC95)
endif()
if("COMPONENT_QUECTEL_M26=1" IN_LIST MBED_TARGET_DEFINITIONS)
add_subdirectory(COMPONENT_QUECTEL_M26)
endif()

20
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/CMakeLists.txt
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@ -1,20 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
QUECTEL_BC95.cpp
QUECTEL_BC95_CellularContext.cpp
QUECTEL_BC95_CellularInformation.cpp
QUECTEL_BC95_CellularNetwork.cpp
QUECTEL_BC95_CellularStack.cpp
)
if("TARGET_ADV_WISE_1570" IN_LIST MBED_TARGET_LABELS)
add_subdirectory(TARGET_ADV_WISE_1570)
endif()

127
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95.cpp
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@ -1,127 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BC95_CellularNetwork.h"
#include "QUECTEL_BC95_CellularContext.h"
#include "QUECTEL_BC95_CellularInformation.h"
#include "QUECTEL_BC95.h"
#include "CellularLog.h"
#define CONNECT_DELIM "\r\n"
#define CONNECT_BUFFER_SIZE (1280 + 80 + 80) // AT response + sscanf format
#define CONNECT_TIMEOUT 8000
using namespace events;
using namespace mbed;
static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = {
AT_CellularNetwork::RegistrationModeLAC, // C_EREG
AT_CellularNetwork::RegistrationModeDisable, // C_GREG
AT_CellularNetwork::RegistrationModeDisable, // C_REG
1, // AT_CGSN_WITH_TYPE
1, // AT_CGDATA
0, // AT_CGAUTH, BC95_AT_Commands_Manual_V1.9
1, // AT_CNMI
1, // AT_CSMP
1, // AT_CMGF
1, // AT_CSDH
1, // PROPERTY_IPV4_STACK
1, // PROPERTY_IPV6_STACK
0, // PROPERTY_IPV4V6_STACK
1, // PROPERTY_NON_IP_PDP_TYPE
0, // PROPERTY_AT_CGEREP,
0, // PROPERTY_AT_COPS_FALLBACK_AUTO
7, // PROPERTY_SOCKET_COUNT
1, // PROPERTY_IP_TCP
1, // PROPERTY_IP_UDP
0, // PROPERTY_AT_SEND_DELAY
};
QUECTEL_BC95::QUECTEL_BC95(FileHandle *fh) : AT_CellularDevice(fh)
{
set_cellular_properties(cellular_properties);
}
nsapi_error_t QUECTEL_BC95::get_sim_state(SimState &state)
{
_at.lock();
_at.flush();
nsapi_error_t err = _at.at_cmd_discard("+NCCID", "?");
_at.unlock();
state = SimStateReady;
if (err != NSAPI_ERROR_OK) {
tr_warn("SIM not readable.");
state = SimStateUnknown;
}
return err;
}
AT_CellularNetwork *QUECTEL_BC95::open_network_impl(ATHandler &at)
{
return new QUECTEL_BC95_CellularNetwork(at, *this);
}
AT_CellularContext *QUECTEL_BC95::create_context_impl(ATHandler &at, const char *apn, bool cp_req, bool nonip_req)
{
return new QUECTEL_BC95_CellularContext(at, this, apn, cp_req, nonip_req);
}
AT_CellularInformation *QUECTEL_BC95::open_information_impl(ATHandler &at)
{
return new QUECTEL_BC95_CellularInformation(at, *this);
}
nsapi_error_t QUECTEL_BC95::init()
{
setup_at_handler();
_at.lock();
_at.flush();
nsapi_error_t err = _at.at_cmd_discard("", ""); //Send AT
if (!err) {
err = _at.at_cmd_discard("+CMEE", "=1"); // verbose responses
}
if (!err) {
err = _at.at_cmd_discard("+CFUN", "=", "%d", 1);
}
if (!err) {
err = _at.get_last_error();
}
_at.unlock();
return err;
}
nsapi_error_t QUECTEL_BC95::set_baud_rate_impl(int baud_rate)
{
return _at.at_cmd_discard("+NATSPEED", "=", "%d%d%d%d%d%d%d", baud_rate, 30, 0, 2, 1, 0, 0);
}
#if MBED_CONF_QUECTEL_BC95_PROVIDE_DEFAULT
#include "drivers/BufferedSerial.h"
CellularDevice *CellularDevice::get_default_instance()
{
static BufferedSerial serial(MBED_CONF_QUECTEL_BC95_TX, MBED_CONF_QUECTEL_BC95_RX, MBED_CONF_QUECTEL_BC95_BAUDRATE);
#if defined(MBED_CONF_QUECTEL_BC95_RTS) && defined(MBED_CONF_QUECTEL_BC95_CTS)
tr_debug("QUECTEL_BC95 flow control: RTS %d CTS %d", MBED_CONF_QUECTEL_BC95_RTS, MBED_CONF_QUECTEL_BC95_CTS);
serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_QUECTEL_BC95_RTS, MBED_CONF_QUECTEL_BC95_CTS);
#endif
static QUECTEL_BC95 device(&serial);
return &device;
}
#endif

52
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95.h
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@ -1,52 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BC95_H_
#define QUECTEL_BC95_H_
#ifdef TARGET_FF_ARDUINO
#ifndef MBED_CONF_QUECTEL_BC95_TX
#define MBED_CONF_QUECTEL_BC95_TX D1
#endif
#ifndef MBED_CONF_QUECTEL_BC95_RX
#define MBED_CONF_QUECTEL_BC95_RX D0
#endif
#endif /* TARGET_FF_ARDUINO */
#include "AT_CellularDevice.h"
namespace mbed {
class QUECTEL_BC95 : public AT_CellularDevice {
public:
QUECTEL_BC95(FileHandle *fh);
public: // AT_CellularDevice
virtual nsapi_error_t get_sim_state(SimState &state);
protected: // AT_CellularDevice
virtual AT_CellularNetwork *open_network_impl(ATHandler &at);
virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual AT_CellularInformation *open_information_impl(ATHandler &at);
virtual nsapi_error_t set_baud_rate_impl(int baud_rate);
virtual nsapi_error_t init();
public: // NetworkInterface
void handle_urc(FileHandle *fh);
};
} // namespace mbed
#endif // QUECTEL_BC95_H_

52
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularContext.cpp
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@ -1,52 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BC95_CellularContext.h"
#include "QUECTEL_BC95_CellularStack.h"
#include "CellularLog.h"
namespace mbed {
QUECTEL_BC95_CellularContext::QUECTEL_BC95_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) :
AT_CellularContext(at, device, apn, cp_req, nonip_req)
{
}
QUECTEL_BC95_CellularContext::~QUECTEL_BC95_CellularContext()
{
}
#if !NSAPI_PPP_AVAILABLE
NetworkStack *QUECTEL_BC95_CellularContext::get_stack()
{
if (_pdp_type == NON_IP_PDP_TYPE || _cp_in_use) {
tr_error("Requesting stack for NON-IP context! Should request control plane netif: get_cp_netif()");
return NULL;
}
if (!_stack) {
_stack = new QUECTEL_BC95_CellularStack(_at, _cid, (nsapi_ip_stack_t)_pdp_type, *get_device());
}
return _stack;
}
#endif // #if !NSAPI_PPP_AVAILABLE
const char *QUECTEL_BC95_CellularContext::get_nonip_context_type_str()
{
return "NONIP";
}
} /* namespace mbed */

38
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularContext.h
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@ -1,38 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BC95_CELLULARCONTEXT_H_
#define QUECTEL_BC95_CELLULARCONTEXT_H_
#include "AT_CellularContext.h"
namespace mbed {
class QUECTEL_BC95_CellularContext: public AT_CellularContext {
public:
QUECTEL_BC95_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual ~QUECTEL_BC95_CellularContext();
protected:
#if !NSAPI_PPP_AVAILABLE
virtual NetworkStack *get_stack();
#endif // #if !NSAPI_PPP_AVAILABLE
virtual const char *get_nonip_context_type_str();
};
} /* namespace mbed */
#endif // QUECTEL_BC95_CELLULARCONTEXT_H_

35
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularInformation.cpp
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@ -1,35 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BC95_CellularInformation.h"
namespace mbed {
QUECTEL_BC95_CellularInformation::QUECTEL_BC95_CellularInformation(ATHandler &at, AT_CellularDevice &device) : AT_CellularInformation(at, device)
{
}
QUECTEL_BC95_CellularInformation::~QUECTEL_BC95_CellularInformation()
{
}
// According to BC95_AT_Commands_Manual_V1.9
nsapi_error_t QUECTEL_BC95_CellularInformation::get_iccid(char *buf, size_t buf_size)
{
return _at.at_cmd_str("+NCCID", "?", buf, buf_size);
}
} /* namespace mbed */

35
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularInformation.h
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@ -1,35 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BC95_CELLULARINFORMATION_H_
#define QUECTEL_BC95_CELLULARINFORMATION_H_
#include "AT_CellularInformation.h"
namespace mbed {
class QUECTEL_BC95_CellularInformation : public AT_CellularInformation {
public:
QUECTEL_BC95_CellularInformation(ATHandler &at, AT_CellularDevice &device);
virtual ~QUECTEL_BC95_CellularInformation();
public:
virtual nsapi_error_t get_iccid(char *buf, size_t buf_size);
};
} /* namespace mbed */
#endif /* QUECTEL_BC95_CELLULARINFORMATION_H_ */

63
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularNetwork.cpp
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@ -1,63 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BC95_CellularNetwork.h"
using namespace mbed;
QUECTEL_BC95_CellularNetwork::QUECTEL_BC95_CellularNetwork(ATHandler &atHandler, AT_CellularDevice &device) : AT_CellularNetwork(atHandler, device)
{
_op_act = RAT_NB1;
}
QUECTEL_BC95_CellularNetwork::~QUECTEL_BC95_CellularNetwork()
{
}
nsapi_error_t QUECTEL_BC95_CellularNetwork::set_access_technology_impl(RadioAccessTechnology opRat)
{
if (opRat != RAT_NB1) {
// only rat that is supported by this modem
_op_act = RAT_NB1;
return NSAPI_ERROR_UNSUPPORTED;
}
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_BC95_CellularNetwork::clear()
{
nsapi_error_t err = AT_CellularNetwork::clear();
#if MBED_CONF_CELLULAR_CONTROL_PLANE_OPT
if (!err) {
err = _at.at_cmd_discard("+CGDCONT", "=", "%d", 0);
#ifdef MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN
err = _at.at_cmd_discard("+CGDCONT", "=", "%d%s%s", 1, "NONIP", MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN);
#endif
if (!err) {
err = _at.at_cmd_discard("+CIPCA", "=", "%d%d", 3, 1); // EPS Attach without PDN connection
}
if (!err) {
_at.lock();
_at.cmd_start("AT+NCONFIG=\"AUTOCONNECT\",\"TRUE\""); // disable auto connect to IP context
_at.cmd_stop_read_resp();
err = _at.unlock_return_error();
}
}
#endif
return err;
}

35
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularNetwork.h
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@ -1,35 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BC95_CELLULAR_NETWORK_H_
#define QUECTEL_BC95_CELLULAR_NETWORK_H_
#include "AT_CellularNetwork.h"
namespace mbed {
class QUECTEL_BC95_CellularNetwork : public AT_CellularNetwork {
public:
QUECTEL_BC95_CellularNetwork(ATHandler &atHandler, AT_CellularDevice &device);
virtual ~QUECTEL_BC95_CellularNetwork();
protected:
virtual nsapi_error_t set_access_technology_impl(RadioAccessTechnology opRat);
virtual nsapi_error_t clear();
};
} // namespace mbed
#endif // QUECTEL_BC95_CELLULAR_NETWORK_H_

315
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularStack.cpp
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@ -1,315 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtos/ThisThread.h"
#include "mbed_error.h"
#include "platform/mbed_atomic.h"
#include "events/EventQueue.h"
#include "events/mbed_shared_queues.h"
#include "QUECTEL_BC95_CellularStack.h"
#include "CellularUtil.h"
#include "CellularLog.h"
#define PACKET_SIZE_MAX 1358
#define TXFULL_EVENT_TIMEOUT 1s
#define AT_UPLINK_BUSY 159
#define AT_UART_BUFFER_ERROR 536
#define AT_BACK_OFF_TIMER 537
using namespace std::chrono;
using namespace mbed;
using namespace mbed_cellular_util;
QUECTEL_BC95_CellularStack::QUECTEL_BC95_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device) :
AT_CellularStack(atHandler, cid, stack_type, device), _event_queue(mbed_event_queue()), _txfull_event_id(0)
{
_at.set_urc_handler("+NSONMI:", mbed::Callback<void()>(this, &QUECTEL_BC95_CellularStack::urc_nsonmi));
_at.set_urc_handler("+NSOCLI:", mbed::Callback<void()>(this, &QUECTEL_BC95_CellularStack::urc_nsocli));
}
QUECTEL_BC95_CellularStack::~QUECTEL_BC95_CellularStack()
{
if (_txfull_event_id) {
_event_queue->cancel(_txfull_event_id);
}
_at.set_urc_handler("+NSONMI:", nullptr);
_at.set_urc_handler("+NSOCLI:", nullptr);
}
nsapi_error_t QUECTEL_BC95_CellularStack::socket_listen(nsapi_socket_t handle, int backlog)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_BC95_CellularStack::socket_accept(void *server, void **socket, SocketAddress *addr)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_BC95_CellularStack::socket_connect(nsapi_socket_t handle, const SocketAddress &address)
{
CellularSocket *socket = (CellularSocket *)handle;
_at.lock();
if (socket->id == -1) {
const nsapi_error_t error_create = create_socket_impl(socket);
if (error_create != NSAPI_ERROR_OK) {
return error_create;
}
}
_at.cmd_start("AT+NSOCO=");
_at.write_int(socket->id);
_at.write_string(address.get_ip_address(), false);
_at.write_int(address.get_port());
_at.cmd_stop_read_resp();
_at.unlock();
if (_at.get_last_error() == NSAPI_ERROR_OK) {
socket->remoteAddress = address;
socket->connected = true;
return NSAPI_ERROR_OK;
}
return NSAPI_ERROR_NO_CONNECTION;
}
void QUECTEL_BC95_CellularStack::urc_nsonmi()
{
int sock_id = _at.read_int();
for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) {
CellularSocket *sock = _socket[i];
if (sock && sock->id == sock_id) {
if (sock->_cb) {
sock->_cb(sock->_data);
}
break;
}
}
}
void QUECTEL_BC95_CellularStack::urc_nsocli()
{
int sock_id = _at.read_int();
const nsapi_error_t err = _at.get_last_error();
if (err != NSAPI_ERROR_OK) {
return;
}
CellularSocket *sock = find_socket(sock_id);
if (sock) {
sock->closed = true;
if (sock->_cb) {
sock->_cb(sock->_data);
}
tr_info("Socket closed %d", sock_id);
}
}
nsapi_error_t QUECTEL_BC95_CellularStack::socket_close_impl(int sock_id)
{
CellularSocket *sock = find_socket(sock_id);
if (sock && sock->closed) {
return NSAPI_ERROR_OK;
}
sock->txfull_event = false;
nsapi_error_t err = _at.at_cmd_discard("+NSOCL", "=", "%d", sock_id);
tr_info("Close socket: %d error: %d", sock_id, err);
return err;
}
nsapi_error_t QUECTEL_BC95_CellularStack::create_socket_impl(CellularSocket *socket)
{
int sock_id = -1;
bool socketOpenWorking = false;
if (socket->proto == NSAPI_UDP) {
_at.cmd_start_stop("+NSOCR", "=DGRAM,", "%d%d%d%s", 17, socket->localAddress.get_port(), 1, ((_ip_ver_sendto == NSAPI_IPv4) ? "AF_INET" : "AF_INET6"));
} else if (socket->proto == NSAPI_TCP) {
_at.cmd_start_stop("+NSOCR", "=STREAM,", "%d%d%d%s", 6, socket->localAddress.get_port(), 1, ((_ip_ver_sendto == NSAPI_IPv4) ? "AF_INET" : "AF_INET6"));
} else {
return NSAPI_ERROR_PARAMETER;
}
_at.resp_start();
sock_id = _at.read_int();
_at.resp_stop();
socketOpenWorking = (_at.get_last_error() == NSAPI_ERROR_OK);
if (!socketOpenWorking || (sock_id == -1)) {
tr_error("Socket create failed!");
return NSAPI_ERROR_NO_SOCKET;
}
tr_info("Socket create id: %d", sock_id);
socket->id = sock_id;
return NSAPI_ERROR_OK;
}
nsapi_size_or_error_t QUECTEL_BC95_CellularStack::socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size)
{
//AT_CellularStack::socket_sendto(...) will create a socket on modem if it wasn't
// open already.
MBED_ASSERT(socket->id != -1);
if (_ip_ver_sendto != address.get_ip_version()) {
_ip_ver_sendto = address.get_ip_version();
socket_close_impl(socket->id);
create_socket_impl(socket);
}
int sent_len = 0;
if (size > PACKET_SIZE_MAX) {
return NSAPI_ERROR_PARAMETER;
}
int retry = 0;
retry_send:
if (socket->proto == NSAPI_UDP) {
_at.cmd_start("AT+NSOST=");
_at.write_int(socket->id);
_at.write_string(address.get_ip_address(), false);
_at.write_int(address.get_port());
_at.write_int(size);
} else if (socket->proto == NSAPI_TCP) {
_at.cmd_start("AT+NSOSD=");
_at.write_int(socket->id);
_at.write_int(size);
} else {
return NSAPI_ERROR_PARAMETER;
}
_at.write_hex_string((char *)data, size, false);
_at.cmd_stop();
_at.resp_start();
// skip socket id
_at.skip_param();
sent_len = _at.read_int();
_at.resp_stop();
if (_at.get_last_error() == NSAPI_ERROR_OK) {
return sent_len;
}
// check for network congestion
device_err_t err = _at.get_last_device_error();
if (
(
err.errType == DeviceErrorTypeErrorCME
&& (err.errCode == AT_UART_BUFFER_ERROR || err.errCode == AT_BACK_OFF_TIMER)
)
|| err.errCode == AT_UPLINK_BUSY
) {
if (socket->proto == NSAPI_UDP) {
if (retry < 3) {
retry++;
tr_warn("Socket %d sendto EAGAIN", socket->id);
rtos::ThisThread::sleep_for(30ms);
_at.clear_error();
goto retry_send;
}
return NSAPI_ERROR_NO_MEMORY;
}
_socket_mutex.lock();
if (!socket->txfull_event && !_txfull_event_id) {
tr_warn("socket %d tx full", socket->id);
socket->txfull_event = true;
_txfull_event_id = _event_queue->call_in(TXFULL_EVENT_TIMEOUT, callback(this, &QUECTEL_BC95_CellularStack::txfull_event_timeout));
if (!_txfull_event_id) {
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_ENOMEM), \
"QUECTEL_BC95_CellularStack::socket_sendto_impl(): unable to add event to queue. Increase \"events.shared-eventsize\"\n");
_socket_mutex.unlock();
return NSAPI_ERROR_NO_MEMORY;
}
}
_socket_mutex.unlock();
return NSAPI_ERROR_WOULD_BLOCK;
}
return _at.get_last_error();
}
nsapi_size_or_error_t QUECTEL_BC95_CellularStack::socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size)
{
//AT_CellularStack::socket_recvfrom(...) will create a socket on modem if it wasn't
// open already.
MBED_ASSERT(socket->id != -1);
nsapi_size_or_error_t recv_len = 0;
int port;
char ip_address[NSAPI_IP_SIZE];
_at.cmd_start_stop("+NSORF", "=", "%d%d", socket->id, size < PACKET_SIZE_MAX ? size : PACKET_SIZE_MAX);
_at.resp_start();
// receiving socket id
_at.skip_param();
_at.read_string(ip_address, sizeof(ip_address));
port = _at.read_int();
recv_len = _at.read_int();
int hexlen = _at.read_hex_string((char *)buffer, recv_len);
// remaining length
_at.skip_param();
_at.resp_stop();
if (!recv_len || (recv_len == -1) || (_at.get_last_error() != NSAPI_ERROR_OK)) {
return NSAPI_ERROR_WOULD_BLOCK;
}
if (address) {
address->set_ip_address(ip_address);
address->set_port(port);
}
if (recv_len != hexlen) {
tr_error("Not received as much data as expected. Should receive: %d bytes, received: %d bytes", recv_len, hexlen);
}
return recv_len;
}
void QUECTEL_BC95_CellularStack::txfull_event_timeout()
{
_socket_mutex.lock();
_txfull_event_id = 0;
for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) {
CellularSocket *sock = _socket[i];
if (sock && sock->_cb && sock->txfull_event) {
sock->txfull_event = false;
sock->_cb(sock->_data);
}
}
_socket_mutex.unlock();
}

61
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/QUECTEL_BC95_CellularStack.h
View File

@ -1,61 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BC95_CELLULARSTACK_H_
#define QUECTEL_BC95_CELLULARSTACK_H_
#include "AT_CellularStack.h"
namespace mbed {
class QUECTEL_BC95_CellularStack : public AT_CellularStack {
public:
QUECTEL_BC95_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device);
virtual ~QUECTEL_BC95_CellularStack();
protected: // NetworkStack
virtual nsapi_error_t socket_listen(nsapi_socket_t handle, int backlog);
virtual nsapi_error_t socket_accept(nsapi_socket_t server,
nsapi_socket_t *handle, SocketAddress *address = 0);
virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address);
protected: // AT_CellularStack
virtual nsapi_error_t socket_close_impl(int sock_id);
virtual nsapi_error_t create_socket_impl(CellularSocket *socket);
virtual nsapi_size_or_error_t socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size);
virtual nsapi_size_or_error_t socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size);
private:
// URC handlers
void urc_nsonmi();
void urc_nsocli();
events::EventQueue *_event_queue;
int _txfull_event_id;
void txfull_event_timeout();
};
} // namespace mbed
#endif /* QUECTEL_BC95_CELLULARSTACK_H_ */

12
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/TARGET_ADV_WISE_1570/CMakeLists.txt
View File

@ -1,12 +0,0 @@
# Copyright (c) 2024 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
ONBOARD_QUECTEL_BC95.cpp
)

64
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/TARGET_ADV_WISE_1570/ONBOARD_QUECTEL_BC95.cpp
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@ -1,64 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if MBED_CONF_NSAPI_PRESENT
#include "ONBOARD_QUECTEL_BC95.h"
#include "drivers/BufferedSerial.h"
#include "CellularLog.h"
using namespace mbed;
ONBOARD_QUECTEL_BC95::ONBOARD_QUECTEL_BC95(FileHandle *fh) : QUECTEL_BC95(fh)
{
}
nsapi_error_t ONBOARD_QUECTEL_BC95::hard_power_on()
{
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BC95::hard_power_off()
{
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BC95::soft_power_on()
{
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BC95::soft_power_off()
{
return NSAPI_ERROR_OK;
}
CellularDevice *CellularDevice::get_target_default_instance()
{
static BufferedSerial serial(MDMTXD, MDMRXD, 9600);
#if DEVICE_SERIAL_FC
if (MDMRTS != NC && MDMCTS != NC) {
tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS);
serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS);
}
#endif
static ONBOARD_QUECTEL_BC95 device(&serial);
return &device;
}
#endif // MBED_CONF_NSAPI_PRESENT

37
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/TARGET_ADV_WISE_1570/ONBOARD_QUECTEL_BC95.h
View File

@ -1,37 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ONBOARD_QUECTEL_BC95_
#define ONBOARD_QUECTEL_BC95_
#include "QUECTEL_BC95.h"
namespace mbed {
class ONBOARD_QUECTEL_BC95 : public QUECTEL_BC95 {
public:
ONBOARD_QUECTEL_BC95(FileHandle *fh);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
};
} // namespace mbed
#endif // ONBOARD_QUECTEL_BC95_

29
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BC95/mbed_lib.json
View File

@ -1,29 +0,0 @@
{
"name": "QUECTEL_BC95",
"config": {
"tx": {
"help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rx": {
"help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rts": {
"help": "RTS pin for serial connection",
"value": null
},
"cts": {
"help": "CTS pin for serial connection",
"value": null
},
"baudrate" : {
"help": "Serial connection baud rate",
"value": 9600
},
"provide-default": {
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
}
}

21
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/CMakeLists.txt
View File

@ -1,21 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
QUECTEL_BG96.cpp
QUECTEL_BG96_CellularContext.cpp
QUECTEL_BG96_CellularInformation.cpp
QUECTEL_BG96_CellularNetwork.cpp
QUECTEL_BG96_CellularStack.cpp
QUECTEL_BG96_ControlPlane_netif.cpp
)
if("TARGET_WIO_BG96" IN_LIST MBED_TARGET_LABELS)
add_subdirectory(TARGET_WIO_BG96)
endif()

222
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96.cpp
View File

@ -1,222 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtos/ThisThread.h"
#include "QUECTEL_BG96.h"
#include "QUECTEL_BG96_CellularNetwork.h"
#include "QUECTEL_BG96_CellularStack.h"
#include "QUECTEL_BG96_CellularInformation.h"
#include "QUECTEL_BG96_CellularContext.h"
#include "CellularLog.h"
using std::milli;
using namespace std::chrono;
using namespace mbed;
using namespace events;
using namespace rtos;
#define CONNECT_DELIM "\r\n"
#define CONNECT_BUFFER_SIZE (1280 + 80 + 80) // AT response + sscanf format
#define CONNECT_TIMEOUT 8000
#define DEVICE_READY_URC "CPIN:"
#if !defined(MBED_CONF_QUECTEL_BG96_PWR)
#define MBED_CONF_QUECTEL_BG96_PWR NC
#endif
#if !defined(MBED_CONF_QUECTEL_BG96_RST)
#define MBED_CONF_QUECTEL_BG96_RST NC
#endif
#if !defined(MBED_CONF_QUECTEL_BG96_POLARITY)
#define MBED_CONF_QUECTEL_BG96_POLARITY 1 // active high
#endif
static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = {
AT_CellularNetwork::RegistrationModeLAC, // C_EREG
AT_CellularNetwork::RegistrationModeLAC, // C_GREG
AT_CellularNetwork::RegistrationModeLAC, // C_REG
0, // AT_CGSN_WITH_TYPE
0, // AT_CGDATA
1, // AT_CGAUTH
1, // AT_CNMI
1, // AT_CSMP
1, // AT_CMGF
1, // AT_CSDH
1, // PROPERTY_IPV4_STACK
1, // PROPERTY_IPV6_STACK
0, // PROPERTY_IPV4V6_STACK
1, // PROPERTY_NON_IP_PDP_TYPE
1, // PROPERTY_AT_CGEREP,
1, // PROPERTY_AT_COPS_FALLBACK_AUTO
12, // PROPERTY_SOCKET_COUNT
1, // PROPERTY_IP_TCP
1, // PROPERTY_IP_UDP
0, // PROPERTY_AT_SEND_DELAY
};
QUECTEL_BG96::QUECTEL_BG96(FileHandle *fh, PinName pwr, bool active_high, PinName rst)
: AT_CellularDevice(fh),
_active_high(active_high),
_pwr(pwr, !_active_high),
_rst(rst, !_active_high)
{
set_cellular_properties(cellular_properties);
}
void QUECTEL_BG96::set_at_urcs_impl()
{
_at.set_urc_handler("+QIURC: \"pdpde", mbed::Callback<void()>(this, &QUECTEL_BG96::urc_pdpdeact));
}
AT_CellularNetwork *QUECTEL_BG96::open_network_impl(ATHandler &at)
{
return new QUECTEL_BG96_CellularNetwork(at, *this);
}
AT_CellularContext *QUECTEL_BG96::create_context_impl(ATHandler &at, const char *apn, bool cp_req, bool nonip_req)
{
return new QUECTEL_BG96_CellularContext(at, this, apn, cp_req, nonip_req);
}
AT_CellularInformation *QUECTEL_BG96::open_information_impl(ATHandler &at)
{
return new QUECTEL_BG96_CellularInformation(at, *this);
}
void QUECTEL_BG96::set_ready_cb(Callback<void()> callback)
{
_at.set_urc_handler(DEVICE_READY_URC, callback);
}
nsapi_error_t QUECTEL_BG96::soft_power_on()
{
if (_pwr.is_connected()) {
tr_info("QUECTEL_BG96::soft_power_on");
// check if modem was powered on already
if (!wake_up()) {
if (!wake_up(true)) {
tr_error("Modem not responding");
soft_power_off();
return NSAPI_ERROR_DEVICE_ERROR;
}
}
}
#if defined (MBED_CONF_QUECTEL_BG96_RTS) && defined(MBED_CONF_QUECTEL_BG96_CTS)
if (_at.at_cmd_discard("+IFC", "=", "%d%d", 2, 2) != NSAPI_ERROR_OK) {
tr_warn("Set flow control failed");
return NSAPI_ERROR_DEVICE_ERROR;
}
#endif
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_BG96::soft_power_off()
{
_at.lock();
_at.cmd_start("AT+QPOWD");
_at.cmd_stop_read_resp();
if (_at.get_last_error() != NSAPI_ERROR_OK) {
tr_warn("Force modem off");
if (_pwr.is_connected()) {
press_button(_pwr, 650ms); // BG96_Hardware_Design_V1.1: Power off signal at least 650 ms
}
}
return _at.unlock_return_error();
}
#if MBED_CONF_QUECTEL_BG96_PROVIDE_DEFAULT
#include "drivers/BufferedSerial.h"
CellularDevice *CellularDevice::get_default_instance()
{
static BufferedSerial serial(MBED_CONF_QUECTEL_BG96_TX, MBED_CONF_QUECTEL_BG96_RX, MBED_CONF_QUECTEL_BG96_BAUDRATE);
#if defined (MBED_CONF_QUECTEL_BG96_RTS) && defined(MBED_CONF_QUECTEL_BG96_CTS)
tr_debug("QUECTEL_BG96 flow control: RTS %d CTS %d", MBED_CONF_QUECTEL_BG96_RTS, MBED_CONF_QUECTEL_BG96_CTS);
serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_QUECTEL_BG96_RTS, MBED_CONF_QUECTEL_BG96_CTS);
#endif
static QUECTEL_BG96 device(&serial,
MBED_CONF_QUECTEL_BG96_PWR,
MBED_CONF_QUECTEL_BG96_POLARITY,
MBED_CONF_QUECTEL_BG96_RST);
return &device;
}
#endif
void QUECTEL_BG96::urc_pdpdeact()
{
_at.lock();
_at.skip_param();
int cid = _at.read_int();
const nsapi_error_t err = _at.unlock_return_error();
if (err != NSAPI_ERROR_OK) {
return;
}
send_disconnect_to_context(cid);
}
void QUECTEL_BG96::press_button(DigitalOut &button, duration<uint32_t, milli> timeout)
{
if (!button.is_connected()) {
return;
}
button = _active_high;
ThisThread::sleep_for(timeout);
button = !_active_high;
}
bool QUECTEL_BG96::wake_up(bool reset)
{
// check if modem is already ready
_at.lock();
_at.flush();
_at.set_at_timeout(30ms);
_at.cmd_start("AT");
_at.cmd_stop_read_resp();
nsapi_error_t err = _at.get_last_error();
_at.restore_at_timeout();
_at.unlock();
// modem is not responding, power it on
if (err != NSAPI_ERROR_OK) {
if (!reset) {
// BG96_Hardware_Design_V1.1 requires VBAT to be stable over 30 ms, that's handled above
tr_info("Power on modem");
press_button(_pwr, 250ms); // BG96_Hardware_Design_V1.1 requires time 100 ms, but 250 ms seems to be more robust
} else {
tr_warn("Reset modem");
press_button(_rst, 150ms); // BG96_Hardware_Design_V1.1 requires RESET_N timeout at least 150 ms
}
_at.lock();
// According to BG96_Hardware_Design_V1.1 USB is active after 4.2s, but it seems to take over 5s
_at.set_at_timeout(6s);
_at.resp_start();
_at.set_stop_tag("RDY");
bool rdy = _at.consume_to_stop_tag();
_at.set_stop_tag(OK);
_at.restore_at_timeout();
_at.unlock();
if (!rdy) {
return false;
}
}
// sync to check that AT is really responsive and to clear garbage
return _at.sync(500);
}

61
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96.h
View File

@ -1,61 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_H_
#define QUECTEL_BG96_H_
#ifdef TARGET_FF_ARDUINO
#ifndef MBED_CONF_QUECTEL_BG96_TX
#define MBED_CONF_QUECTEL_BG96_TX D1
#endif
#ifndef MBED_CONF_QUECTEL_BG96_RX
#define MBED_CONF_QUECTEL_BG96_RX D0
#endif
#endif /* TARGET_FF_ARDUINO */
#include <chrono>
#include "DigitalOut.h"
#include "AT_CellularDevice.h"
namespace mbed {
class QUECTEL_BG96 : public AT_CellularDevice {
public:
QUECTEL_BG96(FileHandle *fh, PinName pwr = NC, bool active_high = true, PinName rst = NC);
protected: // AT_CellularDevice
virtual AT_CellularNetwork *open_network_impl(ATHandler &at);
virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual AT_CellularInformation *open_information_impl(ATHandler &at);
virtual void set_ready_cb(Callback<void()> callback);
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
virtual void set_at_urcs_impl();
public:
void handle_urc(FileHandle *fh);
private:
void press_button(DigitalOut &button, std::chrono::duration<uint32_t, std::milli> timeout);
bool wake_up(bool reset = false);
bool _active_high;
DigitalOut _pwr;
DigitalOut _rst;
void urc_pdpdeact();
};
} // namespace mbed
#endif // QUECTEL_BG96_H_

189
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularContext.cpp
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@ -1,189 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BG96_CellularContext.h"
#include "QUECTEL_BG96_CellularStack.h"
#include "QUECTEL_BG96_ControlPlane_netif.h"
#include "CellularLog.h"
#include "Semaphore.h"
namespace mbed {
// Non-IP context supported only for context id 1
#define NIDD_PDP_CONTEXT_ID 1
// Timeout to wait for URC indicating NIDD connection opening
#define NIDD_OPEN_URC_TIMEOUT 3000
QUECTEL_BG96_CellularContext::QUECTEL_BG96_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) :
AT_CellularContext(at, device, apn, cp_req, nonip_req)
{
if (_nonip_req) {
_at.set_urc_handler("+QIND:", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularContext::urc_nidd));
}
}
QUECTEL_BG96_CellularContext::~QUECTEL_BG96_CellularContext()
{
if (_nonip_req) {
_at.set_urc_handler("+QIND:", nullptr);
}
}
#if !NSAPI_PPP_AVAILABLE
NetworkStack *QUECTEL_BG96_CellularContext::get_stack()
{
if (_pdp_type == NON_IP_PDP_TYPE || (_nonip_req && _pdp_type != DEFAULT_PDP_TYPE)) {
tr_error("Requesting stack for NON-IP context! Should request control plane netif: get_cp_netif()");
return NULL;
}
if (!_stack) {
_stack = new QUECTEL_BG96_CellularStack(_at, _cid, (nsapi_ip_stack_t)_pdp_type, *get_device());
}
return _stack;
}
#endif // #if !NSAPI_PPP_AVAILABLE
ControlPlane_netif *QUECTEL_BG96_CellularContext::get_cp_netif()
{
if (!_cp_netif) {
_cp_netif = new QUECTEL_BG96_ControlPlane_netif(_at, _cid, *get_device());
}
return _cp_netif;
}
nsapi_error_t QUECTEL_BG96_CellularContext::do_user_authentication()
{
uint8_t type = (uint8_t)_pdp_type;
if ((uint8_t)_pdp_type < 1) {
type = 1;
}
if (_pwd && _uname) {
if (_at.at_cmd_discard("+QICSGP", "=", "%d%d%s%s%s%d", _cid, type,
_apn, _uname, _pwd, _authentication_type) != NSAPI_ERROR_OK) {
return NSAPI_ERROR_AUTH_FAILURE;
}
} else {
if (_at.at_cmd_discard("+QICSGP", "=", "%d%d%s", _cid, type,
_apn) != NSAPI_ERROR_OK) {
return NSAPI_ERROR_AUTH_FAILURE;
}
}
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_BG96_CellularContext::activate_non_ip_context()
{
// Open the NIDD connection
nsapi_size_or_error_t ret = _at.at_cmd_discard("+QCFGEXT", "=\"nipd\",1");
if (ret == NSAPI_ERROR_OK) {
_at.lock();
_at.set_at_timeout(NIDD_OPEN_URC_TIMEOUT);
_at.resp_start("+QIND:");
urc_nidd();
_at.restore_at_timeout();
_at.unlock();
if (_cid == -1) {
return NSAPI_ERROR_NO_CONNECTION;
}
}
return (ret == NSAPI_ERROR_OK) ? NSAPI_ERROR_OK : NSAPI_ERROR_NO_CONNECTION;
}
void QUECTEL_BG96_CellularContext::activate_context()
{
tr_info("Activate PDP context %d", _cid);
if (_at.at_cmd_discard("+QIACT", "=", "%d", _cid) == NSAPI_ERROR_OK) {
_is_context_activated = true;
}
}
void QUECTEL_BG96_CellularContext::deactivate_context()
{
_at.at_cmd_discard("+QIDEACT", "=", "%d", _cid);
}
void QUECTEL_BG96_CellularContext::deactivate_non_ip_context()
{
// Close the NIDD connection
_at.at_cmd_discard("+QCFGEXT", "=\"nipd\",0");
}
void QUECTEL_BG96_CellularContext::urc_nidd()
{
char nipd_string[6];
// skip "nipd"
_at.skip_param();
_at.read_string(nipd_string, sizeof(nipd_string));
if (!strcmp(nipd_string, "recv")) {
cp_data_received();
} else if (!strcmp(nipd_string, "open")) {
urc_nidd_open();
} else if (!strcmp(nipd_string, "close")) {
urc_nidd_close();
}
}
void QUECTEL_BG96_CellularContext::urc_nidd_open()
{
int err = _at.read_int();
if (!err) {
_is_context_active = true;
_is_context_activated = true;
_cid = NIDD_PDP_CONTEXT_ID;
} else {
tr_error("NIDD connection open failed with error: %d", err);
}
}
void QUECTEL_BG96_CellularContext::urc_nidd_close()
{
set_disconnect();
}
nsapi_error_t QUECTEL_BG96_CellularContext::setup_control_plane_opt()
{
_at.lock();
_at.at_cmd_discard("+QCFGEXT", "=\"pdp_type\",", "%d%s%s", NIDD_PDP_CONTEXT_ID, "Non-IP", _apn);
_at.at_cmd_discard("+CFUN", "=0");
_at.at_cmd_discard("+CFUN", "=1");
// Configure Non-IP outgoing data type - 0 for no exception data
nsapi_error_t err = _at.at_cmd_discard("+QCFGEXT", "=\"nipdcfg\",0,", "%s", _apn);
if (err == NSAPI_ERROR_OK) {
_cp_in_use = true;
if (_nonip_req) {
_pdp_type = NON_IP_PDP_TYPE;
}
}
return _at.unlock_return_error();
}
} /* namespace mbed */

49
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularContext.h
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@ -1,49 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_CELLULARCONTEXT_H_
#define QUECTEL_BG96_CELLULARCONTEXT_H_
#include "AT_CellularContext.h"
namespace mbed {
class QUECTEL_BG96_CellularContext: public AT_CellularContext {
public:
QUECTEL_BG96_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual ~QUECTEL_BG96_CellularContext();
protected:
#if !NSAPI_PPP_AVAILABLE
virtual NetworkStack *get_stack();
#endif // #if !NSAPI_PPP_AVAILABLE
virtual ControlPlane_netif *get_cp_netif();
virtual nsapi_error_t do_user_authentication();
virtual nsapi_error_t activate_non_ip_context();
virtual nsapi_error_t setup_control_plane_opt();
virtual void deactivate_non_ip_context();
virtual void deactivate_context();
virtual void activate_context();
private:
void urc_nidd();
void urc_nidd_open();
void urc_nidd_close();
};
} /* namespace mbed */
#endif // QUECTEL_BG96_CELLULARCONTEXT_H_

40
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularInformation.cpp
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/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BG96_CellularInformation.h"
namespace mbed {
QUECTEL_BG96_CellularInformation::QUECTEL_BG96_CellularInformation(ATHandler &at, AT_CellularDevice &device) : AT_CellularInformation(at, device)
{
}
QUECTEL_BG96_CellularInformation::~QUECTEL_BG96_CellularInformation()
{
}
// According to BG96_AT_Commands_Manual_V2.0
nsapi_error_t QUECTEL_BG96_CellularInformation::get_iccid(char *buf, size_t buf_size)
{
return _at.at_cmd_str("+QCCID", "", buf, buf_size);
}
nsapi_error_t QUECTEL_BG96_CellularInformation::get_revision(char *buf, size_t buf_size)
{
return get_info("AT+QGMR", buf, buf_size);
}
} /* namespace mbed */

36
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularInformation.h
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@ -1,36 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_CELLULARINFORMATION_H_
#define QUECTEL_BG96_CELLULARINFORMATION_H_
#include "AT_CellularInformation.h"
namespace mbed {
class QUECTEL_BG96_CellularInformation: public AT_CellularInformation {
public:
QUECTEL_BG96_CellularInformation(ATHandler &at, AT_CellularDevice &device);
virtual ~QUECTEL_BG96_CellularInformation();
public: // AT_CellularInformation
virtual nsapi_error_t get_iccid(char *buf, size_t buf_size);
virtual nsapi_error_t get_revision(char *buf, size_t buf_size);
};
} /* namespace mbed */
#endif /* QUECTEL_BG96_CELLULARINFORMATION_H_ */

79
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularNetwork.cpp
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/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_BG96_CellularNetwork.h"
#include "QUECTEL_BG96_CellularStack.h"
#include "CellularLog.h"
using namespace mbed;
QUECTEL_BG96_CellularNetwork::QUECTEL_BG96_CellularNetwork(ATHandler &atHandler, AT_CellularDevice &device) : AT_CellularNetwork(atHandler, device)
{
}
QUECTEL_BG96_CellularNetwork::~QUECTEL_BG96_CellularNetwork()
{
}
nsapi_error_t QUECTEL_BG96_CellularNetwork::set_access_technology_impl(RadioAccessTechnology opsAct)
{
_at.lock();
switch (opsAct) {
case RAT_CATM1:
_at.at_cmd_discard("+QCFG", "=\"nwscanseq\",020301");
_at.at_cmd_discard("+QCFG", "=\"nwscanmode\",3,1");
_at.at_cmd_discard("+QCFG", "=\"iotopmode\",0,1");
break;
case RAT_NB1:
_at.at_cmd_discard("+QCFG", "=\"nwscanseq\",030201");
_at.at_cmd_discard("+QCFG", "=\"nwscanmode\",3,1");
_at.at_cmd_discard("+QCFG", "=\"iotopmode\",1,1");
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
// enable ePCO IE for DNS address
_at.cmd_start("AT+QNVFW=");
_at.write_string("/nv/item_files/modem/nas/nas_ciot_capability_config");
_at.write_string("0101", false);
#endif
break;
case RAT_GSM:
case RAT_GSM_COMPACT:
case RAT_UTRAN:
case RAT_EGPRS:
_at.at_cmd_discard("+QCFG", "=\"nwscanseq\",010203");
_at.at_cmd_discard("+QCFG", "=\"nwscanmode\",1,1");
break;
default:
_at.at_cmd_discard("+QCFG", "=\"nwscanseq\",020301");
_at.at_cmd_discard("+QCFG", "=\"nwscanmode\",0,1");
_at.at_cmd_discard("+QCFG", "=\"iotopmode\",2,1");
_at.unlock();
_op_act = RAT_UNKNOWN;
return NSAPI_ERROR_UNSUPPORTED;
}
return _at.unlock_return_error();
}
void QUECTEL_BG96_CellularNetwork::get_context_state_command()
{
// read active contexts
_at.cmd_start_stop("+QIACT", "?");
_at.resp_start("+QIACT:");
}

38
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularNetwork.h
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/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_CELLULAR_NETWORK_H_
#define QUECTEL_BG96_CELLULAR_NETWORK_H_
#include "AT_CellularNetwork.h"
namespace mbed {
class QUECTEL_BG96_CellularNetwork : public AT_CellularNetwork {
public:
QUECTEL_BG96_CellularNetwork(ATHandler &atHandler, AT_CellularDevice &device);
virtual ~QUECTEL_BG96_CellularNetwork();
protected:
virtual nsapi_error_t set_access_technology_impl(RadioAccessTechnology opRat);
virtual void get_context_state_command();
};
} // namespace mbed
#endif // QUECTEL_BG96_CELLULAR_NETWORK_H_

709
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularStack.cpp
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/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <string.h>
#include "QUECTEL/BG96/QUECTEL_BG96_CellularStack.h"
#include "CellularLog.h"
#include "netsocket/TLSSocket.h"
#include "CellularUtil.h"
// Ref: Quectel_BG96_SSL_AT_Commands_Manual, ch 2.1.1 AT+QSSLCFG
static const int BG96_SUPPORTED_SSL_VERSION = 4; // All
static const char BG96_SUPPORTED_CIPHER_SUITE[] = "0xFFFF"; // Support all
// TODO: At the moment we support only one active SSL context
// Later can be expanded to support multiple contexts. Modem supports IDs 0-5.
static const int sslctxID = 0;
static const int BG96_ASYNC_DNS_QUERY_ID = 1; // BG96 driver only supports one request, so using id 1
using namespace mbed;
using namespace std::chrono_literals;
QUECTEL_BG96_CellularStack::QUECTEL_BG96_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device) :
AT_CellularStack(atHandler, cid, stack_type, device)
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
#if (MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES != 1)
#error Define cellular.offload-dns-queries to null or 1.
#endif
, _dns_callback(NULL), _dns_version(NSAPI_UNSPEC)
#endif
, _tls_sec_level(0)
{
_at.set_urc_handler("+QIURC: \"recv", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularStack::urc_qiurc_recv));
_at.set_urc_handler("+QIURC: \"close", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularStack::urc_qiurc_closed));
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
_at.set_urc_handler("+QIURC: \"dnsgip\",", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularStack::urc_qiurc_dnsgip));
#endif
_at.set_urc_handler("+QSSLURC: \"recv", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularStack::urc_qiurc_recv));
_at.set_urc_handler("+QSSLURC: \"close", mbed::Callback<void()>(this, &QUECTEL_BG96_CellularStack::urc_qiurc_closed));
// TODO: this needs to be handled properly, but now making just a quick hack
// Close all SSL sockets if open. This can happen for example if application processor
// was reset but modem not. Old sockets are still up and running and it prevents
// new SSL configurations and creating new sockets.
for (int i = 0; i < 12; i++) {
_at.clear_error();
tr_debug("Closing SSL socket %d...", i);
_at.at_cmd_discard("+QSSLCLOSE", "=", "%d", i);
}
_at.clear_error();
}
QUECTEL_BG96_CellularStack::~QUECTEL_BG96_CellularStack()
{
}
nsapi_error_t QUECTEL_BG96_CellularStack::socket_listen(nsapi_socket_t handle, int backlog)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_BG96_CellularStack::socket_accept(void *server, void **socket, SocketAddress *addr)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_BG96_CellularStack::socket_connect(nsapi_socket_t handle, const SocketAddress &address)
{
CellularSocket *socket = (CellularSocket *)handle;
int modem_connect_id = -1;
int err = NSAPI_ERROR_NO_CONNECTION;
int request_connect_id = find_socket_index(socket);
// assert here as its a programming error if the socket container doesn't contain
// specified handle
MBED_ASSERT(request_connect_id != -1);
_at.lock();
if (socket->proto == NSAPI_TCP) {
if (socket->tls_socket) {
if (_tls_sec_level == 0) {
_at.unlock();
return NSAPI_ERROR_AUTH_FAILURE;
}
_at.at_cmd_discard("+QSSLOPEN", "=", "%d%d%d%s%d%d", _cid, sslctxID, request_connect_id,
address.get_ip_address(), address.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, true);
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
if (err == BG96_SOCKET_BIND_FAIL) {
socket->id = -1;
_at.unlock();
return NSAPI_ERROR_PARAMETER;
}
socket_close_impl(modem_connect_id);
_at.at_cmd_discard("+QSSLOPEN", "=", "%d%d%d%s%d%d", _cid, sslctxID, request_connect_id,
address.get_ip_address(), address.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, true);
}
} else {
char ipdot[NSAPI_IP_SIZE];
ip2dot(address, ipdot);
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "TCP",
ipdot, address.get_port(), socket->localAddress.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, false);
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
if (err == BG96_SOCKET_BIND_FAIL) {
socket->id = -1;
_at.unlock();
return NSAPI_ERROR_PARAMETER;
}
socket_close_impl(modem_connect_id);
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "TCP",
ipdot, address.get_port(), socket->localAddress.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, false);
}
}
}
// If opened successfully BUT not requested one, close it
if (!err && (modem_connect_id != request_connect_id)) {
_at.at_cmd_discard("+QICLOSE", "=", "%d", modem_connect_id);
}
nsapi_error_t ret_val = _at.get_last_error();
_at.unlock();
if ((!err) && (ret_val == NSAPI_ERROR_OK) && (modem_connect_id == request_connect_id)) {
socket->id = request_connect_id;
socket->remoteAddress = address;
socket->connected = true;
return NSAPI_ERROR_OK;
}
return err;
}
nsapi_error_t QUECTEL_BG96_CellularStack::get_ip_address(SocketAddress *address)
{
if (!address) {
return NSAPI_ERROR_PARAMETER;
}
_at.lock();
_at.cmd_start_stop("+QIACT", "?");
_at.resp_start("+QIACT:");
int32_t context_type = 0;
if (_at.info_resp()) {
_at.skip_param(); // ID
_at.skip_param(); // State
context_type = _at.read_int();
if (context_type == 1) {
_stack_type = IPV4_STACK;
} else if (context_type == 2) {
_stack_type = IPV6_STACK;
}
if (_at.read_string(_ip, PDP_IPV6_SIZE) != -1) {
mbed_cellular_util::convert_ipv6(_ip);
address->set_ip_address(_ip);
}
}
_at.resp_stop();
_at.unlock();
return (context_type > 0) ? NSAPI_ERROR_OK : NSAPI_ERROR_NO_ADDRESS;
}
void QUECTEL_BG96_CellularStack::urc_qiurc_recv()
{
urc_qiurc(URC_RECV);
}
void QUECTEL_BG96_CellularStack::urc_qiurc_closed()
{
urc_qiurc(URC_CLOSED);
}
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
bool QUECTEL_BG96_CellularStack::read_dnsgip(SocketAddress &address, nsapi_version_t _dns_version)
{
if (_at.read_int() == 0) {
int count = _at.read_int();
_at.skip_param();
for (; count > 0; count--) {
_at.resp_start("+QIURC: \"dnsgip\",");
char ipAddress[NSAPI_IP_SIZE];
_at.read_string(ipAddress, sizeof(ipAddress));
if (address.set_ip_address(ipAddress)) {
if (_dns_version == NSAPI_UNSPEC || _dns_version == address.get_ip_version()) {
return true;
}
}
}
}
return false;
}
void QUECTEL_BG96_CellularStack::urc_qiurc_dnsgip()
{
if (!_dns_callback) {
return;
}
SocketAddress address;
if (read_dnsgip(address, _dns_version)) {
_dns_callback(1, &address);
} else {
_dns_callback(NSAPI_ERROR_DNS_FAILURE, NULL);
}
_dns_callback = NULL;
}
#endif
void QUECTEL_BG96_CellularStack::urc_qiurc(urc_type_t urc_type)
{
_at.lock();
_at.skip_param();
const int sock_id = _at.read_int();
const nsapi_error_t err = _at.unlock_return_error();
if (err != NSAPI_ERROR_OK) {
return;
}
CellularSocket *sock = find_socket(sock_id);
if (sock) {
if (urc_type == URC_CLOSED) {
tr_info("Socket closed %d", sock_id);
sock->closed = true;
}
if (sock->_cb) {
sock->_cb(sock->_data);
}
}
}
nsapi_error_t QUECTEL_BG96_CellularStack::socket_close_impl(int sock_id)
{
_at.set_at_timeout(BG96_CLOSE_SOCKET_TIMEOUT);
nsapi_error_t err;
CellularSocket *socket = find_socket(sock_id);
if (socket && socket->tls_socket) {
err = _at.at_cmd_discard("+QSSLCLOSE", "=", "%d", sock_id);
if (err == NSAPI_ERROR_OK) {
// Disable TLSSocket settings to prevent reuse on next socket without setting the values
_tls_sec_level = 0;
err = _at.at_cmd_discard("+QSSLCFG", "=\"seclevel\",", "%d%d", sslctxID, _tls_sec_level);
}
} else {
err = _at.at_cmd_discard("+QICLOSE", "=", "%d", sock_id);
}
_at.restore_at_timeout();
return err;
}
void QUECTEL_BG96_CellularStack::handle_open_socket_response(int &modem_connect_id, int &err, bool tlssocket)
{
// OK
// QIOPEN -> should be handled as URC?
_at.set_at_timeout(BG96_CREATE_SOCKET_TIMEOUT);
if (tlssocket) {
_at.resp_start("+QSSLOPEN:");
} else {
_at.resp_start("+QIOPEN:");
}
_at.restore_at_timeout();
modem_connect_id = _at.read_int();
err = _at.read_int();
if (tlssocket && err != 0) {
err = NSAPI_ERROR_AUTH_FAILURE;
}
}
nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *socket)
{
int modem_connect_id = -1;
int remote_port = 0;
int err = -1;
int request_connect_id = find_socket_index(socket);
// assert here as its a programming error if the socket container doesn't contain
// specified handle
MBED_ASSERT(request_connect_id != -1);
if (socket->proto == NSAPI_UDP && !socket->connected) {
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "UDP SERVICE",
(_ip_ver_sendto == NSAPI_IPv4) ? "127.0.0.1" : "0:0:0:0:0:0:0:1",
remote_port, socket->localAddress.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, false);
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
if (err == BG96_SOCKET_BIND_FAIL) {
socket->id = -1;
return NSAPI_ERROR_PARAMETER;
}
socket_close_impl(modem_connect_id);
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "UDP SERVICE",
(_ip_ver_sendto == NSAPI_IPv4) ? "127.0.0.1" : "0:0:0:0:0:0:0:1",
remote_port, socket->localAddress.get_port(), 0);
handle_open_socket_response(modem_connect_id, err, false);
}
} else if (socket->proto == NSAPI_UDP && socket->connected) {
char ipdot[NSAPI_IP_SIZE];
ip2dot(socket->remoteAddress, ipdot);
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d", _cid, request_connect_id, "UDP",
ipdot, socket->remoteAddress.get_port());
handle_open_socket_response(modem_connect_id, err, false);
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
if (err == BG96_SOCKET_BIND_FAIL) {
socket->id = -1;
return NSAPI_ERROR_PARAMETER;
}
socket_close_impl(modem_connect_id);
_at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d", _cid, request_connect_id, "UDP",
ipdot, socket->remoteAddress.get_port());
handle_open_socket_response(modem_connect_id, err, false);
}
}
// If opened successfully BUT not requested one, close it
if (!err && (modem_connect_id != request_connect_id)) {
socket_close_impl(modem_connect_id);
}
nsapi_error_t ret_val = _at.get_last_error();
if (ret_val == NSAPI_ERROR_OK && (modem_connect_id == request_connect_id)) {
socket->id = request_connect_id;
}
return ret_val;
}
nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size)
{
if (_ip_ver_sendto != address.get_ip_version()) {
_ip_ver_sendto = address.get_ip_version();
socket_close_impl(socket->id);
create_socket_impl(socket);
}
int sent_len = 0;
int sent_len_before = 0;
int sent_len_after = 0;
if (socket->tls_socket) {
sent_len_after = size;
} else {
// Get the sent count before sending
_at.at_cmd_int("+QISEND", "=", sent_len_before, "%d%d", socket->id, 0);
}
// Send
if (socket->proto == NSAPI_UDP) {
if (size > BG96_MAX_SEND_SIZE) {
return NSAPI_ERROR_PARAMETER;
}
char ipdot[NSAPI_IP_SIZE];
ip2dot(address, ipdot);
_at.cmd_start_stop("+QISEND", "=", "%d%d%s%d", socket->id, size,
ipdot, address.get_port());
_at.resp_start(">");
_at.write_bytes((uint8_t *)data, size);
_at.resp_start();
_at.set_stop_tag("\r\n");
// Possible responses are SEND OK, SEND FAIL or ERROR.
char response[16];
response[0] = '\0';
_at.read_string(response, sizeof(response));
_at.resp_stop();
if (strcmp(response, "SEND OK") != 0) {
return NSAPI_ERROR_DEVICE_ERROR;
}
} else {
const char *buf = (const char *)data;
nsapi_size_t blk = BG96_MAX_SEND_SIZE;
nsapi_size_t count = size;
while (count > 0) {
if (count < blk) {
blk = count;
}
if (socket->tls_socket) {
_at.cmd_start_stop("+QSSLSEND", "=", "%d%d", socket->id, blk);
}
else {
_at.cmd_start_stop("+QISEND", "=", "%d%d", socket->id, blk);
}
_at.resp_start(">");
_at.write_bytes((uint8_t *)buf, blk);
_at.resp_start();
_at.set_stop_tag("\r\n");
// Possible responses are SEND OK, SEND FAIL or ERROR.
char response[16];
response[0] = '\0';
_at.read_string(response, sizeof(response));
_at.resp_stop();
if (strcmp(response, "SEND OK") != 0) {
return NSAPI_ERROR_DEVICE_ERROR;
}
buf += blk;
count -= blk;
}
}
// Get the sent count after sending
nsapi_size_or_error_t err = NSAPI_ERROR_OK;
if (!socket->tls_socket) {
err = _at.at_cmd_int("+QISEND", "=", sent_len_after, "%d%d", socket->id, 0);
}
if (err == NSAPI_ERROR_OK) {
sent_len = sent_len_after - sent_len_before;
return sent_len;
}
return err;
}
nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size)
{
nsapi_size_or_error_t recv_len = 0;
int port = -1;
char ip_address[NSAPI_IP_SIZE + 1];
if (socket->proto == NSAPI_TCP) {
// do not read more than max size
size = size > BG96_MAX_RECV_SIZE ? BG96_MAX_RECV_SIZE : size;
if (socket->tls_socket) {
_at.cmd_start_stop("+QSSLRECV", "=", "%d%d", socket->id, size);
} else {
_at.cmd_start_stop("+QIRD", "=", "%d%d", socket->id, size);
}
} else {
_at.cmd_start_stop("+QIRD", "=", "%d", socket->id);
}
if (socket->tls_socket) {
_at.resp_start("+QSSLRECV:");
} else {
_at.resp_start("+QIRD:");
}
recv_len = _at.read_int();
if (recv_len > 0) {
// UDP has remote_IP and remote_port parameters
if (socket->proto == NSAPI_UDP) {
_at.read_string(ip_address, sizeof(ip_address));
port = _at.read_int();
}
// do not read more than buffer size
recv_len = recv_len > (nsapi_size_or_error_t)size ? size : recv_len;
_at.read_bytes((uint8_t *)buffer, recv_len);
}
_at.resp_stop();
// We block only if 0 recv length really means no data.
// If 0 is followed by ip address and port can be an UDP 0 length packet
if (!recv_len && port < 0) {
return NSAPI_ERROR_WOULD_BLOCK;
}
if (address) {
address->set_ip_address(ip_address);
address->set_port(port);
}
return recv_len;
}
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
nsapi_error_t QUECTEL_BG96_CellularStack::gethostbyname(const char *host, SocketAddress *address,
nsapi_version_t version, const char *interface_name)
{
(void) interface_name;
MBED_ASSERT(host);
MBED_ASSERT(address);
_at.lock();
if (_dns_callback) {
_at.unlock();
return NSAPI_ERROR_BUSY;
}
if (!address->set_ip_address(host)) {
_at.set_at_timeout(1min); // from BG96_TCP/IP_AT_Commands_Manual_V1.0
_at.at_cmd_discard("+QIDNSGIP", "=", "%d%s", _cid, host);
_at.resp_start("+QIURC: \"dnsgip\",");
_at.restore_at_timeout();
if (!read_dnsgip(*address, version)) {
_at.unlock();
return NSAPI_ERROR_DNS_FAILURE;
}
}
return _at.unlock_return_error();
}
nsapi_value_or_error_t QUECTEL_BG96_CellularStack::gethostbyname_async(const char *host, hostbyname_cb_t callback,
nsapi_version_t version, const char *interface_name)
{
(void) interface_name;
MBED_ASSERT(host);
MBED_ASSERT(callback);
_at.lock();
if (_dns_callback) {
_at.unlock();
return NSAPI_ERROR_BUSY;
}
_at.at_cmd_discard("+QIDNSGIP", "=", "%d%s", _cid, host);
if (!_at.get_last_error()) {
_dns_callback = callback;
_dns_version = version;
}
return _at.unlock_return_error() ? NSAPI_ERROR_DNS_FAILURE : BG96_ASYNC_DNS_QUERY_ID;
}
nsapi_error_t QUECTEL_BG96_CellularStack::gethostbyname_async_cancel(int id)
{
_at.lock();
_dns_callback = NULL;
_at.unlock();
return NSAPI_ERROR_OK;
}
#endif
void QUECTEL_BG96_CellularStack::ip2dot(const SocketAddress &ip, char *dot)
{
if (ip.get_ip_version() == NSAPI_IPv6) {
const uint8_t *bytes = (uint8_t *)ip.get_ip_bytes();
for (int i = 0; i < NSAPI_IPv6_BYTES; i += 2) {
if (i != 0) {
*dot++ = ':';
}
dot += sprintf(dot, "%x", (*(bytes + i) << 8 | *(bytes + i + 1)));
}
} else if (ip.get_ip_version() == NSAPI_IPv4) {
strcpy(dot, ip.get_ip_address());
} else {
*dot = '\0';
}
}
#if defined(MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET) && (MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET)
nsapi_error_t QUECTEL_BG96_CellularStack::set_to_modem_impl(const char *filename, const char *config, const char *data, size_t size)
{
// Delete old file from the modem.
_at.at_cmd_discard("+QFDEL", "=", "%s", filename);
_at.clear_error(); // Ignore error if file didn't exist
// Upload new file to modem
_at.cmd_start_stop("+QFUPL", "=", "%s%d", filename, size);
_at.resp_start("CONNECT");
_at.write_bytes((uint8_t *)data, size);
_at.resp_start("+QFUPL:");
size_t upload_size = _at.read_int();
_at.resp_stop();
if (upload_size != size) {
tr_error("Upload error! orig = %d, uploaded = %d", size, upload_size);
return NSAPI_ERROR_DEVICE_ERROR;
}
// Configure into use
_at.at_cmd_discard("+QSSLCFG", "=", "%s%d%s", config, sslctxID, filename);
return _at.get_last_error();
}
nsapi_error_t QUECTEL_BG96_CellularStack::setsockopt(nsapi_socket_t handle, int level,
int optname, const void *optval, unsigned optlen)
{
CellularSocket *socket = (CellularSocket *)handle;
nsapi_error_t ret = NSAPI_ERROR_OK;
if (level == NSAPI_TLSSOCKET_LEVEL) {
if (optval) {
_at.lock();
switch (optname) {
case NSAPI_TLSSOCKET_ENABLE: {
MBED_ASSERT(optlen == sizeof(bool));
bool *enabled = (bool *)optval;
if (socket->proto == NSAPI_TCP) {
socket->tls_socket = enabled;
if (enabled) {
_at.at_cmd_discard("+QSSLCFG", "=\"seclevel\",", "%d%d", sslctxID, _tls_sec_level);
_at.at_cmd_discard("+QSSLCFG", "=\"sslversion\",", "%d%d", sslctxID, BG96_SUPPORTED_SSL_VERSION);
_at.cmd_start("AT+QSSLCFG=\"ciphersuite\",");
_at.write_int(sslctxID);
_at.write_string(BG96_SUPPORTED_CIPHER_SUITE, false);
_at.cmd_stop_read_resp();
ret = _at.get_last_error();
}
} else {
tr_error("Trying to set non-TCPSocket as TLSSocket");
ret = NSAPI_ERROR_PARAMETER;
}
}
break;
case NSAPI_TLSSOCKET_SET_HOSTNAME: {
const char *hostname = (const char *)optval;
_at.at_cmd_discard("+QSSLCFG", "=\"checkhost\",", "%d%s", sslctxID, hostname);
ret = _at.get_last_error();
}
break;
case NSAPI_TLSSOCKET_SET_CACERT: {
const char *cacert = (const char *)optval;
ret = set_to_modem_impl("cacert.pem", "cacert", cacert, optlen);
// Set sec level to "Manage server authentication" if only cacert is in use
if (ret == NSAPI_ERROR_OK && _tls_sec_level == 0) {
_tls_sec_level = 1;
}
}
break;
case NSAPI_TLSSOCKET_SET_CLCERT: {
const char *clcert = (const char *)optval;
ret = set_to_modem_impl("clcert.pem", "clientcert", clcert, optlen);
// Set sec level to "Manage server and client authentication if requested by the remote server"
if (ret == NSAPI_ERROR_OK) {
_tls_sec_level = 2;
}
}
break;
case NSAPI_TLSSOCKET_SET_CLKEY: {
const char *clkey = (const char *)optval;
ret = set_to_modem_impl("client.key", "clientkey", clkey, optlen);
// Set sec level to "Manage server and client authentication if requested by the remote server"
if (ret == NSAPI_ERROR_OK) {
_tls_sec_level = 2;
}
}
break;
default:
tr_error("Unsupported sockopt (%d)", optname);
ret = NSAPI_ERROR_UNSUPPORTED;
}
_at.unlock();
} else {
tr_error("No optval!");
ret = NSAPI_ERROR_PARAMETER;
}
} else {
tr_warning("Unsupported level (%d)", level);
ret = NSAPI_ERROR_UNSUPPORTED;
}
return ret;
}
#endif

111
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_CellularStack.h
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@ -1,111 +0,0 @@
/*
* Copyright (c) 2017, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_CELLULARSTACK_H_
#define QUECTEL_BG96_CELLULARSTACK_H_
#include "AT_CellularStack.h"
namespace mbed {
#define BG96_CREATE_SOCKET_TIMEOUT 150s
#define BG96_CLOSE_SOCKET_TIMEOUT 20s // TCP socket max timeout is >10sec
#define BG96_MAX_RECV_SIZE 1500
#define BG96_MAX_SEND_SIZE 1460
#define BG96_SOCKET_BIND_FAIL 556
typedef enum {
URC_RECV,
URC_CLOSED,
} urc_type_t;
class QUECTEL_BG96_CellularStack : public AT_CellularStack {
public:
QUECTEL_BG96_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device);
virtual ~QUECTEL_BG96_CellularStack();
protected: // NetworkStack
virtual nsapi_error_t socket_listen(nsapi_socket_t handle, int backlog);
virtual nsapi_error_t socket_accept(nsapi_socket_t server,
nsapi_socket_t *handle, SocketAddress *address = 0);
virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address);
virtual nsapi_error_t get_ip_address(SocketAddress *address);
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
virtual nsapi_error_t gethostbyname(const char *host, SocketAddress *address, nsapi_version_t version, const char *interface_name);
virtual nsapi_value_or_error_t gethostbyname_async(const char *host, hostbyname_cb_t callback, nsapi_version_t version = NSAPI_UNSPEC,
const char *interface_name = NULL);
virtual nsapi_error_t gethostbyname_async_cancel(int id);
#endif
#if defined(MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET) && (MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET)
virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level,
int optname, const void *optval, unsigned optlen);
#endif
protected: // AT_CellularStack
virtual nsapi_error_t socket_close_impl(int sock_id);
virtual nsapi_error_t create_socket_impl(CellularSocket *socket);
virtual nsapi_size_or_error_t socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size);
virtual nsapi_size_or_error_t socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size);
private:
// URC handler
void urc_qiurc(urc_type_t urc_type);
// URC handler for socket data being received
void urc_qiurc_recv();
// URC handler for socket being closed
void urc_qiurc_closed();
void handle_open_socket_response(int &modem_connect_id, int &err, bool tlssocket);
#if defined(MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET) && (MBED_CONF_NSAPI_OFFLOAD_TLSSOCKET)
nsapi_error_t set_to_modem_impl(const char *filename, const char *config, const char *data, size_t size);
#endif
#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES
// URC handler for DNS query
void urc_qiurc_dnsgip();
// read DNS query result
bool read_dnsgip(SocketAddress &address, nsapi_version_t _dns_version);
hostbyname_cb_t _dns_callback;
nsapi_version_t _dns_version;
#endif
uint8_t _tls_sec_level;
/** Convert IP address to dotted string representation
*
* BG96 requires consecutive zeros so can't use get_ip_address or ip6tos directly.
*
* @param ip address
* @param dot buffer with size NSAPI_IPv6, where address is written zero terminated
*/
void ip2dot(const SocketAddress &ip, char *dot);
};
} // namespace mbed
#endif /* QUECTEL_BG96_CELLULARSTACK_H_ */

82
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_ControlPlane_netif.cpp
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@ -1,82 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "CellularUtil.h"
#include "QUECTEL_BG96_ControlPlane_netif.h"
#include "CellularLog.h"
using namespace mbed_cellular_util;
namespace mbed {
QUECTEL_BG96_ControlPlane_netif::QUECTEL_BG96_ControlPlane_netif(ATHandler &at, int cid, AT_CellularDevice &device) : AT_ControlPlane_netif(at, cid, device)
{}
nsapi_size_or_error_t QUECTEL_BG96_ControlPlane_netif::send(const void *data, nsapi_size_t size)
{
if (size > 100) { // from BG96_NIDD_AT_Commands_Manual_V1.0
return NSAPI_ERROR_PARAMETER;
}
_at.lock();
_at.cmd_start("AT+QCFGEXT=\"nipds\",1,");
_at.write_hex_string((const char *)data, size);
_at.write_int(2 * size);
_at.cmd_stop_read_resp();
nsapi_error_t err = _at.unlock_return_error();
return (err == NSAPI_ERROR_OK) ? size : err;
}
nsapi_size_or_error_t QUECTEL_BG96_ControlPlane_netif::recv(void *buffer, nsapi_size_t size)
{
_at.lock();
_at.cmd_start_stop("+QCFGEXT", "=", "%s%d", "nipdr", 0);
_at.resp_start("+QCFGEXT:");
// skip 3 params: "nipdr",<total_receive_length>,<have_read_length>
_at.skip_param(3);
// get to <unread_length>
int unread_length = _at.read_int();
_at.resp_stop();
if (!unread_length || unread_length == -1) {
_at.unlock();
return NSAPI_ERROR_WOULD_BLOCK;
}
if ((nsapi_size_t)unread_length > size) {
tr_warn("recv %d/%d", size, unread_length);
unread_length = size;
}
_at.cmd_start_stop("+QCFGEXT", "=", "%s%d%d", "nipdr", unread_length, 1);
_at.resp_start("+QCFGEXT:");
_at.skip_param(); // skip "nipdr"
nsapi_size_t read_length = _at.read_int();
ssize_t read_len = _at.read_hex_string((char *)buffer, read_length);
_at.resp_stop();
nsapi_error_t err = _at.unlock_return_error();
if (err == NSAPI_ERROR_OK && read_len) {
return read_len;
}
return NSAPI_ERROR_WOULD_BLOCK;
}
} // mbed namespace

36
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/QUECTEL_BG96_ControlPlane_netif.h
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@ -1,36 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_BG96_CONTROLPLANE_NETIF_H_
#define QUECTEL_BG96_CONTROLPLANE_NETIF_H_
#include "AT_ControlPlane_netif.h"
namespace mbed {
class QUECTEL_BG96_ControlPlane_netif: public AT_ControlPlane_netif {
public:
QUECTEL_BG96_ControlPlane_netif(ATHandler &at, int cid, AT_CellularDevice &device);
virtual ~QUECTEL_BG96_ControlPlane_netif() {};
// ControlPlane_netif
nsapi_size_or_error_t send(const void *data, nsapi_size_t size);
nsapi_size_or_error_t recv(void *buffer, nsapi_size_t size);
};
} /* namespace mbed */
#endif // QUECTEL_BG96_CONTROLPLANE_NETIF_H_

12
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/TARGET_WIO_BG96/CMakeLists.txt
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@ -1,12 +0,0 @@
# Copyright (c) 2024 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
ONBOARD_QUECTEL_BG96.cpp
)

120
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/TARGET_WIO_BG96/ONBOARD_QUECTEL_BG96.cpp
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@ -1,120 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if MBED_CONF_CELLULAR_PRESENT
#include "ONBOARD_QUECTEL_BG96.h"
#include "gpio_api.h"
#include "platform/mbed_thread.h"
#include "PinNames.h"
#include "drivers/BufferedSerial.h"
#define WAIT_AFTER_POWR_CHANGED (1000) // [msec.]
using namespace mbed;
ONBOARD_QUECTEL_BG96::ONBOARD_QUECTEL_BG96(FileHandle *fh) : QUECTEL_BG96(fh)
{
onboard_modem_init();
}
nsapi_error_t ONBOARD_QUECTEL_BG96::hard_power_on()
{
onboard_modem_init();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BG96::hard_power_off()
{
onboard_modem_deinit();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BG96::soft_power_on()
{
onboard_modem_power_up();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_BG96::soft_power_off()
{
onboard_modem_power_down();
return NSAPI_ERROR_OK;
}
void ONBOARD_QUECTEL_BG96::press_power_button(int time_ms)
{
gpio_t gpio;
gpio_init_out_ex(&gpio, PWRKEY, 1);
thread_sleep_for(time_ms);
gpio_write(&gpio, 0);
}
void ONBOARD_QUECTEL_BG96::onboard_modem_init()
{
gpio_t gpio;
// Power Supply
gpio_init_out_ex(&gpio, M_POWR, 0);
// Turn On/Off
gpio_init_out_ex(&gpio, PWRKEY, 0);
gpio_init_out_ex(&gpio, RESET_MODULE, 0);
// Status Indication
gpio_init_in_ex(&gpio, MDMSTAT, PullUp);
// Main UART Interface
gpio_init_out_ex(&gpio, MDMDTR, 0);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
}
void ONBOARD_QUECTEL_BG96::onboard_modem_deinit()
{
onboard_modem_power_down();
}
void ONBOARD_QUECTEL_BG96::onboard_modem_power_up()
{
gpio_t gpio;
// Power supply ON
gpio_init_out_ex(&gpio, M_POWR, 1);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
// Turn on
thread_sleep_for(100);
press_power_button(200);
}
void ONBOARD_QUECTEL_BG96::onboard_modem_power_down()
{
gpio_t gpio;
// Power supply OFF
gpio_init_out_ex(&gpio, M_POWR, 0);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
}
CellularDevice *CellularDevice::get_target_default_instance()
{
static BufferedSerial serial(MDMTXD, MDMRXD, 115200);
static ONBOARD_QUECTEL_BG96 device(&serial);
return &device;
}
#endif // MBED_CONF_CELLULAR_PRESENT

48
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/TARGET_WIO_BG96/ONBOARD_QUECTEL_BG96.h
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@ -1,48 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ONBOARD_QUECTEL_BG96_
#define ONBOARD_QUECTEL_BG96_
#include "QUECTEL_BG96.h"
namespace mbed {
class ONBOARD_QUECTEL_BG96 : public QUECTEL_BG96 {
public:
ONBOARD_QUECTEL_BG96(FileHandle *fh);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
private:
void press_power_button(int time_ms);
void onboard_modem_init();
void onboard_modem_deinit();
void onboard_modem_power_up();
void onboard_modem_power_down();
};
} // namespace mbed
#endif // ONBOARD_QUECTEL_BG96_

41
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_BG96/mbed_lib.json
View File

@ -1,41 +0,0 @@
{
"name": "QUECTEL_BG96",
"config": {
"tx": {
"help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rx": {
"help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rts": {
"help": "RTS pin for serial connection",
"value": null
},
"cts": {
"help": "CTS pin for serial connection",
"value": null
},
"pwr": {
"help": "Power control pin",
"value": null
},
"rst": {
"help": "Reset control pin",
"value": null
},
"polarity": {
"help": "Pin polarity, 1 = Active high, 0 = Active low",
"value": null
},
"baudrate" : {
"help": "Serial connection baud rate",
"value": 115200
},
"provide-default": {
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
}
}

16
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/CMakeLists.txt
View File

@ -1,16 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
QUECTEL_EC2X.cpp
)
if("MTS_DRAGONFLY_L496VG" IN_LIST MBED_TARGET_LABELS)
add_subdirectory(TARGET_MTS_DRAGONFLY_L496VG)
endif()

156
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/QUECTEL_EC2X.cpp
View File

@ -1,156 +0,0 @@
/*
* Copyright (c) 2019, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_EC2X.h"
#include "PinNames.h"
#include "AT_CellularNetwork.h"
#include "rtos/ThisThread.h"
#include "drivers/BufferedSerial.h"
using namespace std::chrono;
using namespace mbed;
using namespace rtos;
using namespace events;
#if !defined(MBED_CONF_QUECTEL_EC2X_PWR)
#define MBED_CONF_QUECTEL_EC2X_PWR NC
#endif
#if !defined(MBED_CONF_QUECTEL_EC2X_RST)
#define MBED_CONF_QUECTEL_EC2X_RST NC
#endif
#if !defined(MBED_CONF_QUECTEL_EC2X_TX)
#define MBED_CONF_QUECTEL_EC2X_TX NC
#endif
#if !defined(MBED_CONF_QUECTEL_EC2X_RX)
#define MBED_CONF_QUECTEL_EC2X_RX NC
#endif
#if !defined(MBED_CONF_QUECTEL_EC2X_POLARITY)
#define MBED_CONF_QUECTEL_EC2X_POLARITY 1 // active high
#endif
#if !defined(MBED_CONF_QUECTEL_EC2X_START_TIMEOUT)
#define MBED_CONF_QUECTEL_EC2X_START_TIMEOUT 15000
#endif
static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = {
AT_CellularNetwork::RegistrationModeLAC, // C_EREG
AT_CellularNetwork::RegistrationModeLAC, // C_GREG
AT_CellularNetwork::RegistrationModeLAC, // C_REG
0, // AT_CGSN_WITH_TYPE
1, // AT_CGDATA
0, // AT_CGAUTH
1, // AT_CNMI
1, // AT_CSMP
1, // AT_CMGF
1, // AT_CSDH
1, // PROPERTY_IPV4_STACK
1, // PROPERTY_IPV6_STACK
1, // PROPERTY_IPV4V6_STACK
0, // PROPERTY_NON_IP_PDP_TYPE
1, // PROPERTY_AT_CGEREP,
1, // PROPERTY_AT_COPS_FALLBACK_AUTO
0, // PROPERTY_SOCKET_COUNT
0, // PROPERTY_IP_TCP
0, // PROPERTY_IP_UDP
0, // PROPERTY_AT_SEND_DELAY
};
QUECTEL_EC2X::QUECTEL_EC2X(FileHandle *fh, PinName pwr, bool active_high, PinName rst)
: AT_CellularDevice(fh),
_active_high(active_high),
_pwr_key(pwr, !_active_high),
_rst(rst, !_active_high)
{
set_cellular_properties(cellular_properties);
}
#if MBED_CONF_QUECTEL_EC2X_PROVIDE_DEFAULT
CellularDevice *CellularDevice::get_default_instance()
{
static BufferedSerial serial(MBED_CONF_QUECTEL_EC2X_TX,
MBED_CONF_QUECTEL_EC2X_RX,
MBED_CONF_QUECTEL_EC2X_BAUDRATE);
#if defined(MBED_CONF_QUECTEL_EC2X_RTS) && defined(MBED_CONF_QUECTEL_EC2X_CTS)
serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_QUECTEL_EC2X_RTS, MBED_CONF_QUECTEL_EC2X_CTS);
#endif
static QUECTEL_EC2X device(&serial,
MBED_CONF_QUECTEL_EC2X_PWR,
MBED_CONF_QUECTEL_EC2X_POLARITY,
MBED_CONF_QUECTEL_EC2X_RST);
return &device;
}
#endif
nsapi_error_t QUECTEL_EC2X::press_power_button(duration<uint32_t, std::milli> timeout)
{
if (_pwr_key.is_connected()) {
_pwr_key = _active_high;
ThisThread::sleep_for(timeout);
_pwr_key = !_active_high;
ThisThread::sleep_for(100ms);
}
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_EC2X::hard_power_on()
{
return press_power_button(600ms);
}
nsapi_error_t QUECTEL_EC2X::hard_power_off()
{
return press_power_button(750ms);
}
nsapi_error_t QUECTEL_EC2X::soft_power_on()
{
if (_rst.is_connected()) {
_rst = _active_high;
ThisThread::sleep_for(460ms);
_rst = !_active_high;
ThisThread::sleep_for(100ms);
_at.lock();
_at.set_at_timeout(milliseconds(MBED_CONF_QUECTEL_EC2X_START_TIMEOUT));
_at.resp_start();
_at.set_stop_tag("RDY");
bool rdy = _at.consume_to_stop_tag();
_at.set_stop_tag(OK);
_at.unlock();
if (!rdy) {
return NSAPI_ERROR_DEVICE_ERROR;
}
}
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_EC2X::soft_power_off()
{
return hard_power_off();
}

51
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/QUECTEL_EC2X.h
View File

@ -1,51 +0,0 @@
/*
* Copyright (c) 2019, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_EC2X_H
#define QUECTEL_EC2X_H
#include <chrono>
#include "DigitalOut.h"
#include "AT_CellularDevice.h"
namespace mbed {
class QUECTEL_EC2X : public AT_CellularDevice {
public:
/**
* Constructs the Quectel EC2X series driver. It is mandatory to provide
* a FileHandle object, the power pin and the polarity of the pin.
* Providing reset pin is optional.
*/
QUECTEL_EC2X(FileHandle *fh, PinName pwr, bool active_high, PinName rst = NC);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
private:
nsapi_error_t press_power_button(std::chrono::duration<uint32_t, std::milli> timeout);
bool _active_high;
DigitalOut _pwr_key;
DigitalOut _rst;
};
} // namespace mbed
#endif // QUECTEL_EC2X_H

12
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/TARGET_MTS_DRAGONFLY_L496VG/CMakeLists.txt
View File

@ -1,12 +0,0 @@
# Copyright (c) 2024 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
ONBOARD_QUECTEL_EG25.cpp
)

220
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.cpp
View File

@ -1,220 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if MBED_CONF_NSAPI_PRESENT
#include "QUECTEL_EC2X.h"
#include "ONBOARD_QUECTEL_EG25.h"
#include "gpio_api.h"
#include "platform/mbed_thread.h"
#include "PinNames.h"
#include "drivers/BufferedSerial.h"
#include "CellularLog.h"
#include "mbed_wait_api.h"
using namespace mbed;
ONBOARD_QUECTEL_EG25::ONBOARD_QUECTEL_EG25(FileHandle *fh, PinName pwr, bool active_high, PinName rst) : QUECTEL_EC2X(fh, pwr, active_high, rst)
{
initialized = 0;
ls = new DigitalOut(LS_LED);
net_status = new InterruptIn(NET_STATUS);
}
nsapi_error_t ONBOARD_QUECTEL_EG25::hard_power_on()
{
onboard_modem_init();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_EG25::hard_power_off()
{
onboard_modem_deinit();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_EG25::soft_power_on()
{
// See base function description. This function is for power on but reset too.
onboard_modem_power_down();
onboard_modem_power_up();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_EG25::soft_power_off()
{
onboard_modem_power_down();
return NSAPI_ERROR_OK;
}
CellularDevice *CellularDevice::get_target_default_instance()
{
static BufferedSerial serial(MDMTXD, MDMRXD, 115200);
#if DEVICE_SERIAL_FC
if (MDMRTS != NC && MDMCTS != NC) {
tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS);
serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS);
}
#endif
static ONBOARD_QUECTEL_EG25 device(&serial, MDMPWRON, 0, MDMRST);
return &device;
}
void ONBOARD_QUECTEL_EG25::press_power_button(int time_us)
{
gpio_t gpio;
gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrainNoPull, 0);
wait_us(time_us);
gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
}
void ONBOARD_QUECTEL_EG25::onboard_modem_init()
{
// PWRKEY/RADIO_ONOFF = output open drain
// RADIO_PWR = Enables the regulator. High = on. Has pulldown on board.
// RADIO_RESET/MDMRST = Reset the radio. Open drain or float.
// RADIO_STATUS/STATUS = input with pull up. Gets driven low when radio is on.
gpio_t gpio;
// Enable radio power regulator and buffer, configure RESET_N and PWR_ON.
gpio_init_inout(&gpio, RADIO_PWR, PIN_OUTPUT, PushPullNoPull, 1);
gpio_init_inout(&gpio, BUF_EN, PIN_OUTPUT, OpenDrainNoPull, 0);
// MDMRST and MDMPWRON get driven low via open drain.
gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
gpio_init_in_ex(&gpio, RADIO_STATUS, PullUp);
// Quectel hardware design guide recommends >= 30ms from powered until
// PWRKEY(MDMPWRON) is pulled low.
wait_us(40000);
initialized = 1;
}
void ONBOARD_QUECTEL_EG25::onboard_modem_deinit()
{
// Make sure to power down before removing power!
onboard_modem_power_down();
gpio_t gpio;
// Set all to inputs no pull. Let pull resistors do their thing. Allows
// for lowest power draw. Disable radio power regulator and buffer.
gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
gpio_init_inout(&gpio, BUF_EN, PIN_INPUT, PullNone, 1);
gpio_init_inout(&gpio, RADIO_PWR, PIN_INPUT, PullNone, 0);
initialized = 0;
}
void ONBOARD_QUECTEL_EG25::link_status()
{
ls->write(net_status->read());
}
void ONBOARD_QUECTEL_EG25::onboard_modem_power_up()
{
// NET_STATUS = input. InterruptIn make LS LED follow.
// LS_LED = output. Follow NET_STATUS.
net_status->rise(callback(this, &ONBOARD_QUECTEL_EG25::link_status));
net_status->fall(callback(this, &ONBOARD_QUECTEL_EG25::link_status));
// Make sure the radio is initialized so it can be powered on.
if (!initialized) {
onboard_modem_init();
}
gpio_t status;
gpio_init_in_ex(&status, RADIO_STATUS, PullUp);
int radio_off = gpio_read(&status);
// If radio is on, do nothing.
if (!radio_off) {
return;
}
// Activate PWRKEY at least 500ms to turn on.
press_power_button(550000);
// Wait 10s for status to go low before retrying.
uint8_t timeout = 10;
do {
thread_sleep_for(1000);
radio_off = gpio_read(&status);
if (!timeout--) {
press_power_button(550000);
timeout = 10;
}
} while (radio_off);
_at.lock();
_at.set_at_timeout(15000);
_at.resp_start();
_at.set_stop_tag("RDY");
bool rdy = _at.consume_to_stop_tag();
_at.set_stop_tag(OK);
_at.unlock();
if (rdy) {
tr_debug("Radio outputted RDY");
} else {
tr_debug("Radio did not output RDY within 15s.");
}
}
void ONBOARD_QUECTEL_EG25::onboard_modem_power_down()
{
gpio_t status;
gpio_init_in_ex(&status, RADIO_STATUS, PullUp);
// Need volatile so status check is not optimized out.
volatile int radio_off = gpio_read(&status);
// Do nothing if it's already off.
if (radio_off) {
return;
}
// Make sure the I/O are properly initialized.
if (!initialized) {
onboard_modem_init();
}
do {
// Activate PWRKEY for at least 650ms to turn off.
press_power_button(680000);
// Wait 40s for status to go high before resetting.
uint8_t timeout = 40;
do {
thread_sleep_for(1000);
radio_off = gpio_read(&status);
} while (!radio_off && timeout);
if (radio_off) {
break;
} else {
onboard_modem_reset();
}
} while (!radio_off);
}
void ONBOARD_QUECTEL_EG25::onboard_modem_reset()
{
gpio_t gpio;
gpio_init_inout(&gpio, MDMRST, PIN_OUTPUT, OpenDrainNoPull, 0);
thread_sleep_for(500);
gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
thread_sleep_for(100);
}
#endif // MBED_CONF_NSAPI_PRESENT

49
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.h
View File

@ -1,49 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ONBOARD_QUECTEL_EG25_H
#define ONBOARD_QUECTEL_EG25_H
#include "QUECTEL_EC2X.h"
namespace mbed {
class ONBOARD_QUECTEL_EG25 : public QUECTEL_EC2X {
public:
ONBOARD_QUECTEL_EG25(FileHandle *fh, PinName pwr, bool active_high, PinName rst);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
private:
uint8_t initialized;
DigitalOut *ls;
InterruptIn *net_status;
void link_status();
void press_power_button(int time_ms);
void onboard_modem_init();
void onboard_modem_deinit();
void onboard_modem_power_up();
void onboard_modem_power_down();
void onboard_modem_reset();
};
} // namespace mbed
#endif // ONBOARD_QUECTEL_EG25_H

45
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_EC2X/mbed_lib.json
View File

@ -1,45 +0,0 @@
{
"name": "QUECTEL_EC2X",
"config": {
"tx": {
"help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rx": {
"help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rts": {
"help": "RTS pin for serial connection",
"value": null
},
"cts": {
"help": "CTS pin for serial connection",
"value": null
},
"pwr": {
"help": "Power control pin",
"value": null
},
"rst": {
"help": "Reset control pin",
"value": null
},
"polarity": {
"help": "Pin polarity, 1 = Active high, 0 = Active low",
"value": null
},
"baudrate" : {
"help": "Serial connection baud rate",
"value": 115200
},
"start-timeout": {
"help": "How long to wait for modem to start after reset (milliseconds)",
"value": 15000
},
"provide-default": {
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
}
}

15
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/CMakeLists.txt
View File

@ -1,15 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
QUECTEL_M26.cpp
QUECTEL_M26_CellularContext.cpp
QUECTEL_M26_CellularInformation.cpp
QUECTEL_M26_CellularStack.cpp
)

108
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26.cpp
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@ -1,108 +0,0 @@
/*
#include <M26/QUECTEL_M26_CellularInformation.h>
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "AT_CellularNetwork.h"
#include "QUECTEL_M26_CellularContext.h"
#include "QUECTEL_M26.h"
#include "CellularLog.h"
using namespace mbed;
static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = {
AT_CellularNetwork::RegistrationModeDisable,// C_EREG
AT_CellularNetwork::RegistrationModeLAC, // C_GREG
AT_CellularNetwork::RegistrationModeDisable,// C_REG
0, // AT_CGSN_WITH_TYPE
1, // AT_CGDATA
0, // AT_CGAUTH
1, // AT_CNMI
1, // AT_CSMP
1, // AT_CMGF
1, // AT_CSDH
1, // PROPERTY_IPV4_STACK
0, // PROPERTY_IPV6_STACK
0, // PROPERTY_IPV4V6_STACK
0, // PROPERTY_NON_IP_PDP_TYPE
1, // PROPERTY_AT_CGEREP
1, // PROPERTY_AT_COPS_FALLBACK_AUTO
6, // PROPERTY_SOCKET_COUNT
1, // PROPERTY_IP_TCP
1, // PROPERTY_IP_UDP
0, // PROPERTY_AT_SEND_DELAY
};
QUECTEL_M26::QUECTEL_M26(FileHandle *fh) : AT_CellularDevice(fh)
{
set_cellular_properties(cellular_properties);
}
nsapi_error_t QUECTEL_M26::get_sim_state(SimState &state)
{
char buf[13];
_at.lock();
nsapi_error_t err = _at.at_cmd_str("+CPIN", "?", buf, 13);
tr_debug("CPIN: %s", buf);
_at.unlock();
if (memcmp(buf, "READY", 5) == 0) {
state = SimStateReady;
} else if (memcmp(buf, "SIM PIN", 7) == 0) {
state = SimStatePinNeeded;
} else if (memcmp(buf, "SIM PUK", 7) == 0) {
state = SimStatePukNeeded;
} else if (memcmp(buf, "PH_SIM PIN", 10) == 0) {
state = SimStatePinNeeded;
} else if (memcmp(buf, "PH_SIM PUK", 10) == 0) {
state = SimStatePukNeeded;
} else if (memcmp(buf, "SIM PIN2", 8) == 0) {
state = SimStatePinNeeded;
} else if (memcmp(buf, "SIM PUK2", 8) == 0) {
state = SimStatePukNeeded;
} else {
state = SimStateUnknown; // SIM may not be ready yet
}
return err;
}
AT_CellularContext *QUECTEL_M26::create_context_impl(ATHandler &at, const char *apn, bool cp_req, bool nonip_req)
{
return new QUECTEL_M26_CellularContext(at, this, apn, cp_req, nonip_req);
}
nsapi_error_t QUECTEL_M26::shutdown()
{
return _at.at_cmd_discard("+QPOWD", "=0");
}
#if MBED_CONF_QUECTEL_M26_PROVIDE_DEFAULT
#include "drivers/BufferedSerial.h"
CellularDevice *CellularDevice::get_default_instance()
{
static BufferedSerial serial(MBED_CONF_QUECTEL_M26_TX, MBED_CONF_QUECTEL_M26_RX, MBED_CONF_QUECTEL_M26_BAUDRATE);
#if defined (MBED_CONF_QUECTEL_M26_RTS) && defined(MBED_CONF_QUECTEL_M26_CTS)
tr_debug("QUECTEL_M26 flow control: RTS %d CTS %d", MBED_CONF_QUECTEL_M26_RTS, MBED_CONF_QUECTEL_M26_CTS);
serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_QUECTEL_M26_RTS, MBED_CONF_QUECTEL_M26_CTS);
#endif
static QUECTEL_M26 device(&serial);
return &device;
}
#endif

48
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26.h
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@ -1,48 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_M26_H_
#define QUECTEL_M26_H_
#ifdef TARGET_FF_ARDUINO
#ifndef MBED_CONF_QUECTEL_M26_TX
#define MBED_CONF_QUECTEL_M26_TX D1
#endif
#ifndef MBED_CONF_QUECTEL_M26_RX
#define MBED_CONF_QUECTEL_M26_RX D0
#endif
#endif /* TARGET_FF_ARDUINO */
#include "AT_CellularDevice.h"
namespace mbed {
class QUECTEL_M26 : public AT_CellularDevice {
public:
QUECTEL_M26(FileHandle *fh);
protected: // AT_CellularDevice
virtual nsapi_error_t get_sim_state(SimState &state);
virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual nsapi_error_t shutdown();
public: // NetworkInterface
void handle_urc(FileHandle *fh);
};
} // namespace mbed
#endif // QUECTEL_M26_H_

56
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularContext.cpp
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@ -1,56 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_M26_CellularContext.h"
#include "QUECTEL_M26_CellularStack.h"
namespace mbed {
QUECTEL_M26_CellularContext::QUECTEL_M26_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) :
AT_CellularContext(at, device, apn, cp_req, nonip_req)
{
}
#if !NSAPI_PPP_AVAILABLE
NetworkStack *QUECTEL_M26_CellularContext::get_stack()
{
if (!_stack) {
_stack = new QUECTEL_M26_CellularStack(_at, _cid, (nsapi_ip_stack_t)_pdp_type, *get_device());
if (static_cast<QUECTEL_M26_CellularStack *>(_stack)->socket_stack_init() != NSAPI_ERROR_OK) {
delete _stack;
_stack = NULL;
}
}
return _stack;
}
#endif // #if !NSAPI_PPP_AVAILABLE
nsapi_error_t QUECTEL_M26_CellularContext::do_user_authentication()
{
nsapi_error_t err = NSAPI_ERROR_OK;
if (_pwd && _uname) {
err = _at.at_cmd_discard("^SISO", "=", "%d%s%s%s", 1, _apn, _uname, _pwd);
} else {
err = _at.at_cmd_discard("^SISO", "=", "%d%s", 1, _apn);
}
if (err != NSAPI_ERROR_OK) {
return NSAPI_ERROR_AUTH_FAILURE;
}
return err;
}
} /* namespace mbed */

37
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularContext.h
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@ -1,37 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_M26_CELLULARCONTEXT_H_
#define QUECTEL_M26_CELLULARCONTEXT_H_
#include "AT_CellularContext.h"
namespace mbed {
class QUECTEL_M26_CellularContext: public AT_CellularContext {
public:
QUECTEL_M26_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false);
protected:
#if !NSAPI_PPP_AVAILABLE
virtual NetworkStack *get_stack();
#endif // #if !NSAPI_PPP_AVAILABLE
virtual nsapi_error_t do_user_authentication();
};
} /* namespace mbed */
#endif // QUECTEL_M26_CELLULARCONTEXT_H_

31
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularInformation.cpp
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@ -1,31 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_M26_CellularInformation.h"
using namespace mbed;
QUECTEL_M26_CellularInformation::QUECTEL_M26_CellularInformation(ATHandler &atHandler, AT_CellularDevice &device) : AT_CellularInformation(atHandler, device)
{
}
// According to M26_AT_Commands_Manual_V1.9
nsapi_error_t QUECTEL_M26_CellularInformation::get_iccid(char *buf, size_t buf_size)
{
return _at.at_cmd_str("+CCID", "", buf, buf_size);
}

35
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularInformation.h
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@ -1,35 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_M26_CELLULAR_INFORMATION_H_
#define QUECTEL_M26_CELLULAR_INFORMATION_H_
#include "AT_CellularInformation.h"
namespace mbed {
class QUECTEL_M26_CellularInformation : public AT_CellularInformation {
public:
QUECTEL_M26_CellularInformation(ATHandler &atHandler, AT_CellularDevice &device);
public: //from CellularInformation
virtual nsapi_error_t get_iccid(char *buf, size_t buf_size);
};
} // namespace mbed
#endif // QUECTEL_M26_CELLULAR_INFORMATION_H_

538
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularStack.cpp
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@ -1,538 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtos/Kernel.h"
#include "QUECTEL/M26/QUECTEL_M26_CellularStack.h"
#include "CellularLog.h"
using namespace std::chrono;
#define SOCKET_SEND_READY_TIMEOUT 30s
#define SOCKET_READ_TIMEOUT 1s
using namespace mbed;
QUECTEL_M26_CellularStack::QUECTEL_M26_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device) :
AT_CellularStack(atHandler, cid, stack_type, device)
{
_at.set_urc_handler("+QIRDI:", Callback<void()>(this, &QUECTEL_M26_CellularStack::urc_qiurc));
_at.set_urc_handler("0, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_0));
_at.set_urc_handler("1, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_1));
_at.set_urc_handler("2, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_2));
_at.set_urc_handler("3, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_3));
_at.set_urc_handler("4, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_4));
_at.set_urc_handler("5, CLOSED", Callback<void()>(this, &QUECTEL_M26_CellularStack::socket_closed_5));
}
QUECTEL_M26_CellularStack::~QUECTEL_M26_CellularStack()
{
_at.set_urc_handler("5, CLOSED", nullptr);
_at.set_urc_handler("4, CLOSED", nullptr);
_at.set_urc_handler("3, CLOSED", nullptr);
_at.set_urc_handler("2, CLOSED", nullptr);
_at.set_urc_handler("1, CLOSED", nullptr);
_at.set_urc_handler("0, CLOSED", nullptr);
_at.set_urc_handler("+QIRDI:", nullptr);
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_listen(nsapi_socket_t handle, int backlog)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_accept(void *server, void **socket, SocketAddress *addr)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_bind(nsapi_socket_t handle, const SocketAddress &addr)
{
return NSAPI_ERROR_UNSUPPORTED;
}
void QUECTEL_M26_CellularStack::socket_closed(int sock_id)
{
CellularSocket *sock = find_socket(sock_id);
if (sock) {
tr_info("Socket closed %d", sock_id);
sock->closed = true;
}
}
void QUECTEL_M26_CellularStack::socket_closed_0()
{
socket_closed(0);
}
void QUECTEL_M26_CellularStack::socket_closed_1()
{
socket_closed(1);
}
void QUECTEL_M26_CellularStack::socket_closed_2()
{
socket_closed(2);
}
void QUECTEL_M26_CellularStack::socket_closed_3()
{
socket_closed(3);
}
void QUECTEL_M26_CellularStack::socket_closed_4()
{
socket_closed(4);
}
void QUECTEL_M26_CellularStack::socket_closed_5()
{
socket_closed(5);
}
void QUECTEL_M26_CellularStack::urc_qiurc()
{
int sock_id = 0;
_at.lock();
(void) _at.skip_param(); /*<id> AT+QIFGCNT*/
(void) _at.skip_param(); /*<sc> 1 Client, 2 Server*/
sock_id = _at.read_int();
(void) _at.skip_param(); /*<num>*/
(void) _at.skip_param(); /*<len>*/
(void) _at.skip_param(); /*<tlen>*/
_at.unlock();
for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) {
CellularSocket *sock = _socket[i];
if (sock && sock->id == sock_id) {
if (sock->_cb) {
sock->_cb(sock->_data);
}
break;
}
}
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_stack_init()
{
int tcpip_mode = 1;
int mux_mode = 0;
int cache_mode = 0;
nsapi_error_t ret_val;
tr_debug("QUECTEL_M26_CellularStack:%s:%u: START ", __FUNCTION__, __LINE__);
_at.lock();
/*AT+QIFGCNT=0*/
_at.at_cmd_discard("+QIFGCNT", "=", "%d", 0);
ret_val = _at.get_last_error();
if (ret_val != NSAPI_ERROR_OK) {
_at.unlock();
return NSAPI_ERROR_DEVICE_ERROR;
}
#if 0
if (_pwd && _uname) {
_at.at_cmd_discard("+QICSGP", "=", "%d%s%s%s", 1, _apn, _uname, _pwd);
} else {
_at.at_cmd_discard("+QICSGP", "=", "%d%s", 1, _apn);
}
#endif
ret_val = _at.get_last_error();
if (ret_val != NSAPI_ERROR_OK) {
_at.unlock();
return NSAPI_ERROR_DEVICE_ERROR;
}
/*AT+QIMODE=0 Set transparent mode*/
_at.cmd_start_stop("+QIMODE", "?");
_at.resp_start("+QIMODE:");
if (_at.info_resp()) {
tcpip_mode = _at.read_int();
}
_at.resp_stop();
if (tcpip_mode) {
_at.at_cmd_discard("+QIMODE", "=", "%d", 0);
}
ret_val = _at.get_last_error();
if (ret_val != NSAPI_ERROR_OK) {
_at.unlock();
return NSAPI_ERROR_DEVICE_ERROR;
}
/*AT+QIMUX=1*/
_at.cmd_start_stop("+QIMUX", "?");
_at.resp_start("+QIMUX:");
if (_at.info_resp()) {
mux_mode = _at.read_int();
}
_at.resp_stop();
if (!mux_mode) {
_at.at_cmd_discard("+QIMUX", "=", "%d", 1);
}
ret_val = _at.get_last_error();
if (ret_val != NSAPI_ERROR_OK) {
_at.unlock();
return NSAPI_ERROR_DEVICE_ERROR;
}
/*AT+QINDI=2*/
_at.cmd_start_stop("+QINDI", "?");
_at.resp_start();
if (_at.info_resp()) {
cache_mode = _at.read_int();
}
_at.resp_stop();
if (cache_mode != 2) {
_at.at_cmd_discard("+QINDI", "=", "%d", 2);
}
ret_val = _at.get_last_error();
if (ret_val != NSAPI_ERROR_OK) {
_at.unlock();
return NSAPI_ERROR_DEVICE_ERROR;
}
_at.unlock();
tr_debug("QUECTEL_M26_CellularStack:%s:%u: SUCCESS ", __FUNCTION__, __LINE__);
return NSAPI_ERROR_OK;
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_close_impl(int sock_id)
{
tr_debug("QUECTEL_M26_CellularStack:%s:%u:", __FUNCTION__, __LINE__);
return _at.at_cmd_discard("+QICLOSE", "=", "%d", sock_id);
}
void QUECTEL_M26_CellularStack::handle_open_socket_response(int &modem_connect_id, int &err)
{
char status[15];
tr_debug("QUECTEL_M26_CellularStack:%s:%u: START", __FUNCTION__, __LINE__);
_at.resp_start("ALREADY CONNECT");
if (_at.info_resp()) {
/* ALREADY CONNECT: The request socket already connected */
err = 0;
return;
}
_at.resp_stop();
if (_at.get_last_error() != NSAPI_ERROR_OK) {
/* ERROR: The command format error */
err = 1;
return;
}
tr_debug("QUECTEL_M26_CellularStack:%s:%u: OK", __FUNCTION__, __LINE__);
_at.set_at_timeout(M26_CREATE_SOCKET_TIMEOUT);
_at.resp_start();
_at.set_stop_tag("\r\n");
modem_connect_id = _at.read_int();
_at.read_string(status, sizeof(status), true);
_at.resp_stop();
_at.restore_at_timeout();
if ((!strcmp(status, "CONNECT FAIL")) || (_at.get_last_error() != NSAPI_ERROR_OK)) {
err = 1;
return;
}
err = 0;
tr_debug("QUECTEL_M26_CellularStack:%s:%u: END [%s, %d]", __FUNCTION__, __LINE__, status, err);
}
nsapi_error_t QUECTEL_M26_CellularStack::socket_connect(nsapi_socket_t handle, const SocketAddress &address)
{
CellularSocket *socket = (CellularSocket *)handle;
int modem_connect_id = -1;
int err = -1;
int request_connect_id = find_socket_index(socket);
// assert here as its a programming error if the socket container doesn't contain
// specified handle
MBED_ASSERT(request_connect_id != -1);
_at.lock();
if (socket->proto == NSAPI_TCP) {
_at.cmd_start_stop("+QIOPEN", "=", "%d%s%s%d", request_connect_id, "TCP",
address.get_ip_address(), address.get_port());;
handle_open_socket_response(modem_connect_id, err);
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
_at.at_cmd_discard("+QICLOSE", "=", "%d", modem_connect_id);
_at.cmd_start_stop("+QIOPEN", "=", "%d%s%s%d", request_connect_id, "TCP",
address.get_ip_address(), address.get_port());
handle_open_socket_response(modem_connect_id, err);
}
}
// If opened successfully BUT not requested one, close it
if (!err && (modem_connect_id != request_connect_id)) {
_at.at_cmd_discard("+QICLOSE", "=", "%d", modem_connect_id);
}
nsapi_error_t ret_val = _at.get_last_error();
_at.unlock();
if ((ret_val == NSAPI_ERROR_OK) && (modem_connect_id == request_connect_id)) {
socket->remoteAddress = address;
socket->connected = true;
return NSAPI_ERROR_OK;
}
return NSAPI_ERROR_NO_CONNECTION;
}
nsapi_error_t QUECTEL_M26_CellularStack::create_socket_impl(CellularSocket *socket)
{
// This modem is a special case. It takes in the socket ID rather than spitting
// it out. So we will first try to use the index of the socket construct as the id
// but if another opened socket is already opened with that id we will pick the next
// id which is not in use
bool duplicate = false;
int potential_sid = -1;
int index = find_socket_index(socket);
for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) {
CellularSocket *sock = _socket[i];
if (sock && sock != socket && sock->id == index) {
duplicate = true;
} else if (duplicate && !sock) {
potential_sid = i;
break;
}
}
if (duplicate) {
index = potential_sid;
}
int request_connect_id = index;
int modem_connect_id = request_connect_id;
int err = -1;
nsapi_error_t ret_val;
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[%d,%d]", __FUNCTION__, __LINE__, socket->proto, socket->connected);
if (socket->connected) {
_at.cmd_start_stop("+QIOPEN", "=", "%d%s%s%d", request_connect_id, (socket->proto == NSAPI_TCP) ? "TCP" : "UDP",
socket->remoteAddress.get_ip_address(), socket->remoteAddress.get_port());
handle_open_socket_response(modem_connect_id, err);
/* Close and retry if socket create fail */
if ((_at.get_last_error() != NSAPI_ERROR_OK) || err) {
_at.at_cmd_discard("+QICLOSE", "=", "%d", modem_connect_id);
_at.cmd_start_stop("+QIOPEN", "=", "%d%s%s%d", request_connect_id, (socket->proto == NSAPI_TCP) ? "TCP" : "UDP",
socket->remoteAddress.get_ip_address(), socket->remoteAddress.get_port());
handle_open_socket_response(modem_connect_id, err);
}
/* If opened successfully BUT not requested one, close it */
if (!err && (modem_connect_id != request_connect_id)) {
_at.at_cmd_discard("+QICLOSE", "=", "%d", modem_connect_id);
}
ret_val = _at.get_last_error();
if ((ret_val == NSAPI_ERROR_OK) && (modem_connect_id == request_connect_id)) {
socket->id = request_connect_id;
}
return ret_val;
} else {
ret_val = NSAPI_ERROR_OK;
}
tr_debug("QUECTEL_M26_CellularStack:%s:%u: END [%d]", __FUNCTION__, __LINE__, ret_val);
return ret_val;
}
nsapi_size_or_error_t QUECTEL_M26_CellularStack::socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size)
{
int sent_len = size;
int sent_acked = 0;
int sent_nacked = 0;
int sent_len_before = 0;
int sent_len_after = 0;
nsapi_error_t error;
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[%d-%d]", __FUNCTION__, __LINE__, sent_len, size);
if (sent_len == 0 || size > M26_SENT_BYTE_MAX) {
tr_error("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_PARAMETER]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_PARAMETER;
}
if (socket->id == -1) {
socket->remoteAddress = address;
socket->connected = true;
nsapi_error_t ret_val = create_socket_impl(socket);
if ((ret_val != NSAPI_ERROR_OK) || (socket->id == -1)) {
tr_error("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_NO_SOCKET]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_NO_SOCKET;
}
}
if (socket->proto == NSAPI_TCP) {
bool ready_to_send = false;
auto start_time = rtos::Kernel::Clock::now() ;
while (!ready_to_send && rtos::Kernel::Clock::now() < start_time + SOCKET_SEND_READY_TIMEOUT) {
_at.cmd_start_stop("+QISACK", "=", "%d", socket->id);
_at.resp_start("+QISACK:");
sent_len_before = _at.read_int();
sent_acked = _at.read_int();
(void)sent_acked;
sent_nacked = _at.read_int();
_at.resp_stop();
if (_at.get_last_error() != NSAPI_ERROR_OK) {
tr_error("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_DEVICE_ERROR]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_DEVICE_ERROR;
}
if (sent_nacked == 0) {
ready_to_send = true;
} else {
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_WOULD_BLOCK]", __FUNCTION__, __LINE__);
}
}
}
_at.cmd_start_stop("+QISEND", "=", "%d%d", socket->id, sent_len);
_at.resp_start(">");
_at.write_bytes((uint8_t *)data, sent_len);
_at.resp_start();
_at.set_stop_tag("\r\n");
// Possible responses are SEND OK, SEND FAIL or ERROR.
char response[16];
response[0] = '\0';
_at.read_string(response, sizeof(response));
_at.resp_stop();
if (strcmp(response, "SEND OK") != 0) {
return NSAPI_ERROR_DEVICE_ERROR;
}
if (_at.get_last_error() != NSAPI_ERROR_OK) {
tr_error("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_DEVICE_ERROR]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_DEVICE_ERROR;
}
if (socket->proto == NSAPI_TCP) {
_at.cmd_start_stop("+QISACK", "=", "%d", socket->id);
_at.resp_start("+QISACK:");
sent_len_after = _at.read_int();
sent_acked = _at.read_int();
(void)sent_acked; // avoid compile warning, used only for debugging
sent_nacked = _at.read_int();
_at.resp_stop();
error = _at.get_last_error();
if (error == NSAPI_ERROR_OK) {
sent_len = sent_len_after - sent_len_before;
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[TCP: BA %d-%d, ACK %d-%d,LEN %d-%d]", __FUNCTION__, __LINE__, sent_len_before, sent_len_after, sent_acked, sent_nacked, sent_len, size);
return sent_len;
}
tr_error("QUECTEL_M26_CellularStack:%s:%u:[TCP: %d]", __FUNCTION__, __LINE__, error);
return error;
}
error = _at.get_last_error();
if (error == NSAPI_ERROR_OK) {
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[UDP: %d]", __FUNCTION__, __LINE__, sent_len);
return sent_len;
}
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[ERROR: %d]", __FUNCTION__, __LINE__, error);
return error;
}
nsapi_size_or_error_t QUECTEL_M26_CellularStack::socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size)
{
int port;
char type[8];
char ip_address[NSAPI_IP_SIZE + 1];
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[%d]", __FUNCTION__, __LINE__, size);
auto start_time = rtos::Kernel::Clock::now();
nsapi_size_t len = 0;
for (; len < size;) {
unsigned int read_len = (size - len > M26_RECV_BYTE_MAX) ? M26_RECV_BYTE_MAX : size - len;
_at.cmd_start_stop("+QIRD", "=", "%d%d%d%d", 0, 1, socket->id, read_len);
nsapi_size_t recv_len = 0;
_at.resp_start("+QIRD:");
if (_at.info_resp()) {
_at.set_delimiter(':');
_at.read_string(ip_address, sizeof(ip_address));
_at.set_default_delimiter();
port = _at.read_int();
_at.read_string(type, sizeof(type));
recv_len = _at.read_int();
_at.read_bytes((uint8_t *)buffer + len, recv_len);
len += recv_len;
}
_at.resp_stop();
if (_at.get_last_error() != NSAPI_ERROR_OK) {
tr_warn("QUECTEL_M26_CellularStack:%s:%u:[ERROR NSAPI_ERROR_OK]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_DEVICE_ERROR;
}
if (rtos::Kernel::Clock::now() > start_time + SOCKET_READ_TIMEOUT) {
tr_warn("QUECTEL_M26_CellularStack:%s:%u:[ERROR NSAPI_ERROR_TIMEOUT]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_TIMEOUT;
}
if (recv_len == 0 || recv_len < read_len) {
break;
}
}
if (len == 0) {
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[ERROR NSAPI_ERROR_WOULD_BLOCK]", __FUNCTION__, __LINE__);
return NSAPI_ERROR_WOULD_BLOCK;
}
if (address) {
address->set_ip_address(ip_address);
address->set_port(port);
}
tr_debug("QUECTEL_M26_CellularStack:%s:%u:[%d]", __FUNCTION__, __LINE__, len);
return len;
}

79
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/QUECTEL_M26_CellularStack.h
View File

@ -1,79 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_M26_CELLULARSTACK_H_
#define QUECTEL_M26_CELLULARSTACK_H_
#include "AT_CellularStack.h"
using namespace std::chrono_literals;
namespace mbed {
#define M26_CREATE_SOCKET_TIMEOUT 75s
#define M26_SENT_BYTE_MAX 1460
#define M26_RECV_BYTE_MAX 1024
class QUECTEL_M26_CellularStack : public AT_CellularStack {
public:
QUECTEL_M26_CellularStack(ATHandler &atHandler, int cid, nsapi_ip_stack_t stack_type, AT_CellularDevice &device);
virtual ~QUECTEL_M26_CellularStack();
/** Initialize
* Must be called immediately after constructor to initialize IP stack on the modem.
* @return NSAPI_ERROR_OK on success
*/
nsapi_error_t socket_stack_init();
protected: // NetworkStack
virtual nsapi_error_t socket_listen(nsapi_socket_t handle, int backlog);
virtual nsapi_error_t socket_accept(nsapi_socket_t server,
nsapi_socket_t *handle, SocketAddress *address = 0);
virtual nsapi_error_t socket_bind(nsapi_socket_t handle, const SocketAddress &address);
virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address);
protected: // AT_CellularStack
virtual nsapi_error_t socket_close_impl(int sock_id);
virtual nsapi_error_t create_socket_impl(CellularSocket *socket);
virtual nsapi_size_or_error_t socket_sendto_impl(CellularSocket *socket, const SocketAddress &address,
const void *data, nsapi_size_t size);
virtual nsapi_size_or_error_t socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address,
void *buffer, nsapi_size_t size);
private:
// URC handlers
void urc_qiurc();
void socket_closed(int sock_id);
void socket_closed_0();
void socket_closed_1();
void socket_closed_2();
void socket_closed_3();
void socket_closed_4();
void socket_closed_5();
void handle_open_socket_response(int &modem_connect_id, int &err);
};
} // namespace mbed
#endif /* QUECTEL_M26_CELLULARSTACK_H_ */

29
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_M26/mbed_lib.json
View File

@ -1,29 +0,0 @@
{
"name": "QUECTEL_M26",
"config": {
"tx": {
"help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rx": {
"help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rts": {
"help": "RTS pin for serial connection",
"value": null
},
"cts": {
"help": "CTS pin for serial connection",
"value": null
},
"baudrate" : {
"help": "Serial connection baud rate",
"value": 115200
},
"provide-default": {
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
}
}

17
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/CMakeLists.txt
View File

@ -1,17 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
QUECTEL_UG96.cpp
QUECTEL_UG96_CellularContext.cpp
)
if("TARGET_WIO_3G" IN_LIST MBED_TARGET_LABELS)
add_subdirectory(TARGET_WIO_3G)
endif()

75
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/QUECTEL_UG96.cpp
View File

@ -1,75 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_UG96.h"
#include "QUECTEL_UG96_CellularContext.h"
#include "AT_CellularNetwork.h"
using namespace mbed;
using namespace events;
#define CONNECT_DELIM "\r\n"
#define CONNECT_BUFFER_SIZE (1280 + 80 + 80) // AT response + sscanf format
#define CONNECT_TIMEOUT 8000
static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = {
AT_CellularNetwork::RegistrationModeDisable,// C_EREG
AT_CellularNetwork::RegistrationModeLAC, // C_GREG
AT_CellularNetwork::RegistrationModeLAC, // C_REG
1, // AT_CGSN_WITH_TYPE
1, // AT_CGDATA
1, // AT_CGAUTH
1, // AT_CNMI
1, // AT_CSMP
1, // AT_CMGF
1, // AT_CSDH
1, // PROPERTY_IPV4_STACK
0, // PROPERTY_IPV6_STACK
0, // PROPERTY_IPV4V6_STACK
0, // PROPERTY_NON_IP_PDP_TYPE
1, // PROPERTY_AT_CGEREP,
1, // PROPERTY_AT_COPS_FALLBACK_AUTO
0, // PROPERTY_SOCKET_COUNT
0, // PROPERTY_IP_TCP
0, // PROPERTY_IP_UDP
0, // PROPERTY_AT_SEND_DELAY
};
QUECTEL_UG96::QUECTEL_UG96(FileHandle *fh) : AT_CellularDevice(fh)
{
set_cellular_properties(cellular_properties);
}
AT_CellularContext *QUECTEL_UG96::create_context_impl(ATHandler &at, const char *apn, bool cp_req, bool nonip_req)
{
return new QUECTEL_UG96_CellularContext(at, this, apn, cp_req, nonip_req);
}
#if MBED_CONF_QUECTEL_UG96_PROVIDE_DEFAULT
#include "drivers/BufferedSerial.h"
CellularDevice *CellularDevice::get_default_instance()
{
static BufferedSerial serial(MBED_CONF_QUECTEL_UG96_TX, MBED_CONF_QUECTEL_UG96_RX, MBED_CONF_QUECTEL_UG96_BAUDRATE);
#if defined (MBED_CONF_QUECTEL_UG96_RTS) && defined (MBED_CONF_QUECTEL_UG96_CTS)
tr_debug("QUECTEL_UG96 flow control: RTS %d CTS %d", MBED_CONF_QUECTEL_UG96_RTS, MBED_CONF_QUECTEL_UG96_CTS);
serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_QUECTEL_UG96_RTS, MBED_CONF_QUECTEL_UG96_CTS);
#endif
static QUECTEL_UG96 device(&serial);
return &device;
}
#endif

54
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/QUECTEL_UG96.h
View File

@ -1,54 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_UG96_H_
#define QUECTEL_UG96_H_
#ifdef TARGET_FF_ARDUINO
#ifndef MBED_CONF_QUECTEL_UG96_TX
#define MBED_CONF_QUECTEL_UG96_TX D1
#endif
#ifndef MBED_CONF_QUECTEL_UG96_RX
#define MBED_CONF_QUECTEL_UG96_RX D0
#endif
#endif /* TARGET_FF_ARDUINO */
#include "AT_CellularDevice.h"
namespace mbed {
#ifdef TARGET_WIO_3G
#define CELLULAR_SERIAL_TX PA_2
#define CELLULAR_SERIAL_RX PA_3
#else
#define CELLULAR_SERIAL_TX PC_1
#define CELLULAR_SERIAL_RX PC_0
#endif
class QUECTEL_UG96 : public AT_CellularDevice {
public:
QUECTEL_UG96(FileHandle *fh);
protected: // AT_CellularDevice
virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false);
public: // NetworkInterface
void handle_urc(FileHandle *fh);
};
} // namespace mbed
#endif // QUECTEL_UG96_H_

44
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/QUECTEL_UG96_CellularContext.cpp
View File

@ -1,44 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "QUECTEL_UG96_CellularContext.h"
namespace mbed {
QUECTEL_UG96_CellularContext::QUECTEL_UG96_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) :
AT_CellularContext(at, device, apn, cp_req, nonip_req)
{
}
QUECTEL_UG96_CellularContext::~QUECTEL_UG96_CellularContext()
{
}
nsapi_error_t QUECTEL_UG96_CellularContext::do_user_authentication()
{
nsapi_error_t err = NSAPI_ERROR_OK;
if (_pwd && _uname) {
err = _at.at_cmd_discard("+QICSGP", "=", "%d%d%s%s%s%d", _cid, 1, _apn,
_uname, _pwd, _authentication_type);
if (err != NSAPI_ERROR_OK) {
return NSAPI_ERROR_AUTH_FAILURE;
}
}
return err;
}
} /* namespace mbed */

35
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/QUECTEL_UG96_CellularContext.h
View File

@ -1,35 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef QUECTEL_UG96_CELLULARCONTEXT_H_
#define QUECTEL_UG96_CELLULARCONTEXT_H_
#include "AT_CellularContext.h"
namespace mbed {
class QUECTEL_UG96_CellularContext: public AT_CellularContext {
public:
QUECTEL_UG96_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false);
virtual ~QUECTEL_UG96_CellularContext();
protected:
virtual nsapi_error_t do_user_authentication();
};
} /* namespace mbed */
#endif // QUECTEL_UG96_CELLULARCONTEXT_H_

12
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/TARGET_WIO_3G/CMakeLists.txt
View File

@ -1,12 +0,0 @@
# Copyright (c) 2024 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
target_include_directories(mbed-cellular
PUBLIC
.
)
target_sources(mbed-cellular
PRIVATE
ONBOARD_QUECTEL_UG96.cpp
)

124
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/TARGET_WIO_3G/ONBOARD_QUECTEL_UG96.cpp
View File

@ -1,124 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if MBED_CONF_NSAPI_PRESENT
#include "ONBOARD_QUECTEL_UG96.h"
#include "gpio_api.h"
#include "platform/mbed_thread.h"
#include "PinNames.h"
#include "drivers/BufferedSerial.h"
#define WAIT_AFTER_POWR_CHANGED (1000) // [msec.]
using namespace mbed;
ONBOARD_QUECTEL_UG96::ONBOARD_QUECTEL_UG96(FileHandle *fh) : QUECTEL_UG96(fh)
{
onboard_modem_init();
}
nsapi_error_t ONBOARD_QUECTEL_UG96::hard_power_on()
{
onboard_modem_init();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_UG96::hard_power_off()
{
onboard_modem_deinit();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_UG96::soft_power_on()
{
onboard_modem_power_up();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_QUECTEL_UG96::soft_power_off()
{
onboard_modem_power_down();
return NSAPI_ERROR_OK;
}
void ONBOARD_QUECTEL_UG96::press_power_button(int time_ms)
{
gpio_t gpio;
gpio_init_out_ex(&gpio, PWRKEY, 1);
thread_sleep_for(time_ms);
gpio_write(&gpio, 0);
}
void ONBOARD_QUECTEL_UG96::onboard_modem_init()
{
gpio_t gpio;
// Power Supply
gpio_init_out_ex(&gpio, M_POWR, 0);
// Turn On/Off
gpio_init_out_ex(&gpio, PWRKEY, 0);
gpio_init_out_ex(&gpio, RESET_MODULE, 0);
// Status Indication
gpio_init_in_ex(&gpio, MDMSTAT, PullUp);
// Main UART Interface
gpio_init_out_ex(&gpio, MDMDTR, 0);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
}
void ONBOARD_QUECTEL_UG96::onboard_modem_deinit()
{
gpio_t gpio;
// Power supply OFF
gpio_init_out_ex(&gpio, M_POWR, 0);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
}
void ONBOARD_QUECTEL_UG96::onboard_modem_power_up()
{
gpio_t gpio;
// Power supply ON
gpio_init_out_ex(&gpio, M_POWR, 1);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
// Turn on
thread_sleep_for(100);
press_power_button(200);
}
void ONBOARD_QUECTEL_UG96::onboard_modem_power_down()
{
gpio_t gpio;
// Power supply OFF
gpio_init_out_ex(&gpio, M_POWR, 0);
thread_sleep_for(WAIT_AFTER_POWR_CHANGED);
}
CellularDevice *CellularDevice::get_target_default_instance()
{
static BufferedSerial serial(MDMTXD, MDMRXD, 115200);
static ONBOARD_QUECTEL_UG96 device(&serial);
return &device;
}
#endif // MBED_CONF_NSAPI_PRESENT

48
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/TARGET_WIO_3G/ONBOARD_QUECTEL_UG96.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ONBOARD_QUECTEL_UG96_
#define ONBOARD_QUECTEL_UG96_
#include "QUECTEL_UG96.h"
namespace mbed {
class ONBOARD_QUECTEL_UG96 : public QUECTEL_UG96 {
public:
ONBOARD_QUECTEL_UG96(FileHandle *fh);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
private:
void press_power_button(int time_ms);
void onboard_modem_init();
void onboard_modem_deinit();
void onboard_modem_power_up();
void onboard_modem_power_down();
};
} // namespace mbed
#endif // ONBOARD_QUECTEL_UG96_

29
connectivity/drivers/cellular/QUECTEL/COMPONENT_QUECTEL_UG96/mbed_lib.json
View File

@ -1,29 +0,0 @@
{
"name": "QUECTEL_UG96",
"config": {
"tx": {
"help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rx": {
"help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.",
"value": null
},
"rts": {
"help": "RTS pin for serial connection",
"value": null
},
"cts": {
"help": "CTS pin for serial connection",
"value": null
},
"baudrate" : {
"help": "Serial connection baud rate",
"value": 115200
},
"provide-default": {
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
}
}

4
connectivity/netsocket/tests/TESTS/netsocket/nidd/main.cpp
View File

@ -51,11 +51,7 @@ void drop_bad_packets(CellularNonIPSocket &sock, int orig_timeout)
bool check_oversized_packets(nsapi_error_t error, int &size)
{
if (error == NSAPI_ERROR_PARAMETER) {
#if MBED_CONF_QUECTEL_BG96_PROVIDE_DEFAULT
size = 100; // see BG96 driver
#else
size = 1280; // see TS 23.060 for MTU recommendations
#endif
return true;
}
return false;

1
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/CMakeLists.txt
View File

@ -2,7 +2,6 @@
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_DISCO_F413ZH EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MTS_DRAGONFLY_F413RH EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_NUCLEO_F413ZH EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/CMakeLists.txt
View File

@ -1,16 +0,0 @@
# Copyright (c) 2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-mts-dragonfly-f413rh INTERFACE)
target_sources(mbed-mts-dragonfly-f413rh
INTERFACE
PeripheralPins.c
)
target_include_directories(mbed-mts-dragonfly-f413rh
INTERFACE
.
)
target_link_libraries(mbed-mts-dragonfly-f413rh INTERFACE mbed-stm32f413xh)

289
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralPins.c
View File

@ -1,289 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
//==============================================================================
// Notes
//
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
// HW peripheral instances. You can use them the same way as any other "normal"
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
// pinout image on mbed.org.
//
// - The pins which are connected to other components present on the board have
// the comment "Connected to xxx". The pin function may not work properly in this
// case. These pins may not be displayed on the board pinout image on mbed.org.
// Please read the board reference manual and schematic for more information.
//
// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
//
//==============================================================================
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
{NC, NC, 0}
};
//*** DAC ***
MBED_WEAK const PinMap PinMap_DAC[] = {
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
{PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
{PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
{NC, NC, 0}
};
//*** PWM ***
// TIM5 cannot be used because already used by the us_ticker
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
{PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
{PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
{PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
{PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
{PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
//*** CAN ***
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
{PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
{PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
{PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
{PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
{PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{NC, NC, 0}
};
//*** QUADSPI ***
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
{NC, NC, 0}
};

224
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PinNames.h
View File

@ -1,224 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: MTS_DRAGONFLY_F413RH */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
// Not connected
NC = -1,
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PC_0 = 0x20,
PC_1 = 0x21,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_7 = 0x27,
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_2 = 0x32,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
// Arduino connector namings
ARDUINO_UNO_A0 = PC_2,
ARDUINO_UNO_A1 = PC_0,
ARDUINO_UNO_A2 = PC_4,
ARDUINO_UNO_A3 = PB_0,
ARDUINO_UNO_A4 = PC_1,
ARDUINO_UNO_A5 = PC_9,
ARDUINO_UNO_D0 = PA_3,
ARDUINO_UNO_D1 = PA_2,
ARDUINO_UNO_D2 = PB_15,
ARDUINO_UNO_D3 = PA_0,
ARDUINO_UNO_D4 = PA_7,
ARDUINO_UNO_D5 = PA_9,
ARDUINO_UNO_D6 = PA_1,
ARDUINO_UNO_D7 = PA_8,
ARDUINO_UNO_D8 = PB_1,
ARDUINO_UNO_D9 = PB_13,
ARDUINO_UNO_D10 = PC_8,
ARDUINO_UNO_D11 = PB_5,
ARDUINO_UNO_D12 = PA_6,
ARDUINO_UNO_D13 = PA_5,
ARDUINO_UNO_D14 = PB_9,
ARDUINO_UNO_D15 = PB_8,
// Generic signals namings
LED_RED = PA_0,
SERIAL_TX = ARDUINO_UNO_D1,
SERIAL_RX = ARDUINO_UNO_D0,
SERIAL_RTS = ARDUINO_UNO_D3,
SERIAL_CTS = ARDUINO_UNO_D6,
SERIAL_DCD = ARDUINO_UNO_D4,
SERIAL_DSR = ARDUINO_UNO_D5,
SERIAL_DTR = ARDUINO_UNO_D7,
SERIAL_RI = ARDUINO_UNO_D8,
// STDIO for console print
#if defined(MBED_CONF_TARGET_STDIO_UART_TX)
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
CONSOLE_TX = PB_6,
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART_RX)
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
CONSOLE_RX = PB_7,
#endif
RADIO_TX = PC_6,
RADIO_RX = PC_7,
RADIO_RTS = PB_10,
RADIO_CTS = PB_12,
RADIO_DCD = NC,
RADIO_DSR = NC,
RADIO_DTR = NC,
RADIO_RI = NC,
MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16
MDMTXD = RADIO_TX, // Transmit Data
MDMRXD = RADIO_RX, // Receive Data
MDMRTS = RADIO_RTS, // Request to Send
MDMCTS = RADIO_CTS, // Clear to Send
MDMDCD = RADIO_DCD, // Data Carrier Detect
MDMDSR = RADIO_DSR, // Data Set Ready
MDMDTR = RADIO_DTR, // Data Terminal Ready
MDMRI = RADIO_RI, // Ring Indicator
WAKEUP = ARDUINO_UNO_D3,
// I2C1 and I2C3 are available on Arduino pins
I2C1_SCL = ARDUINO_UNO_D15,
I2C1_SDA = ARDUINO_UNO_D14,
I2C3_SCL = ARDUINO_UNO_D7,
I2C3_SDA = ARDUINO_UNO_A5,
// legacy definitions
// SPI1 and SPI2 are available on Arduino pins
SPI1_MOSI = ARDUINO_UNO_D11,
SPI1_MISO = ARDUINO_UNO_D12,
SPI1_SCK = ARDUINO_UNO_D13,
SPI2_MOSI = ARDUINO_UNO_D2,
SPI2_MISO = ARDUINO_UNO_A0,
SPI2_SCK = ARDUINO_UNO_D9,
// SPI3 connects to flash part
SPI3_MOSI = PC_12,
SPI3_MISO = PC_11,
SPI3_SCK = PC_10,
// legacy definitions
SPI_CS1 = PA_4,
SPI_CS2 = PB_14,
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
USB_OTG_FS_SOF = PA_8,
USB_OTG_FS_VBUS = PA_9
} PinName;
// Standardized LED and button names
#define LED1 ARDUINO_UNO_D3
#define LED_RED LED1
#define ACTIVE_HIGH_POLARITY 1
#define ACTIVE_LOW_POLARITY 0
#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY
#ifdef __cplusplus
}
#endif
#endif

2
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/CMakeLists.txt
View File

@ -2,8 +2,6 @@
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_NUCLEO_F439ZI EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_WIO_3G EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_WIO_BG96 EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S)

16
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/CMakeLists.txt
View File

@ -1,16 +0,0 @@
# Copyright (c) 2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-wio-3g INTERFACE)
target_sources(mbed-wio-3g
INTERFACE
PeripheralPins.c
)
target_include_directories(mbed-wio-3g
INTERFACE
.
)
target_link_libraries(mbed-wio-3g INTERFACE mbed-stm32f439xi)

350
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c
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@ -1,350 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause-Clear
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
// =====
// Note: Commented lines are alternative possibilities which are not used per default.
// If you change them, you will have also to modify the corresponding xxx_api.c file
// for pwmout, analogin, analogout, ...
// =====
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
// {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
// {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
// {PA_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // A4(GROVE)
// {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // A4(GROVE)
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // A5(GROVE)
// {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // A5(GROVE)
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // A6(GROVE)
// {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // A6(GROVE)
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // A7(GROVE)
// {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // A7(GROVE)
// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // BAT_C
// {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // BAT_C
// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PB_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)},
// {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)},
// {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)},
// {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)},
// {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
{NC, NC, 0}
};
//*** DAC ***
MBED_WEAK const PinMap PinMap_DAC[] = {
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // A4(GROVE)
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // A5(GROVE)
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // I2C1_SDA(GROVE)
// {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
// {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
// {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
// {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // I2C1_SCL(GROVE)
// {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
// {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
//*** PWM ***
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (TIM5 used by us_ticker)
// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 (pin used by ethernet)
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (TIM5 used by us_ticker) (pin used by ethernet)
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 (pin used by ethernet)
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (TIM5 used by us_ticker)
// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 (pin used by ethernet)
// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - ARDUINO A0
{PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (TIM5 used by us_ticker) - ARDUINO A0
// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - ARDUINO A0
// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO D13
{PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO D13
// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D12
{PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (pin used by usb)
// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (pin used by usb)
// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 (pin used by usb)
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED1)
// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 (pin used by LED1)
// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED1)
// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates)
// HW solder bridge update : SB121 off, SB122 on
// SW : config from json files
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2)
// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D15
{PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D14
// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D14
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP7 ON)
// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 (pin used by LED3)
// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED3)
// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED3)
{PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
{PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
{PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
{PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D10
{PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D9
{PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
{PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
{PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - ARDUINO D6
{PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - ARDUINO D5
{PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - ARDUINO D3
{PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
{PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
{PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
{PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
{PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
// {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_TX(RXD_MODULE)
// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // USART1_TX(GROVE)
// {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D38(GROVE)
// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
// {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // DB_TX(DAPLink)
// {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
// {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
// {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_RX(TXD_MODULE)
// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // USART1_RX(GROVE)
// {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D39(GROVE)
// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
// {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // DB_RX(DAPLink)
// {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
// {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_RTS(CTS_MODULE)
// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
// {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_CTS(RTS_MODULE)
// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
// {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A7(GROVE)
// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_MOSI
// {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A6(GROVE)
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D20(GROVE)
// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_MISO
// {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A5(GROVE)
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D19(GROVE)
// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_SCK
// {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A4(GROVE)
// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // I2C1_SDA(GROVE)
// {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
// {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
// {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};

233
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h
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@ -1,233 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause-Clear
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: WIO_3G */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PC_0 = 0x20,
PC_1 = 0x21,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_7 = 0x27,
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_0 = 0x30,
PD_1 = 0x31,
PD_2 = 0x32,
PD_3 = 0x33,
PD_4 = 0x34,
PD_5 = 0x35,
PD_6 = 0x36,
PD_7 = 0x37,
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_11 = 0x3B,
PD_12 = 0x3C,
PD_13 = 0x3D,
PD_14 = 0x3E,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_2 = 0x42,
PE_3 = 0x43,
PE_4 = 0x44,
PE_5 = 0x45,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
PE_12 = 0x4C,
PE_13 = 0x4D,
PE_14 = 0x4E,
PE_15 = 0x4F,
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
PF_6 = 0x56,
PF_7 = 0x57,
PF_8 = 0x58,
PF_9 = 0x59,
PF_10 = 0x5A,
PF_11 = 0x5B,
PF_12 = 0x5C,
PF_13 = 0x5D,
PF_14 = 0x5E,
PF_15 = 0x5F,
PG_0 = 0x60,
PG_1 = 0x61,
PG_2 = 0x62,
PG_3 = 0x63,
PG_4 = 0x64,
PG_5 = 0x65,
PG_6 = 0x66,
PG_7 = 0x67,
PG_8 = 0x68,
PG_9 = 0x69,
PG_10 = 0x6A,
PG_11 = 0x6B,
PG_12 = 0x6C,
PG_13 = 0x6D,
PG_14 = 0x6E,
PG_15 = 0x6F,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
D38 = PC_6,
D39 = PC_7,
D20 = PB_4,
D19 = PB_3,
A6 = PA_6,
A7 = PA_7,
A4 = PA_4,
A5 = PA_5,
RXD = PB_7,
TXD = PB_6,
// STDIO for console print
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
CONSOLE_TX = PD_8,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
CONSOLE_RX = PD_9,
#endif
// Quectel UG96 cellular modem
MDMTXD = PA_2,
MDMRXD = PA_3,
MDMCTS = PA_0,
MDMRTS = PA_1,
MDMSTAT = PB_15,
MDMDTR = PC_5,
M_POWR = PE_9,
// Internal control signals
RGB_POWR = PE_8,
GRO_POWR = PB_10,
PWRKEY = PB_5,
RESET_MODULE = PD_5,
// Standardized button names
SPI_MOSI = PC_12,
SPI_MISO = PC_11,
SPI_SCK = PC_10,
SPI_CS = PD_0,
PWM_OUT = D39,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
// Standardized LED and button names
#define LED1 PB_11
#define LED_RED LED1
#define BUTTON1 PC_13
#ifdef __cplusplus
}
#endif
#endif

17
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_BG96/CMakeLists.txt
View File

@ -1,17 +0,0 @@
# Copyright (c) 2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-wio-bg96 INTERFACE)
target_sources(mbed-wio-bg96
INTERFACE
PeripheralPins.c
ONBOARD_QUECTEL_BG96.cpp
)
target_include_directories(mbed-wio-bg96
INTERFACE
.
)
target_link_libraries(mbed-wio-bg96 INTERFACE mbed-stm32f439xi)

350
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_BG96/PeripheralPins.c
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@ -1,350 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause-Clear
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
// =====
// Note: Commented lines are alternative possibilities which are not used per default.
// If you change them, you will have also to modify the corresponding xxx_api.c file
// for pwmout, analogin, analogout, ...
// =====
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
// {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
// {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
// {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
// {PA_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // A4(GROVE)
// {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // A4(GROVE)
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // A5(GROVE)
// {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // A5(GROVE)
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // A6(GROVE)
// {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // A6(GROVE)
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // A7(GROVE)
// {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // A7(GROVE)
// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // BAT_C
// {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // BAT_C
// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PB_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
// {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
// {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
// {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)},
// {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)},
// {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)},
// {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)},
// {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
{NC, NC, 0}
};
//*** DAC ***
MBED_WEAK const PinMap PinMap_DAC[] = {
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // A4(GROVE)
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // A5(GROVE)
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // I2C1_SDA(GROVE)
// {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
// {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
// {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
// {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // I2C1_SCL(GROVE)
// {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
// {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
//*** PWM ***
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (TIM5 used by us_ticker)
// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 (pin used by ethernet)
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (TIM5 used by us_ticker) (pin used by ethernet)
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 (pin used by ethernet)
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (TIM5 used by us_ticker)
// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 (pin used by ethernet)
// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - ARDUINO A0
{PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (TIM5 used by us_ticker) - ARDUINO A0
// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - ARDUINO A0
// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO D13
{PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO D13
// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D12
{PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (pin used by usb)
// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (pin used by usb)
// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 (pin used by usb)
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED1)
// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 (pin used by LED1)
// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED1)
// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates)
// HW solder bridge update : SB121 off, SB122 on
// SW : config from json files
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2)
// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D15
{PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D14
// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D14
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP7 ON)
// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 (pin used by LED3)
// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED3)
// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED3)
{PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
{PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
{PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
{PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D10
{PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D9
{PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
{PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
{PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - ARDUINO D6
{PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - ARDUINO D5
{PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - ARDUINO D3
{PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
{PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
{PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
{PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
{PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
// {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_TX(RXD_MODULE)
// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // USART1_TX(GROVE)
// {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D38(GROVE)
// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
// {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // DB_TX(DAPLink)
// {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
// {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
// {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_RX(TXD_MODULE)
// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // USART1_RX(GROVE)
// {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D39(GROVE)
// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
// {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // DB_RX(DAPLink)
// {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
// {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
// {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_RTS(CTS_MODULE)
// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
// {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // USART2_CTS(RTS_MODULE)
// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
// {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
// {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A7(GROVE)
// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_MOSI
// {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A6(GROVE)
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D20(GROVE)
// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_MISO
// {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A5(GROVE)
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D19(GROVE)
// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // SD_SCK
// {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // A4(GROVE)
// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // I2C1_SDA(GROVE)
// {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
// {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
// {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
// {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
// {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
// {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
// {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};

231
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_BG96/PinNames.h
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@ -1,231 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause-Clear
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: WIO_BG96 */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PC_0 = 0x20,
PC_1 = 0x21,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_7 = 0x27,
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_0 = 0x30,
PD_1 = 0x31,
PD_2 = 0x32,
PD_3 = 0x33,
PD_4 = 0x34,
PD_5 = 0x35,
PD_6 = 0x36,
PD_7 = 0x37,
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_11 = 0x3B,
PD_12 = 0x3C,
PD_13 = 0x3D,
PD_14 = 0x3E,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_2 = 0x42,
PE_3 = 0x43,
PE_4 = 0x44,
PE_5 = 0x45,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
PE_12 = 0x4C,
PE_13 = 0x4D,
PE_14 = 0x4E,
PE_15 = 0x4F,
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
PF_6 = 0x56,
PF_7 = 0x57,
PF_8 = 0x58,
PF_9 = 0x59,
PF_10 = 0x5A,
PF_11 = 0x5B,
PF_12 = 0x5C,
PF_13 = 0x5D,
PF_14 = 0x5E,
PF_15 = 0x5F,
PG_0 = 0x60,
PG_1 = 0x61,
PG_2 = 0x62,
PG_3 = 0x63,
PG_4 = 0x64,
PG_5 = 0x65,
PG_6 = 0x66,
PG_7 = 0x67,
PG_8 = 0x68,
PG_9 = 0x69,
PG_10 = 0x6A,
PG_11 = 0x6B,
PG_12 = 0x6C,
PG_13 = 0x6D,
PG_14 = 0x6E,
PG_15 = 0x6F,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
D38 = PC_6,
D39 = PC_7,
D20 = PB_4,
D19 = PB_3,
A6 = PA_6,
A7 = PA_7,
A4 = PA_4,
A5 = PA_5,
RXD = PB_7,
TXD = PB_6,
// STDIO for console print
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
CONSOLE_TX = PD_8,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
CONSOLE_RX = PD_9,
#endif
// Quectel UG96 cellular modem
MDMTXD = PA_2,
MDMRXD = PA_3,
MDMCTS = PA_0,
MDMRTS = PA_1,
MDMSTAT = PB_15,
MDMDTR = PC_5,
M_POWR = PE_9,
// Internal control signals
RGB_POWR = PE_8,
GRO_POWR = PB_10,
PWRKEY = PB_5,
RESET_MODULE = PD_5,
SPI_MOSI = PC_12,
SPI_MISO = PC_11,
SPI_SCK = PC_10,
SPI_CS = PD_0,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
// Standardized LED and button names
#define LED1 PB_11
#define LED_RED LED1
#define BUTTON1 PC_13
#ifdef __cplusplus
}
#endif
#endif

1
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/CMakeLists.txt
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@ -3,7 +3,6 @@
add_subdirectory(TARGET_DISCO_L476VG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_NUCLEO_L476RG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_RHOMBIO_L476DMW1K EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S)

16
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/CMakeLists.txt
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@ -1,16 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-rhombio-l476dmw1k INTERFACE)
target_sources(mbed-rhombio-l476dmw1k
INTERFACE
PeripheralPins.c
)
target_include_directories(mbed-rhombio-l476dmw1k
INTERFACE
.
)
target_link_libraries(mbed-rhombio-l476dmw1k INTERFACE mbed-stm32l476xg)

382
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c
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@ -1,382 +0,0 @@
/* mbed Microcontroller Library
*
* SPDX-License-Identifier: BSD-3-Clause
*******************************************************************************
* Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
//==============================================================================
// Notes
//
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
// HW peripheral instances. You can use them the same way as any other "normal"
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
// pinout image on mbed.org.
//
// - The pins which are other components present on the board have
// the comment "Connected to xxx". The pin function may not work properly in this
// case. These pins may not be displayed on the board pinout image on mbed.org.
// Please read the board reference manual and schematic for more information.
//
// - Warning: pins the default STDIO_UART_TX and STDIO_UART_RX pins are commented
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
//
//==============================================================================
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // rhomb.io AD0
{PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // rhomb.io AD0
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // rhomb.io AD1
{PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // rhomb.io AD1
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // rhomb.io UART-A_TXD
{PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // rhomb.io UART-A_TXD
{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // rhomb.io UART-A_RXD
{PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // rhomb.io UART-A_RXD
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // rhomb.io AD2
{PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // rhomb.io AD2
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // rhomb.io SPIA_CLK
{PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // rhomb.io SPIA_CLK
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // rhomb.io SPIA_MISO
{PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // rhomb.io SPIA_MISO
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // rhomb.io SPIA_MOSI
{PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // rhomb.io SPIA_MOSI
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // rhomb.io AD3
{PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // rhomb.io AD3
{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // rhomb.io NMI
{PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // rhomb.io NMI
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // rhomb.io AD5
{PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // rhomb.io AD5
{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // rhomb.io AD5
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // rhomb.io AD4
{PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // rhomb.io AD4
{PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // rhomb.io AD4
{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // rhomb.io CAPT1 (R19 must be populated)
{PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // rhomb.io CAPT1 (R19 must be populated)
{PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // rhomb.io CAPT1 (R19 must be populated)
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // rhomb.io CAPT0 (R18 must be populated)
{PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // rhomb.io CAPT0 (R18 must be populated)
{PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // rhomb.io CAPT0 (R18 must be populated)
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // rhomb.io AD8
{PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // rhomb.io AD8
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // rhomb.io AD7
{PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // rhomb.io AD7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
{NC, NC, 0}
};
//*** DAC ***
MBED_WEAK const PinMap PinMap_DAC[] = {
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // rhomb.io AD2
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // rhomb.io SPIA_CLK
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io INT1
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SDA // Connected to ATECC608A
{PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io QSPI_CS0 /
{PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS1
{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD4
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io SPI-A_CS0
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SCL // Connected to ATECC608A
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io IO2
{PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS2
{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD5
{NC, NC, 0}
};
//*** PWM ***
// TIM5 cannot be used because already used by the us_ticker
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io AD0
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // rhomb.io AD0
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io AD1
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // rhomb.io AD1
{PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io AD1
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io UART-A_TXD
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // rhomb.io UART-A_TXD
{PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io UART-A_TXD
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io UART-A_RXD
// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // rhomb.io UART-A_RXD
{PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io UART-A_RXD
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io SPI-A_CLK
{PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_CLK
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SPI-A_MISO
{PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io SPI-A_MISO
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_MOSI
{PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SPI-A_MOSI
{PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_MOSI
{PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io SPI-A_MOSI
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io IO3
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io IO4
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io OTG_ID
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io OTG_N
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io INT2
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io AD3
{PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io AD3
{PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io AD3
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io NMI
{PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io NMI
{PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io NMI
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io INT0
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io IO1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io IO0
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io SPI-A_CS0
{PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // rhomb.io SPI-A_CS0
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io INT1
{PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // rhomb.io INT1
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io I2C-A_SCL
{PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io I2C-A_SCL
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io I2C-A_SDA
{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io I2C-A_SDA
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io IO2
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io QSPI_CS0
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_CS2
{PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io SPI-A_CS2
{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io SPI-A_CS1
{PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io SPI-A_CS1
{PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io SPI-A_CS1
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io IO7
{PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io IO7
{PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io IO7
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io PWM3
{PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // rhomb.io PWM3
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io PWM0
{PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // rhomb.io PWM0
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SDIO_DATA0
{PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // rhomb.io SDIO_DATA0
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SDIO_DATA1
{PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // rhomb.io SDIO_DATA1
{PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io IO12
{PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io IO13
{PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io PWM2
{PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io SDIO_CDN
{PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io RESET_OUT
{PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io USB_SWITCH
{PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SAI-A_SDO
{PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SAI-A_LRCLK
{PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SAI-A_BCLK
{PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SAI-A_SDI
{PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io IO5
{PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io PWM1
{PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io QSPI_CLK
{PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io QSPI_MEM_CS
{PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io QSPI_IO0
{PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io QSPI_IO1
{PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io QSPI_IO2
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD0
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_TXD
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO4
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io SPI-A_CS0
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO2
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io QSPI_CS0
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD4
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_N
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA2
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA2
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CLK
{PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_TXD
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_TXD
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD1
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RXD
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_ID
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT1
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io IO2
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI_CS0
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD5
{PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_P
{PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA3
{PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA3
{PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CMD
{PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_RXD
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_RXD
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD1
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_P
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT2
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io NMI
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT0
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO1
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io 1WIRE // Connected to DS28E05X
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS1
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_CMD
{PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RTS
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO12
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD0
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_MISO
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_N
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO1
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO0
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT1
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS2
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io SPI-A_CS2
{PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_CTS
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO11
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MOSI
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO0
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO0
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO7
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO14
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_CLK
{PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_RTS
{PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO3
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MISO
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO1
{PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO1
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS1
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO15
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA3
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_CTS
{PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO2
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_CLK
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT0
{PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT0
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO2
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS2
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA2
{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_TX
{PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO1
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io AD2
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io AD2
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT2
{PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT2
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io I2C-A_SDA
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io 1WIRE // Connected to DS28E05X
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_RX
{PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO0
{NC, NC, 0}
};
//*** CAN ***
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_N
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SCL
{PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_RX
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_P
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SDA
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_TX
{NC, NC, 0}
};
//*** QUADSPI ***
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};

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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h
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@ -1,343 +0,0 @@
/* mbed Microcontroller Library
*
* SPDX-License-Identifier: BSD-3-Clause
*******************************************************************************
* Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: RHOMBIO_L476DMW1K */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ALT0 = 0x100,
ALT1 = 0x200,
ALT2 = 0x300,
} ALTx;
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0 | ALT0,
PA_1 = 0x01,
PA_1_ALT0 = PA_1 | ALT0,
PA_2 = 0x02,
PA_2_ALT0 = PA_2 | ALT0,
PA_3 = 0x03,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = PB_5 | ALT0,
PB_6 = 0x16,
PB_6_ALT0 = PB_6 | ALT0,
PB_7 = 0x17,
PB_7_ALT0 = PB_7 | ALT0,
PB_8 = 0x18,
PB_8_ALT0 = PB_8 | ALT0,
PB_9 = 0x19,
PB_9_ALT0 = PB_9 | ALT0,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_13_ALT0 = PB_13 | ALT0,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_0 = 0x30,
PD_1 = 0x31,
PD_2 = 0x32,
PD_3 = 0x33,
PD_4 = 0x34,
PD_5 = 0x35,
PD_6 = 0x36,
PD_7 = 0x37,
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_11 = 0x3B,
PD_12 = 0x3C,
PD_13 = 0x3D,
PD_14 = 0x3E,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_2 = 0x42,
PE_3 = 0x43,
PE_4 = 0x44,
PE_5 = 0x45,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
PE_12 = 0x4C,
PE_13 = 0x4D,
PE_14 = 0x4E,
PE_15 = 0x4F,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
// STDIO for console print
CONSOLE_TX = PC_4,
CONSOLE_RX = PC_5,
I2C_SCL = PB_8,
I2C_SDA = PB_9,
SPI_MOSI = PA_7,
SPI_MISO = PA_6,
SPI_SCK = PA_5,
SPI_CS = PB_6,
PWM_OUT = PC_7,
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,
SYS_JTMS_SWDIO = PA_13,
SYS_JTRST = PB_4,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PE_12,
QSPI_FLASH1_IO1 = PE_13,
QSPI_FLASH1_IO2 = PE_14,
QSPI_FLASH1_IO3 = PE_15,
QSPI_FLASH1_SCK = PE_10,
QSPI_FLASH1_CSN = PE_11,
// rhomb.io system namings //.........................
NMI = PB_1,
INT0 = PB_3,
INT1 = PB_7,
INT2 = PA_15,
IO0 = PB_5,
IO1 = PB_4,
IO2 = PB_10,
IO3 = PA_8,
IO4 = PA_9,
IO5 = PE_8,
IO6 = PE_7,
IO7 = PB_15,
IO8 = PC_13,
IO9 = PD_7,
IO10 = PD_10,
IO11 = PD_11,
IO12 = PD_12,
IO13 = PD_13,
IO14 = PC_3,
IO15 = PC_2,
PWM0 = PC_7,
PWM1 = PE_9,
PWM2 = PD_14,
PWM3 = PC_6,
PWM4 = PB_2,
UART_A_RXD = PA_3,
UART_A_TXD = PA_2,
UART_A_CTS = PD_3,
UART_A_RTS = PD_4,
UART_B_RXD = PD_6,
UART_B_TXD = PD_5,
UART_C_RXD = PD_9,
UART_C_TXD = PD_8,
I2C_A_SDA = PB_9,
I2C_A_SCL = PB_8,
I2C_B_SDA = PB_14, // R14 must be populated/closed (default is open)
I2C_B_SCL = PB_13, // R15 must be populated/closed (default is open)
SPI_A_MOSI = PA_7,
SPI_A_MISO = PA_6,
SPI_A_CLK = PA_5,
SPI_A_CS0 = PB_6,
SPI_A_CS1 = PB_14,
SPI_A_CS2 = PB_13,
QSPI_IO0 = PE_12,
QSPI_IO1 = PE_13,
QSPI_IO2 = PE_14,
QSPI_IO3 = PE_15,
QSPI_CLK = PE_10,
QSPI_CS0 = PB_11,
QSPI_MEM_CS = PE_11,
_1WIRE = PB_12,
CAN_A_RX = PD_0,
CAN_A_TX = PD_1,
SDIO_DATAO = PC_8,
SDIO_DATA1 = PC_9,
SDIO_DATA2 = PC_10,
SDIO_DATA3 = PC_11,
SDIO_CLK = PC_12,
SDIO_CMD = PD_2,
SDIO_CDN = PD_15,
SAI_A_BCLK = PE_5,
SAI_A_LRCLK = PE_4,
SAI_A_SDI = PE_6,
SAI_A_SDO = PE_3,
SAI_A_MCLK = PE_2,
OTG_P = PA_12,
OTG_N = PA_11,
OTG_ID = PA_10,
AD0 = PA_0,
AD1 = PA_1,
AD2 = PA_4,
AD3 = PB_0,
AD4 = PC_1,
AD5 = PC_0,
// AD6 not used
AD7 = PC_5,
AD8 = PC_4,
COMP_A_P = PC_5,
COMP_A_N = PC_4,
CAPT0 = PC_3, // R18 must be populated/closed (default is open)
CAPT1 = PC_2, // R19 must be populated/closed (default is open)
SWDIO = PA_13,
SWCLK = PA_14,
RSTOUT = PE_0,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
// Standardized LED and button names
#define LED1 PC_7 // LED Green
#define BUTTON1 PB_1
#ifdef __cplusplus
}
#endif
#endif

1
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/CMakeLists.txt
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@ -1,7 +1,6 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_ADV_WISE_1570 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_NUCLEO_L486RG EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")

17
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_ADV_WISE_1570/CMakeLists.txt
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@ -1,17 +0,0 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-adv-wise-1570 INTERFACE)
target_sources(mbed-adv-wise-1570
INTERFACE
PeripheralPins.c
system_clock.c
)
target_include_directories(mbed-adv-wise-1570
INTERFACE
.
)
target_link_libraries(mbed-adv-wise-1570 INTERFACE mbed-stm32l486xg)

137
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
// =====
// Note: Commented lines are alternative possibilities which are not used per default.
// If you change them, you will have also to modify the corresponding xxx_api.c file
// for pwmout, analogin, analogout, ...
// =====
//*** ADC ***
const PinMap PinMap_ADC[] = {
{ADC00, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6
{ADC01, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3
{ADC02, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
{NC, NC, 0}
};
const PinMap PinMap_ADC_Internal[] = {
{NC, NC, 0}
};
//*** DAC ***
const PinMap PinMap_DAC[] = {
{NC, NC, 0}
};
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
{I2C0_SDA, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{I2C1_SDA, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{I2C0_SCL, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{I2C1_SCL, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
//*** PWM ***
// Warning: TIM5 cannot be used because already used by the us_ticker.
const PinMap PinMap_PWM[] = {
{PWM0_OUT, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
{PWM1_OUT, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{NC, NC, 0}
};
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{UART2_TX, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{UART_TXD, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{LPUART1_TX, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{UART1_TX, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{UART2_RX, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{UART_RXD, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{LPUART1_RX, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{UART1_RX, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{UART_RTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{UART_CTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{SPI_MOSI, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{SPI_MISO, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{SPI_SCK, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{SPI_CS0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{NC, NC, 0}
};
const PinMap PinMap_CAN_RD[] = {
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{NC, NC, 0}
};

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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_ADV_WISE_1570/PinNames.h
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@ -1,274 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: ADV_WISE_1570 */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PC_0 = 0x20,
PC_1 = 0x21,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_7 = 0x27,
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_2 = 0x32,
PH_0 = 0x70,
PH_1 = 0x71,
// Not connected
NC = (int)0xFFFFFFFF,
// MCU pins
CB_RESET_OUT = PA_8,
CB_PWR_ON = PA_11,
UART3_TX = PC_10,
UART3_RX = PC_11,
UART3_RTS = PB_13,
UART3_CTS = PB_14,
GPIO0 = PB_9,
GPIO1 = PC_7,
GPIO2 = PB_15,
GPIO3 = PB_12,
GPIO4 = PC_8,
GPIO5 = PC_13,
W_DISABLE = PB_2,
I2C0_SDA = PB_7,
I2C0_SCL = PB_6,
SPI_MOSI = PA_7,
SPI_MISO = PA_6,
SPI_SCK = PA_5,
SPI_CS0 = PA_4,
SPI_CS = SPI_CS0,
I2C1_SDA = PB_11,
I2C1_SCL = PB_10,
PWM0_OUT = PB_0,
PWM1_OUT = PB_1,
ADC00 = PA_1,
ADC01 = PC_2,
ADC02 = PC_4,
BACKUP = PA_12,
RESET_IN = PC_9,
WAKE = PA_0,
// UARTs
UART1_TX = PA_9,
UART1_RX = PA_10,
LPUART1_TX = PC_1,
LPUART1_RX = PC_0,
UART2_TX = PA_2,
UART2_RX = PA_3,
// Aliases
SERIAL_TX = UART3_TX,
SERIAL_RX = UART3_RX,
SERIAL_CTS = UART3_CTS,
SERIAL_RTS = UART3_RTS,
UART_TXD = UART3_TX,
UART_RXD = UART3_RX,
UART_CTS = UART3_CTS,
UART_RTS = UART3_RTS,
ADC_BC95 = PC_5,
MDMTXD = LPUART1_TX,
MDMRXD = LPUART1_RX,
// STDIO for console print
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
CONSOLE_TX = UART3_TX,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
CONSOLE_RX = UART3_RX,
#endif
// Module external pins
P_1 = NC,
P_2 = NC,
P_3 = NC,
P_4 = NC,
P_5 = NC,
P_6 = NC,
P_7 = NC,
P_8 = NC,
P_9 = NC,
P_10 = NC,
P_11 = NC,
P_12 = NC,
P_13 = NC,
P_14 = NC,
P_15 = NC,
P_16 = CB_RESET_OUT,
P_17 = NC,
P_18 = NC,
P_19 = NC,
P_20 = CB_PWR_ON,
P_21 = NC,
P_22 = UART3_TX,
P_23 = NC,
P_24 = NC,
P_25 = NC,
P_26 = NC,
P_27 = NC,
P_28 = NC,
P_29 = NC,
P_30 = NC,
P_31 = NC,
P_32 = UART3_RX,
P_33 = NC,
P_34 = UART3_RTS,
P_35 = I2C1_SDA,
P_36 = UART3_CTS,
P_37 = I2C1_SCL,
P_38 = GPIO0,
P_39 = NC,
P_40 = GPIO1,
P_41 = PWM0_OUT,
P_42 = GPIO2,
P_43 = PWM1_OUT,
P_44 = GPIO3,
P_45 = NC,
P_46 = GPIO4,
P_47 = ADC00,
P_48 = GPIO5,
P_49 = ADC01,
P_50 = NC,
P_51 = NC,
P_52 = NC,
P_53 = ADC02,
P_54 = NC,
P_55 = NC,
P_56 = W_DISABLE,
P_57 = NC,
P_58 = I2C0_SDA,
P_59 = NC,
P_60 = I2C0_SCL,
P_61 = NC,
P_62 = SPI_MOSI,
P_63 = NC,
P_64 = SPI_MISO,
P_65 = NC,
P_66 = SPI_SCK,
P_67 = BACKUP,
P_68 = SPI_CS0,
P_69 = NC,
P_70 = NC,
P_71 = RESET_IN,
P_72 = NC,
P_73 = WAKE,
P_74 = NC,
P_75 = NC,
MDMRTS = NC,
MDMCTS = NC,
} PinName;
// Standardized LED and button names
#define LED1 PB_15 // Green
#define LED2 PB_1 // Blue
#define LED3 PB_0 // Red
#define BUTTON1 PC_13
#ifdef __cplusplus
}
#endif
#endif

309
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_ADV_WISE_1570/system_clock.c
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/* mbed Microcontroller Library
* Copyright (c) 2016-2020 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
* | 3- USE_PLL_HSI (internal 16 MHz)
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 80
* AHBCLK (MHz) | 80
* APB1CLK (MHz) | 80
* APB2CLK (MHz) | 80
* USB capable | YES
*-----------------------------------------------------------------------------
**/
#include "stm32l4xx.h"
#include "mbed_error.h"
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
#define USE_PLL_HSI 0x2 // Use HSI internal clock
#define USE_PLL_MSI 0x1 // Use MSI internal clock
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
uint8_t SetSysClock_PLL_HSI(void);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
uint8_t SetSysClock_PLL_MSI(void);
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
/* 4- If fail start with MSI clock */
if (SetSysClock_PLL_MSI() == 0)
#endif
{
{
error("SetSysClock failed\n");
}
}
}
}
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 1
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
#endif
}
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
// Enable HSE oscillator and activate PLL with HSE as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
}
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
return 0; // FAIL
}
#if DEVICE_USBDEVICE
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}
#endif /* DEVICE_USBDEVICE */
// Select LSE output as LPUART1 clock source
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1;
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
RCC_PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
// Enable HSI oscillator and activate PLL with HSI as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
return 0; // FAIL
}
#if DEVICE_USBDEVICE
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}
#endif /* DEVICE_USBDEVICE */
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 3
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
#endif
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
/******************************************************************************/
/* PLL (clocked by MSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_MSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
#if DEVICE_USBDEVICE
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#endif /* DEVICE_USBDEVICE */
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
return 0; // FAIL
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 4
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
#endif
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

1
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/CMakeLists.txt
View File

@ -2,7 +2,6 @@
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_DISCO_L496AG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MTS_DRAGONFLY_L496VG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_NUCLEO_L496ZG EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")

17
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/CMakeLists.txt
View File

@ -1,17 +0,0 @@
# Copyright (c) 2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-mts-dragonfly-l496vg INTERFACE)
target_sources(mbed-mts-dragonfly-l496vg
INTERFACE
PeripheralPins.c
TargetInit.c
)
target_include_directories(mbed-mts-dragonfly-l496vg
INTERFACE
.
)
target_link_libraries(mbed-mts-dragonfly-l496vg INTERFACE mbed-stm32l496xg)

350
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PeripheralPins.c
View File

@ -1,350 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
//==============================================================================
// Notes
//
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
// HW peripheral instances. You can use them the same way as any other "normal"
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
// pinout image on mbed.org.
//
// - The pins which are connected to other components present on the board have
// the comment "Connected to xxx". The pin function may not work properly in this
// case. These pins may not be displayed on the board pinout image on mbed.org.
// Please read the board reference manual and schematic for more information.
//
// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
//
//==============================================================================
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
{PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
{PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
{PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
{PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
{PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
{PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
{PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
{PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to QSPI_BK1_IO2 [MX25R6435FM2IL0_SIO2]
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
{PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
{PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
{PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
{PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
{PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
{PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
{PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
{PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
{PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
{PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
{NC, NC, 0}
};
//*** DAC ***
MBED_WEAK const PinMap PinMap_DAC[] = {
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{PC_1_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
{PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
{PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
{PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{PC_0_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
{NC, NC, 0}
};
//*** PWM ***
// TIM5 cannot be used because already used by the us_ticker
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
{PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
{PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
{PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
{PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
{PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
{PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
{PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
{PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
{PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
{PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
{PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
//*** CAN ***
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
{PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)},
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
{PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
{PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)},
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
//*** QUADSPI ***
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{NC, NC, 0}
};
//*** USBDEVICE ***
MBED_WEAK const PinMap PinMap_USB_FS[] = {
// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
{PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
// {PA_13, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
// {PA_14, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
// {PC_9, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
{NC, NC, 0}
};

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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PinNames.h
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@ -1,368 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
/* MBED TARGET LIST: MTS_DRAGONFLY_L471QG */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ALT0 = 0x100,
ALT1 = 0x200,
ALT2 = 0x300,
} ALTx;
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0 | ALT0, // same pin used for alternate HW
PA_1 = 0x01,
PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW
PA_2 = 0x02,
PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW
PA_3 = 0x03,
PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW
PA_4 = 0x04,
PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW
PA_5 = 0x05,
PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW
PA_6 = 0x06,
PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW
PA_7 = 0x07,
PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW
PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW
PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW
PB_0 = 0x10,
PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW
PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW
PB_1 = 0x11,
PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW
PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW
PB_4 = 0x14,
PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW
PB_5 = 0x15,
PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW
PB_6 = 0x16,
PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW
PB_7 = 0x17,
PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW
PB_8 = 0x18,
PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW
PB_9 = 0x19,
PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW
PB_10 = 0x1A,
PB_10_ALT0 = PB_10 | ALT0, // same pin used for alternate HW
PB_11 = 0x1B,
PB_11_ALT0 = PB_11 | ALT0, // same pin used for alternate HW
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_13_ALT0 = PB_13 | ALT0, // same pin used for alternate HW
PB_14 = 0x1E,
PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW
PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW
PB_15 = 0x1F,
PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW
PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW
PC_0 = 0x20,
PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW
PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW
PC_1 = 0x21,
PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW
PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW
PC_2 = 0x22,
PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW
PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW
PC_3 = 0x23,
PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW
PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW
PC_4 = 0x24,
PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW
PC_5 = 0x25,
PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW
PC_6 = 0x26,
PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW
PC_7 = 0x27,
PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW
PC_8 = 0x28,
PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW
PC_9 = 0x29,
PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW
PC_10 = 0x2A,
PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW
PC_11 = 0x2B,
PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_0 = 0x30,
PD_1 = 0x31,
PD_2 = 0x32,
PD_3 = 0x33,
PD_4 = 0x34,
PD_5 = 0x35,
PD_6 = 0x36,
PD_7 = 0x37,
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_11 = 0x3B,
PD_12 = 0x3C,
PD_13 = 0x3D,
PD_14 = 0x3E,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_2 = 0x42,
PE_3 = 0x43,
PE_4 = 0x44,
PE_5 = 0x45,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
PE_12 = 0x4C,
PE_13 = 0x4D,
PE_14 = 0x4E,
PE_15 = 0x4F,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
#ifdef TARGET_FF_ARDUINO_UNO
ARDUINO_UNO_A0 = PC_2,
ARDUINO_UNO_A1 = PC_0,
ARDUINO_UNO_A2 = PC_4,
ARDUINO_UNO_A3 = PB_0,
ARDUINO_UNO_A4 = PC_1,
ARDUINO_UNO_A5 = PC_9,
ARDUINO_UNO_D0 = PA_3,
ARDUINO_UNO_D1 = PA_2,
ARDUINO_UNO_D2 = PB_15,
ARDUINO_UNO_D3 = PA_0,
ARDUINO_UNO_D4 = PA_7,
ARDUINO_UNO_D5 = PA_9,
ARDUINO_UNO_D6 = PA_1,
ARDUINO_UNO_D7 = PA_8,
ARDUINO_UNO_D8 = PB_1,
ARDUINO_UNO_D9 = PB_13,
ARDUINO_UNO_D10 = PC_8,
ARDUINO_UNO_D11 = PB_5,
ARDUINO_UNO_D12 = PA_6,
ARDUINO_UNO_D13 = PA_5,
ARDUINO_UNO_D14 = PB_9,
ARDUINO_UNO_D15 = PB_8,
#endif
// 40 pin
IO_00 = ARDUINO_UNO_D1,
IO_01 = ARDUINO_UNO_D4,
IO_02 = ARDUINO_UNO_D8,
IO_03 = ARDUINO_UNO_D6,
IO_04 = ARDUINO_UNO_D11,
IO_05 = ARDUINO_UNO_D13,
IO_06 = ARDUINO_UNO_D15,
IO_07 = ARDUINO_UNO_D2,
IO_08 = ARDUINO_UNO_A0,
IO_09 = ARDUINO_UNO_A3,
IO_10 = ARDUINO_UNO_A1,
IO_11 = ARDUINO_UNO_A4,
IO_12 = ARDUINO_UNO_A2,
IO_13 = ARDUINO_UNO_D9,
IO_14 = ARDUINO_UNO_A5,
IO_15 = ARDUINO_UNO_D14,
IO_16 = ARDUINO_UNO_D12,
IO_17 = ARDUINO_UNO_D10,
IO_18 = ARDUINO_UNO_D3,
IO_19 = ARDUINO_UNO_D5,
IO_20 = ARDUINO_UNO_D7,
IO_21 = ARDUINO_UNO_D0,
// 40 pin USB debug port
CONSOLE_TX = PB_6,
CONSOLE_RX = PB_7,
// UARTS to external I/O
UART2_TX = ARDUINO_UNO_D1,
UART2_RX = ARDUINO_UNO_D0,
UART2_RTS = ARDUINO_UNO_D6,
UART2_CTS = ARDUINO_UNO_D3,
UART2_DSR = ARDUINO_UNO_D5,
UART2_DTR = ARDUINO_UNO_D7,
UART2_DCD = ARDUINO_UNO_D4,
UART2_RI = ARDUINO_UNO_D8,
UART1_TX = PB_6,
UART1_RX = PB_7,
UART1_RTS = PB_3,
UART1_CTS = PB_4,
// 40 pin JTAG/SWD
J_TCK = PA_14, // a.k.a. SWCLK
J_TDI = PA_15,
J_RST = PB_4,
J_TDO = PB_3, // a.k.a. SWO
J_TMS = PA_13, // a.k.a. SWDIO
// Exteranl serial port
SERIAL_TX = ARDUINO_UNO_D1,
SERIAL_RX = ARDUINO_UNO_D0,
SERIAL_RTS = ARDUINO_UNO_D6,
SERIAL_CTS = ARDUINO_UNO_D3,
SERIAL_DCD = ARDUINO_UNO_D4,
SERIAL_DSR = ARDUINO_UNO_D5,
SERIAL_DTR = ARDUINO_UNO_D7,
SERIAL_RI = ARDUINO_UNO_D8,
// SPI1 and SPI2 are available on Arduino pins
SPI1_MOSI = ARDUINO_UNO_D11,
SPI1_MISO = ARDUINO_UNO_D12,
SPI1_SCK = ARDUINO_UNO_D13,
SPI2_MOSI = ARDUINO_UNO_D2,
SPI2_MISO = ARDUINO_UNO_A0,
SPI2_SCK = ARDUINO_UNO_D9,
// QuadSPI connects to flash part
QSPI_FLASH1_SCK = PE_10,
QSPI_FLASH1_CSN = PE_11,
QSPI_FLASH1_IO0 = PE_12,
QSPI_FLASH1_IO1 = PE_13,
QSPI_FLASH1_IO2 = PE_14,
QSPI_FLASH1_IO3 = PE_15,
// I2C1 and I2C3 are available on Arduino pins
I2C1_SCL = ARDUINO_UNO_D15,
I2C1_SDA = ARDUINO_UNO_D14,
I2C2_SCL = PB_10,
I2C2_SDA = PB_14,
I2C3_SCL = ARDUINO_UNO_A1,
I2C3_SDA = ARDUINO_UNO_A4,
// Cellular radio (note: no DSR signal)
RADIO_PWR = PE_0,
RADIO_RESET = PE_1,
RADIO_TX = PD_8,
RADIO_RX = PD_9,
RADIO_RI = PD_10,
RADIO_CTS = PD_11,
RADIO_RTS = PD_12,
RADIO_DTR = PD_13,
RADIO_DCD = PD_14,
RADIO_ONOFF = PE_2,
RADIO_STATUS = PE_3,
AP_READY = PE_4,
RADIO_WAKEUP = PE_5,
NET_MODE = PD_3,
NET_STATUS = PD_2,
VRAD_ALERT = PB_2,
MON_1V8 = PC_5,
RADIO_VDD_EXT = MON_1V8,
MDMPWRON = RADIO_ONOFF, // 3G_ONOFF DragonFly Design Guide, Page No. 16
MDMRST = RADIO_RESET,
MDMTXD = RADIO_TX, // Transmit Data
MDMRXD = RADIO_RX, // Receive Data
MDMRTS = RADIO_RTS, // Request to Send
MDMCTS = RADIO_CTS, // Clear to Send
MDMDCD = RADIO_DCD, // Data Carrier Detect
MDMDTR = RADIO_DTR, // Data Terminal Ready
MDMRI = RADIO_RI, // Ring Indicator
// Power control for level shifter and SPI flash. Low powers on.
BUF_EN = PD_15,
VMEM_EN = PE_7,
// Voltage measuring
VCC_IN_MEAS_EN = PE_8,
VCC_IN_MEAS = PC_3,
INPUT_POWER = PC_7,
// GNSS/GPS
GPS_ANT_PWR_EN = PE_9,
// Wake up from Standby/Shutdown options are PA0 & PA2.
WAKEUP = ARDUINO_UNO_D3,
// Wake up build Options
STM_WKUP = PC_13,
// CAN
CAN_TX = ARDUINO_UNO_D14,
CAN_RX = ARDUINO_UNO_D15,
// build option
CAN1_TX = PD_1,
CAN1_RX = PD_0,
CAN2_RX = PB_12,
CAN2_TX = ARDUINO_UNO_D9,
LS_LED = PE_6,
// Not connected
NC = (int) 0xFFFFFFFF
} PinName;
// Standardized LED and button names
#define LED1 PA_0
#ifdef __cplusplus
}
#endif
#endif

30
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/TargetInit.c
View File

@ -1,30 +0,0 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2015-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "stm32l4xx.h"
void TargetBSP_Init(void)
{
/* Enable the flash memory so greentea tests for QuadSPI work. */
/* The application can set it high to disable and save power. */
__HAL_RCC_GPIOE_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
GPIO_InitStruct.Pin = GPIO_PIN_7;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7, GPIO_PIN_RESET);
}

310
targets/cmsis_mcu_descriptions.json5
View File

@ -4867,98 +4867,6 @@
"sub_family": "STM32F412",
"vendor": "STMicroelectronics:13"
},
"STM32F413RHTx": {
"algorithms": [
{
"default": true,
"file_name": "CMSIS/Flash/STM32F4xx_1536.FLM",
"ram_size": null,
"ram_start": null,
"size": 1572864,
"start": 134217728
},
{
"default": false,
"file_name": "CMSIS/Flash/STM32F413xx_423xx_OPT.FLM",
"ram_size": null,
"ram_start": null,
"size": 4,
"start": 536854528
}
],
"family": "STM32F4 Series",
"from_pack": {
"pack": "STM32F4xx_DFP",
"url": "http://www.keil.com/pack",
"vendor": "Keil",
"version": "2.13.0"
},
"memories": {
"IRAM1": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": true,
"size": 327680,
"start": 536870912,
"startup": false
},
"IROM1": {
"access": {
"execute": true,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": false
},
"default": true,
"size": 1572864,
"start": 134217728,
"startup": true
}
},
"name": "STM32F413RHTx",
"processor": {
"Symmetric": {
"core": "CortexM4",
"fpu": "SinglePrecision",
"mpu": "Present",
"units": 1
}
},
"sectors": [
[
134217728,
16384
],
[
134283264,
65536
],
[
134348800,
131072
],
[
536836096,
528
],
[
536854528,
4
]
],
"sub_family": "STM32F413",
"vendor": "STMicroelectronics:13"
},
"STM32F413ZHTx": {
"algorithms": [
{
@ -5174,133 +5082,6 @@
"sub_family": "STM32F429",
"vendor": "STMicroelectronics:13"
},
"STM32F439VITx": {
"algorithms": [
{
"default": true,
"file_name": "CMSIS/Flash/STM32F4xx_2048.FLM",
"ram_size": null,
"ram_start": null,
"size": 2097152,
"start": 134217728
},
{
"default": false,
"file_name": "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM",
"ram_size": null,
"ram_start": null,
"size": 8,
"start": 536854528
},
{
"default": false,
"file_name": "CMSIS/Flash/STM32F4xx_OTP.FLM",
"ram_size": null,
"ram_start": null,
"size": 528,
"start": 536836096
}
],
"family": "STM32F4 Series",
"from_pack": {
"pack": "STM32F4xx_DFP",
"url": "http://www.keil.com/pack",
"vendor": "Keil",
"version": "2.13.0"
},
"memories": {
"IRAM1": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": true,
"size": 196608,
"start": 536870912,
"startup": false
},
"IRAM2": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": false,
"size": 65536,
"start": 268435456,
"startup": false
},
"IROM1": {
"access": {
"execute": true,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": false
},
"default": true,
"size": 2097152,
"start": 134217728,
"startup": true
}
},
"name": "STM32F439VITx",
"processor": {
"Symmetric": {
"core": "CortexM4",
"fpu": "SinglePrecision",
"mpu": "Present",
"units": 1
}
},
"sectors": [
[
134217728,
16384
],
[
134283264,
65536
],
[
134348800,
131072
],
[
135266304,
16384
],
[
135331840,
65536
],
[
135397376,
131072
],
[
536836096,
528
],
[
536854528,
8
]
],
"sub_family": "STM32F439",
"vendor": "STMicroelectronics:13"
},
"STM32F439ZITx": {
"algorithms": [
{
@ -9789,97 +9570,6 @@
"sub_family": "STM32L496",
"vendor": "STMicroelectronics:13"
},
"STM32L496VGTx": {
"algorithms": [
{
"default": true,
"file_name": "CMSIS/Flash/STM32L4xx_1024.FLM",
"ram_size": null,
"ram_start": null,
"size": 1048576,
"start": 134217728
},
{
"default": false,
"file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM",
"ram_size": null,
"ram_start": null,
"size": 20,
"start": 536836096
}
],
"family": "STM32L4 Series",
"from_pack": {
"pack": "STM32L4xx_DFP",
"url": "http://www.keil.com/pack",
"vendor": "Keil",
"version": "2.2.0"
},
"memories": {
"IRAM1": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": true,
"size": 262144,
"start": 536870912,
"startup": false
},
"IRAM2": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": false,
"size": 65536,
"start": 268435456,
"startup": false
},
"IROM1": {
"access": {
"execute": true,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": false
},
"default": true,
"size": 1048576,
"start": 134217728,
"startup": true
}
},
"name": "STM32L496VGTx",
"processor": {
"Symmetric": {
"core": "CortexM4",
"fpu": "SinglePrecision",
"mpu": "Present",
"units": 1
}
},
"sectors": [
[
134217728,
2048
]
],
"sub_family": "STM32L496",
"vendor": "STMicroelectronics:13"
},
"STM32L496ZGTx": {
"algorithms": [
{

22
targets/drivers.json5
View File

@ -81,28 +81,8 @@
"description": "Cellular module from this Multitech board. I have been unable to figure out its exact part number from the available docs...",
"friendly_name": "Multitech Dragonfly Nano Cellular"
},
"COMPONENT_QUECTEL_EC2X": {
"description": "EC2X and EG25 families of cellular modules",
"friendly_name": "Quectel EC2X"
},
"COMPONENT_QUECTEL_BG96": {
"description": "LTE module",
"friendly_name": "Quectel BG96"
},
"COMPONENT_QUECTEL_UG96": {
"description": "3G cellular module",
"friendly_name": "Quectel UG96"
},
"COMPONENT_QUECTEL_BC95": {
"description": "Narrowband Internet of Things (NB-IoT) cellular module",
"friendly_name": "Quectel BC95"
},
"COMPONENT_QUECTEL_M26": {
"description": "GSM GPRS cellular module",
"friendly_name": "Quectel M26"
},
"COMPONENT_RIOTMICRO_RM1000": {
"description": "LTE + NB-IoT cellular module",
"description": "LTE + Narrowband Internet of Things (NB-IoT) cellular module",
"friendly_name": "Riot Micro RM1000"
},
"COMPONENT_TELIT_HE910": {

158
targets/targets.json5
View File

@ -1969,42 +1969,6 @@
"TRNG"
]
},
// As of 2024, I am unable to find any device being sold by multitech that
// is called a dragonfly and has an STM32F413RHTx MCU.
// That would make this target a candidate for removal.
// It was originally added via a rather vague PR here:
// https://github.com/ARMmbed/mbed-os/pull/11573
"MTS_DRAGONFLY_F413RH": {
"inherits": [
"MCU_STM32F413xH"
],
"supported_form_factors": [
"ARDUINO_UNO"
],
"config": {
"hse_value": {
"help": "HSE via 26MHz xtal",
"value": "26000000",
"macro_name": "HSE_VALUE"
}
},
"overrides": {
"tickless-from-us-ticker": true,
"lse_available": 0
},
"detect_code": [
"0316"
],
"device_has_remove": [
"SERIAL_FC"
],
"components_add": [
"SPIF",
"TELIT_HE910"
],
"device_name": "STM32F413RHTx",
"image_url": "https://static-data2.manualslib.com/product-images/de1/2702201/multitech-multiconnect-dragonfly-mtq-mna1-b02.jpg"
},
"DISCO_F413ZH": {
"inherits": [
"MCU_STM32F413xH"
@ -2138,63 +2102,6 @@
"TRNG"
]
},
// Note: It seems like Seeed no longer sells this board.
// That would make this target a candidate for removal.
"WIO_3G": {
"inherits": [
"MCU_STM32F439xI"
],
"config": {
"clock_source_usb": {
"help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
"value": "1",
"macro_name": "CLOCK_SOURCE_USB"
}
},
"overrides": {
"clock_source": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
"network-default-interface-type": "CELLULAR"
},
"detect_code": [
"9014"
],
"components_add": [
"QUECTEL_UG96"
],
"device_name": "STM32F439VITx",
"image_url": "https://os.mbed.com/media/cache/platforms/Wio_3G.png.250x250_q85.png"
},
// Note: It seems like Seeed no longer sells any WIO boards with BG96 cellular modules.
// That would make this target a candidate for removal.
"WIO_BG96": {
"inherits": [
"MCU_STM32F439xI"
],
"config": {
"clock_source_usb": {
"help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
"value": "0",
"macro_name": "CLOCK_SOURCE_USB"
}
},
"overrides": {
"clock_source": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
"network-default-interface-type": "CELLULAR"
},
"device_has_remove": [
"CAN"
],
"detect_code": [
"9015"
],
"device_name": "STM32F439VITx",
"components_add": [
"SD",
"QUECTEL_BG96"
],
"image_url": "https://os.mbed.com/media/cache/platforms/Wio_3G-1.png.250x250_q85.png.250x250_q85.png"
},
"NUCLEO_F439ZI": {
"inherits": [
"MCU_STM32F439xI"
@ -4391,24 +4298,6 @@
"device_name": "STM32L476VGTx",
"image_url": "https://static5.arrow.com/pdfs/2015/11/2/7/58/36/906/st_/manual/stm32l476g-disco_fig.1.jpg"
},
// As of 2024, rhomb.io seems to be effectively dead as a company -- their website is down, and
// their github and twitter have been inactive since 2021.
// So, this board seems to no longer exist and is a candidate for removal.
"RHOMBIO_L476DMW1K": {
"inherits": [
"MCU_STM32L476xG"
],
"components_add": [
"QSPIF"
],
"detect_code": [
"1500"
],
"device_has_add": [
"QSPI"
],
"device_name": "STM32L476VGTx"
},
"MCU_STM32L486xG": {
"inherits": [
"MCU_STM32L4"
@ -4439,28 +4328,6 @@
"device_name": "STM32L486RGTx",
"image_url": "https://www.st.com/bin/ecommerce/api/image.PF260945.en.feature-description-include-personalized-no-cpn-medium.jpg"
},
// AKA Advantech WISE-1570
// This board is EOL from the manufacturer so it is a candidate for removal.
"ADV_WISE_1570": {
"inherits": [
"MCU_STM32L486xG"
],
"overrides": {
"clock_source": "USE_PLL_HSE_XTAL"
},
"detect_code": [
"0460"
],
"macros_add": [
"WISE_1570"
],
"device_name": "STM32L486RGTx",
"OUTPUT_EXT": "hex",
"components_add": [
"QUECTEL_BC95"
],
"image_url": "https://www.sphinxcomputer.de/produktdb/images/products/6821_25480.png"
},
"MCU_STM32L496xG": {
"inherits": [
"MCU_STM32L4"
@ -4525,31 +4392,6 @@
"0828"
]
},
// Note: I have not been able to find any record of a board with this target ID ever being
// sold by Multitech. It was added by this PR: https://github.com/ARMmbed/mbed-os/pull/15012
// If you cannot actually buy the board that this target is for, that would make it a candidate for removal.
// I have emailed multitech about it, and they never responded.
"MTS_DRAGONFLY_L496VG": {
"inherits": [
"MCU_STM32L496xG"
],
"supported_form_factors": [
"ARDUINO_UNO"
],
"components_add": [
"QSPIF",
"QUECTEL_EC2X"
],
"device_has_add": [
"USBDEVICE",
"QSPI"
],
"detect_code": [
"0313"
],
"device_name": "STM32L496VGTx"
},
"MCU_STM32L4P5xG": {
"inherits": [
"MCU_STM32L4"

30
tools/python/mbed_tools/cli/cmsis_mcu_descr.py
View File

@ -24,6 +24,7 @@ import os
import datetime
import logging
import json
import sys
from typing import Set, Dict, Any
LOGGER = logging.getLogger(__name__)
@ -121,8 +122,33 @@ def find_unused():
print("No MCU descriptions can be pruned, all are used.")
return
print("The following MCU descriptions are not used and should be pruned from cmsis_mcu_descriptions.json")
print("The following MCU descriptions are not used and should be pruned from cmsis_mcu_descriptions.json5")
print("\n".join(removable_mcus))
sys.exit(1)
@cmsis_mcu_descr.command(
name="check-missing",
short_help="Check if there are any missing MCU descriptions used by targets.json5."
)
def check_missing():
used_mcu_names = get_mcu_names_used_by_targets_json5()
# Accumulate set of all keys in cmsis_mcu_descriptions.json
LOGGER.info("Scanning cmsis_mcu_descriptions.json for missing MCUs...")
cmsis_mcu_descriptions_json_contents: Dict[str, Any] = decode_json_file(CMSIS_MCU_DESCRIPTIONS_JSON_PATH)
available_mcu_names = cmsis_mcu_descriptions_json_contents.keys()
# Are there any missing?
missing_mcu_names = used_mcu_names - available_mcu_names
if len(missing_mcu_names) == 0:
print("No missing MCUs, no work to do.")
return
print("The following MCU descriptions are used by targets.json5 and need to be added to"
" cmsis_mcu_descriptions.json5:")
print("\n".join(missing_mcu_names))
sys.exit(1)
@cmsis_mcu_descr.command(
@ -163,3 +189,5 @@ def fetch_missing():
print(f"Add the following entries to {CMSIS_MCU_DESCRIPTIONS_JSON_PATH}:")
print(json.dumps(missing_mcus_dict, indent=4, sort_keys=True))
sys.exit(1)

4
tools/test_configs/NIDDInterface.json
View File

@ -28,10 +28,6 @@
},
"target_overrides": {
"*": {
"QUECTEL_BG96.provide-default": false,
"QUECTEL_BC95.provide-default": false,
"UBLOX_N2XX.provide-default": false,
"cellular.clear-on-connect": true,
"cellular.radio-access-technology": 9,