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Merge pull request #12394 from miteshdedhia7/pr/bug-fix-misc 

Fix SDIO communication issue on Cypress 1M boards and other minor fixes
pull/12405/head
Martin Kojtal 2020-02-10 14:05:11 +00:00 committed by GitHub
parent 7fd5119b89 df5ac6483b
commit 88438dfd6c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
18 changed files with 101 additions and 79 deletions
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18
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp
View File

@ -250,7 +250,9 @@ nsapi_error_t WhdSTAInterface::connect()
// initialize wiced, this is noop if already init
if (!_whd_emac.powered_up) {
_whd_emac.power_up();
if(!_whd_emac.power_up()) {
return NSAPI_ERROR_DEVICE_ERROR;
}
}
res = whd_management_set_event_handler(_whd_emac.ifp, sta_link_change_events,
@ -322,7 +324,9 @@ nsapi_error_t WhdSTAInterface::connect()
void WhdSTAInterface::wifi_on()
{
if (!_whd_emac.powered_up) {
_whd_emac.power_up();
if(!_whd_emac.power_up()) {
CY_ASSERT(false);
}
}
}
@ -384,11 +388,14 @@ int8_t WhdSTAInterface::get_rssi()
// initialize wiced, this is noop if already init
if (!_whd_emac.powered_up) {
_whd_emac.power_up();
if(!_whd_emac.power_up()) {
CY_ASSERT(false);
}
}
res = (whd_result_t)whd_wifi_get_rssi(_whd_emac.ifp, &rssi);
if (res != 0) {
CY_ASSERT(false);
return 0;
}
@ -463,7 +470,9 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re
// initialize wiced, this is noop if already init
if (!_whd_emac.powered_up) {
_whd_emac.power_up();
if(!_whd_emac.power_up()) {
return NSAPI_ERROR_DEVICE_ERROR;
}
}
interal_scan_data.sema = new Semaphore();
@ -476,7 +485,6 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re
whd_result_t whd_res;
int res;
whd_res = (whd_result_t)whd_wifi_scan(_whd_emac.ifp, WHD_SCAN_TYPE_ACTIVE, WHD_BSS_TYPE_ANY,
NULL, NULL, NULL, NULL, whd_scan_handler, &internal_scan_result, &interal_scan_data);
if (whd_res != WHD_SUCCESS) {

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void)
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz)
{
uint16_t u16Div;
u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz;
/*
* The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB
* by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required
* SDIO operating frequency.
*/
u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz);
Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1));
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void)
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz)
{
uint16_t u16Div;
u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz;
/*
* The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB
* by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required
* SDIO operating frequency.
*/
u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz);
Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1));
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void)
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz)
{
uint16_t u16Div;
u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz;
/*
* The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB
* by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required
* SDIO operating frequency.
*/
u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz);
Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1));
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void)
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz)
{
uint16_t u16Div;
u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz;
/*
* The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB
* by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required
* SDIO operating frequency.
*/
u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz);
Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1));
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

6
targets/targets.json
View File

@ -13868,17 +13868,11 @@
"ANALOGOUT",
"QSPI"
],
"macros_remove": [
"MBEDTLS_CONFIG_HW_SUPPORT"
],
"extra_labels_add": [
"PSOC6_01",
"MXCRYPTO_01",
"CORDIO"
],
"extra_labels_remove": [
"MXCRYPTO"
],
"macros_add": [
"CY8C6247FDI_D52",
"CYHAL_UDB_SDIO",