ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

astyle fixes on QSPI API/driver/tests

pull/7783/head
Maciej Bocianski 2018-08-21 10:39:05 +02:00
parent ad49388888
commit 883ea2f1d1
6 changed files with 72 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
TESTS/mbed_hal/qspi/main.cpp
View File

@ -99,12 +99,11 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
int erase_time = 0, write_time = 0, read_time = 0; int erase_time = 0, write_time = 0, read_time = 0;
size_t buf_len = data_size; size_t buf_len = data_size;
for (uint32_t tc = 0; tc < test_count; tc++) for (uint32_t tc = 0; tc < test_count; tc++) {
{
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
srand (ticker_read(get_us_ticker_data())); srand(ticker_read(get_us_ticker_data()));
for(uint32_t i = 0; i < data_size; i++) { for (uint32_t i = 0; i < data_size; i++) {
tx_buf[i] = (uint8_t)(rand() & 0xFF); tx_buf[i] = (uint8_t)(rand() & 0xFF);
} }
@ -127,8 +126,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
} }
const uint32_t write_size = data_size / write_count; const uint32_t write_size = data_size / write_count;
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) {
{
ret = write_enable(qspi); ret = write_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
@ -157,8 +155,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
memset(rx_buf, 0, sizeof(rx_buf)); memset(rx_buf, 0, sizeof(rx_buf));
const uint32_t read_size = data_size / read_count; const uint32_t read_size = data_size / read_count;
qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles); qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles);
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size) for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size) {
{
timer.reset(); timer.reset();
timer.start(); timer.start();
@ -352,21 +349,21 @@ void qspi_frequency_test(void)
flash_init(qspi); flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS); _qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/2); ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 2);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly // check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi); flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS); _qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/4); ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 4);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly // check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi); flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS); _qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/8); ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 8);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly // check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);

6
TESTS/mbed_hal/qspi/qspi_test_utils.cpp
View File

@ -32,7 +32,7 @@ void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_w
qspi_address_size_t addr_size, qspi_alt_size_t alt_size, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
int dummy_cycles) int dummy_cycles)
{ {
memset(&_cmd, 0, sizeof(qspi_command_t) ); memset(&_cmd, 0, sizeof(qspi_command_t));
_cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true; _cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true;
_cmd.instruction.bus_width = inst_width; _cmd.instruction.bus_width = inst_width;
@ -62,7 +62,7 @@ void QspiCommand::build(int instruction, int address, int alt)
} }
} }
qspi_command_t* QspiCommand::get() qspi_command_t *QspiCommand::get()
{ {
return &_cmd; return &_cmd;
} }
@ -175,7 +175,7 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str)
for (uint32_t j = 0; j < reg_size; j++) { for (uint32_t j = 0; j < reg_size; j++) {
utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j); utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j);
for(int i = 0; i < 8; i++) { for (int i = 0; i < 8; i++) {
utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1"); utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1");
} }
utest_printf("\r\n"); utest_printf("\r\n");

2
TESTS/mbed_hal/qspi/qspi_test_utils.h
View File

@ -36,7 +36,7 @@ public:
void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE); void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
qspi_command_t * get(); qspi_command_t *get();
private: private:
qspi_command_t _cmd; qspi_command_t _cmd;

12
drivers/QSPI.cpp
View File

@ -22,7 +22,7 @@
namespace mbed { namespace mbed {
QSPI* QSPI::_owner = NULL; QSPI *QSPI::_owner = NULL;
SingletonPtr<PlatformMutex> QSPI::_mutex; SingletonPtr<PlatformMutex> QSPI::_mutex;
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi() QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
@ -144,10 +144,10 @@ qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned in
qspi_status_t ret_status = QSPI_STATUS_ERROR; qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) { if (_initialized) {
if ( (rx_length != NULL) && (rx_buffer != NULL) ) { if ((rx_length != NULL) && (rx_buffer != NULL)) {
if (*rx_length != 0) { if (*rx_length != 0) {
lock(); lock();
if ( true == _acquire()) { if (true == _acquire()) {
_build_qspi_command(instruction, address, alt); _build_qspi_command(instruction, address, alt);
if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) { if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
ret_status = QSPI_STATUS_OK; ret_status = QSPI_STATUS_OK;
@ -168,7 +168,7 @@ qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned i
qspi_status_t ret_status = QSPI_STATUS_ERROR; qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) { if (_initialized) {
if ( (tx_length != NULL) && (tx_buffer != NULL) ) { if ((tx_length != NULL) && (tx_buffer != NULL)) {
if (*tx_length != 0) { if (*tx_length != 0) {
lock(); lock();
if (true == _acquire()) { if (true == _acquire()) {
@ -223,7 +223,7 @@ bool QSPI::_initialize()
return _initialized; return _initialized;
} }
qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode ); qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
if (QSPI_STATUS_OK == ret) { if (QSPI_STATUS_OK == ret) {
_initialized = true; _initialized = true;
} else { } else {
@ -247,7 +247,7 @@ bool QSPI::_acquire()
void QSPI::_build_qspi_command(int instruction, int address, int alt) void QSPI::_build_qspi_command(int instruction, int address, int alt)
{ {
memset( &_qspi_command, 0, sizeof(qspi_command_t) ); memset(&_qspi_command, 0, sizeof(qspi_command_t));
//Set up instruction phase parameters //Set up instruction phase parameters
_qspi_command.instruction.bus_width = _inst_width; _qspi_command.instruction.bus_width = _inst_width;
if (instruction != -1) { if (instruction != -1) {

5
drivers/QSPI.h
View File

@ -80,7 +80,7 @@ public:
* default value = 0 * default value = 0
* *
*/ */
QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel=NC, int mode=0); QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
/** Configure the data transmission format /** Configure the data transmission format
* *
@ -181,7 +181,8 @@ protected:
virtual void unlock(void); virtual void unlock(void);
public: public:
virtual ~QSPI() { virtual ~QSPI()
{
} }
protected: protected: