mirror of https://github.com/ARMmbed/mbed-os.git
Error resolve, bug fix and 2 new targets information add
1. Resolve the Error: L6218E: Undefined symbol flash_get_erase_value 2. Bug fix (ADC, USART, etc.) 3. Modify the wrong name (TATGET_GigaDevice-->TARGET_GigaDevice) 4. Add new targets (GD32-F450ZI and GD32-E103VB) support to target.json 5. Add INITIAL_SP macro for GD32-F450ZI and GD32-E103VBpull/8725/head
c_jin
parent
95f7a97a9b
commit
881561ac5e
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@ -43,9 +43,9 @@ typedef enum {
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UART_4 = (int)UART4
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UART_4 = (int)UART4
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} UARTName;
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} UARTName;
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#define STDIO_UART_TX PORTA_9
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#define STDIO_UART_TX PORTC_10
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#define STDIO_UART_RX PORTA_10
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#define STDIO_UART_RX PORTC_11
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#define STDIO_UART UART_0
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#define STDIO_UART UART_2
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typedef enum {
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typedef enum {
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SPI_0 = (int)SPI0,
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SPI_0 = (int)SPI0,
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@ -272,7 +272,7 @@ const PinMap PinMap_UART_TX[] = {
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{PORTB_10, UART_2, 7},
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{PORTB_10, UART_2, 7},
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{PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */
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{PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */
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{PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */
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{PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */
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{PORTC_10, UART_3, 7},
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{PORTC_10_MUL0, UART_3, 7},
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{PORTC_12, UART_4, 7},
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{PORTC_12, UART_4, 7},
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{NC, NC, 0}
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{NC, NC, 0}
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};
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};
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@ -284,8 +284,8 @@ const PinMap PinMap_UART_RX[] = {
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{PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */
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{PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */
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{PORTB_11, UART_2, 1},
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{PORTB_11, UART_2, 1},
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{PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */
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{PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */
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{PORTD_9, UART_2, 1 | (6 << 3)}, /* PGPIO_USART2_RX_PARTIAL_REMAP */
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{PORTD_9, UART_2, 1 | (6 << 3)}, /* GPIO_USART2_RX_FULL_REMAP */
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{PORTC_11, UART_3, 1},
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{PORTC_11_MUL0, UART_3, 1},
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{PORTD_2, UART_4, 1},
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{PORTD_2, UART_4, 1},
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{NC, NC, 0}
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{NC, NC, 0}
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};
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};
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@ -317,7 +317,7 @@ const PinMap PinMap_SPI_MOSI[] = {
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};
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};
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const PinMap PinMap_SPI_MISO[] = {
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const PinMap PinMap_SPI_MISO[] = {
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{PORTA_6, SPI_0, 1},
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{PORTA_6, SPI_0, 7},
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{PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
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{PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
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{PORTB_14, SPI_1, 7},
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{PORTB_14, SPI_1, 7},
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{NC, NC, 0}
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{NC, NC, 0}
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@ -102,7 +102,9 @@ typedef enum {
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PORTC_9 = 0x29,
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PORTC_9 = 0x29,
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PORTC_9_MUL0 = PORTC_9 | MUL0,
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PORTC_9_MUL0 = PORTC_9 | MUL0,
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PORTC_10 = 0x2A,
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PORTC_10 = 0x2A,
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PORTC_10_MUL0 = PORTC_10 | MUL0,
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PORTC_11 = 0x2B,
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PORTC_11 = 0x2B,
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PORTC_11_MUL0 = PORTC_11 | MUL0,
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PORTC_12 = 0x2C,
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PORTC_12 = 0x2C,
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PORTC_13 = 0x2D,
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PORTC_13 = 0x2D,
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PORTC_14 = 0x2E,
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PORTC_14 = 0x2E,
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@ -152,21 +154,19 @@ typedef enum {
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A1 = PORTC_1,
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A1 = PORTC_1,
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A2 = PORTC_2,
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A2 = PORTC_2,
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A3 = PORTC_3,
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A3 = PORTC_3,
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A4 = PORTC_4,
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A4 = PORTA_0,
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A4_I2C_SDA = PORTC_11,
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A5 = PORTB_1,
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A4_I2C_SCL = PORTC_10,
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A5 = PORTC_5,
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D0 = PORTA_3,
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D0 = PORTA_3,
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D1 = PORTA_2,
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D1 = PORTA_2,
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D2 = PORTA_4,
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D2 = PORTE_4,
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D3 = PORTC_6,
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D3 = PORTD_12,
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D4 = PORTB_3,
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D4 = PORTB_3,
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D5 = PORTC_7,
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D5 = PORTC_7,
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D6 = PORTC_8,
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D6 = PORTB_0,
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D7 = PORTB_4,
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D7 = PORTB_4,
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D8 = PORTB_5,
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D8 = PORTD_11,
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D9 = PORTC_9,
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D9 = PORTE_5,
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D10 = PORTA_1,
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D10 = PORTA_8,
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D11 = PORTB_15,
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D11 = PORTB_15,
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D12 = PORTB_14,
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D12 = PORTB_14,
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D13 = PORTB_13,
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D13 = PORTB_13,
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@ -177,29 +177,44 @@ typedef enum {
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LED2 = PORTE_1,
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LED2 = PORTE_1,
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LED3 = PORTE_6,
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LED3 = PORTE_6,
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KEY2 = PORTA_0,
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KEY1 = PORTE_2,
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KEY3 = PORTB_1,
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KEY2 = PORTE_7,
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BUTTON1 = KEY2,
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BUTTON1 = KEY1,
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BUTTON2 = KEY3,
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BUTTON2 = KEY2,
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SERIAL_TX = PORTA_9,
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SERIAL_TX = PORTC_10,
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SERIAL_RX = PORTA_10,
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SERIAL_RX = PORTC_11,
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USBTX = PORTA_9,
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USBTX = SERIAL_TX,
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USBRX = PORTA_10,
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USBRX = SERIAL_RX,
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I2C_SCL = PORTB_6,
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I2C_SCL = D15,
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I2C_SDA = PORTB_7,
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I2C_SDA = D14,
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SPI_MOSI = PORTA_7,
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SPI_MOSI = D11,
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SPI_MISO = PORTA_6,
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SPI_MISO = D12,
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SPI_SCK = PORTA_5,
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SPI_SCK = D13,
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SPI_CS = PORTE_3,
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SPI_CS = D10,
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PWM_OUT = PORTA_7,
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PWM_OUT = D9,
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USBFS_VBUS = PORTA_9,
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USBFS_DM = PORTA_11,
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USBFS_DP = PORTA_12,
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RMII_TX_EN = PORTB_11,
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RMII_TXD0 = PORTB_12,
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RMII_TXD1 = PORTB_13,
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RMII_RXD0 = PORTC_4,
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RMII_RXD1 = PORTC_5,
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RMII_CRS_DV = PORTA_7,
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RMII_MDC = PORTC_1,
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RMII_MDIO = PORTA_2,
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RMII_INT = PORTB_0,
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RMII_REF_CLK = PORTA_1,
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NC = (int)0xFFFFFFFF
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NC = (int)0xFFFFFFFF
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} PinName;
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} PinName;
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/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE, 5=PORTF)
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/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE)
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BIT[3:0] pin number */
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BIT[3:0] pin number */
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#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF)
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#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF)
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#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF))
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#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF))
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@ -208,7 +223,7 @@ typedef enum {
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#define GD_PIN_MODE_GET(X) (X & 0x07)
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#define GD_PIN_MODE_GET(X) (X & 0x07)
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#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03)
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#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03)
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#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F)
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#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F)
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#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x0F)
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#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x1F)
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/* Defines GPIO pin direction */
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/* Defines GPIO pin direction */
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typedef enum {
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typedef enum {
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@ -1,27 +1,27 @@
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#! armcc -E
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#! armcc -E
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; *************************************************************
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *** Scatter-Loading Description File generated by uVision ***
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; *****
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; *****
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#if !defined(MBED_APP_START)
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x08000000
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#define MBED_APP_START 0x08000000
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#endif
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#endif
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#if !defined(MBED_APP_SIZE)
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x100000
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#define MBED_APP_SIZE 0x100000
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#endif
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#endif
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*.o (RESET, +First)
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*(InRoot$$Sections)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+RO)
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}
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}
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; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
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; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
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RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
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RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
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.ANY (+RW +ZI)
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.ANY (+RW +ZI)
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}
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}
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}
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}
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@ -1,27 +1,27 @@
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#! armcc -E
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#! armcc -E
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; *************************************************************
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *** Scatter-Loading Description File generated by uVision ***
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; *****
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; *****
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#if !defined(MBED_APP_START)
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x08000000
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#define MBED_APP_START 0x08000000
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#endif
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#endif
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#if !defined(MBED_APP_SIZE)
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x100000
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#define MBED_APP_SIZE 0x100000
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#endif
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#endif
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*.o (RESET, +First)
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*(InRoot$$Sections)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+RO)
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}
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}
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; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
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; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
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RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
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RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
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.ANY (+RW +ZI)
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.ANY (+RW +ZI)
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}
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}
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}
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}
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@ -1,123 +1,123 @@
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/* specify memory regions */
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/* specify memory regions */
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MEMORY
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MEMORY
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{
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150
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RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150
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}
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}
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/* define output sections */
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/* define output sections */
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ENTRY(Reset_Handler)
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ENTRY(Reset_Handler)
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SECTIONS
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SECTIONS
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{
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{
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.text :
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.text :
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{
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{
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KEEP(*(.isr_vector))
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KEEP(*(.isr_vector))
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*(.text*)
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.init))
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KEEP(*(.fini))
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KEEP(*(.fini))
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/* .ctors */
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(SORT(.ctors.*))
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*(.ctors)
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*(.ctors)
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/* .dtors */
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(SORT(.dtors.*))
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*(.dtors)
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*(.dtors)
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*(.rodata*)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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KEEP(*(.eh_frame*))
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} > FLASH
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} > FLASH
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.ARM.extab :
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.ARM.extab :
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{
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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} > FLASH
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__exidx_start = .;
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__exidx_start = .;
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.ARM.exidx :
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.ARM.exidx :
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{
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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} > FLASH
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__exidx_end = .;
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__exidx_end = .;
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__etext = .;
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__etext = .;
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_sidata = .;
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_sidata = .;
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.data : AT (__etext)
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.data : AT (__etext)
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{
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{
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__data_start__ = .;
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__data_start__ = .;
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_sdata = .;
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_sdata = .;
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*(vtable)
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*(vtable)
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*(.data*)
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*(.data*)
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. = ALIGN(4);
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. = ALIGN(4);
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/* preinit data */
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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. = ALIGN(4);
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/* init data */
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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. = ALIGN(4);
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/* finit data */
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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PROVIDE_HIDDEN (__fini_array_end = .);
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|
||||||
KEEP(*(.jcr*))
|
KEEP(*(.jcr*))
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
/* All data end */
|
/* All data end */
|
||||||
__data_end__ = .;
|
__data_end__ = .;
|
||||||
_edata = .;
|
_edata = .;
|
||||||
|
|
||||||
} > RAM
|
} > RAM
|
||||||
|
|
||||||
.bss :
|
.bss :
|
||||||
{
|
{
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
__bss_start__ = .;
|
__bss_start__ = .;
|
||||||
_sbss = .;
|
_sbss = .;
|
||||||
*(.bss*)
|
*(.bss*)
|
||||||
*(COMMON)
|
*(COMMON)
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
__bss_end__ = .;
|
__bss_end__ = .;
|
||||||
_ebss = .;
|
_ebss = .;
|
||||||
} > RAM
|
} > RAM
|
||||||
|
|
||||||
.heap (COPY):
|
.heap (COPY):
|
||||||
{
|
{
|
||||||
__end__ = .;
|
__end__ = .;
|
||||||
end = __end__;
|
end = __end__;
|
||||||
*(.heap*)
|
*(.heap*)
|
||||||
__HeapLimit = .;
|
__HeapLimit = .;
|
||||||
} > RAM
|
} > RAM
|
||||||
|
|
||||||
.stack_dummy (COPY):
|
.stack_dummy (COPY):
|
||||||
{
|
{
|
||||||
*(.stack*)
|
*(.stack*)
|
||||||
} > RAM
|
} > RAM
|
||||||
|
|
||||||
/* initializes stack on the end of block */
|
/* initializes stack on the end of block */
|
||||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||||
_estack = __StackTop;
|
_estack = __StackTop;
|
||||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||||
PROVIDE(__stack = __StackTop);
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1,36 +1,36 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
/*-Editor annotation file-*/
|
/*-Editor annotation file-*/
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
|
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
|
||||||
/*-Specials-*/
|
/*-Specials-*/
|
||||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||||
/*-Memory Regions-*/
|
/*-Memory Regions-*/
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||||
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
|
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
|
||||||
define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F;
|
define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F;
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000150;
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000150;
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
||||||
/*-Sizes-*/
|
/*-Sizes-*/
|
||||||
/*Heap 1/4 of ram and stack 1/8*/
|
/*Heap 1/4 of ram and stack 1/8*/
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x3000;
|
define symbol __ICFEDIT_size_cstack__ = 0x3000;
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x6000;
|
define symbol __ICFEDIT_size_heap__ = 0x6000;
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
define memory mem with size = 4G;
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
initialize by copy { readwrite };
|
||||||
do not initialize { section .noinit };
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
place in ROM_region { readonly };
|
||||||
place in RAM_region { readwrite,
|
place in RAM_region { readwrite,
|
||||||
block HEAP, block CSTACK };
|
block HEAP, block CSTACK };
|
||||||
|
|
@ -1,386 +1,386 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f30x.h
|
\file gd32f30x.h
|
||||||
\brief general definitions for GD32F30x
|
\brief general definitions for GD32F30x
|
||||||
|
|
||||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
All rights reserved.
|
All rights reserved.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
list of conditions and the following disclaimer.
|
list of conditions and the following disclaimer.
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
this list of conditions and the following disclaimer in the documentation
|
this list of conditions and the following disclaimer in the documentation
|
||||||
and/or other materials provided with the distribution.
|
and/or other materials provided with the distribution.
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
may be used to endorse or promote products derived from this software without
|
may be used to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef GD32F30X_H
|
#ifndef GD32F30X_H
|
||||||
#define GD32F30X_H
|
#define GD32F30X_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* define GD32F30x */
|
/* define GD32F30x */
|
||||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||||
/* #define GD32F30X_HD */
|
/* #define GD32F30X_HD */
|
||||||
/* #define GD32F30X_XD */
|
/* #define GD32F30X_XD */
|
||||||
/* #define GD32F30X_CL */
|
/* #define GD32F30X_CL */
|
||||||
#endif /* define GD32F30x */
|
#endif /* define GD32F30x */
|
||||||
|
|
||||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||||
#error "Please select the target GD32F30x device in gd32f30x.h file"
|
#error "Please select the target GD32F30x device in gd32f30x.h file"
|
||||||
#endif /* undefine GD32F30x tip */
|
#endif /* undefine GD32F30x tip */
|
||||||
|
|
||||||
|
|
||||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||||
#if !defined HXTAL_VALUE
|
#if !defined HXTAL_VALUE
|
||||||
#ifdef GD32F30X_CL
|
#ifdef GD32F30X_CL
|
||||||
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
|
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
|
||||||
#else
|
#else
|
||||||
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
|
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
|
||||||
#endif /* HXTAL_VALUE */
|
#endif /* HXTAL_VALUE */
|
||||||
#endif /* high speed crystal oscillator value */
|
#endif /* high speed crystal oscillator value */
|
||||||
|
|
||||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
|
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
|
||||||
#endif /* high speed crystal oscillator startup timeout */
|
#endif /* high speed crystal oscillator startup timeout */
|
||||||
|
|
||||||
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
|
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
|
||||||
#if !defined (IRC48M_VALUE)
|
#if !defined (IRC48M_VALUE)
|
||||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||||
#endif /* internal 48MHz RC oscillator value */
|
#endif /* internal 48MHz RC oscillator value */
|
||||||
|
|
||||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||||
#if !defined (IRC8M_VALUE)
|
#if !defined (IRC8M_VALUE)
|
||||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||||
#endif /* internal 8MHz RC oscillator value */
|
#endif /* internal 8MHz RC oscillator value */
|
||||||
|
|
||||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||||
|
|
||||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||||
#if !defined (IRC40K_VALUE)
|
#if !defined (IRC40K_VALUE)
|
||||||
#define IRC40K_VALUE ((uint32_t)40000)
|
#define IRC40K_VALUE ((uint32_t)40000)
|
||||||
#endif /* internal 40KHz RC oscillator value */
|
#endif /* internal 40KHz RC oscillator value */
|
||||||
|
|
||||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||||
#if !defined (LXTAL_VALUE)
|
#if !defined (LXTAL_VALUE)
|
||||||
#define LXTAL_VALUE ((uint32_t)32768)
|
#define LXTAL_VALUE ((uint32_t)32768)
|
||||||
#endif /* low speed crystal oscillator value */
|
#endif /* low speed crystal oscillator value */
|
||||||
|
|
||||||
/* GD32F30x firmware library version number V1.0 */
|
/* GD32F30x firmware library version number V1.0 */
|
||||||
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||||
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||||
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||||
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|
||||||
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||||
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||||
|(__GD32F30x_STDPERIPH_VERSION_RC))
|
|(__GD32F30x_STDPERIPH_VERSION_RC))
|
||||||
|
|
||||||
/* configuration of the Cortex-M4 processor and core peripherals */
|
/* configuration of the Cortex-M4 processor and core peripherals */
|
||||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||||
#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */
|
#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */
|
||||||
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
|
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
|
||||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||||
/* define interrupt number */
|
/* define interrupt number */
|
||||||
typedef enum IRQn
|
typedef enum IRQn
|
||||||
{
|
{
|
||||||
/* Cortex-M4 processor exceptions numbers */
|
/* Cortex-M4 processor exceptions numbers */
|
||||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
|
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
|
||||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
|
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
|
||||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
|
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
|
||||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
|
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
|
||||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
|
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
|
||||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
|
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
|
||||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
|
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
|
||||||
/* interruput numbers */
|
/* interruput numbers */
|
||||||
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
|
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
|
||||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||||
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
|
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
|
||||||
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
|
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
|
||||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
||||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
||||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
||||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
||||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
||||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
|
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
|
||||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
|
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
|
||||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||||
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
|
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
|
||||||
#ifdef GD32F30X_HD
|
#ifdef GD32F30X_HD
|
||||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||||
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
|
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
|
||||||
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
|
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
|
||||||
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
|
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
|
||||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
||||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||||
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
|
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
|
||||||
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
|
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
|
||||||
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
|
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
|
||||||
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
|
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
|
||||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
|
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
|
||||||
#endif /* GD32F30X_HD */
|
#endif /* GD32F30X_HD */
|
||||||
|
|
||||||
#ifdef GD32F30X_XD
|
#ifdef GD32F30X_XD
|
||||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
|
TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
|
||||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||||
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
|
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
|
||||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
|
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
|
||||||
#endif /* GD32F30X_XD */
|
#endif /* GD32F30X_XD */
|
||||||
|
|
||||||
#ifdef GD32F30X_CL
|
#ifdef GD32F30X_CL
|
||||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
||||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||||
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
|
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
|
||||||
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||||
USBFS_IRQn = 67, /*!< USBFS global interrupt */
|
USBFS_IRQn = 67, /*!< USBFS global interrupt */
|
||||||
#endif /* GD32F30X_CL */
|
#endif /* GD32F30X_CL */
|
||||||
|
|
||||||
} IRQn_Type;
|
} IRQn_Type;
|
||||||
|
|
||||||
/* includes */
|
/* includes */
|
||||||
#include "core_cm4.h"
|
#include "core_cm4.h"
|
||||||
#include "system_gd32f30x.h"
|
#include "system_gd32f30x.h"
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#define GD_MBED_USED
|
#define GD_MBED_USED
|
||||||
|
|
||||||
#ifdef GD_MBED_USED
|
#ifdef GD_MBED_USED
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
GD_OK = 0x00U,
|
GD_OK = 0x00U,
|
||||||
GD_ERROR = 0x01U,
|
GD_ERROR = 0x01U,
|
||||||
GD_BUSY = 0x02U,
|
GD_BUSY = 0x02U,
|
||||||
GD_TIMEOUT = 0x03U
|
GD_TIMEOUT = 0x03U
|
||||||
}gd_status_enum;
|
}gd_status_enum;
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
OP_STATE_RESET = 0x00U,
|
OP_STATE_RESET = 0x00U,
|
||||||
OP_STATE_READY = 0x01U,
|
OP_STATE_READY = 0x01U,
|
||||||
OP_STATE_BUSY = 0x02U,
|
OP_STATE_BUSY = 0x02U,
|
||||||
OP_STATE_TIMEOUT = 0x03U,
|
OP_STATE_TIMEOUT = 0x03U,
|
||||||
OP_STATE_ERROR = 0x04U,
|
OP_STATE_ERROR = 0x04U,
|
||||||
OP_STATE_ABORT = 0x05U,
|
OP_STATE_ABORT = 0x05U,
|
||||||
OP_STATE_LISTEN = 0x06U,
|
OP_STATE_LISTEN = 0x06U,
|
||||||
|
|
||||||
OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
|
OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
|
||||||
OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
|
OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
|
||||||
|
|
||||||
OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
|
OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
|
||||||
OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
|
OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
|
||||||
|
|
||||||
OP_STATE_BUTT
|
OP_STATE_BUTT
|
||||||
}operation_state_enum;
|
}operation_state_enum;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* enum definitions */
|
/* enum definitions */
|
||||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||||
|
|
||||||
/* bit operations */
|
/* bit operations */
|
||||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||||
|
|
||||||
/* main flash and SRAM memory map */
|
/* main flash and SRAM memory map */
|
||||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||||
|
|
||||||
/* peripheral memory map */
|
/* peripheral memory map */
|
||||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||||
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
||||||
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
||||||
|
|
||||||
/* advanced peripheral bus 1 memory map */
|
/* advanced peripheral bus 1 memory map */
|
||||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||||
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
||||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
||||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||||
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
|
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
|
||||||
|
|
||||||
/* advanced peripheral bus 2 memory map */
|
/* advanced peripheral bus 2 memory map */
|
||||||
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
||||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
||||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||||
|
|
||||||
/* advanced high performance bus 1 memory map */
|
/* advanced high performance bus 1 memory map */
|
||||||
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
||||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
||||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
||||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
||||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
||||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
||||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
||||||
|
|
||||||
/* define marco USE_STDPERIPH_DRIVER */
|
/* define marco USE_STDPERIPH_DRIVER */
|
||||||
#if !defined USE_STDPERIPH_DRIVER
|
#if !defined USE_STDPERIPH_DRIVER
|
||||||
#define USE_STDPERIPH_DRIVER
|
#define USE_STDPERIPH_DRIVER
|
||||||
#endif
|
#endif
|
||||||
#ifdef USE_STDPERIPH_DRIVER
|
#ifdef USE_STDPERIPH_DRIVER
|
||||||
#include "gd32f30x_libopt.h"
|
#include "gd32f30x_libopt.h"
|
||||||
#endif /* USE_STDPERIPH_DRIVER */
|
#endif /* USE_STDPERIPH_DRIVER */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -1,65 +1,65 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f30x_libopt.h
|
\file gd32f30x_libopt.h
|
||||||
\brief library optional for gd32f30x
|
\brief library optional for gd32f30x
|
||||||
|
|
||||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
All rights reserved.
|
All rights reserved.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
list of conditions and the following disclaimer.
|
list of conditions and the following disclaimer.
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
this list of conditions and the following disclaimer in the documentation
|
this list of conditions and the following disclaimer in the documentation
|
||||||
and/or other materials provided with the distribution.
|
and/or other materials provided with the distribution.
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
may be used to endorse or promote products derived from this software without
|
may be used to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef GD32F30X_LIBOPT_H
|
#ifndef GD32F30X_LIBOPT_H
|
||||||
#define GD32F30X_LIBOPT_H
|
#define GD32F30X_LIBOPT_H
|
||||||
|
|
||||||
#include "gd32f30x_rcu.h"
|
#include "gd32f30x_rcu.h"
|
||||||
#include "gd32f30x_adc.h"
|
#include "gd32f30x_adc.h"
|
||||||
#include "gd32f30x_can.h"
|
#include "gd32f30x_can.h"
|
||||||
#include "gd32f30x_crc.h"
|
#include "gd32f30x_crc.h"
|
||||||
#include "gd32f30x_ctc.h"
|
#include "gd32f30x_ctc.h"
|
||||||
#include "gd32f30x_dac.h"
|
#include "gd32f30x_dac.h"
|
||||||
#include "gd32f30x_dbg.h"
|
#include "gd32f30x_dbg.h"
|
||||||
#include "gd32f30x_dma.h"
|
#include "gd32f30x_dma.h"
|
||||||
#include "gd32f30x_exti.h"
|
#include "gd32f30x_exti.h"
|
||||||
#include "gd32f30x_fmc.h"
|
#include "gd32f30x_fmc.h"
|
||||||
#include "gd32f30x_fwdgt.h"
|
#include "gd32f30x_fwdgt.h"
|
||||||
#include "gd32f30x_gpio.h"
|
#include "gd32f30x_gpio.h"
|
||||||
#include "gd32f30x_i2c.h"
|
#include "gd32f30x_i2c.h"
|
||||||
#include "gd32f30x_pmu.h"
|
#include "gd32f30x_pmu.h"
|
||||||
#include "gd32f30x_bkp.h"
|
#include "gd32f30x_bkp.h"
|
||||||
#include "gd32f30x_rtc.h"
|
#include "gd32f30x_rtc.h"
|
||||||
#include "gd32f30x_sdio.h"
|
#include "gd32f30x_sdio.h"
|
||||||
#include "gd32f30x_spi.h"
|
#include "gd32f30x_spi.h"
|
||||||
#include "gd32f30x_timer.h"
|
#include "gd32f30x_timer.h"
|
||||||
#include "gd32f30x_usart.h"
|
#include "gd32f30x_usart.h"
|
||||||
#include "gd32f30x_wwdgt.h"
|
#include "gd32f30x_wwdgt.h"
|
||||||
#include "gd32f30x_misc.h"
|
#include "gd32f30x_misc.h"
|
||||||
#include "gd32f30x_enet.h"
|
#include "gd32f30x_enet.h"
|
||||||
#include "gd32f30x_exmc.h"
|
#include "gd32f30x_exmc.h"
|
||||||
|
|
||||||
#endif /* GD32F30X_LIBOPT_H */
|
#endif /* GD32F30X_LIBOPT_H */
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,58 +1,58 @@
|
||||||
/*!
|
/*!
|
||||||
\file system_gd32f30x.h
|
\file system_gd32f30x.h
|
||||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||||
GD32F30x Device Series
|
GD32F30x Device Series
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Copyright (c) 2012 ARM LIMITED
|
/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
|
||||||
All rights reserved.
|
All rights reserved.
|
||||||
Redistribution and use in source and binary forms, with or without
|
Redistribution and use in source and binary forms, with or without
|
||||||
modification, are permitted provided that the following conditions are met:
|
modification, are permitted provided that the following conditions are met:
|
||||||
- Redistributions of source code must retain the above copyright
|
- Redistributions of source code must retain the above copyright
|
||||||
notice, this list of conditions and the following disclaimer.
|
notice, this list of conditions and the following disclaimer.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
notice, this list of conditions and the following disclaimer in the
|
notice, this list of conditions and the following disclaimer in the
|
||||||
documentation and/or other materials provided with the distribution.
|
documentation and/or other materials provided with the distribution.
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
to endorse or promote products derived from this software without
|
to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
*
|
*
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
---------------------------------------------------------------------------*/
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
#ifndef SYSTEM_GD32F30X_H
|
#ifndef SYSTEM_GD32F30X_H
|
||||||
#define SYSTEM_GD32F30X_H
|
#define SYSTEM_GD32F30X_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
/* system clock frequency (core clock) */
|
/* system clock frequency (core clock) */
|
||||||
extern uint32_t SystemCoreClock;
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* initialize the system and update the SystemCoreClock variable */
|
/* initialize the system and update the SystemCoreClock variable */
|
||||||
extern void SystemInit (void);
|
extern void SystemInit (void);
|
||||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||||
extern void SystemCoreClockUpdate (void);
|
extern void SystemCoreClockUpdate (void);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* SYSTEM_GD32F30X_H */
|
#endif /* SYSTEM_GD32F30X_H */
|
||||||
|
|
@ -89,7 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
|
||||||
adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1);
|
adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1);
|
||||||
adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE);
|
adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE);
|
||||||
adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE);
|
adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE);
|
||||||
adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
|
adc_external_trigger_config(obj->adc, ADC_REGULAR_CHANNEL, ENABLE);
|
||||||
adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
||||||
|
|
||||||
/* ADC enable */
|
/* ADC enable */
|
||||||
|
|
|
||||||
|
|
@ -192,4 +192,14 @@ uint32_t flash_get_size(const flash_t *obj)
|
||||||
return FLASH_SIZE;
|
return FLASH_SIZE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Get the flash erase value
|
||||||
|
*
|
||||||
|
* @param obj The flash object
|
||||||
|
* @return The flash erase value
|
||||||
|
*/
|
||||||
|
uint8_t flash_get_erase_value(const flash_t *obj)
|
||||||
|
{
|
||||||
|
return 0xFF;
|
||||||
|
}
|
||||||
|
|
||||||
#endif /* DEVICE_FLASH */
|
#endif /* DEVICE_FLASH */
|
||||||
|
|
|
||||||
|
|
@ -22,7 +22,7 @@
|
||||||
int mbed_sdk_inited = 0;
|
int mbed_sdk_inited = 0;
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -34,7 +34,7 @@ extern void ticker_32bits_timer_init(void);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
|
||||||
|
|
@ -177,7 +177,7 @@ void serial_baud(serial_t *obj, int baudrate)
|
||||||
struct serial_s *p_obj = GET_SERIAL_S(obj);
|
struct serial_s *p_obj = GET_SERIAL_S(obj);
|
||||||
|
|
||||||
/* store the UEN flag */
|
/* store the UEN flag */
|
||||||
uen_flag = USART_CTL0(USART0) & USART_CTL0_UEN;
|
uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN;
|
||||||
|
|
||||||
/* disable the USART clock first */
|
/* disable the USART clock first */
|
||||||
usart_disable(p_obj->uart);
|
usart_disable(p_obj->uart);
|
||||||
|
|
|
||||||
|
|
@ -27,7 +27,7 @@ extern void ticker_timer_data_restore(void);
|
||||||
extern int serial_busy_state_check(void);
|
extern int serial_busy_state_check(void);
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
|
||||||
|
|
@ -29,6 +29,22 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(TARGET_GD32E103VB)
|
||||||
|
|
||||||
|
#ifndef INITIAL_SP
|
||||||
|
#define INITIAL_SP (0x20008000UL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(TARGET_GD32F450ZI)
|
||||||
|
|
||||||
|
#ifndef INITIAL_SP
|
||||||
|
#define INITIAL_SP (0x20070000UL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS))
|
#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS))
|
||||||
extern uint32_t __StackLimit[];
|
extern uint32_t __StackLimit[];
|
||||||
extern uint32_t __StackTop[];
|
extern uint32_t __StackTop[];
|
||||||
|
|
|
||||||
|
|
@ -7438,7 +7438,8 @@
|
||||||
"USTICKER",
|
"USTICKER",
|
||||||
"ANALOGIN",
|
"ANALOGIN",
|
||||||
"INTERRUPTIN",
|
"INTERRUPTIN",
|
||||||
"PORTIN", "PORTINOUT",
|
"PORTIN",
|
||||||
|
"PORTINOUT",
|
||||||
"PORTOUT",
|
"PORTOUT",
|
||||||
"PWMOUT",
|
"PWMOUT",
|
||||||
"SERIAL"
|
"SERIAL"
|
||||||
|
|
@ -7470,5 +7471,57 @@
|
||||||
"overrides": {
|
"overrides": {
|
||||||
"network-default-interface-type": "ETHERNET"
|
"network-default-interface-type": "ETHERNET"
|
||||||
}
|
}
|
||||||
|
},
|
||||||
|
"GD32_F450ZI": {
|
||||||
|
"inherits": ["GD32_Target"],
|
||||||
|
"supported_form_factors": ["ARDUINO"],
|
||||||
|
"core": "Cortex-M4",
|
||||||
|
"extra_labels_add": ["GD32F4XX", "GD32F450ZI", "GD_EMAC"],
|
||||||
|
"device_has_add": [
|
||||||
|
"RTC",
|
||||||
|
"I2C",
|
||||||
|
"CAN",
|
||||||
|
"I2CSLAVE",
|
||||||
|
"ANALOGOUT",
|
||||||
|
"SPI",
|
||||||
|
"SPISLAVE",
|
||||||
|
"SERIAL_ASYNCH",
|
||||||
|
"SERIAL_FC",
|
||||||
|
"EMAC",
|
||||||
|
"FLASH",
|
||||||
|
"SLEEP",
|
||||||
|
"MPU",
|
||||||
|
"TRNG",
|
||||||
|
"LPTICKER"
|
||||||
|
],
|
||||||
|
"device_name": "GD32F450ZI",
|
||||||
|
"detect_code": ["1702"],
|
||||||
|
"macros_add": ["GD32F450"],
|
||||||
|
"release_versions": ["5"],
|
||||||
|
"overrides": {
|
||||||
|
"network-default-interface-type": "ETHERNET"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"GD32_E103VB": {
|
||||||
|
"inherits": ["GD32_Target"],
|
||||||
|
"supported_form_factors": ["ARDUINO"],
|
||||||
|
"core": "Cortex-M23",
|
||||||
|
"extra_labels_add": ["GD32E10X", "GD32E103VB"],
|
||||||
|
"device_has_add": [
|
||||||
|
"RTC",
|
||||||
|
"I2C",
|
||||||
|
"CAN",
|
||||||
|
"I2CSLAVE",
|
||||||
|
"ANALOGOUT",
|
||||||
|
"SPI",
|
||||||
|
"SPISLAVE",
|
||||||
|
"SERIAL_ASYNCH",
|
||||||
|
"SERIAL_FC",
|
||||||
|
"FLASH",
|
||||||
|
"SLEEP"
|
||||||
|
],
|
||||||
|
"detect_code": ["1703"],
|
||||||
|
"macros_add": ["GD32E10X"],
|
||||||
|
"release_versions": ["5"]
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue