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Merge pull request #14348 from harmut01/baremetal_arm_fm 

Add bare metal support to ARM FM targets
pull/14374/head
Martin Kojtal 2021-03-03 08:54:42 +00:00 committed by GitHub
parent 876032b818 3c57f384b1
commit 87cededeee
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 102 additions and 57 deletions
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29
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -52,17 +52,24 @@
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

29
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -52,17 +52,24 @@
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

29
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -52,17 +52,24 @@
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

29
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -52,17 +52,24 @@
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

29
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -52,17 +52,24 @@
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#endif
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

14
targets/targets.json
View File

@ -6545,8 +6545,7 @@
"public": false,
"supported_toolchains": [
"GCC_ARM",
"ARM",
"IAR"
"ARM"
],
"OUTPUT_EXT": "elf",
"device_has": [
@ -6578,6 +6577,17 @@
],
"overrides": {
"network-default-interface-type": "ETHERNET"
},
"supported_application_profiles" : ["full", "bare-metal"],
"supported_c_libs": {
"arm": [
"std",
"small"
],
"gcc_arm": [
"std",
"small"
]
}
},
"FVP_MPS2_M0": {