diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
index 965a2d7c2d..7e06c7d938 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
@@ -64,7 +64,6 @@
   */
 
 #include "stm32f4xx_hal.h"
-#include "error.h" /* [ADDED FOR MBED] */
 
 /**
   * @}
@@ -292,7 +291,11 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLQ            = 7;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
-    error("System clock initialization failed.");
+    // System clock initialization failed
+    while(1)
+    {
+      // [TODO] Put something here to tell the user that a problem occured...
+    }
   }
  
   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
@@ -303,7 +306,11 @@ void SystemClock_Config(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;   // 84 MHz (SPI1 clock...)
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
   {
-    error("System clock initialization failed.");
+    // System clock initialization failed
+    while(1)
+    {
+      // [TODO] Put something here to tell the user that a problem occured...
+    }
   }
 
   /* Update the SystemCoreClock variable