mirror of https://github.com/ARMmbed/mbed-os.git
Resolved review comments
parent
d4eba5c0a7
commit
8622f66b46
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@ -31,35 +31,14 @@
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namespace mbed {
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class RawCAN: public CAN {
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public:
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RawCAN(PinName rd, PinName td);
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using CAN::CAN;
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/** Initialize CAN interface and set the frequency
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*
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* @param rd the read pin
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* @param td the transmit pin
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* @param hz the bus frequency in hertz
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*/
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RawCAN(PinName rd, PinName td, int hz);
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/** Initialize CAN interface
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*
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* @param pinmap reference to structure which holds static pinmap
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* @param td the transmit pin
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* @param hz the bus frequency in hertz
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/** Overriding lock apis to create unlocked CAN
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*/
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virtual ~RawCAN() {};
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void lock() override {};
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void unlock() override {};
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/** Read a CANMessage from the bus.
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*
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* @param msg A CANMessage to read to.
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* @param handle message filter handle (0 for any message)
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*
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* @returns
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* 0 if no message arrived,
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* 1 if message arrived
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*/
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int read(CANMessage &msg, int handle = 0);
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};
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}
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@ -1,43 +0,0 @@
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/*
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* Copyright (C) 2021, STMicroelectronics, All Rights Reserved
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "drivers/RawCan.h"
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#if DEVICE_CAN
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#include "platform/mbed_power_mgmt.h"
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namespace mbed {
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RawCAN::RawCAN(PinName rd, PinName td): CAN(rd, td) {}
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RawCAN::RawCAN(PinName rd, PinName td, int hz): CAN(rd, td, hz) {}
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/* There are situations where the RX interrupt of CAN are cleared only by
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* CAN read operations and locks are not allowed in ISR context in mbed
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* hence this provides an unlocked read to resolve such problem without
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* any effect on the performance. This will work only in case of a single
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* thread accessing a CAN instance, multiple threads will lead to race conditions
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*/
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int RawCAN::read(CANMessage &msg, int handle)
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{
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int ret = can_read(&_can, &msg, handle);
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return ret;
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}
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}
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#endif //DEVICE_CAN
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@ -155,7 +155,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -145,7 +145,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -154,7 +154,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -142,7 +142,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -157,7 +157,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -166,7 +166,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -156,7 +156,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -156,7 +156,7 @@ struct can_s {
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CAN_HandleTypeDef CanHandle;
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int index;
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int hz;
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int rxIrqStatus;
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int rxIrqEnabled;
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};
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#endif
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@ -778,7 +778,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
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{
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irq_handler = handler;
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can_irq_ids[obj->index] = id;
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obj->rxIrqStatus = false;
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obj->rxIrqEnabled = false;
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}
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void can_irq_free(can_t *obj)
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@ -788,7 +788,7 @@ void can_irq_free(can_t *obj)
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can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
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CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
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can_irq_ids[obj->index] = 0;
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obj->rxIrqStatus = DISABLED;
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obj->rxIrqEnabled = false;
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}
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void can_free(can_t *obj)
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@ -1014,7 +1014,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
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/* Release the FIFO */
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can->RF0R |= CAN_RF0R_RFOM0;
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if(obj->rxIrqStatus == ENABLED) {
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if(obj->rxIrqEnabled == true) {
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__HAL_CAN_ENABLE_IT(&obj->CanHandle, CAN_IT_FMP0);
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}
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@ -1031,7 +1031,7 @@ void can_reset(can_t *obj)
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/* restore registers state as saved in obj context */
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can_registers_init(obj);
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obj->rxIrqStatus = DISABLED;
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obj->rxIrqEnabled = false;
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}
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unsigned char can_rderror(can_t *obj)
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@ -1184,7 +1184,7 @@ static void can_irq(CANName name, int id)
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tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
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tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
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// In legacy can, reading is the only way to clear rx interrupt. But can_read has mutex locks
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// In legacy can (bxCAN and earlier), reading is the only way to clear rx interrupt. But can_read has mutex locks
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// since mutexes cannot be used in ISR context, rx interrupt is masked here to temporary disable it
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// rx interrupts will be unamsked in read operation. reads must be deffered to thread context.
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__HAL_CAN_DISABLE_IT(&CanHandle, CAN_IT_FMP0);
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@ -1288,7 +1288,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
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ier = CAN_IT_FMP0;
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irq_n = CAN1_IRQ_RX_IRQN;
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vector = (uint32_t)&CAN1_IRQ_RX_VECT;
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obj->rxIrqStatus = ENABLED;
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obj->rxIrqEnabled = true;
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break;
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case IRQ_TX:
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ier = CAN_IT_TME;
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@ -1321,7 +1321,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
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ier = CAN_IT_FMP0;
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irq_n = CAN2_IRQ_RX_IRQN;
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vector = (uint32_t)&CAN2_IRQ_RX_VECT;
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obj->rxIrqStatus = ENABLED;
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obj->rxIrqEnabled = true;
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break;
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case IRQ_TX:
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ier = CAN_IT_TME;
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@ -1355,7 +1355,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
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ier = CAN_IT_FMP0;
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irq_n = CAN3_IRQ_RX_IRQN;
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vector = (uint32_t)&CAN3_IRQ_RX_VECT;
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obj->rxIrqStatus = ENABLED;
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obj->rxIrqEnabled = true;
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break;
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case IRQ_TX:
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ier = CAN_IT_TME;
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