mirror of https://github.com/ARMmbed/mbed-os.git
code formating, CR changes corrected spi_init() to properly handle re-initialization… #3842
parent
afdbcd3db9
commit
842bfc70f7
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@ -49,28 +49,33 @@ extern "C" {
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#define STDIO_UART_RX RX_PIN_NUMBER
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#define STDIO_UART UART_0
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typedef enum {
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typedef enum
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{
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UART_0 = (int)NRF_UART0_BASE
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} UARTName;
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typedef enum {
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typedef enum
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{
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SPI_0 = (int)NRF_SPI0_BASE,
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SPI_1 = (int)NRF_SPI1_BASE,
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SPIS = (int)NRF_SPIS1_BASE
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} SPIName;
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typedef enum {
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typedef enum
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{
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PWM_1 = 0,
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PWM_2
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} PWMName;
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typedef enum {
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typedef enum
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{
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I2C_0 = (int)NRF_TWI0_BASE,
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I2C_1 = (int)NRF_TWI1_BASE
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} I2CName;
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typedef enum {
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typedef enum
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{
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ADC0_0 = (int)0
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} ADCName;
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@ -43,7 +43,8 @@
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extern "C" {
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#endif
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typedef enum {
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typedef enum
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{
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Port0 = 0, //GPIO pins 0-31 -> 0.0-0.31
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Port1 = 1 //GPIO pins 32-47 -> 1.0-1.15
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} PortName;
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@ -29,7 +29,8 @@
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#error not recognized gpio count for mcu
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#endif
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typedef struct {
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typedef struct
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{
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bool used_as_gpio : 1;
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PinDirection direction : 1;
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bool init_high : 1;
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@ -45,8 +46,8 @@ typedef struct {
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typedef uint32_t gpio_mask_t;
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#endif
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gpio_mask_t m_gpio_initialized;
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gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT];
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static gpio_mask_t m_gpio_initialized;
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static gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT];
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/***********
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@ -54,20 +55,22 @@ gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT];
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***********/
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static gpio_irq_handler m_irq_handler;
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static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0};
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gpio_mask_t m_gpio_irq_enabled;
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static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0};
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static gpio_mask_t m_gpio_irq_enabled;
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static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
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{
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nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin);
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gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL;
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if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) {
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if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin))
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{
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if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise)
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|| ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) {
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m_irq_handler(m_channel_ids[pin], event);
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}
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|| ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall))
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{
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m_irq_handler(m_channel_ids[pin], event);
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}
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}
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}
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@ -76,7 +79,8 @@ void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c
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void gpio_init(gpio_t *obj, PinName pin)
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{
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obj->pin = pin;
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if (pin == (PinName)NC) {
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if (pin == (PinName)NC)
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{
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return;
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}
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MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
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@ -92,20 +96,26 @@ void gpio_init(gpio_t *obj, PinName pin)
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int gpio_read(gpio_t *obj)
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{
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MBED_ASSERT(obj->pin != (PinName)NC);
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if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT) {
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if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT)
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{
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return (nrf_gpio_pin_out_read(obj->pin) ? 1 : 0);
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} else {
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}
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else
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{
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return nrf_gpio_pin_read(obj->pin);
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}
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}
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static void gpiote_pin_uninit(uint8_t pin)
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{
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if (m_gpio_initialized & ((gpio_mask_t)1 << pin)) {
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if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) {
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if (m_gpio_initialized & ((gpio_mask_t)1 << pin))
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{
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if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq))
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{
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nrf_drv_gpiote_out_uninit(pin);
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}
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else {
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else
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{
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nrf_drv_gpiote_in_uninit(pin);
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}
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}
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@ -113,16 +123,19 @@ static void gpiote_pin_uninit(uint8_t pin)
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static void gpio_apply_config(uint8_t pin)
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{
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if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq) {
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if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq)
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{
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if ((m_gpio_cfg[pin].direction == PIN_INPUT)
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|| (m_gpio_cfg[pin].used_as_irq)) {
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|| (m_gpio_cfg[pin].used_as_irq))
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{
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//Configure as input.
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nrf_drv_gpiote_in_config_t cfg;
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cfg.hi_accuracy = false;
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cfg.is_watcher = false;
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cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE;
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if (m_gpio_cfg[pin].used_as_irq) {
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if (m_gpio_cfg[pin].used_as_irq)
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{
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cfg.pull = NRF_GPIO_PIN_PULLUP;
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nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler);
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if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin))
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@ -131,8 +144,10 @@ static void gpio_apply_config(uint8_t pin)
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nrf_drv_gpiote_in_event_enable(pin, true);
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}
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}
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else {
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switch(m_gpio_cfg[pin].pull) {
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else
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{
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switch (m_gpio_cfg[pin].pull)
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{
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case PullUp:
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cfg.pull = NRF_GPIO_PIN_PULLUP;
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break;
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@ -146,14 +161,16 @@ static void gpio_apply_config(uint8_t pin)
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nrf_drv_gpiote_in_init(pin, &cfg, NULL);
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}
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}
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else {
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else
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{
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// Configure as output.
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nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high);
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nrf_drv_gpiote_out_init(pin, &cfg);
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}
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m_gpio_initialized |= ((gpio_mask_t)1 << pin);
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}
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else {
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else
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{
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m_gpio_initialized &= ~((gpio_mask_t)1 << pin);
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}
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}
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@ -161,7 +178,7 @@ static void gpio_apply_config(uint8_t pin)
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void gpio_mode(gpio_t *obj, PinMode mode)
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{
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MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT);
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MBED_ASSERT(obj->pin != (PinName)NC);
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gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change.
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@ -172,7 +189,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
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void gpio_dir(gpio_t *obj, PinDirection direction)
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{
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MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT);
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MBED_ASSERT(obj->pin != (PinName)NC);
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gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change.
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@ -187,7 +204,8 @@ void gpio_dir(gpio_t *obj, PinDirection direction)
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int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
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{
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if (pin == NC) {
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if (pin == NC)
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{
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return -1;
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}
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MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
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@ -223,19 +241,25 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
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(m_gpio_irq_enabled & ((gpio_mask_t)1 << obj->ch)) &&
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(cfg->irq_rise || cfg->irq_fall);
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if (event == IRQ_RISE) {
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if (event == IRQ_RISE)
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{
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cfg->irq_rise = enable ? true : false;
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}
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else if (event == IRQ_FALL) {
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else if (event == IRQ_FALL)
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{
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cfg->irq_fall = enable ? true : false;
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}
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bool irq_enabled_after = cfg->irq_rise || cfg->irq_fall;
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if (irq_enabled_before != irq_enabled_after) {
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if (irq_enabled_after) {
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if (irq_enabled_before != irq_enabled_after)
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{
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if (irq_enabled_after)
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{
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gpio_irq_enable(obj);
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} else {
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}
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else
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{
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gpio_irq_disable(obj);
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}
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}
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@ -245,7 +269,8 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
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void gpio_irq_enable(gpio_irq_t *obj)
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{
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m_gpio_irq_enabled |= ((gpio_mask_t)1 << obj->ch);
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if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) {
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if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall)
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{
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nrf_drv_gpiote_in_event_enable(obj->ch, true);
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}
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}
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@ -24,20 +24,26 @@
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extern "C" {
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#endif
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typedef struct {
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typedef struct
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{
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PinName pin;
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} gpio_t;
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static inline void gpio_write(gpio_t *obj, int value) {
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static inline void gpio_write(gpio_t *obj, int value)
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{
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MBED_ASSERT(obj->pin != (PinName)NC);
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if (value) {
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if (value)
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{
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nrf_gpio_pin_set(obj->pin);
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} else {
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}
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else
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{
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nrf_gpio_pin_clear(obj->pin);
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}
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}
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static inline int gpio_is_connected(const gpio_t *obj) {
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static inline int gpio_is_connected(const gpio_t *obj)
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{
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return obj->pin != (PinName)NC;
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}
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@ -101,18 +101,18 @@ void SPI1_TWI1_IRQHandler(void);
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static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] =
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{
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#if TWI0_ENABLED
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#if TWI0_ENABLED
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{
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SPI0_TWI0_IRQn,
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(uint32_t) SPI0_TWI0_IRQHandler
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},
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#endif
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#if TWI1_ENABLED
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#endif
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#if TWI1_ENABLED
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{
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SPI1_TWI1_IRQn,
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(uint32_t) SPI1_TWI1_IRQHandler
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}
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#endif
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#endif
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};
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#ifdef NRF51
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#define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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@ -124,9 +124,12 @@ static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] =
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#if DEVICE_I2C_ASYNCH
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static void start_asynch_rx(twi_info_t *twi_info, NRF_TWI_Type *twi)
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{
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if (twi_info->rx_length == 1 && twi_info->stop) {
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if (twi_info->rx_length == 1 && twi_info->stop)
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{
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nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
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} else {
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}
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else
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{
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nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
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}
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nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX);
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@ -137,7 +140,8 @@ static void twi_irq_handler(uint8_t instance_idx)
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twi_info_t *twi_info = &m_twi_info[instance_idx];
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NRF_TWI_Type *twi = m_twi_instances[instance_idx];
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) {
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
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{
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nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
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// In case of an error, force STOP.
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@ -148,33 +152,44 @@ static void twi_irq_handler(uint8_t instance_idx)
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uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
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twi_info->events |= I2C_EVENT_ERROR;
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if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) {
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if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
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{
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twi_info->events |= I2C_EVENT_ERROR_NO_SLAVE;
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}
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if (errorsrc & NRF_TWI_ERROR_DATA_NACK) {
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if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
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{
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twi_info->events |= I2C_EVENT_TRANSFER_EARLY_NACK;
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}
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}
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bool finished = false;
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) {
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT))
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{
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nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
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MBED_ASSERT(twi_info->tx_length > 0);
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--(twi_info->tx_length);
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// Send next byte if there is still something to be sent.
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if (twi_info->tx_length > 0) {
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if (twi_info->tx_length > 0)
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{
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nrf_twi_txd_set(twi, *(twi_info->tx));
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++(twi_info->tx);
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// It TX is done, start RX if requested.
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} else if (twi_info->rx_length > 0) {
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// It TX is done, start RX if requested.
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}
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else if (twi_info->rx_length > 0)
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{
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start_asynch_rx(twi_info, twi);
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// If there is nothing more to do, finalize the transfer.
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} else {
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if (twi_info->stop) {
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// If there is nothing more to do, finalize the transfer.
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}
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else
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{
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if (twi_info->stop)
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{
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nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
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} else {
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}
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else
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{
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nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
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finished = true;
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}
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@ -182,7 +197,8 @@ static void twi_irq_handler(uint8_t instance_idx)
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}
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}
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) {
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if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY))
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{
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nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
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MBED_ASSERT(twi_info->rx_length > 0);
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@ -190,15 +206,19 @@ static void twi_irq_handler(uint8_t instance_idx)
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++(twi_info->rx);
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--(twi_info->rx_length);
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if (twi_info->rx_length > 0) {
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if (twi_info->rx_length > 0)
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{
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// If more bytes should be received, resume the transfer
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// (in case the stop condition should be generated after the next
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// byte, change the shortcuts configuration first).
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if (twi_info->rx_length == 1 && twi_info->stop) {
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if (twi_info->rx_length == 1 && twi_info->stop)
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{
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nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
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}
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nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
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} else {
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}
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else
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{
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// If all requested bytes were received, finalize the transfer.
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finished = true;
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twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE;
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@ -208,7 +228,8 @@ static void twi_irq_handler(uint8_t instance_idx)
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if (finished ||
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nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED) ||
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(nrf_twi_int_enable_check(twi, NRF_TWI_INT_SUSPENDED_MASK) &&
|
||||
nrf_twi_event_check(twi, NRF_TWI_EVENT_SUSPENDED))) {
|
||||
nrf_twi_event_check(twi, NRF_TWI_EVENT_SUSPENDED)))
|
||||
{
|
||||
// There is no need to clear the STOPPED and SUSPENDED events here,
|
||||
// they will no longer generate the interrupt - see below.
|
||||
|
||||
|
@ -217,7 +238,8 @@ static void twi_irq_handler(uint8_t instance_idx)
|
|||
nrf_twi_int_disable(twi, UINT32_MAX);
|
||||
twi_info->active = false;
|
||||
|
||||
if (twi_info->handler) {
|
||||
if (twi_info->handler)
|
||||
{
|
||||
twi_info->handler();
|
||||
}
|
||||
}
|
||||
|
@ -264,13 +286,16 @@ static void twi_clear_bus(twi_info_t *twi_info)
|
|||
configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_OUTPUT);
|
||||
// In case SDA is low, make up to 9 cycles on SCL line to help the slave
|
||||
// that pulls SDA low release it.
|
||||
if (!nrf_gpio_pin_read(twi_info->pselsda)) {
|
||||
if (!nrf_gpio_pin_read(twi_info->pselsda))
|
||||
{
|
||||
nrf_gpio_pin_set(twi_info->pselscl);
|
||||
configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_OUTPUT);
|
||||
nrf_delay_us(4);
|
||||
|
||||
for (int i = 0; i < 9; i++) {
|
||||
if (nrf_gpio_pin_read(twi_info->pselsda)) {
|
||||
for (int i = 0; i < 9; i++)
|
||||
{
|
||||
if (nrf_gpio_pin_read(twi_info->pselsda))
|
||||
{
|
||||
break;
|
||||
}
|
||||
nrf_gpio_pin_clear(twi_info->pselscl);
|
||||
|
@ -289,10 +314,13 @@ static void twi_clear_bus(twi_info_t *twi_info)
|
|||
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < TWI_COUNT; ++i) {
|
||||
|
||||
for (i = 0; i < TWI_COUNT; ++i)
|
||||
{
|
||||
if (m_twi_info[i].initialized &&
|
||||
m_twi_info[i].pselsda == (uint32_t)sda &&
|
||||
m_twi_info[i].pselscl == (uint32_t)scl) {
|
||||
m_twi_info[i].pselscl == (uint32_t)scl)
|
||||
{
|
||||
TWI_IDX(obj) = i;
|
||||
TWI_INFO(obj)->frequency = NRF_TWI_FREQ_100K;
|
||||
i2c_reset(obj);
|
||||
|
@ -300,8 +328,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
|||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < TWI_COUNT; ++i) {
|
||||
if (!m_twi_info[i].initialized) {
|
||||
for (i = 0; i < TWI_COUNT; ++i)
|
||||
{
|
||||
if (!m_twi_info[i].initialized)
|
||||
{
|
||||
TWI_IDX(obj) = i;
|
||||
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
|
@ -350,7 +380,8 @@ int i2c_start(i2c_t *obj)
|
|||
{
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
if (twi_info->active) {
|
||||
if (twi_info->active)
|
||||
{
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
@ -368,11 +399,15 @@ int i2c_stop(i2c_t *obj)
|
|||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
|
||||
uint32_t remaining_time = TIMEOUT_VALUE;
|
||||
do {
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED)) {
|
||||
|
||||
do
|
||||
{
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
} while (--remaining_time);
|
||||
}
|
||||
while (--remaining_time);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
@ -382,11 +417,16 @@ void i2c_frequency(i2c_t *obj, int hz)
|
|||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
|
||||
|
||||
if (hz < 250000) {
|
||||
if (hz < 250000)
|
||||
{
|
||||
twi_info->frequency = NRF_TWI_FREQ_100K;
|
||||
} else if (hz < 400000) {
|
||||
}
|
||||
else if (hz < 400000)
|
||||
{
|
||||
twi_info->frequency = NRF_TWI_FREQ_250K;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
twi_info->frequency = NRF_TWI_FREQ_400K;
|
||||
}
|
||||
nrf_twi_frequency_set(twi, twi_info->frequency);
|
||||
|
@ -422,7 +462,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
|||
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
if (twi_info->active) {
|
||||
if (twi_info->active)
|
||||
{
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
@ -432,9 +473,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
|||
start_twi_read(twi, address);
|
||||
|
||||
int result = length;
|
||||
while (length > 0) {
|
||||
|
||||
while (length > 0)
|
||||
{
|
||||
int byte_read_result = i2c_byte_read(obj, (stop && length == 1));
|
||||
if (byte_read_result < 0) {
|
||||
if (byte_read_result < 0)
|
||||
{
|
||||
// When an error occurs, return the number of bytes that have been
|
||||
// received successfully.
|
||||
result -= length;
|
||||
|
@ -446,7 +490,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
|||
--length;
|
||||
}
|
||||
|
||||
if (stop) {
|
||||
if (stop)
|
||||
{
|
||||
(void)i2c_stop(obj);
|
||||
}
|
||||
|
||||
|
@ -460,16 +505,21 @@ static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data)
|
|||
|
||||
nrf_twi_txd_set(twi, data);
|
||||
uint32_t remaining_time = TIMEOUT_VALUE;
|
||||
do {
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) {
|
||||
|
||||
do
|
||||
{
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT))
|
||||
{
|
||||
nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
|
||||
return 1; // ACK received
|
||||
}
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) {
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
|
||||
{
|
||||
nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
|
||||
return 0; // some error occurred
|
||||
}
|
||||
} while (--remaining_time);
|
||||
}
|
||||
while (--remaining_time);
|
||||
|
||||
return 2; // timeout;
|
||||
}
|
||||
|
@ -492,7 +542,8 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
|||
{
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
if (twi_info->active) {
|
||||
if (twi_info->active)
|
||||
{
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
@ -503,26 +554,36 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
|||
|
||||
// Special case - transaction with no data.
|
||||
// It can be used to check if a slave acknowledges the address.
|
||||
if (length == 0) {
|
||||
if (length == 0)
|
||||
{
|
||||
nrf_twi_event_t event;
|
||||
if (stop) {
|
||||
if (stop)
|
||||
{
|
||||
event = NRF_TWI_EVENT_STOPPED;
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
event = NRF_TWI_EVENT_SUSPENDED;
|
||||
nrf_twi_event_clear(twi, event);
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
|
||||
}
|
||||
uint32_t remaining_time = TIMEOUT_VALUE;
|
||||
do {
|
||||
if (nrf_twi_event_check(twi, event)) {
|
||||
|
||||
do
|
||||
{
|
||||
if (nrf_twi_event_check(twi, event))
|
||||
{
|
||||
break;
|
||||
}
|
||||
} while (--remaining_time);
|
||||
}
|
||||
while (--remaining_time);
|
||||
|
||||
uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
|
||||
if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) {
|
||||
if (!stop) {
|
||||
if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
|
||||
{
|
||||
if (!stop)
|
||||
{
|
||||
i2c_stop(obj);
|
||||
}
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
|
@ -532,20 +593,29 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
|||
}
|
||||
|
||||
int result = length;
|
||||
do {
|
||||
|
||||
do
|
||||
{
|
||||
uint8_t byte_write_result = twi_byte_write(twi, (uint8_t)*data++);
|
||||
if (byte_write_result != 1) {
|
||||
if (byte_write_result == 0) {
|
||||
if (byte_write_result != 1)
|
||||
{
|
||||
if (byte_write_result == 0)
|
||||
{
|
||||
// Check what kind of error has been signaled by TWI.
|
||||
uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
|
||||
if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) {
|
||||
if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
|
||||
{
|
||||
result = I2C_ERROR_NO_SLAVE;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
// Some other error - return the number of bytes that
|
||||
// have been sent successfully.
|
||||
result -= length;
|
||||
}
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
result = I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
// Force STOP condition.
|
||||
|
@ -553,9 +623,11 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
|||
break;
|
||||
}
|
||||
--length;
|
||||
} while (length > 0);
|
||||
}
|
||||
while (length > 0);
|
||||
|
||||
if (stop) {
|
||||
if (stop)
|
||||
{
|
||||
(void)i2c_stop(obj);
|
||||
}
|
||||
|
||||
|
@ -566,22 +638,28 @@ int i2c_byte_read(i2c_t *obj, int last)
|
|||
{
|
||||
NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
|
||||
|
||||
if (last) {
|
||||
if (last)
|
||||
{
|
||||
nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
|
||||
}
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
|
||||
|
||||
uint32_t remaining_time = TIMEOUT_VALUE;
|
||||
do {
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) {
|
||||
|
||||
do
|
||||
{
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY))
|
||||
{
|
||||
nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
|
||||
return nrf_twi_rxd_get(twi);
|
||||
}
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) {
|
||||
if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
|
||||
{
|
||||
nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
} while (--remaining_time);
|
||||
}
|
||||
while (--remaining_time);
|
||||
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
@ -590,16 +668,22 @@ int i2c_byte_write(i2c_t *obj, int data)
|
|||
{
|
||||
NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
if (twi_info->start_twi) {
|
||||
if (twi_info->start_twi)
|
||||
{
|
||||
twi_info->start_twi = false;
|
||||
|
||||
if (data & 1) {
|
||||
if (data & 1)
|
||||
{
|
||||
start_twi_read(twi, data);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
start_twi_write(twi, data);
|
||||
}
|
||||
return 1;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
|
||||
// 0 - TWI signaled error (NAK is the only possibility here)
|
||||
// 1 - ACK received
|
||||
|
@ -618,7 +702,8 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length,
|
|||
(void)hint;
|
||||
|
||||
twi_info_t *twi_info = TWI_INFO(obj);
|
||||
if (twi_info->active) {
|
||||
if (twi_info->active)
|
||||
{
|
||||
return;
|
||||
}
|
||||
twi_info->active = true;
|
||||
|
@ -643,21 +728,29 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length,
|
|||
nrf_twi_address_set(twi, twi_address(address));
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
|
||||
// TX only, or TX + RX (after a repeated start).
|
||||
if (tx_length > 0) {
|
||||
if (tx_length > 0)
|
||||
{
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX);
|
||||
nrf_twi_txd_set(twi, *(twi_info->tx));
|
||||
++(twi_info->tx);
|
||||
// RX only.
|
||||
} else if (rx_length > 0) {
|
||||
// RX only.
|
||||
}
|
||||
else if (rx_length > 0)
|
||||
{
|
||||
start_asynch_rx(twi_info, twi);
|
||||
// Both 'tx_length' and 'rx_length' are 0 - this case may be used
|
||||
// to test if the slave is presentand ready for transfer (by just
|
||||
// sending the address and checking if it is acknowledged).
|
||||
} else {
|
||||
// Both 'tx_length' and 'rx_length' are 0 - this case may be used
|
||||
// to test if the slave is presentand ready for transfer (by just
|
||||
// sending the address and checking if it is acknowledged).
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX);
|
||||
if (stop) {
|
||||
if (stop)
|
||||
{
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
|
||||
nrf_twi_int_enable(twi, NRF_TWI_INT_SUSPENDED_MASK);
|
||||
}
|
||||
|
|
|
@ -28,7 +28,8 @@ static volatile uint32_t _entry_count = 0;
|
|||
void core_util_critical_section_enter()
|
||||
{
|
||||
// if a critical section has already been entered, just update the counter
|
||||
if (_entry_count) {
|
||||
if (_entry_count)
|
||||
{
|
||||
++_entry_count;
|
||||
return;
|
||||
}
|
||||
|
@ -47,7 +48,8 @@ void core_util_critical_section_exit()
|
|||
--_entry_count;
|
||||
|
||||
// If their is other segments which have entered the critical section, just leave
|
||||
if (_entry_count) {
|
||||
if (_entry_count)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -48,36 +48,43 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct serial_s {
|
||||
struct serial_s
|
||||
{
|
||||
uint32_t placeholder; // struct is unused by nRF5x API implementation
|
||||
}; // but it must be not empty (required by strict compiler - IAR)
|
||||
|
||||
struct spi_s {
|
||||
struct spi_s
|
||||
{
|
||||
uint8_t spi_idx;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
struct port_s
|
||||
{
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct pwmout_s {
|
||||
struct pwmout_s
|
||||
{
|
||||
PWMName pwm_name;
|
||||
PinName pin;
|
||||
uint8_t pwm_channel;
|
||||
void * pwm_struct;
|
||||
};
|
||||
|
||||
struct i2c_s {
|
||||
struct i2c_s
|
||||
{
|
||||
uint8_t twi_idx;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
struct analogin_s
|
||||
{
|
||||
ADCName adc;
|
||||
uint8_t adc_pin;
|
||||
};
|
||||
|
||||
struct gpio_irq_s {
|
||||
struct gpio_irq_s
|
||||
{
|
||||
uint32_t ch;
|
||||
};
|
||||
|
||||
|
|
|
@ -38,10 +38,21 @@
|
|||
|
||||
#include "port_api.h"
|
||||
#include "pinmap.h"
|
||||
#include "gpio_api.h"
|
||||
|
||||
static NRF_GPIO_Type * const m_ports[] = GPIO_REG_LIST;
|
||||
|
||||
#if defined(TARGET_MCU_NRF51822)
|
||||
static const uint32_t m_gpio_pin_count[] = {31};
|
||||
#elif defined(TARGET_MCU_NRF52832)
|
||||
static const uint32_t m_gpio_pin_count[] = {32};
|
||||
#elif defined(TARGET_MCU_NRF52840)
|
||||
static const uint32_t m_gpio_pin_count[] = {32, 16};
|
||||
#else
|
||||
#error not recognized gpio count for mcu
|
||||
#endif
|
||||
|
||||
#define GPIO_PORT_COUNT (sizeof(m_gpio_pin_count)/sizeof(uint32_t))
|
||||
|
||||
|
||||
PinName port_pin(PortName port, int pin_n)
|
||||
{
|
||||
|
@ -50,6 +61,8 @@ PinName port_pin(PortName port, int pin_n)
|
|||
|
||||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
|
||||
{
|
||||
MBED_ASSERT((uint32_t)port < GPIO_PORT_COUNT);
|
||||
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
|
@ -60,8 +73,10 @@ void port_mode(port_t *obj, PinMode mode)
|
|||
{
|
||||
uint32_t i;
|
||||
// The mode is set per pin: reuse pinmap logic
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
|
||||
{
|
||||
if (obj->mask & (1 << i))
|
||||
{
|
||||
pin_mode(port_pin(obj->port, i), mode);
|
||||
}
|
||||
}
|
||||
|
@ -72,29 +87,37 @@ void port_dir(port_t *obj, PinDirection dir)
|
|||
int i;
|
||||
|
||||
volatile uint32_t *reg_cnf = (volatile uint32_t*) m_ports[obj->port]->PIN_CNF;
|
||||
|
||||
switch (dir) {
|
||||
case PIN_INPUT:
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
switch (dir)
|
||||
{
|
||||
case PIN_INPUT:
|
||||
|
||||
for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
|
||||
{
|
||||
if (obj->mask & (1 << i))
|
||||
{
|
||||
reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
break;
|
||||
|
||||
case PIN_OUTPUT:
|
||||
|
||||
for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
|
||||
{
|
||||
if (obj->mask & (1 << i))
|
||||
{
|
||||
reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -66,11 +66,13 @@ extern uint32_t __Vectors[];
|
|||
void nrf_reloc_vector_table(void)
|
||||
{
|
||||
// Copy and switch to dynamic vectors
|
||||
uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START;
|
||||
uint32_t i;
|
||||
for (i = 0; i< NVIC_NUM_VECTORS; i++) {
|
||||
nrf_dispatch_vector[i] = old_vectors[i];
|
||||
}
|
||||
uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i< NVIC_NUM_VECTORS; i++)
|
||||
{
|
||||
nrf_dispatch_vector[i] = old_vectors[i];
|
||||
}
|
||||
|
||||
sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector);
|
||||
sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector);
|
||||
}
|
||||
|
|
|
@ -80,7 +80,9 @@ time_t rtc_read(void)
|
|||
void rtc_write(time_t t)
|
||||
{
|
||||
uint32_t seconds;
|
||||
do {
|
||||
|
||||
do
|
||||
{
|
||||
seconds = rtc_seconds_get();
|
||||
m_time_base = t - seconds;
|
||||
// If the number of seconds indicated by the counter changed during the
|
||||
|
|
|
@ -83,39 +83,40 @@
|
|||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
typedef struct {
|
||||
bool initialized;
|
||||
uint32_t irq_context;
|
||||
uart_irq_handler irq_handler;
|
||||
typedef struct
|
||||
{
|
||||
bool initialized;
|
||||
uint32_t irq_context;
|
||||
uart_irq_handler irq_handler;
|
||||
|
||||
uint32_t pselrxd;
|
||||
uint32_t pseltxd;
|
||||
uint32_t pselcts;
|
||||
uint32_t pselrts;
|
||||
nrf_uart_hwfc_t hwfc;
|
||||
nrf_uart_parity_t parity;
|
||||
uint32_t pselrxd;
|
||||
uint32_t pseltxd;
|
||||
uint32_t pselcts;
|
||||
uint32_t pselrts;
|
||||
nrf_uart_hwfc_t hwfc;
|
||||
nrf_uart_parity_t parity;
|
||||
nrf_uart_baudrate_t baudrate;
|
||||
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
bool volatile rx_active;
|
||||
bool volatile rx_active;
|
||||
uint8_t *rx_buffer;
|
||||
size_t rx_length;
|
||||
size_t rx_pos;
|
||||
void (*rx_asynch_handler)();
|
||||
uint8_t char_match;
|
||||
size_t rx_length;
|
||||
size_t rx_pos;
|
||||
void (*rx_asynch_handler)();
|
||||
uint8_t char_match;
|
||||
|
||||
bool volatile tx_active;
|
||||
bool volatile tx_active;
|
||||
const uint8_t *tx_buffer;
|
||||
size_t tx_length;
|
||||
size_t tx_pos;
|
||||
void (*tx_asynch_handler)();
|
||||
size_t tx_length;
|
||||
size_t tx_pos;
|
||||
void (*tx_asynch_handler)();
|
||||
|
||||
uint32_t events_wanted;
|
||||
uint32_t events_occured;
|
||||
uint32_t events_wanted;
|
||||
uint32_t events_occured;
|
||||
|
||||
#define UART_IRQ_TX 1
|
||||
#define UART_IRQ_RX 2
|
||||
uint8_t irq_enabled;
|
||||
#define UART_IRQ_TX 1
|
||||
#define UART_IRQ_RX 2
|
||||
uint8_t irq_enabled;
|
||||
#endif // DEVICE_SERIAL_ASYNCH
|
||||
} uart_ctlblock_t;
|
||||
|
||||
|
@ -130,7 +131,8 @@ static void end_asynch_rx(void)
|
|||
{
|
||||
// If RX interrupt is activated for synchronous operations,
|
||||
// don't disable it, just stop handling it here.
|
||||
if (!(UART_CB.irq_enabled & UART_IRQ_RX)) {
|
||||
if (!(UART_CB.irq_enabled & UART_IRQ_RX))
|
||||
{
|
||||
nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
|
||||
}
|
||||
UART_CB.rx_active = false;
|
||||
|
@ -139,7 +141,8 @@ static void end_asynch_tx(void)
|
|||
{
|
||||
// If TX interrupt is activated for synchronous operations,
|
||||
// don't disable it, just stop handling it here.
|
||||
if (!(UART_CB.irq_enabled & UART_IRQ_TX)) {
|
||||
if (!(UART_CB.irq_enabled & UART_IRQ_TX))
|
||||
{
|
||||
nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
|
||||
}
|
||||
UART_CB.tx_active = false;
|
||||
|
@ -149,10 +152,12 @@ static void end_asynch_tx(void)
|
|||
void UART_IRQ_HANDLER(void)
|
||||
{
|
||||
if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY) &&
|
||||
nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)) {
|
||||
nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY))
|
||||
{
|
||||
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.rx_active) {
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.rx_active)
|
||||
{
|
||||
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
|
||||
|
||||
uint8_t rx_data = nrf_uart_rxd_get(UART_INSTANCE);
|
||||
|
@ -162,21 +167,26 @@ void UART_IRQ_HANDLER(void)
|
|||
// If character matching should be performed, check if the current
|
||||
// data matches the given one.
|
||||
if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH &&
|
||||
rx_data == UART_CB.char_match) {
|
||||
rx_data == UART_CB.char_match)
|
||||
{
|
||||
// If it does, report the match and abort further receiving.
|
||||
UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH;
|
||||
if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) {
|
||||
if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH)
|
||||
{
|
||||
end_rx = true;
|
||||
}
|
||||
}
|
||||
if (++UART_CB.rx_pos >= UART_CB.rx_length) {
|
||||
if (++UART_CB.rx_pos >= UART_CB.rx_length)
|
||||
{
|
||||
UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE;
|
||||
end_rx = true;
|
||||
}
|
||||
if (end_rx) {
|
||||
if (end_rx)
|
||||
{
|
||||
end_asynch_rx();
|
||||
|
||||
if (UART_CB.rx_asynch_handler) {
|
||||
if (UART_CB.rx_asynch_handler)
|
||||
{
|
||||
// Use local variable to make it possible to start a next
|
||||
// transfer from callback routine.
|
||||
void (*handler)() = UART_CB.rx_asynch_handler;
|
||||
|
@ -186,26 +196,31 @@ void UART_IRQ_HANDLER(void)
|
|||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (UART_CB.irq_handler) {
|
||||
if (UART_CB.irq_handler)
|
||||
{
|
||||
UART_CB.irq_handler(UART_CB.irq_context, RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY) &&
|
||||
nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) {
|
||||
nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY))
|
||||
{
|
||||
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.tx_active) {
|
||||
if (++UART_CB.tx_pos <= UART_CB.tx_length) {
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.tx_active)
|
||||
{
|
||||
if (++UART_CB.tx_pos <= UART_CB.tx_length)
|
||||
{
|
||||
// When there is still something to send, clear the TXDRDY event
|
||||
// and put next byte to transmitter.
|
||||
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
|
||||
nrf_uart_txd_set(UART_INSTANCE,
|
||||
UART_CB.tx_buffer[UART_CB.tx_pos]);
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
// When the TXDRDY event is set after the last byte to be sent
|
||||
// has been passed to the transmitter, the job is done and TX
|
||||
// complete can be indicated.
|
||||
|
@ -214,7 +229,8 @@ void UART_IRQ_HANDLER(void)
|
|||
end_asynch_tx();
|
||||
|
||||
UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE;
|
||||
if (UART_CB.tx_asynch_handler) {
|
||||
if (UART_CB.tx_asynch_handler)
|
||||
{
|
||||
// Use local variable to make it possible to start a next
|
||||
// transfer from callback routine.
|
||||
void (*handler)() = UART_CB.tx_asynch_handler;
|
||||
|
@ -224,27 +240,33 @@ void UART_IRQ_HANDLER(void)
|
|||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (UART_CB.irq_handler) {
|
||||
if (UART_CB.irq_handler)
|
||||
{
|
||||
UART_CB.irq_handler(UART_CB.irq_context, TxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR)) {
|
||||
if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR))
|
||||
{
|
||||
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR);
|
||||
|
||||
uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE);
|
||||
if (UART_CB.rx_asynch_handler) {
|
||||
if (UART_CB.rx_asynch_handler)
|
||||
{
|
||||
UART_CB.events_occured |= SERIAL_EVENT_ERROR;
|
||||
if (errorsrc & NRF_UART_ERROR_PARITY_MASK) {
|
||||
if (errorsrc & NRF_UART_ERROR_PARITY_MASK)
|
||||
{
|
||||
UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR;
|
||||
}
|
||||
if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) {
|
||||
if (errorsrc & NRF_UART_ERROR_FRAMING_MASK)
|
||||
{
|
||||
UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR;
|
||||
}
|
||||
if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) {
|
||||
if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK)
|
||||
{
|
||||
UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR;
|
||||
}
|
||||
UART_CB.rx_asynch_handler();
|
||||
|
@ -253,7 +275,9 @@ void UART_IRQ_HANDLER(void)
|
|||
#endif // DEVICE_SERIAL_ASYNCH
|
||||
}
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx)
|
||||
{
|
||||
|
||||
NVIC_SetVector(UART0_IRQn, (uint32_t) UART0_IRQHandler);
|
||||
|
||||
|
@ -262,27 +286,32 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
|||
(tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx;
|
||||
UART_CB.pselrxd =
|
||||
(rx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rx;
|
||||
if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED) {
|
||||
if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_pin_set(UART_CB.pseltxd);
|
||||
nrf_gpio_cfg_output(UART_CB.pseltxd);
|
||||
}
|
||||
if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED) {
|
||||
if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_input(UART_CB.pselrxd, NRF_GPIO_PIN_NOPULL);
|
||||
}
|
||||
|
||||
if (UART_CB.initialized) {
|
||||
if (UART_CB.initialized)
|
||||
{
|
||||
// For already initialized peripheral it is sufficient to reconfigure
|
||||
// RX/TX pins only.
|
||||
|
||||
// Ensure that there is no unfinished TX transfer.
|
||||
while (!serial_writable(obj)) {
|
||||
while (!serial_writable(obj))
|
||||
{
|
||||
}
|
||||
// UART pins can be configured only when the peripheral is disabled.
|
||||
nrf_uart_disable(UART_INSTANCE);
|
||||
nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
|
||||
nrf_uart_enable(UART_INSTANCE);
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
UART_CB.baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_BAUDRATE;
|
||||
UART_CB.parity = (nrf_uart_parity_t)UART_DEFAULT_PARITY;
|
||||
UART_CB.hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_HWFC;
|
||||
|
@ -295,10 +324,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
|||
nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX);
|
||||
|
||||
nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
|
||||
NRF_UART_INT_MASK_TXDRDY);
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
NRF_UART_INT_MASK_TXDRDY);
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR);
|
||||
#endif
|
||||
#endif
|
||||
nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY);
|
||||
|
||||
// TX interrupt needs to be signaled when transmitter buffer is empty,
|
||||
|
@ -315,7 +344,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
|||
nrf_uart_hwfc_pins_disconnect(UART_INSTANCE);
|
||||
nrf_uart_enable(UART_INSTANCE);
|
||||
nrf_uart_txd_set(UART_INSTANCE, 0);
|
||||
while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) {
|
||||
|
||||
while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY))
|
||||
{
|
||||
}
|
||||
nrf_uart_disable(UART_INSTANCE);
|
||||
|
||||
|
@ -324,7 +355,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
|||
nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
|
||||
nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate);
|
||||
nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
|
||||
if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED) {
|
||||
if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED)
|
||||
{
|
||||
internal_set_hwfc(FlowControlRTSCTS,
|
||||
(PinName) UART_CB.pselrts, (PinName) UART_CB.pselcts);
|
||||
}
|
||||
|
@ -334,11 +366,13 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
|||
UART_CB.initialized = true;
|
||||
}
|
||||
|
||||
if (tx == STDIO_UART_TX && rx == STDIO_UART_RX) {
|
||||
if (tx == STDIO_UART_TX && rx == STDIO_UART_RX)
|
||||
{
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
stdio_uart_inited = 0;
|
||||
}
|
||||
}
|
||||
|
@ -347,7 +381,8 @@ void serial_free(serial_t *obj)
|
|||
{
|
||||
(void)obj;
|
||||
|
||||
if (UART_CB.initialized) {
|
||||
if (UART_CB.initialized)
|
||||
{
|
||||
nrf_uart_disable(UART_INSTANCE);
|
||||
nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
|
||||
NRF_UART_INT_MASK_TXDRDY |
|
||||
|
@ -388,14 +423,18 @@ void serial_baud(serial_t *obj, int baudrate)
|
|||
{ 1000000, UART_BAUDRATE_BAUDRATE_Baud1M }
|
||||
};
|
||||
|
||||
if (baudrate <= 1200) {
|
||||
if (baudrate <= 1200)
|
||||
{
|
||||
UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
|
||||
return;
|
||||
}
|
||||
|
||||
int const item_cnt = sizeof(acceptedSpeeds)/sizeof(acceptedSpeeds[0]);
|
||||
for (int i = 1; i < item_cnt; i++) {
|
||||
if ((uint32_t)baudrate < acceptedSpeeds[i][0]) {
|
||||
|
||||
for (int i = 1; i < item_cnt; i++)
|
||||
{
|
||||
if ((uint32_t)baudrate < acceptedSpeeds[i][0])
|
||||
{
|
||||
UART_INSTANCE->BAUDRATE = acceptedSpeeds[i - 1][1];
|
||||
return;
|
||||
}
|
||||
|
@ -409,17 +448,24 @@ void serial_format(serial_t *obj,
|
|||
{
|
||||
(void)obj;
|
||||
|
||||
if (data_bits != 8) {
|
||||
if (data_bits != 8)
|
||||
{
|
||||
error("UART supports only 8 data bits.\r\n");
|
||||
}
|
||||
if (stop_bits != 1) {
|
||||
if (stop_bits != 1)
|
||||
{
|
||||
error("UART supports only 1 stop bits.\r\n");
|
||||
}
|
||||
if (parity == ParityNone) {
|
||||
if (parity == ParityNone)
|
||||
{
|
||||
UART_CB.parity = NRF_UART_PARITY_EXCLUDED;
|
||||
} else if (parity == ParityEven) {
|
||||
}
|
||||
else if (parity == ParityEven)
|
||||
{
|
||||
UART_CB.parity = NRF_UART_PARITY_INCLUDED;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
error("UART supports only even parity.\r\n");
|
||||
}
|
||||
|
||||
|
@ -437,29 +483,34 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
|
|||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
||||
{
|
||||
(void)obj;
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
if (enable)
|
||||
{
|
||||
switch (irq)
|
||||
{
|
||||
case RxIrq:
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
UART_CB.irq_enabled |= UART_IRQ_RX;
|
||||
#endif
|
||||
#endif
|
||||
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
|
||||
break;
|
||||
|
||||
case TxIrq:
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
UART_CB.irq_enabled |= UART_IRQ_TX;
|
||||
#endif
|
||||
#endif
|
||||
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (irq) {
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (irq)
|
||||
{
|
||||
case RxIrq:
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
UART_CB.irq_enabled &= ~UART_IRQ_RX;
|
||||
if (!UART_CB.rx_active)
|
||||
#endif
|
||||
#endif
|
||||
{
|
||||
nrf_uart_int_disable(UART_INSTANCE,
|
||||
NRF_UART_INT_MASK_RXDRDY);
|
||||
|
@ -467,10 +518,10 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
|||
break;
|
||||
|
||||
case TxIrq:
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
UART_CB.irq_enabled &= ~UART_IRQ_TX;
|
||||
if (!UART_CB.tx_active)
|
||||
#endif
|
||||
#endif
|
||||
{
|
||||
nrf_uart_int_disable(UART_INSTANCE,
|
||||
NRF_UART_INT_MASK_TXDRDY);
|
||||
|
@ -482,7 +533,8 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
|||
|
||||
int serial_getc(serial_t *obj)
|
||||
{
|
||||
while (!serial_readable(obj)) {
|
||||
while (!serial_readable(obj))
|
||||
{
|
||||
}
|
||||
|
||||
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
|
||||
|
@ -491,7 +543,8 @@ int serial_getc(serial_t *obj)
|
|||
|
||||
void serial_putc(serial_t *obj, int c)
|
||||
{
|
||||
while (!serial_writable(obj)) {
|
||||
while (!serial_writable(obj))
|
||||
{
|
||||
}
|
||||
|
||||
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
|
||||
|
@ -502,7 +555,8 @@ int serial_readable(serial_t *obj)
|
|||
{
|
||||
(void)obj;
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.rx_active) {
|
||||
if (UART_CB.rx_active)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -513,7 +567,8 @@ int serial_writable(serial_t *obj)
|
|||
{
|
||||
(void)obj;
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
if (UART_CB.tx_active) {
|
||||
if (UART_CB.tx_active)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -546,11 +601,13 @@ static void internal_set_hwfc(FlowControl type,
|
|||
UART_CB.pselcts =
|
||||
((txflow == NC) || (type == FlowControlRTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)txflow;
|
||||
|
||||
if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED) {
|
||||
if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_pin_set(UART_CB.pselrts);
|
||||
nrf_gpio_cfg_output(UART_CB.pselrts);
|
||||
}
|
||||
if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED) {
|
||||
if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED)
|
||||
{
|
||||
nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL);
|
||||
}
|
||||
|
||||
|
@ -571,7 +628,8 @@ void serial_set_flow_control(serial_t *obj, FlowControl type,
|
|||
}
|
||||
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
void serial_clear(serial_t *obj)
|
||||
{
|
||||
(void)obj;
|
||||
}
|
||||
|
||||
|
@ -584,7 +642,8 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length,
|
|||
(void)obj;
|
||||
(void)tx_width;
|
||||
(void)hint;
|
||||
if (UART_CB.tx_active || !tx_length) {
|
||||
if (UART_CB.tx_active || !tx_length)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -608,7 +667,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length,
|
|||
(void)obj;
|
||||
(void)rx_width;
|
||||
(void)hint;
|
||||
if (UART_CB.rx_active || !rx_length) {
|
||||
if (UART_CB.rx_active || !rx_length)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
#define FPU_EXCEPTION_MASK 0x0000009F
|
||||
|
||||
void sleep(void)
|
||||
void hal_sleep(void)
|
||||
{
|
||||
// ensure debug is disconnected if semihost is enabled....
|
||||
|
||||
|
@ -41,10 +41,13 @@ void sleep(void)
|
|||
#endif
|
||||
|
||||
// If the SoftDevice is enabled, its API must be used to go to sleep.
|
||||
if (softdevice_handler_is_enabled()) {
|
||||
if (softdevice_handler_is_enabled())
|
||||
{
|
||||
sd_power_mode_set(NRF_POWER_MODE_LOWPWR);
|
||||
sd_app_evt_wait();
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
NRF_POWER->TASKS_LOWPWR = 1;
|
||||
|
||||
// Note: it is not sufficient to just use WFE here, since the internal
|
||||
|
@ -61,10 +64,13 @@ void sleep(void)
|
|||
__WFE();
|
||||
|
||||
// Test if there is an interrupt pending (mask reserved regions)
|
||||
if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK)) {
|
||||
if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK))
|
||||
{
|
||||
// Ok, there is an interrut pending, no need to go to sleep
|
||||
return;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
// next event will wakeup the CPU
|
||||
// If an interrupt occured between the test of SCB->ICSR and this
|
||||
// instruction, WFE will just not put the CPU to sleep
|
||||
|
@ -73,8 +79,7 @@ void sleep(void)
|
|||
}
|
||||
}
|
||||
|
||||
void deepsleep(void)
|
||||
void hal_deepsleep(void)
|
||||
{
|
||||
sleep();
|
||||
// NRF_POWER->SYSTEMOFF=1;
|
||||
hal_sleep();
|
||||
}
|
||||
|
|
|
@ -58,16 +58,18 @@
|
|||
#define MASTER_INST(obj) (&m_instances[SPI_IDX(obj)].master)
|
||||
#define SLAVE_INST(obj) (&m_instances[SPI_IDX(obj)].slave)
|
||||
|
||||
typedef struct {
|
||||
bool initialized;
|
||||
bool master;
|
||||
typedef struct
|
||||
{
|
||||
bool initialized;
|
||||
bool master;
|
||||
uint8_t sck_pin;
|
||||
uint8_t mosi_pin;
|
||||
uint8_t miso_pin;
|
||||
uint8_t ss_pin;
|
||||
uint8_t spi_mode;
|
||||
nrf_drv_spi_frequency_t frequency;
|
||||
volatile union {
|
||||
volatile union
|
||||
{
|
||||
bool busy; // master
|
||||
bool readable; // slave
|
||||
} flag;
|
||||
|
@ -81,8 +83,9 @@ typedef struct {
|
|||
} spi_info_t;
|
||||
static spi_info_t m_spi_info[SPI_COUNT];
|
||||
|
||||
typedef struct {
|
||||
nrf_drv_spi_t master;
|
||||
typedef struct
|
||||
{
|
||||
nrf_drv_spi_t master;
|
||||
nrf_drv_spis_t slave;
|
||||
} sdk_driver_instances_t;
|
||||
|
||||
|
@ -90,25 +93,25 @@ void SPI0_TWI0_IRQHandler(void);
|
|||
void SPI1_TWI1_IRQHandler(void);
|
||||
void SPIM2_SPIS2_SPI2_IRQHandler(void);
|
||||
|
||||
static const peripheral_handler_desc_t spi_hanlder_desc[SPI_COUNT] = {
|
||||
static const peripheral_handler_desc_t spi_handler_desc[SPI_COUNT] = {
|
||||
#if SPI0_ENABLED
|
||||
{
|
||||
SPIS0_IRQ,
|
||||
SPI0_IRQ,
|
||||
(uint32_t) SPI0_TWI0_IRQHandler
|
||||
},
|
||||
#endif
|
||||
#if SPI1_ENABLED
|
||||
{
|
||||
SPIS1_IRQ,
|
||||
SPI1_IRQ,
|
||||
(uint32_t) SPI1_TWI1_IRQHandler
|
||||
},
|
||||
#endif
|
||||
#if SPI2_ENABLED
|
||||
{
|
||||
SPIS2_IRQ,
|
||||
SPI2_IRQ,
|
||||
(uint32_t) SPIM2_SPIS2_SPI2_IRQHandler
|
||||
},
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
@ -138,9 +141,11 @@ static void master_event_handler(uint8_t spi_idx,
|
|||
{
|
||||
spi_info_t *p_spi_info = &m_spi_info[spi_idx];
|
||||
|
||||
if (p_event->type == NRF_DRV_SPI_EVENT_DONE) {
|
||||
if (p_event->type == NRF_DRV_SPI_EVENT_DONE)
|
||||
{
|
||||
p_spi_info->flag.busy = false;
|
||||
if (p_spi_info->handler) {
|
||||
if (p_spi_info->handler)
|
||||
{
|
||||
void (*handler)(void) = (void (*)(void))p_spi_info->handler;
|
||||
p_spi_info->handler = 0;
|
||||
handler();
|
||||
|
@ -179,7 +184,8 @@ static void slave_event_handler(uint8_t spi_idx,
|
|||
{
|
||||
spi_info_t *p_spi_info = &m_spi_info[spi_idx];
|
||||
|
||||
if (event.evt_type == NRF_DRV_SPIS_XFER_DONE) {
|
||||
if (event.evt_type == NRF_DRV_SPIS_XFER_DONE)
|
||||
{
|
||||
// Signal that there is some data received that could be read.
|
||||
p_spi_info->flag.readable = true;
|
||||
|
||||
|
@ -254,12 +260,35 @@ void spi_init(spi_t *obj,
|
|||
PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < SPI_COUNT; ++i) {
|
||||
|
||||
// This block is only a workaround that allows to create SPI object several
|
||||
// times, what would be otherwise impossible in the current implementation
|
||||
// of mbed driver that does not call spi_free() from SPI destructor.
|
||||
// Once this mbed's imperfection is corrected, this block should be removed.
|
||||
for (i = 0; i < SPI_COUNT; ++i)
|
||||
{
|
||||
spi_info_t *p_spi_info = &m_spi_info[i];
|
||||
if (!p_spi_info->initialized) {
|
||||
|
||||
NVIC_SetVector(spi_hanlder_desc[i].IRQn, spi_hanlder_desc[i].vector);
|
||||
|
||||
|
||||
if (p_spi_info->initialized &&
|
||||
p_spi_info->mosi_pin == (uint8_t)mosi &&
|
||||
p_spi_info->miso_pin == (uint8_t)miso &&
|
||||
p_spi_info->sck_pin == (uint8_t)sclk &&
|
||||
p_spi_info->ss_pin == (uint8_t)ssel)
|
||||
{
|
||||
// Reuse the already allocated SPI instance (instead of allocating
|
||||
// a new one), if it appears to be initialized with exactly the same
|
||||
// pin assignments.
|
||||
SPI_IDX(obj) = i;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < SPI_COUNT; ++i)
|
||||
{
|
||||
spi_info_t *p_spi_info = &m_spi_info[i];
|
||||
|
||||
if (!p_spi_info->initialized)
|
||||
{
|
||||
p_spi_info->sck_pin = (uint8_t)sclk;
|
||||
p_spi_info->mosi_pin = (mosi != NC) ?
|
||||
(uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED;
|
||||
|
@ -270,22 +299,25 @@ void spi_init(spi_t *obj,
|
|||
p_spi_info->spi_mode = (uint8_t)NRF_DRV_SPI_MODE_0;
|
||||
p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M;
|
||||
|
||||
NVIC_SetVector(spi_handler_desc[i].IRQn, spi_handler_desc[i].vector);
|
||||
|
||||
// By default each SPI instance is initialized to work as a master.
|
||||
// Should the slave mode be used, the instance will be reconfigured
|
||||
// appropriately in 'spi_format'.
|
||||
nrf_drv_spi_config_t config;
|
||||
prepare_master_config(&config, p_spi_info);
|
||||
|
||||
nrf_drv_spi_t const *p_spi = &m_instances[i].master;
|
||||
ret_code_t ret_code = nrf_drv_spi_init(p_spi,
|
||||
&config, m_master_event_handlers[i]);
|
||||
if (ret_code == NRF_SUCCESS) {
|
||||
nrf_drv_spi_t const *p_spi = &m_instances[i].master;
|
||||
ret_code_t ret_code = nrf_drv_spi_init(p_spi,
|
||||
&config, m_master_event_handlers[i]);
|
||||
if (ret_code == NRF_SUCCESS)
|
||||
{
|
||||
p_spi_info->initialized = true;
|
||||
p_spi_info->master = true;
|
||||
p_spi_info->flag.busy = false;
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
p_spi_info->handler = 0;
|
||||
#endif
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
p_spi_info->handler = 0;
|
||||
#endif
|
||||
SPI_IDX(obj) = i;
|
||||
|
||||
return;
|
||||
|
@ -300,10 +332,13 @@ void spi_init(spi_t *obj,
|
|||
void spi_free(spi_t *obj)
|
||||
{
|
||||
spi_info_t *p_spi_info = SPI_INFO(obj);
|
||||
if (p_spi_info->master) {
|
||||
|
||||
if (p_spi_info->master)
|
||||
{
|
||||
nrf_drv_spi_uninit(MASTER_INST(obj));
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
nrf_drv_spis_uninit(SLAVE_INST(obj));
|
||||
}
|
||||
p_spi_info->initialized = false;
|
||||
|
@ -316,10 +351,12 @@ int spi_busy(spi_t *obj)
|
|||
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave)
|
||||
{
|
||||
if (bits != 8) {
|
||||
if (bits != 8)
|
||||
{
|
||||
error("Only 8-bits SPI is supported\r\n");
|
||||
}
|
||||
if (mode > 3) {
|
||||
if (mode > 3)
|
||||
{
|
||||
error("SPI format error\r\n");
|
||||
}
|
||||
|
||||
|
@ -337,15 +374,18 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
|
|||
|
||||
// If the peripheral is currently working as a master, the SDK driver
|
||||
// it uses needs to be switched from SPI to SPIS.
|
||||
if (p_spi_info->master) {
|
||||
if (p_spi_info->master)
|
||||
{
|
||||
nrf_drv_spi_uninit(MASTER_INST(obj));
|
||||
}
|
||||
// I the SPI mode has to be changed, the SDK's SPIS driver needs to be
|
||||
// re-initialized (there is no other way to change its configuration).
|
||||
else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
|
||||
else if (p_spi_info->spi_mode != (uint8_t)new_mode)
|
||||
{
|
||||
nrf_drv_spis_uninit(SLAVE_INST(obj));
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -377,15 +417,18 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
|
|||
|
||||
// If the peripheral is currently working as a slave, the SDK driver
|
||||
// it uses needs to be switched from SPIS to SPI.
|
||||
if (!p_spi_info->master) {
|
||||
if (!p_spi_info->master)
|
||||
{
|
||||
nrf_drv_spis_uninit(SLAVE_INST(obj));
|
||||
}
|
||||
// I the SPI mode has to be changed, the SDK's SPI driver needs to be
|
||||
// re-initialized (there is no other way to change its configuration).
|
||||
else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
|
||||
else if (p_spi_info->spi_mode != (uint8_t)new_mode)
|
||||
{
|
||||
nrf_drv_spi_uninit(MASTER_INST(obj));
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -404,19 +447,33 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
|
|||
static nrf_drv_spi_frequency_t freq_translate(int hz)
|
||||
{
|
||||
nrf_drv_spi_frequency_t frequency;
|
||||
if (hz<250000) { //125Kbps
|
||||
|
||||
if (hz<250000) //125Kbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_125K;
|
||||
} else if (hz<500000) { //250Kbps
|
||||
}
|
||||
else if (hz<500000) //250Kbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_250K;
|
||||
} else if (hz<1000000) { //500Kbps
|
||||
}
|
||||
else if (hz<1000000) //500Kbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_500K;
|
||||
} else if (hz<2000000) { //1Mbps
|
||||
}
|
||||
else if (hz<2000000) //1Mbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_1M;
|
||||
} else if (hz<4000000) { //2Mbps
|
||||
}
|
||||
else if (hz<4000000) //2Mbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_2M;
|
||||
} else if (hz<8000000) { //4Mbps
|
||||
}
|
||||
else if (hz<8000000) //4Mbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_4M;
|
||||
} else { //8Mbps
|
||||
}
|
||||
else //8Mbps
|
||||
{
|
||||
frequency = NRF_DRV_SPI_FREQ_8M;
|
||||
}
|
||||
return frequency;
|
||||
|
@ -429,7 +486,8 @@ void spi_frequency(spi_t *obj, int hz)
|
|||
|
||||
if (p_spi_info->master)
|
||||
{
|
||||
if (p_spi_info->frequency != new_frequency) {
|
||||
if (p_spi_info->frequency != new_frequency)
|
||||
{
|
||||
p_spi_info->frequency = new_frequency;
|
||||
|
||||
nrf_drv_spi_config_t config;
|
||||
|
@ -450,7 +508,9 @@ int spi_master_write(spi_t *obj, int value)
|
|||
spi_info_t *p_spi_info = SPI_INFO(obj);
|
||||
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
while (p_spi_info->flag.busy) {
|
||||
|
||||
while (p_spi_info->flag.busy)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -459,7 +519,9 @@ int spi_master_write(spi_t *obj, int value)
|
|||
(void)nrf_drv_spi_transfer(MASTER_INST(obj),
|
||||
(uint8_t const *)&p_spi_info->tx_buf, 1,
|
||||
(uint8_t *)&p_spi_info->rx_buf, 1);
|
||||
while (p_spi_info->flag.busy) {
|
||||
|
||||
while (p_spi_info->flag.busy)
|
||||
{
|
||||
}
|
||||
|
||||
return p_spi_info->rx_buf;
|
||||
|
@ -470,14 +532,15 @@ int spi_slave_receive(spi_t *obj)
|
|||
spi_info_t *p_spi_info = SPI_INFO(obj);
|
||||
MBED_ASSERT(!p_spi_info->master);
|
||||
return p_spi_info->flag.readable;
|
||||
;
|
||||
}
|
||||
|
||||
int spi_slave_read(spi_t *obj)
|
||||
{
|
||||
spi_info_t *p_spi_info = SPI_INFO(obj);
|
||||
MBED_ASSERT(!p_spi_info->master);
|
||||
while (!p_spi_info->flag.readable) {
|
||||
|
||||
while (!p_spi_info->flag.readable)
|
||||
{
|
||||
}
|
||||
p_spi_info->flag.readable = false;
|
||||
return p_spi_info->rx_buf;
|
||||
|
|
|
@ -51,7 +51,7 @@
|
|||
//
|
||||
#include "app_util_platform.h"
|
||||
|
||||
bool m_common_rtc_enabled = false;
|
||||
bool m_common_rtc_enabled = false;
|
||||
uint32_t volatile m_common_rtc_overflows = 0;
|
||||
|
||||
#if defined(TARGET_MCU_NRF51822)
|
||||
|
@ -60,18 +60,21 @@ void common_rtc_irq_handler(void)
|
|||
void COMMON_RTC_IRQ_HANDLER(void)
|
||||
#endif
|
||||
{
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT))
|
||||
{
|
||||
us_ticker_irq_handler();
|
||||
}
|
||||
|
||||
#if DEVICE_LOWPOWERTIMER
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT))
|
||||
{
|
||||
|
||||
lp_ticker_irq_handler();
|
||||
}
|
||||
#endif
|
||||
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
|
||||
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW))
|
||||
{
|
||||
nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
|
||||
// Don't disable this event. It shall occur periodically.
|
||||
|
||||
|
@ -85,29 +88,33 @@ __STATIC_INLINE void errata_20(void)
|
|||
#if defined(NRF52_ERRATA_20)
|
||||
if (!softdevice_handler_is_enabled())
|
||||
{
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {}
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
NRF_RTC1->TASKS_STOP = 0;
|
||||
#endif
|
||||
NRF_RTC1->TASKS_STOP = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
|
||||
__stackless __task
|
||||
__stackless __task
|
||||
#endif
|
||||
void RTC1_IRQHandler(void);
|
||||
|
||||
void common_rtc_init(void)
|
||||
{
|
||||
if (m_common_rtc_enabled) {
|
||||
if (m_common_rtc_enabled)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
errata_20();
|
||||
|
||||
|
||||
NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
|
||||
|
||||
|
||||
// RTC is driven by the low frequency (32.768 kHz) clock, a proper request
|
||||
// must be made to have it running.
|
||||
// Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
|
||||
|
@ -128,32 +135,32 @@ void common_rtc_init(void)
|
|||
// events will be enabled or disabled as needed (such approach is more
|
||||
// energy efficient).
|
||||
nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
|
||||
#if DEVICE_LOWPOWERTIMER
|
||||
LP_TICKER_INT_MASK |
|
||||
#endif
|
||||
US_TICKER_INT_MASK |
|
||||
NRF_RTC_INT_OVERFLOW_MASK);
|
||||
#if DEVICE_LOWPOWERTIMER
|
||||
LP_TICKER_INT_MASK |
|
||||
#endif
|
||||
US_TICKER_INT_MASK |
|
||||
NRF_RTC_INT_OVERFLOW_MASK);
|
||||
|
||||
// This event is enabled permanently, since overflow indications are needed
|
||||
// continuously.
|
||||
nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
|
||||
// All other relevant events are initially disabled.
|
||||
nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
|
||||
#if defined(TARGET_MCU_NRF51822)
|
||||
OS_TICK_INT_MASK |
|
||||
#endif
|
||||
#if DEVICE_LOWPOWERTIMER
|
||||
LP_TICKER_INT_MASK |
|
||||
#endif
|
||||
US_TICKER_INT_MASK);
|
||||
#if defined(TARGET_MCU_NRF51822)
|
||||
OS_TICK_INT_MASK |
|
||||
#endif
|
||||
#if DEVICE_LOWPOWERTIMER
|
||||
LP_TICKER_INT_MASK |
|
||||
#endif
|
||||
US_TICKER_INT_MASK);
|
||||
|
||||
nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
|
||||
#ifdef NRF51
|
||||
APP_IRQ_PRIORITY_LOW
|
||||
APP_IRQ_PRIORITY_LOW
|
||||
#elif defined(NRF52) || defined(NRF52840_XXAA)
|
||||
APP_IRQ_PRIORITY_LOWEST
|
||||
APP_IRQ_PRIORITY_LOWEST
|
||||
#endif
|
||||
);
|
||||
);
|
||||
|
||||
nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
|
||||
|
||||
|
@ -192,10 +199,12 @@ void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
|
|||
uint64_t current_time64 = common_rtc_64bit_us_get();
|
||||
// [add upper 32 bits from the current time to the timestamp value]
|
||||
uint64_t timestamp64 = us_timestamp +
|
||||
(current_time64 & ~(uint64_t)0xFFFFFFFF);
|
||||
(current_time64 & ~(uint64_t)0xFFFFFFFF);
|
||||
|
||||
// [if the original timestamp value happens to be after the 32 bit counter
|
||||
// of microsends overflows, correct the upper 32 bits accordingly]
|
||||
if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
|
||||
if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF))
|
||||
{
|
||||
timestamp64 += ((uint64_t)1 << 32);
|
||||
}
|
||||
// [microseconds -> ticks, always round the result up to avoid too early
|
||||
|
@ -209,7 +218,8 @@ void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
|
|||
// value is 2 ticks. This guarantees that the compare trigger is properly
|
||||
// setup before the compare condition occurs.
|
||||
uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
|
||||
if ((int)(compare_value - closest_safe_compare) <= 0) {
|
||||
if ((int)(compare_value - closest_safe_compare) <= 0)
|
||||
{
|
||||
compare_value = closest_safe_compare;
|
||||
}
|
||||
|
||||
|
@ -251,7 +261,7 @@ void us_ticker_clear_interrupt(void)
|
|||
// alternative source of RTOS ticks.
|
||||
#if defined(TARGET_MCU_NRF51822)
|
||||
|
||||
#include "toolchain.h"
|
||||
#include "mbed_toolchain.h"
|
||||
|
||||
|
||||
#define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1)
|
||||
|
@ -273,7 +283,9 @@ static uint32_t previous_tick_cc_value = 0;
|
|||
*/
|
||||
MBED_WEAK uint32_t const os_trv;
|
||||
MBED_WEAK uint32_t const os_clockrate;
|
||||
MBED_WEAK void OS_Tick_Handler() { }
|
||||
MBED_WEAK void OS_Tick_Handler()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
#if defined (__CC_ARM) /* ARMCC Compiler */
|
||||
|
@ -414,14 +426,18 @@ __stackless __task void COMMON_RTC_IRQ_HANDLER(void)
|
|||
* Return the next number of clock cycle needed for the next tick.
|
||||
* @note This function has been carrefuly optimized for a systick occuring every 1000us.
|
||||
*/
|
||||
static uint32_t get_next_tick_cc_delta() {
|
||||
static uint32_t get_next_tick_cc_delta()
|
||||
{
|
||||
uint32_t delta = 0;
|
||||
|
||||
if (os_clockrate != 1000) {
|
||||
if (os_clockrate != 1000)
|
||||
{
|
||||
// In RTX, by default SYSTICK is is used.
|
||||
// A tick event is generated every os_trv + 1 clock cycles of the system timer.
|
||||
delta = os_trv + 1;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
// If the clockrate is set to 1000us then 1000 tick should happen every second.
|
||||
// Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
|
||||
// If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
|
||||
|
@ -437,20 +453,26 @@ static uint32_t get_next_tick_cc_delta() {
|
|||
// Every five ticks (20%, 200 delta in one second), the delta is equal to 32
|
||||
// The remaining (32) deltas equal to 32 are distributed using primes numbers.
|
||||
static uint32_t counter = 0;
|
||||
if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
|
||||
if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503))
|
||||
{
|
||||
delta = 32;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
delta = 33;
|
||||
}
|
||||
++counter;
|
||||
if (counter == 1000) {
|
||||
if (counter == 1000)
|
||||
{
|
||||
counter = 0;
|
||||
}
|
||||
}
|
||||
return delta;
|
||||
}
|
||||
|
||||
static inline void clear_tick_interrupt() {
|
||||
|
||||
static inline void clear_tick_interrupt()
|
||||
{
|
||||
nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
|
||||
nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
|
||||
}
|
||||
|
@ -462,21 +484,31 @@ static inline void clear_tick_interrupt() {
|
|||
* @param val value to check
|
||||
* @return true if the value is included in the range and false otherwise.
|
||||
*/
|
||||
static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
|
||||
static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val)
|
||||
{
|
||||
// regular case, begin < end
|
||||
// return true if begin <= val < end
|
||||
if (begin < end) {
|
||||
if (begin <= val && val < end) {
|
||||
if (begin < end)
|
||||
{
|
||||
if (begin <= val && val < end)
|
||||
{
|
||||
return true;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
// In this case end < begin because it has wrap around the limits
|
||||
// return false if end < val < begin
|
||||
if (end < val && val < begin) {
|
||||
if (end < val && val < begin)
|
||||
{
|
||||
return false;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
@ -486,7 +518,8 @@ static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t va
|
|||
/**
|
||||
* Register the next tick.
|
||||
*/
|
||||
static void register_next_tick() {
|
||||
static void register_next_tick()
|
||||
{
|
||||
previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
|
||||
uint32_t delta = get_next_tick_cc_delta();
|
||||
uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
|
||||
|
@ -502,7 +535,8 @@ static void register_next_tick() {
|
|||
uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
|
||||
|
||||
// If an overflow occur, set the next tick in COUNTER + delta clock cycles
|
||||
if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
|
||||
if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false)
|
||||
{
|
||||
new_compare_value = current_counter + delta;
|
||||
}
|
||||
nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
|
||||
|
@ -545,8 +579,9 @@ void os_tick_irqack(void)
|
|||
* @note This function is exposed by RTX kernel.
|
||||
* @return 1 if the timer has overflowed and 0 otherwise.
|
||||
*/
|
||||
uint32_t os_tick_ovf(void) {
|
||||
uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
|
||||
uint32_t os_tick_ovf(void)
|
||||
{
|
||||
uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
|
||||
uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
|
||||
|
||||
return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
|
||||
|
@ -561,25 +596,35 @@ uint32_t os_tick_ovf(void) {
|
|||
* descending order, even if the internal counter used is an ascending one.
|
||||
* @return the value of the alternative hardware timer.
|
||||
*/
|
||||
uint32_t os_tick_val(void) {
|
||||
uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
|
||||
uint32_t os_tick_val(void)
|
||||
{
|
||||
uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
|
||||
uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
|
||||
|
||||
// do not use os_tick_ovf because its counter value can be different
|
||||
if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
|
||||
if (next_tick_cc_value > previous_tick_cc_value) {
|
||||
if (is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter))
|
||||
{
|
||||
if (next_tick_cc_value > previous_tick_cc_value)
|
||||
{
|
||||
return next_tick_cc_value - current_counter;
|
||||
} else if(current_counter <= next_tick_cc_value) {
|
||||
}
|
||||
else if (current_counter <= next_tick_cc_value)
|
||||
{
|
||||
return next_tick_cc_value - current_counter;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
|
||||
}
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
// use (os_trv + 1) has the base step, can be totally inacurate ...
|
||||
uint32_t clock_cycles_by_tick = os_trv + 1;
|
||||
|
||||
// if current counter has wrap arround, add the limit to it.
|
||||
if (current_counter < next_tick_cc_value) {
|
||||
if (current_counter < next_tick_cc_value)
|
||||
{
|
||||
current_counter = current_counter + MAX_RTC_COUNTER_VAL;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue