mirror of https://github.com/ARMmbed/mbed-os.git
mcr20a use core_util_critical_section functions
parent
65a0a1aecd
commit
83a85d7830
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@ -44,7 +44,7 @@
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#if defined(MBED_CONF_NANOSTACK_CONFIGURATION) && DEVICE_SPI
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#include "platform/arm_hal_interrupt.h"
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#include "platform/mbed_critical.h"
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/*****************************************************************************
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* PRIVATE VARIABLES *
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@ -524,7 +524,7 @@ void MCR20Drv_IRQ_Disable
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void
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)
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{
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platform_enter_critical();
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core_util_critical_section_enter();
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if( mPhyIrqDisableCnt == 0 )
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{
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@ -533,7 +533,7 @@ void
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mPhyIrqDisableCnt++;
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platform_exit_critical();
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core_util_critical_section_exit();
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}
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/*---------------------------------------------------------------------------
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@ -547,7 +547,7 @@ void MCR20Drv_IRQ_Enable
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void
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)
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{
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platform_enter_critical();
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core_util_critical_section_enter();
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if( mPhyIrqDisableCnt )
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{
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@ -559,7 +559,7 @@ void
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}
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}
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platform_exit_critical();
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core_util_critical_section_exit();
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}
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/*---------------------------------------------------------------------------
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@ -1093,7 +1093,6 @@ static void rf_init_phy_mode(void)
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*/
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static void PHY_InterruptHandler(void)
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{
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/* Disable and clear transceiver(IRQ_B) interrupt */
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MCR20Drv_IRQ_Disable();
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irq_thread->signal_set(1);
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}
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@ -1106,6 +1105,7 @@ static void PHY_InterruptThread(void)
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continue;
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}
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handle_interrupt();
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MCR20Drv_IRQ_Enable();
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}
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}
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@ -1113,8 +1113,6 @@ static void handle_interrupt(void)
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{
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uint8_t xcvseqCopy;
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//MCR20Drv_IRQ_Clear();
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/* Read transceiver interrupt status and control registers */
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mStatusAndControlRegs[IRQSTS1] =
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MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[IRQSTS2], 7);
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@ -1158,7 +1156,6 @@ static void handle_interrupt(void)
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MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
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rf_ack_wait_timer_interrupt();
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MCR20Drv_IRQ_Enable();
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return;
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}
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}
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@ -1182,7 +1179,6 @@ static void handle_interrupt(void)
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{
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rf_receive();
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}
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MCR20Drv_IRQ_Enable();
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return;
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}
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@ -1205,12 +1201,10 @@ static void handle_interrupt(void)
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break;
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}
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MCR20Drv_IRQ_Enable();
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return;
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}
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/* Other IRQ. Clear XCVR interrupt flags */
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MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
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MCR20Drv_IRQ_Enable();
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}
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/*
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