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TARGET_STM USB astyle

pull/7375/head
jeromecoutant 2018-06-27 15:01:23 +02:00 committed by adbridge
parent 5612dac3b7
commit 8397a9d38b
8 changed files with 365 additions and 320 deletions
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6
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
View File

@ -42,8 +42,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -92,7 +91,8 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
hpcd.Instance = USB;

9
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
View File

@ -44,8 +44,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -71,8 +70,7 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
uint32_t len;
if (fifo == 0) {
len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ >> 16;
}
else {
} else {
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
}
return len * 4;
@ -90,7 +88,8 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
memset(&hpcd.Init, 0, sizeof(hpcd.Init));

89
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
View File

@ -139,38 +139,46 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
/* hal pcd handler , used for STM32 HAL PCD Layer */
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::~USBHAL(void) {
USBHAL::~USBHAL(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_PCD_DeInit(&hpcd);
delete HALPriv;
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(USBHAL_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(USBHAL_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
void USBHAL::setAddress(uint8_t address)
{
HAL_PCD_SetAddress(&hpcd, address);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags)
{
uint32_t epIndex = EP_ADDR(endpoint);
uint32_t type;
uint32_t len;
@ -193,7 +201,9 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag
type = 3;
break;
}
if (maxPacket > MAXTRANSFER_SIZE) return false;
if (maxPacket > MAXTRANSFER_SIZE) {
return false;
}
if (epIndex & 0x80) {
len = HAL_PCDEx_GetTxFiFo(&hpcd, epIndex & 0x7f);
MBED_ASSERT(len >= maxPacket);
@ -204,15 +214,18 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, hpcd.Setup, MAX_PACKET_SIZE_SETUP);
memset(hpcd.Setup, 0, MAX_PACKET_SIZE_SETUP);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
void USBHAL::EP0read(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t epIndex = EP_ADDR(EP0OUT);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0;
@ -223,7 +236,8 @@ void USBHAL::EP0read(void) {
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, 0);
HALPriv->epComplete[EP0OUT] = 0;
@ -234,21 +248,25 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
/* check that endpoint maximum size is not exceeding TX fifo */
MBED_ASSERT(hpcd.IN_ep[0].maxpacket >= size);
endpointWrite(EP0IN, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
stallEndpoint(EP0IN);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx;
@ -260,14 +278,16 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 0) {
/* no reception possible !!! */
bytesRead = 0;
return EP_COMPLETED;
}else if ((HALPriv->epComplete[endpoint]!=1))
} else if ((HALPriv->epComplete[endpoint] != 1)) {
return EP_PENDING;
}
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *buff = (uint8_t *)HALPriv->pBufRx;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, epIndex);
@ -277,7 +297,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
HAL_StatusTypeDef ret;
@ -286,19 +307,24 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
ret = HAL_PCD_EP_Transmit(&hpcd, epIndex, data, size);
MBED_ASSERT(ret != HAL_BUSY);
// update the status
if (ret != HAL_OK) return EP_INVALID;
if (ret != HAL_OK) {
return EP_INVALID;
}
// fix me return is too simple
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 1)
if (HALPriv->epComplete[endpoint] == 1) {
return EP_COMPLETED;
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
void USBHAL::stallEndpoint(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_StatusTypeDef ret;
HALPriv->epComplete[endpoint] = 0;
@ -306,25 +332,30 @@ void USBHAL::stallEndpoint(uint8_t endpoint) {
MBED_ASSERT(ret != HAL_BUSY);
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
HAL_StatusTypeDef ret;
ret = HAL_PCD_EP_ClrStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret != HAL_BUSY);
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
HAL_PCD_IRQHandler(&instance->hpcd);
}

90
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp
View File

@ -32,11 +32,13 @@ static uint32_t rxFifoCount = 0;
static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
@ -94,32 +96,39 @@ USBHAL::USBHAL(void) {
NVIC_SetPriority(OTG_FS_IRQn, 1);
}
USBHAL::~USBHAL(void) {
USBHAL::~USBHAL(void)
{
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(OTG_FS_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
void USBHAL::setAddress(uint8_t address)
{
OTG_FS->DREGS.DCFG |= (address << 4);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
uint32_t flags) {
uint32_t flags)
{
uint32_t epIndex = endpoint >> 1;
uint32_t type;
@ -151,8 +160,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
if (endpoint == EP0IN) {
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
else {
} else {
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
@ -169,8 +177,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
}
else { // Out endpoint
} else { // Out endpoint
// Set the out EP specific control settings
control |= (1 << 26); // CNAK
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
@ -182,17 +189,21 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
void USBHAL::EP0read(void)
{
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
uint32_t *buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
@ -203,14 +214,17 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
endpointWrite(0, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
// If we stall the out endpoint here then we have problems transferring
// and setup requests after the (stalled) get device qualifier requests.
// TODO: Find out if this is correct behavior, or whether we are doing
@ -219,7 +233,8 @@ void USBHAL::EP0stall(void) {
// stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
uint32_t epIndex = endpoint >> 1;
uint32_t size = (1 << 19) | // 1 packet
(maximumSize << 0); // Packet size
@ -234,7 +249,8 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
if (!(epComplete & (1 << endpoint))) {
return EP_PENDING;
}
@ -249,7 +265,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
uint32_t epIndex = endpoint >> 1;
OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
(size << 0); // Size of packet
@ -268,7 +285,8 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
if (epComplete & (1 << endpoint)) {
epComplete &= ~(1 << endpoint);
return EP_COMPLETED;
@ -277,36 +295,41 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
void USBHAL::stallEndpoint(uint8_t endpoint)
{
if (endpoint & 0x1) { // In EP
OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
else { // Out EP
} else { // Out EP
OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
suspendStateChanged(1);
};
@ -363,8 +386,7 @@ void USBHAL::usbisr(void) {
// Out packet
if (endpoint == EP0OUT) {
EP0out();
}
else {
} else {
epComplete |= (1 << endpoint);
if ((instance->*(epCallback[endpoint - 2]))()) {
epComplete &= ~(1 << endpoint);

21
features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h
View File

@ -28,8 +28,7 @@
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
typedef struct //000h
{
typedef struct { //000h
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
@ -51,8 +50,7 @@ typedef struct //000h
}
USB_OTG_GREGS;
typedef struct // 800h
{
typedef struct { // 800h
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
@ -70,8 +68,7 @@ typedef struct // 800h
}
USB_OTG_DREGS;
typedef struct
{
typedef struct {
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
@ -83,8 +80,7 @@ typedef struct
}
USB_OTG_INEPREGS;
typedef struct
{
typedef struct {
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
@ -94,8 +90,7 @@ typedef struct
}
USB_OTG_OUTEPREGS;
typedef struct
{
typedef struct {
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
@ -106,8 +101,7 @@ typedef struct
}
USB_OTG_HREGS;
typedef struct
{
typedef struct {
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
@ -117,8 +111,7 @@ typedef struct
}
USB_OTG_HC_REGS;
typedef struct
{
typedef struct {
USB_OTG_GREGS GREGS;
uint32_t RESERVED0[188];
USB_OTG_HREGS HREGS;