diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct
new file mode 100644
index 0000000000..f9ead04667
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S
new file mode 100644
index 0000000000..124a5e65c8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S
@@ -0,0 +1,213 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM0.s
+; * @brief CMSIS Cortex-M0 Core Device Startup File for
+; * Device CMSDK_CM0
+; * @version V3.01
+; * @date 06. March 2012
+; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
+
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
+ DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
+ DCD UART0_Handler ; 16+ 2: UART 0 Handler
+ DCD UART1_Handler ; 16+ 3: UART 1 Handler
+ DCD UART2_Handler ; 16+ 4: UART 2 Handler
+ DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
+ DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
+ DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
+ DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
+ DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
+ DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
+ DCD DMA_Handler ; 16+11: DMA Combined Handler
+ DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
+ DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
+ DCD PWM0_Handler ; 16+14: PWM0 Handler
+ DCD PWM1_Handler ; 16+15: PWM1 Handler
+ DCD PWM2_Handler ; 16+16: PWM2 Handler
+ DCD PWM3_Handler ; 16+17: PWM3 Handler
+ DCD PWM4_Handler ; 16+18: PWM4 Handler
+ DCD PWM5_Handler ; 16+19: PWM5 Handler
+ DCD PWM6_Handler ; 16+20: PWM6 Handler
+ DCD PWM7_Handler ; 16+21: PWM7 Handler
+ DCD RTC_Handler ; 16+22: RTC Handler
+ DCD ADC_Handler ; 16+23: ADC Handler
+ DCD WZTOE_Handler ; 16+24: WZTOE_Handler
+ DCD EXTI_Handler ; 16+25: EXTI_Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Default_Handler PROC
+ EXPORT SSP0_Handler [WEAK]
+ EXPORT SSP1_Handler [WEAK]
+ EXPORT UART0_Handler [WEAK]
+ EXPORT UART1_Handler [WEAK]
+ EXPORT UART2_Handler [WEAK]
+ EXPORT I2C0_Handler [WEAK]
+ EXPORT I2C1_Handler [WEAK]
+ EXPORT PORT0_Handler [WEAK]
+ EXPORT PORT1_Handler [WEAK]
+ EXPORT PORT2_Handler [WEAK]
+ EXPORT PORT3_Handler [WEAK]
+ EXPORT DMA_Handler [WEAK]
+ EXPORT DUALTIMER0_Handler [WEAK]
+ EXPORT DUALTIMER1_Handler [WEAK]
+ EXPORT PWM0_Handler [WEAK]
+ EXPORT PWM1_Handler [WEAK]
+ EXPORT PWM2_Handler [WEAK]
+ EXPORT PWM3_Handler [WEAK]
+ EXPORT PWM4_Handler [WEAK]
+ EXPORT PWM5_Handler [WEAK]
+ EXPORT PWM6_Handler [WEAK]
+ EXPORT PWM7_Handler [WEAK]
+ EXPORT RTC_Handler [WEAK]
+ EXPORT ADC_Handler [WEAK]
+ EXPORT WZTOE_Handler [WEAK]
+ EXPORT EXTI_Handler [WEAK]
+SSP0_Handler
+SSP1_Handler
+UART0_Handler
+UART1_Handler
+UART2_Handler
+I2C0_Handler
+I2C1_Handler
+PORT0_Handler
+PORT1_Handler
+PORT2_Handler
+PORT3_Handler
+DMA_Handler
+DUALTIMER0_Handler
+DUALTIMER1_Handler
+PWM0_Handler
+PWM1_Handler
+PWM2_Handler
+PWM3_Handler
+PWM4_Handler
+PWM5_Handler
+PWM6_Handler
+PWM7_Handler
+RTC_Handler
+ADC_Handler
+WZTOE_Handler
+EXTI_Handler
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct
new file mode 100644
index 0000000000..f9ead04667
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S
new file mode 100644
index 0000000000..5b161ed02e
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S
@@ -0,0 +1,186 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM0.s
+; * @brief CMSIS Cortex-M0 Core Device Startup File for
+; * Device CMSDK_CM0
+; * @version V3.01
+; * @date 06. March 2012
+; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
+
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
+ DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
+ DCD UART0_Handler ; 16+ 2: UART 0 Handler
+ DCD UART1_Handler ; 16+ 3: UART 1 Handler
+ DCD UART2_Handler ; 16+ 4: UART 2 Handler
+ DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
+ DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
+ DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
+ DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
+ DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
+ DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
+ DCD DMA_Handler ; 16+11: DMA Combined Handler
+ DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
+ DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
+ DCD PWM0_Handler ; 16+14: PWM0 Handler
+ DCD PWM1_Handler ; 16+15: PWM1 Handler
+ DCD PWM2_Handler ; 16+16: PWM2 Handler
+ DCD PWM3_Handler ; 16+17: PWM3 Handler
+ DCD PWM4_Handler ; 16+18: PWM4 Handler
+ DCD PWM5_Handler ; 16+19: PWM5 Handler
+ DCD PWM6_Handler ; 16+20: PWM6 Handler
+ DCD PWM7_Handler ; 16+21: PWM7 Handler
+ DCD RTC_Handler ; 16+22: RTC Handler
+ DCD ADC_Handler ; 16+23: ADC Handler
+ DCD WZTOE_Handler ; 16+24: WZTOE_Handler
+ DCD EXTI_Handler ; 16+25: EXTI_Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Default_Handler PROC
+ EXPORT SSP0_Handler [WEAK]
+ EXPORT SSP1_Handler [WEAK]
+ EXPORT UART0_Handler [WEAK]
+ EXPORT UART1_Handler [WEAK]
+ EXPORT UART2_Handler [WEAK]
+ EXPORT I2C0_Handler [WEAK]
+ EXPORT I2C1_Handler [WEAK]
+ EXPORT PORT0_Handler [WEAK]
+ EXPORT PORT1_Handler [WEAK]
+ EXPORT PORT2_Handler [WEAK]
+ EXPORT PORT3_Handler [WEAK]
+ EXPORT DMA_Handler [WEAK]
+ EXPORT DUALTIMER0_Handler [WEAK]
+ EXPORT DUALTIMER1_Handler [WEAK]
+ EXPORT PWM0_Handler [WEAK]
+ EXPORT PWM1_Handler [WEAK]
+ EXPORT PWM2_Handler [WEAK]
+ EXPORT PWM3_Handler [WEAK]
+ EXPORT PWM4_Handler [WEAK]
+ EXPORT PWM5_Handler [WEAK]
+ EXPORT PWM6_Handler [WEAK]
+ EXPORT PWM7_Handler [WEAK]
+ EXPORT RTC_Handler [WEAK]
+ EXPORT ADC_Handler [WEAK]
+ EXPORT WZTOE_Handler [WEAK]
+ EXPORT EXTI_Handler [WEAK]
+SSP0_Handler
+SSP1_Handler
+UART0_Handler
+UART1_Handler
+UART2_Handler
+I2C0_Handler
+I2C1_Handler
+PORT0_Handler
+PORT1_Handler
+PORT2_Handler
+PORT3_Handler
+DMA_Handler
+DUALTIMER0_Handler
+DUALTIMER1_Handler
+PWM0_Handler
+PWM1_Handler
+PWM2_Handler
+PWM3_Handler
+PWM4_Handler
+PWM5_Handler
+PWM6_Handler
+PWM7_Handler
+RTC_Handler
+ADC_Handler
+WZTOE_Handler
+EXTI_Handler
+ B .
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld
new file mode 100644
index 0000000000..0d53146fc5
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld
@@ -0,0 +1,152 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S
new file mode 100644
index 0000000000..2808b2ad57
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S
@@ -0,0 +1,259 @@
+/* File: startup_W7500.s
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 20 Dezember 2012
+ *
+ */
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+
+/*
+// Stack Configuration
+// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+*/
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x200
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+
+/*
+// Heap Configuration
+// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+*/
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+/* Vector Table */
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long SSP0_Handler /* 16+ 0: SSP 0 Handler */
+ .long SSP1_Handler /* 16+ 1: SSP 1 Handler */
+ .long UART0_Handler /* 16+ 2: UART 0 Handler */
+ .long UART1_Handler /* 16+ 3: UART 1 Handler */
+ .long UART2_Handler /* 16+ 4: UART 2 Handler */
+ .long I2C0_Handler /* 16+ 5: I2C 0 Handler */
+ .long I2C1_Handler /* 16+ 6: I2C 1 Handler */
+ .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */
+ .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */
+ .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */
+ .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */
+ .long DMA_Handler /* 16+11: DMA Combined Handler */
+ .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */
+ .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */
+ .long PWM0_Handler /* 16+ 14: PWM0 Handler */
+ .long PWM1_Handler /* 16+ 15: PWM1 Handler */
+ .long PWM2_Handler /* 16+ 16: PWM2 Handler */
+ .long PWM3_Handler /* 16+ 17: PWM3 Handler */
+ .long PWM4_Handler /* 16+ 18: PWM4 Handler */
+ .long PWM5_Handler /* 16+ 19: PWM5 Handler */
+ .long PWM6_Handler /* 16+ 20: PWM6 Handler */
+ .long PWM7_Handler /* 16+ 21: PWM7 Handler */
+ .long RTC_Handler /* 16+ 22: RTC Handler */
+ .long ADC_Handler /* 16+ 23: ADC Handler */
+ .long WZTOE_Handler /* 16+ 24: WZTOE Handler */
+ .long EXTI_Handler /* 16+ 25: EXTI Handler */
+
+ .size __isr_vector, . - __isr_vector
+/* Reset Handler */
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC1
+.LC0:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0
+.LC1:
+
+#ifdef __STARTUP_CLEAR_BSS
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * Loop to zero out BSS section, which uses following symbols
+ * in linker script:
+ * __bss_start__: start of BSS section. Must align to 4
+ * __bss_end__: end of BSS section. Must align to 4
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ subs r2, r1
+ ble .LC3
+
+ movs r0, 0
+.LC2:
+ str r0, [r1, r2]
+ subs r2, 4
+ bge .LC2
+.LC3:
+#endif /* __STARTUP_CLEAR_BSS */
+
+ /*bl _start*/
+ bl main
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+/* System Exception Handlers */
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+
+/* IRQ Handlers */
+
+ def_default_handler SSP0_Handler
+ def_default_handler SSP1_Handler
+ def_default_handler UART0_Handler
+ def_default_handler UART1_Handler
+ def_default_handler UART2_Handler
+ def_default_handler I2C0_Handler
+ def_default_handler I2C1_Handler
+ def_default_handler PORT0_Handler
+ def_default_handler PORT1_Handler
+ def_default_handler PORT2_Handler
+ def_default_handler PORT3_Handler
+
+ def_default_handler DMA_Handler
+ def_default_handler DUALTIMER0_Handler
+ def_default_handler DUALTIMER1_Handler
+ def_default_handler PWM0_Handler
+ def_default_handler PWM1_Handler
+ def_default_handler PWM2_Handler
+ def_default_handler PWM3_Handler
+ def_default_handler PWM4_Handler
+ def_default_handler PWM5_Handler
+ def_default_handler PWM6_Handler
+ def_default_handler PWM7_Handler
+ def_default_handler RTC_Handler
+ def_default_handler ADC_Handler
+ def_default_handler WZTOE_Handler
+ def_default_handler EXTI_Handler
+
+ /*
+ def_default_handler Default_Handler
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+ */
+
+ .end
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o
new file mode 100644
index 0000000000..6154940481
Binary files /dev/null and b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o differ
diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c
new file mode 100644
index 0000000000..03ad45093e
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c
@@ -0,0 +1,136 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+
+
+//*** ADC ***
+const PinMap PinMap_ADC[] = {
+ {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0
+ {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1
+ {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2
+ {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3
+ {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6
+ {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7
+ {NC, NC, 0}
+};
+
+
+//*** SERIAL ***
+const PinMap PinMap_UART_TX[] = {
+ {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PB_2, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PA_9, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_6, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PB_3, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PA_10, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_7, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_PWM[] = {
+ {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_9 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_1 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {NC , NC , 0}
+};
+
diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h
new file mode 100644
index 0000000000..8e8aba2c93
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h
@@ -0,0 +1,236 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM
+#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0)))
+#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F)
+#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F)
+#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F)
+#define WIZ_MODE_INPUT (0)
+#define WIZ_MODE_OUTPUT (1)
+#define WIZ_MODE_AF (2)
+
+#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */
+#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */
+#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */
+#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */
+
+
+#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D)
+#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number
+#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit
+
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+
+typedef enum {
+ // W7500x PORT[5:4] + PIN[3:0])
+ PA_0 = 0x000,
+ PA_1 = 0x001,
+ PA_2 = 0x002,
+ PA_3 = 0x003,
+ PA_4 = 0x004,
+ PA_5 = 0x005,
+ PA_6 = 0x006,
+ PA_7 = 0x007,
+ PA_8 = 0x008,
+ PA_9 = 0x009,
+ PA_10 = 0x00A,
+ PA_11 = 0x00B,
+ PA_12 = 0x00C,
+ PA_13 = 0x00D,
+ PA_14 = 0x00E,
+ PA_15 = 0x00F,
+
+ PB_0 = 0x010,
+ PB_1 = 0x011,
+ PB_2 = 0x012,
+ PB_3 = 0x013,
+ PB_4 = 0x014,
+ PB_5 = 0x015,
+ PB_6 = 0x016,
+ PB_7 = 0x017,
+ PB_8 = 0x018,
+ PB_9 = 0x019,
+ PB_10 = 0x01A,
+ PB_11 = 0x01B,
+ PB_12 = 0x01C,
+ PB_13 = 0x01D,
+ PB_14 = 0x01E,
+ PB_15 = 0x01F,
+
+ PC_0 = 0x020,
+ PC_1 = 0x021,
+ PC_2 = 0x022,
+ PC_3 = 0x023,
+ PC_4 = 0x024,
+ PC_5 = 0x025,
+ PC_6 = 0x026,
+ PC_7 = 0x027,
+ PC_8 = 0x028,
+ PC_9 = 0x029,
+
+ PC_10 = 0x02A,
+ PC_11 = 0x02B,
+ PC_12 = 0x02C,
+ PC_13 = 0x02D,
+ PC_14 = 0x02E,
+ PC_15 = 0x02F,
+
+ PD_0 = 0x030,
+ PD_1 = 0x031,
+ PD_2 = 0x032,
+ PD_3 = 0x033,
+ PD_4 = 0x034,
+
+ PA_00 = PA_0,
+ PA_01 = PA_1,
+ PA_02 = PA_2,
+ PA_03 = PA_3,
+ PA_04 = PA_4,
+ PA_05 = PA_5,
+ PA_06 = PA_6,
+ PA_07 = PA_7,
+ PA_08 = PA_8,
+ PA_09 = PA_9,
+
+ PB_00 = PB_0,
+ PB_01 = PB_1,
+ PB_02 = PB_2,
+ PB_03 = PB_3,
+ PB_04 = PB_4,
+ PB_05 = PB_5,
+ PB_06 = PB_6,
+ PB_07 = PB_7,
+ PB_08 = PB_8,
+ PB_09 = PB_9,
+
+ PC_00 = PC_0,
+ PC_01 = PC_1,
+ PC_02 = PC_2,
+ PC_03 = PC_3,
+ PC_04 = PC_4,
+ PC_05 = PC_5,
+ PC_06 = PC_6,
+ PC_07 = PC_7,
+ PC_08 = PC_8,
+ PC_09 = PC_9,
+
+ PD_00 = PD_0,
+ PD_01 = PD_1,
+ PD_02 = PD_2,
+ PD_03 = PD_3,
+ PD_04 = PD_4,
+
+
+ // Generic signals namings
+ LED_RED = PC_8,
+ LED_GREEN = PC_9,
+ LED_BLUE = PC_5,
+
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_BLUE,
+
+ LEDR = LED_RED,
+ LEDG = LED_GREEN,
+ LEDB = LED_BLUE,
+
+ USBTX = PC_10,
+ USBRX = PC_11,
+
+ // For ECO
+ P5 = PA_5,
+ P6 = PA_6,
+ P7 = PA_7,
+ P8 = PA_8,
+ P9 = PA_9,
+ P10 = PA_10,
+ P11 = PA_11,
+ P12 = PA_12,
+ P13 = PA_13,
+ P14 = PA_14,
+ P15 = PB_0,
+ P16 = PB_1,
+ P17 = PB_2,
+ P18 = PB_3,
+ P19 = PC_5,
+ P20 = PC_4,
+ P21 = PC_0,
+ P22 = PC_1,
+ P23 = PC_2,
+ P24 = PC_3,
+ P25 = PC_8,
+ P26 = PC_9,
+ P27 = PC_12,
+ P28 = PC_13,
+ P29 = PC_14,
+ P30 = PC_15,
+ P31 = PC_6,
+ P32 = PC_7,
+
+ //Use SPI1
+ SD_SEL = PB_0, // SPI1_CS
+ SD_CLK = PB_1, // SPI1_CLK
+ SD_MISO = PB_2, // MOSI1
+ SD_MOSI = PB_3, // MISO1
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 2,
+ PullDefault = PullNone
+} PinMode;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h
new file mode 100644
index 0000000000..2645702c52
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN 1
+#define DEVICE_PORTOUT 1
+#define DEVICE_PORTINOUT 1
+
+#define DEVICE_INTERRUPTIN 1
+
+#define DEVICE_ANALOGIN 1
+#define DEVICE_ANALOGOUT 0 // Not present on this device
+
+#define DEVICE_SERIAL 1
+
+#define DEVICE_I2C 1
+#define DEVICE_I2CSLAVE 0
+
+#define DEVICE_SPI 1
+#define DEVICE_SPISLAVE 1
+
+#define DEVICE_RTC 1
+
+#define DEVICE_PWMOUT 1
+
+#define DEVICE_SLEEP 0
+
+#define DEVICE_ETHERNET 0
+
+
+//=======================================
+
+#define DEVICE_SEMIHOST 0
+#define DEVICE_LOCALFILESYSTEM 0
+#define DEVICE_ID_LENGTH 24
+
+#define DEVICE_DEBUG_AWARENESS 0
+
+#define DEVICE_STDIO_MESSAGES 1
+
+#define STDIO_UART_TX PC_10
+#define STDIO_UART_RX PC_11
+#define STDIO_UART UART_2
+
+
+#define DEVICE_ERROR_RED 0
+
+#include "objects.h"
+
+#endif