From afe8834bb8aa0d094cf629b9c0b11030f48af599 Mon Sep 17 00:00:00 2001 From: deepikabhavnani Date: Wed, 22 Nov 2017 15:41:37 -0600 Subject: [PATCH 01/42] CRC class implementation CRC class `MbedCRC.h` is templated class created to support hardware/software CRCs. Default CRC will be hardware CRC when support for HAL is available. Polynomial tables are available for 8/16 bit CCITT, 7/16 bit for SD card and 32-bit ANSI. Polynomial table implementation will be used if Hardware CRC is not available. In case device does not have hardware CRC and polynomial table is not supported, CRC is still available and is computed runtime bit by bit for all data input. --- drivers/MbedCRC.h | 463 +++++++++++++++++++++++++++++++++++++++++++++ drivers/TableCRC.h | 150 +++++++++++++++ 2 files changed, 613 insertions(+) create mode 100644 drivers/MbedCRC.h create mode 100644 drivers/TableCRC.h diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h new file mode 100644 index 0000000000..c4d35b1a0e --- /dev/null +++ b/drivers/MbedCRC.h @@ -0,0 +1,463 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CRC_API_H +#define MBED_CRC_API_H + +#include +#include "drivers/TableCRC.h" + +#if defined ( __CC_ARM ) +#pragma diag_suppress 62 // Shift count is negative +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wshift-count-negative" +#endif + +namespace mbed { +/** \addtogroup drivers */ +/** @{*/ + +/** CRC Polynomial value + * + * Different polynomial values supported + */ +typedef enum crc_polynomial { + POLY_OTHER = 0, + POLY_8BIT_CCITT = 0x07, // x8+x2+x+1 + POLY_7BIT_SD = 0x9, // x7+x3+1; + POLY_16BIT_CCITT = 0x1021, // x16+x12+x5+1 + POLY_16BIT_IBM = 0x8005, // x16+x15+x2+1 + POLY_32BIT_ANSI = 0x04C11DB7, // x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 +} crc_polynomial_t; + +/** CRC object provides CRC generation through hardware/software + * + * @tparam polynomial CRC polynomial value in hex + * @tparam width CRC polynomial width + */ + +template +class MbedCRC +{ +public: + typedef uint64_t crc_data_size_t; + + /** Lifetime of CRC object + * + * @param initial_xor Inital value/seed to Xor (Default ~0x0) + * @param final_xor Final Xor value (Default ~0x0) + * @param reflect_data + * @param reflect_remainder + */ + MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder); + MbedCRC(); + virtual ~MbedCRC() + { + // Do nothing + } + + /** Initialize a CRC module + * + * @return 0 on success or a negative error code on failure + */ + int32_t init(void) + { + return 0; + } + + /** Deinitialize a CRC module + * + * @return 0 on success, negative error code on failure + */ + int32_t deinit(void) + { + return 0; + } + + /** Compute CRC for the data input + * + * @param buffer Data bytes + * @param size Size of data + * @param crc CRC is the output value + * @return 0 on success, negative error code on failure + */ + int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc) + { + int32_t status; + if (0 != (status = compute_partial_start(crc))) { + *crc = 0; + return status; + } + if (0 != (status = compute_partial(buffer, size, crc))) { + *crc = 0; + return status; + } + if (0 != (status = compute_partial_stop(crc))) { + *crc = 0; + return status; + } + return 0; + } + + /** Compute partial CRC for the data input. + * + * CRC data if not available fully, CRC can be computed in parts with available data. + * Previous CRC output should be passed as argument to the current compute_partial call. + * @pre: Call \ref compute_partial_start to start the partial CRC calculation. + * @post: Call \ref compute_partial_stop to get the final CRC value. + * + * @param buffer Data bytes + * @param size Size of data + * @param crc CRC value is intermediate CRC value filled by API. + * @return 0 on success or a negative error code on failure + * @note: CRC as output in compute_partial is not final CRC value, call @ref compute_partial_stop + * to get final correct CRC value. + */ + int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc) + { + if (NULL == _crc_table) { + // Compute Slow CRC + return bitwise_compute_partial(buffer, size, crc); + } else { + // Table CRC + return table_compute_partial(buffer, size, crc); + } + } + + /** Compute partial start, indicate start of partial computation + * + * This API should be called before performing any partial computation + * with compute_partial API. + * + * @param crc Initial CRC value set by the API + * @return 0 on success or a negative in case of failure + * @note: CRC is an out parameter and must be reused with compute_partial + * and compute_partial_stop without any modifications in application. + */ + int32_t compute_partial_start(uint32_t *crc) + { + MBED_ASSERT(crc != NULL); + *crc = _initial_value; + return 0; + } + + /** Get the final CRC value of partial computation. + * + * CRC value available in partial computation is not correct CRC, as some + * algorithms require remainder to be reflected and final value to be XORed + * This API is used to perform final computation to get correct CRC value. + * + * @param crc CRC result + */ + int32_t compute_partial_stop(uint32_t *crc) + { + MBED_ASSERT(crc != NULL); + uint32_t p_crc = *crc; + if ((width < 8) && (NULL == _crc_table)) { + p_crc = (uint32_t)(p_crc << (8 - width)); + } + *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask(); + return 0; + } + + /** Get the current CRC polynomial + * + * @return Polynomial value + */ + uint32_t get_polynomial(void) const + { + return polynomial; + } + + /** Get the current CRC width + * + * @return CRC width + */ + uint8_t get_width(void) const + { + return width; + } + +private: + uint32_t _initial_value; + uint32_t _final_xor; + bool _reflect_data; + bool _reflect_remainder; + uint32_t *_crc_table; + + /** Get the current CRC data size + * + * @return CRC data size in bytes + */ + uint8_t get_data_size(void) const + { + return (width <= 8 ? 1 : (width <= 16 ? 2 : 4)); + } + + /** Get the top bit of current CRC + * + * @return Top bit is set high for respective data width of current CRC + * Top bit for CRC width less then 8 bits will be set as 8th bit. + */ + uint32_t get_top_bit(void) const + { + return (width < 8 ? (1u << 7) : (uint32_t)(1ul << (width - 1))); + } + + /** Get the CRC data mask + * + * @return CRC data mask is generated based on current CRC width + */ + uint32_t get_crc_mask(void) const + { + return (width < 8 ? ((1u << 8)-1) : (uint32_t)((uint64_t)(1ull << width) - 1)); + } + + /** Final value of CRC is reflected + * + * @param data final crc value, which should be reflected + * @return Reflected CRC value + */ + uint32_t reflect_remainder(uint32_t data) const + { + if (_reflect_remainder) { + uint32_t reflection = 0x0; + uint8_t const nBits = (width < 8 ? 8 : width); + + for (uint8_t bit = 0; bit < nBits; ++bit) { + if (data & 0x01) { + reflection |= (1 << ((nBits - 1) - bit)); + } + data = (data >> 1); + } + return (reflection); + } else { + return data; + } + } + + /** Data bytes are reflected + * + * @param data value to be reflected + * @return Reflected data value + */ + uint32_t reflect_bytes(uint32_t data) const + { + if(_reflect_data) { + uint32_t reflection = 0x0; + + for (uint8_t bit = 0; bit < 8; ++bit) { + if (data & 0x01) { + reflection |= (1 << (7 - bit)); + } + data = (data >> 1); + } + return (reflection); + } else { + return data; + } + } + + /** Bitwise CRC computation + * + * @param buffer data buffer + * @param size size of the data + * @param crc CRC value is filled in, but the value is not the final + * @return 0 on success or a negative error code on failure + */ + int32_t bitwise_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const + { + MBED_ASSERT(crc != NULL); + MBED_ASSERT(buffer != NULL); + + const uint8_t *data = static_cast(buffer); + uint32_t p_crc = *crc; + + if (width < 8) { + uint8_t data_byte; + for (crc_data_size_t byte = 0; byte < size; byte++) { + data_byte = reflect_bytes(data[byte]); + for (uint8_t bit = 8; bit > 0; --bit) { + p_crc <<= 1; + if (( data_byte ^ p_crc) & get_top_bit()) { + p_crc ^= polynomial; + } + data_byte <<= 1; + } + } + } else { + for (crc_data_size_t byte = 0; byte < size; byte++) { + p_crc ^= (reflect_bytes(data[byte]) << (width - 8)); + + // Perform modulo-2 division, a bit at a time + for (uint8_t bit = 8; bit > 0; --bit) { + if (p_crc & get_top_bit()) { + p_crc = (p_crc << 1) ^ polynomial; + } else { + p_crc = (p_crc << 1); + } + } + } + } + *crc = p_crc & get_crc_mask(); + return 0; + } + + /** CRC computation using ROM tables + * + * @param buffer data buffer + * @param size size of the data + * @param crc CRC value is filled in, but the value is not the final + * @return 0 on success or a negative error code on failure + */ + int32_t table_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const + { + MBED_ASSERT(crc != NULL); + MBED_ASSERT(buffer != NULL); + + const uint8_t *data = static_cast(buffer); + uint32_t p_crc = *crc; + uint8_t data_byte = 0; + + if (width <= 8) { + uint8_t *crc_table = (uint8_t *)_crc_table; + for (crc_data_size_t byte = 0; byte < size; byte++) { + data_byte = reflect_bytes(data[byte]) ^ p_crc; + p_crc = crc_table[data_byte]; + } + } else if (width <= 16) { + uint16_t *crc_table = (uint16_t *)_crc_table; + for (crc_data_size_t byte = 0; byte < size; byte++) { + data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8)); + p_crc = crc_table[data_byte] ^ (p_crc << 8); + } + } else { + uint32_t *crc_table = (uint32_t *)_crc_table; + for (crc_data_size_t byte = 0; byte < size; byte++) { + data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8)); + p_crc = crc_table[data_byte] ^ (p_crc << 8); + } + } + *crc = p_crc & get_crc_mask(); + return 0; + } + + /** Constructor init called from all specialized cases of constructor + * Note: All construtor common code should be in this function. + */ + void mbed_crc_ctor(void) const + { + MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported"); + } +}; + +/* Default values for different types of polynomials +*/ +template +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), _crc_table(NULL) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_32bit_ANSI) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_8bit_CCITT) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_7Bit_SD) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_16bit_CCITT) +{ +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_16bit_IBM) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true), + _crc_table((uint32_t *)Table_CRC_32bit_ANSI) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(true), _reflect_remainder(true), + _crc_table((uint32_t *)Table_CRC_16bit_IBM) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(~(0x0)), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_16bit_CCITT) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_7Bit_SD) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_8bit_CCITT) +{ + mbed_crc_ctor(); +} + +#if defined ( __CC_ARM ) +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/** @}*/ +} // namespace mbed + +#endif diff --git a/drivers/TableCRC.h b/drivers/TableCRC.h new file mode 100644 index 0000000000..34704fcef3 --- /dev/null +++ b/drivers/TableCRC.h @@ -0,0 +1,150 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TABLE_CRC_H +#define TABLE_CRC_H + +#include + +namespace mbed { +/** \addtogroup drivers */ +/** @{*/ + +const uint8_t Table_CRC_7Bit_SD[] = { + 0x0, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee, + 0x32, 0x20, 0x16, 0x4, 0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc, + 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8, 0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a, + 0x56, 0x44, 0x72, 0x60, 0x1e, 0xc, 0x3a, 0x28, 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8, + 0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6, 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x2, 0x34, 0x26, + 0xfa, 0xe8, 0xde, 0xcc, 0xb2, 0xa0, 0x96, 0x84, 0x6a, 0x78, 0x4e, 0x5c, 0x22, 0x30, 0x6, 0x14, + 0xac, 0xbe, 0x88, 0x9a, 0xe4, 0xf6, 0xc0, 0xd2, 0x3c, 0x2e, 0x18, 0xa, 0x74, 0x66, 0x50, 0x42, + 0x9e, 0x8c, 0xba, 0xa8, 0xd6, 0xc4, 0xf2, 0xe0, 0xe, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x70, + 0x82, 0x90, 0xa6, 0xb4, 0xca, 0xd8, 0xee, 0xfc, 0x12, 0x0, 0x36, 0x24, 0x5a, 0x48, 0x7e, 0x6c, + 0xb0, 0xa2, 0x94, 0x86, 0xf8, 0xea, 0xdc, 0xce, 0x20, 0x32, 0x4, 0x16, 0x68, 0x7a, 0x4c, 0x5e, + 0xe6, 0xf4, 0xc2, 0xd0, 0xae, 0xbc, 0x8a, 0x98, 0x76, 0x64, 0x52, 0x40, 0x3e, 0x2c, 0x1a, 0x8, + 0xd4, 0xc6, 0xf0, 0xe2, 0x9c, 0x8e, 0xb8, 0xaa, 0x44, 0x56, 0x60, 0x72, 0xc, 0x1e, 0x28, 0x3a, + 0x4a, 0x58, 0x6e, 0x7c, 0x2, 0x10, 0x26, 0x34, 0xda, 0xc8, 0xfe, 0xec, 0x92, 0x80, 0xb6, 0xa4, + 0x78, 0x6a, 0x5c, 0x4e, 0x30, 0x22, 0x14, 0x6, 0xe8, 0xfa, 0xcc, 0xde, 0xa0, 0xb2, 0x84, 0x96, + 0x2e, 0x3c, 0xa, 0x18, 0x66, 0x74, 0x42, 0x50, 0xbe, 0xac, 0x9a, 0x88, 0xf6, 0xe4, 0xd2, 0xc0, + 0x1c, 0xe, 0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2 +}; + +const uint8_t Table_CRC_8bit_CCITT[] = { + 0x0, 0x7, 0xe, 0x9, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, + 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, + 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, + 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, + 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, + 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, + 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x3, 0x4, 0xd, 0xa, + 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, + 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, + 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, + 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, + 0x19, 0x1e, 0x17, 0x10, 0x5, 0x2, 0xb, 0xc, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, + 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, + 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x6, 0x1, 0x8, 0xf, 0x1a, 0x1d, 0x14, 0x13, + 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, + 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 +}; + +const uint16_t Table_CRC_16bit_CCITT[] = { + 0x0, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b, + 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420, 0x1401, + 0x64e6, 0x74c7, 0x44a4, 0x5485, 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738, + 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, + 0x1a71, 0xa50, 0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0xc60, 0x1c41, 0xedae, 0xfd8f, 0xcdec, 0xddcd, + 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0xe70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, 0xa1eb, + 0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0xa1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x2b1, 0x1290, 0x22f3, 0x32d2, + 0x4235, 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x481, 0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8, + 0xe75f, 0xf77e, 0xc71d, 0xd73c, 0x26d3, 0x36f2, 0x691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827, + 0x18c0, 0x8e1, 0x3882, 0x28a3, 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0xaf1, 0x1ad0, 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, + 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0xcc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 0x6e17, 0x7e36, 0x4e55, 0x5e74, + 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +const uint16_t Table_CRC_16bit_IBM[] = { + 0x0, 0x8005, 0x800f, 0xa, 0x801b, 0x1e, 0x14, 0x8011, 0x8033, 0x36, 0x3c, 0x8039, + 0x28, 0x802d, 0x8027, 0x22, 0x8063, 0x66, 0x6c, 0x8069, 0x78, 0x807d, 0x8077, 0x72, + 0x50, 0x8055, 0x805f, 0x5a, 0x804b, 0x4e, 0x44, 0x8041, 0x80c3, 0xc6, 0xcc, 0x80c9, + 0xd8, 0x80dd, 0x80d7, 0xd2, 0xf0, 0x80f5, 0x80ff, 0xfa, 0x80eb, 0xee, 0xe4, 0x80e1, + 0xa0, 0x80a5, 0x80af, 0xaa, 0x80bb, 0xbe, 0xb4, 0x80b1, 0x8093, 0x96, 0x9c, 0x8099, + 0x88, 0x808d, 0x8087, 0x82, 0x8183, 0x186, 0x18c, 0x8189, 0x198, 0x819d, 0x8197, 0x192, + 0x1b0, 0x81b5, 0x81bf, 0x1ba, 0x81ab, 0x1ae, 0x1a4, 0x81a1, 0x1e0, 0x81e5, 0x81ef, 0x1ea, + 0x81fb, 0x1fe, 0x1f4, 0x81f1, 0x81d3, 0x1d6, 0x1dc, 0x81d9, 0x1c8, 0x81cd, 0x81c7, 0x1c2, + 0x140, 0x8145, 0x814f, 0x14a, 0x815b, 0x15e, 0x154, 0x8151, 0x8173, 0x176, 0x17c, 0x8179, + 0x168, 0x816d, 0x8167, 0x162, 0x8123, 0x126, 0x12c, 0x8129, 0x138, 0x813d, 0x8137, 0x132, + 0x110, 0x8115, 0x811f, 0x11a, 0x810b, 0x10e, 0x104, 0x8101, 0x8303, 0x306, 0x30c, 0x8309, + 0x318, 0x831d, 0x8317, 0x312, 0x330, 0x8335, 0x833f, 0x33a, 0x832b, 0x32e, 0x324, 0x8321, + 0x360, 0x8365, 0x836f, 0x36a, 0x837b, 0x37e, 0x374, 0x8371, 0x8353, 0x356, 0x35c, 0x8359, + 0x348, 0x834d, 0x8347, 0x342, 0x3c0, 0x83c5, 0x83cf, 0x3ca, 0x83db, 0x3de, 0x3d4, 0x83d1, + 0x83f3, 0x3f6, 0x3fc, 0x83f9, 0x3e8, 0x83ed, 0x83e7, 0x3e2, 0x83a3, 0x3a6, 0x3ac, 0x83a9, + 0x3b8, 0x83bd, 0x83b7, 0x3b2, 0x390, 0x8395, 0x839f, 0x39a, 0x838b, 0x38e, 0x384, 0x8381, + 0x280, 0x8285, 0x828f, 0x28a, 0x829b, 0x29e, 0x294, 0x8291, 0x82b3, 0x2b6, 0x2bc, 0x82b9, + 0x2a8, 0x82ad, 0x82a7, 0x2a2, 0x82e3, 0x2e6, 0x2ec, 0x82e9, 0x2f8, 0x82fd, 0x82f7, 0x2f2, + 0x2d0, 0x82d5, 0x82df, 0x2da, 0x82cb, 0x2ce, 0x2c4, 0x82c1, 0x8243, 0x246, 0x24c, 0x8249, + 0x258, 0x825d, 0x8257, 0x252, 0x270, 0x8275, 0x827f, 0x27a, 0x826b, 0x26e, 0x264, 0x8261, + 0x220, 0x8225, 0x822f, 0x22a, 0x823b, 0x23e, 0x234, 0x8231, 0x8213, 0x216, 0x21c, 0x8219 +}; + +const uint32_t Table_CRC_32bit_ANSI[] = { + 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13, 0x54bf6a4, 0x808d07d, 0xcc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x315d626, 0x7d4cb91, 0xa97ed48, 0xe56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35, 0x65e2082, 0xb1d065b, 0xfdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +}; +} // namespace mbed + +/** @}*/ +#endif From 8e537115c54efafa7b946d7ff4d994e8755bc062 Mon Sep 17 00:00:00 2001 From: deepikabhavnani Date: Thu, 1 Feb 2018 12:01:17 -0600 Subject: [PATCH 02/42] Removed init/deinit and added cpp file for tables --- drivers/MbedCRC.h | 86 ++++++++++++++++++------- drivers/TableCRC.cpp | 146 +++++++++++++++++++++++++++++++++++++++++++ drivers/TableCRC.h | 129 +++----------------------------------- mbed.h | 1 + 4 files changed, 217 insertions(+), 145 deletions(-) create mode 100644 drivers/TableCRC.cpp diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index c4d35b1a0e..c63d03e520 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,8 +18,9 @@ #include #include "drivers/TableCRC.h" +#include "platform/mbed_assert.h" -#if defined ( __CC_ARM ) +#if defined ( __CC_ARM ) #pragma diag_suppress 62 // Shift count is negative #elif defined ( __GNUC__ ) #pragma GCC diagnostic push @@ -44,9 +45,57 @@ typedef enum crc_polynomial { } crc_polynomial_t; /** CRC object provides CRC generation through hardware/software + * + * ROM polynomial tables for supported polynomials (:: crc_polynomial_t) will be used for + * software CRC computation, if ROM tables are not available then CRC is computed runtime + * bit by bit for all data input. * * @tparam polynomial CRC polynomial value in hex * @tparam width CRC polynomial width + * + * Example: Compute CRC data + * @code + * + * #include "mbed.h" + * #include "drivers/MbedCRC.h" + * + * int main() { + * MbedCRC ct; + * + * char test[] = "123456789"; + * uint32_t crc = 0; + * + * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width()); + * + * ct.compute((void *)test, strlen((const char*)test), &crc); + * + * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc); + * return 0; + * } + * @endcode + * Example: Compute CRC with data available in parts + * @code + * + * #include "mbed.h" + * #include "drivers/MbedCRC.h" + * int main() { + * MbedCRC ct; + * + * char test[] = "123456789"; + * uint32_t crc = 0; + * + * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width()); + * + * ct.compute_partial_start(&crc); + * ct.compute_partial((void *)&test, 4, &crc); + * ct.compute_partial((void *)&test[4], 5, &crc); + * ct.compute_partial_stop(&crc); + * + * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc); + * return 0; + * } + * @endcode + * @ingroup drivers */ template @@ -57,10 +106,18 @@ public: /** Lifetime of CRC object * - * @param initial_xor Inital value/seed to Xor (Default ~0x0) - * @param final_xor Final Xor value (Default ~0x0) + * @param initial_xor Inital value/seed to Xor + * @param final_xor Final Xor value * @param reflect_data * @param reflect_remainder +* @note Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t + * MbedCRC ct; --- Valid POLY_7BIT_SD + * MbedCRC <0x1021, 16> ct; --- Valid POLY_16BIT_CCITT + * MbedCRC ct; --- Invalid, compilation error + * MbedCRC ct (i,f,rd,rr) Consturctor can be used for not supported polynomials + * MbedCRC sd(0, 0, false, false); Constructor can also be used for supported + * polynomials with different intial/final/reflect values + * */ MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder); MbedCRC(); @@ -69,24 +126,6 @@ public: // Do nothing } - /** Initialize a CRC module - * - * @return 0 on success or a negative error code on failure - */ - int32_t init(void) - { - return 0; - } - - /** Deinitialize a CRC module - * - * @return 0 on success, negative error code on failure - */ - int32_t deinit(void) - { - return 0; - } - /** Compute CRC for the data input * * @param buffer Data bytes @@ -96,6 +135,7 @@ public: */ int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc) { + MBED_ASSERT(crc != NULL); int32_t status; if (0 != (status = compute_partial_start(crc))) { *crc = 0; @@ -129,7 +169,7 @@ public: int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc) { if (NULL == _crc_table) { - // Compute Slow CRC + // Compute bitwise CRC return bitwise_compute_partial(buffer, size, crc); } else { // Table CRC diff --git a/drivers/TableCRC.cpp b/drivers/TableCRC.cpp new file mode 100644 index 0000000000..c3380cfd40 --- /dev/null +++ b/drivers/TableCRC.cpp @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +namespace mbed { +/** \addtogroup drivers */ +/** @{*/ + +uint8_t Table_CRC_7Bit_SD[256] = { + 0x0, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee, + 0x32, 0x20, 0x16, 0x4, 0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc, + 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8, 0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a, + 0x56, 0x44, 0x72, 0x60, 0x1e, 0xc, 0x3a, 0x28, 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8, + 0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6, 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x2, 0x34, 0x26, + 0xfa, 0xe8, 0xde, 0xcc, 0xb2, 0xa0, 0x96, 0x84, 0x6a, 0x78, 0x4e, 0x5c, 0x22, 0x30, 0x6, 0x14, + 0xac, 0xbe, 0x88, 0x9a, 0xe4, 0xf6, 0xc0, 0xd2, 0x3c, 0x2e, 0x18, 0xa, 0x74, 0x66, 0x50, 0x42, + 0x9e, 0x8c, 0xba, 0xa8, 0xd6, 0xc4, 0xf2, 0xe0, 0xe, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x70, + 0x82, 0x90, 0xa6, 0xb4, 0xca, 0xd8, 0xee, 0xfc, 0x12, 0x0, 0x36, 0x24, 0x5a, 0x48, 0x7e, 0x6c, + 0xb0, 0xa2, 0x94, 0x86, 0xf8, 0xea, 0xdc, 0xce, 0x20, 0x32, 0x4, 0x16, 0x68, 0x7a, 0x4c, 0x5e, + 0xe6, 0xf4, 0xc2, 0xd0, 0xae, 0xbc, 0x8a, 0x98, 0x76, 0x64, 0x52, 0x40, 0x3e, 0x2c, 0x1a, 0x8, + 0xd4, 0xc6, 0xf0, 0xe2, 0x9c, 0x8e, 0xb8, 0xaa, 0x44, 0x56, 0x60, 0x72, 0xc, 0x1e, 0x28, 0x3a, + 0x4a, 0x58, 0x6e, 0x7c, 0x2, 0x10, 0x26, 0x34, 0xda, 0xc8, 0xfe, 0xec, 0x92, 0x80, 0xb6, 0xa4, + 0x78, 0x6a, 0x5c, 0x4e, 0x30, 0x22, 0x14, 0x6, 0xe8, 0xfa, 0xcc, 0xde, 0xa0, 0xb2, 0x84, 0x96, + 0x2e, 0x3c, 0xa, 0x18, 0x66, 0x74, 0x42, 0x50, 0xbe, 0xac, 0x9a, 0x88, 0xf6, 0xe4, 0xd2, 0xc0, + 0x1c, 0xe, 0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2 +}; + +uint8_t Table_CRC_8bit_CCITT[256] = { + 0x0, 0x7, 0xe, 0x9, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, + 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, + 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, + 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, + 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, + 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, + 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x3, 0x4, 0xd, 0xa, + 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, + 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, + 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, + 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, + 0x19, 0x1e, 0x17, 0x10, 0x5, 0x2, 0xb, 0xc, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, + 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, + 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x6, 0x1, 0x8, 0xf, 0x1a, 0x1d, 0x14, 0x13, + 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, + 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 +}; + +uint16_t Table_CRC_16bit_CCITT[256] = { + 0x0, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b, + 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420, 0x1401, + 0x64e6, 0x74c7, 0x44a4, 0x5485, 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738, + 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, + 0x1a71, 0xa50, 0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0xc60, 0x1c41, 0xedae, 0xfd8f, 0xcdec, 0xddcd, + 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0xe70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, 0xa1eb, + 0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0xa1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x2b1, 0x1290, 0x22f3, 0x32d2, + 0x4235, 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x481, 0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8, + 0xe75f, 0xf77e, 0xc71d, 0xd73c, 0x26d3, 0x36f2, 0x691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827, + 0x18c0, 0x8e1, 0x3882, 0x28a3, 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0xaf1, 0x1ad0, 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, + 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0xcc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 0x6e17, 0x7e36, 0x4e55, 0x5e74, + 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +uint16_t Table_CRC_16bit_IBM[256] = { + 0x0, 0x8005, 0x800f, 0xa, 0x801b, 0x1e, 0x14, 0x8011, 0x8033, 0x36, 0x3c, 0x8039, + 0x28, 0x802d, 0x8027, 0x22, 0x8063, 0x66, 0x6c, 0x8069, 0x78, 0x807d, 0x8077, 0x72, + 0x50, 0x8055, 0x805f, 0x5a, 0x804b, 0x4e, 0x44, 0x8041, 0x80c3, 0xc6, 0xcc, 0x80c9, + 0xd8, 0x80dd, 0x80d7, 0xd2, 0xf0, 0x80f5, 0x80ff, 0xfa, 0x80eb, 0xee, 0xe4, 0x80e1, + 0xa0, 0x80a5, 0x80af, 0xaa, 0x80bb, 0xbe, 0xb4, 0x80b1, 0x8093, 0x96, 0x9c, 0x8099, + 0x88, 0x808d, 0x8087, 0x82, 0x8183, 0x186, 0x18c, 0x8189, 0x198, 0x819d, 0x8197, 0x192, + 0x1b0, 0x81b5, 0x81bf, 0x1ba, 0x81ab, 0x1ae, 0x1a4, 0x81a1, 0x1e0, 0x81e5, 0x81ef, 0x1ea, + 0x81fb, 0x1fe, 0x1f4, 0x81f1, 0x81d3, 0x1d6, 0x1dc, 0x81d9, 0x1c8, 0x81cd, 0x81c7, 0x1c2, + 0x140, 0x8145, 0x814f, 0x14a, 0x815b, 0x15e, 0x154, 0x8151, 0x8173, 0x176, 0x17c, 0x8179, + 0x168, 0x816d, 0x8167, 0x162, 0x8123, 0x126, 0x12c, 0x8129, 0x138, 0x813d, 0x8137, 0x132, + 0x110, 0x8115, 0x811f, 0x11a, 0x810b, 0x10e, 0x104, 0x8101, 0x8303, 0x306, 0x30c, 0x8309, + 0x318, 0x831d, 0x8317, 0x312, 0x330, 0x8335, 0x833f, 0x33a, 0x832b, 0x32e, 0x324, 0x8321, + 0x360, 0x8365, 0x836f, 0x36a, 0x837b, 0x37e, 0x374, 0x8371, 0x8353, 0x356, 0x35c, 0x8359, + 0x348, 0x834d, 0x8347, 0x342, 0x3c0, 0x83c5, 0x83cf, 0x3ca, 0x83db, 0x3de, 0x3d4, 0x83d1, + 0x83f3, 0x3f6, 0x3fc, 0x83f9, 0x3e8, 0x83ed, 0x83e7, 0x3e2, 0x83a3, 0x3a6, 0x3ac, 0x83a9, + 0x3b8, 0x83bd, 0x83b7, 0x3b2, 0x390, 0x8395, 0x839f, 0x39a, 0x838b, 0x38e, 0x384, 0x8381, + 0x280, 0x8285, 0x828f, 0x28a, 0x829b, 0x29e, 0x294, 0x8291, 0x82b3, 0x2b6, 0x2bc, 0x82b9, + 0x2a8, 0x82ad, 0x82a7, 0x2a2, 0x82e3, 0x2e6, 0x2ec, 0x82e9, 0x2f8, 0x82fd, 0x82f7, 0x2f2, + 0x2d0, 0x82d5, 0x82df, 0x2da, 0x82cb, 0x2ce, 0x2c4, 0x82c1, 0x8243, 0x246, 0x24c, 0x8249, + 0x258, 0x825d, 0x8257, 0x252, 0x270, 0x8275, 0x827f, 0x27a, 0x826b, 0x26e, 0x264, 0x8261, + 0x220, 0x8225, 0x822f, 0x22a, 0x823b, 0x23e, 0x234, 0x8231, 0x8213, 0x216, 0x21c, 0x8219 +}; + +uint32_t Table_CRC_32bit_ANSI[256] = { + 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13, 0x54bf6a4, 0x808d07d, 0xcc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x315d626, 0x7d4cb91, 0xa97ed48, 0xe56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35, 0x65e2082, 0xb1d065b, 0xfdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +}; + +/** @}*/ +} // namespace mbed diff --git a/drivers/TableCRC.h b/drivers/TableCRC.h index 34704fcef3..106ad72635 100644 --- a/drivers/TableCRC.h +++ b/drivers/TableCRC.h @@ -23,128 +23,13 @@ namespace mbed { /** \addtogroup drivers */ /** @{*/ -const uint8_t Table_CRC_7Bit_SD[] = { - 0x0, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee, - 0x32, 0x20, 0x16, 0x4, 0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc, - 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8, 0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a, - 0x56, 0x44, 0x72, 0x60, 0x1e, 0xc, 0x3a, 0x28, 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8, - 0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6, 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x2, 0x34, 0x26, - 0xfa, 0xe8, 0xde, 0xcc, 0xb2, 0xa0, 0x96, 0x84, 0x6a, 0x78, 0x4e, 0x5c, 0x22, 0x30, 0x6, 0x14, - 0xac, 0xbe, 0x88, 0x9a, 0xe4, 0xf6, 0xc0, 0xd2, 0x3c, 0x2e, 0x18, 0xa, 0x74, 0x66, 0x50, 0x42, - 0x9e, 0x8c, 0xba, 0xa8, 0xd6, 0xc4, 0xf2, 0xe0, 0xe, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x70, - 0x82, 0x90, 0xa6, 0xb4, 0xca, 0xd8, 0xee, 0xfc, 0x12, 0x0, 0x36, 0x24, 0x5a, 0x48, 0x7e, 0x6c, - 0xb0, 0xa2, 0x94, 0x86, 0xf8, 0xea, 0xdc, 0xce, 0x20, 0x32, 0x4, 0x16, 0x68, 0x7a, 0x4c, 0x5e, - 0xe6, 0xf4, 0xc2, 0xd0, 0xae, 0xbc, 0x8a, 0x98, 0x76, 0x64, 0x52, 0x40, 0x3e, 0x2c, 0x1a, 0x8, - 0xd4, 0xc6, 0xf0, 0xe2, 0x9c, 0x8e, 0xb8, 0xaa, 0x44, 0x56, 0x60, 0x72, 0xc, 0x1e, 0x28, 0x3a, - 0x4a, 0x58, 0x6e, 0x7c, 0x2, 0x10, 0x26, 0x34, 0xda, 0xc8, 0xfe, 0xec, 0x92, 0x80, 0xb6, 0xa4, - 0x78, 0x6a, 0x5c, 0x4e, 0x30, 0x22, 0x14, 0x6, 0xe8, 0xfa, 0xcc, 0xde, 0xa0, 0xb2, 0x84, 0x96, - 0x2e, 0x3c, 0xa, 0x18, 0x66, 0x74, 0x42, 0x50, 0xbe, 0xac, 0x9a, 0x88, 0xf6, 0xe4, 0xd2, 0xc0, - 0x1c, 0xe, 0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2 -}; - -const uint8_t Table_CRC_8bit_CCITT[] = { - 0x0, 0x7, 0xe, 0x9, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, - 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, - 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, - 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, - 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, - 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, - 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x3, 0x4, 0xd, 0xa, - 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, - 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, - 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, - 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, - 0x19, 0x1e, 0x17, 0x10, 0x5, 0x2, 0xb, 0xc, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, - 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, - 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x6, 0x1, 0x8, 0xf, 0x1a, 0x1d, 0x14, 0x13, - 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, - 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 -}; - -const uint16_t Table_CRC_16bit_CCITT[] = { - 0x0, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b, - 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420, 0x1401, - 0x64e6, 0x74c7, 0x44a4, 0x5485, 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738, - 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, - 0x1a71, 0xa50, 0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0xc60, 0x1c41, 0xedae, 0xfd8f, 0xcdec, 0xddcd, - 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0xe70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, 0xa1eb, - 0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0xa1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x2b1, 0x1290, 0x22f3, 0x32d2, - 0x4235, 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x481, 0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8, - 0xe75f, 0xf77e, 0xc71d, 0xd73c, 0x26d3, 0x36f2, 0x691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827, - 0x18c0, 0x8e1, 0x3882, 0x28a3, 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0xaf1, 0x1ad0, 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, - 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0xcc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 0x6e17, 0x7e36, 0x4e55, 0x5e74, - 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 -}; - -const uint16_t Table_CRC_16bit_IBM[] = { - 0x0, 0x8005, 0x800f, 0xa, 0x801b, 0x1e, 0x14, 0x8011, 0x8033, 0x36, 0x3c, 0x8039, - 0x28, 0x802d, 0x8027, 0x22, 0x8063, 0x66, 0x6c, 0x8069, 0x78, 0x807d, 0x8077, 0x72, - 0x50, 0x8055, 0x805f, 0x5a, 0x804b, 0x4e, 0x44, 0x8041, 0x80c3, 0xc6, 0xcc, 0x80c9, - 0xd8, 0x80dd, 0x80d7, 0xd2, 0xf0, 0x80f5, 0x80ff, 0xfa, 0x80eb, 0xee, 0xe4, 0x80e1, - 0xa0, 0x80a5, 0x80af, 0xaa, 0x80bb, 0xbe, 0xb4, 0x80b1, 0x8093, 0x96, 0x9c, 0x8099, - 0x88, 0x808d, 0x8087, 0x82, 0x8183, 0x186, 0x18c, 0x8189, 0x198, 0x819d, 0x8197, 0x192, - 0x1b0, 0x81b5, 0x81bf, 0x1ba, 0x81ab, 0x1ae, 0x1a4, 0x81a1, 0x1e0, 0x81e5, 0x81ef, 0x1ea, - 0x81fb, 0x1fe, 0x1f4, 0x81f1, 0x81d3, 0x1d6, 0x1dc, 0x81d9, 0x1c8, 0x81cd, 0x81c7, 0x1c2, - 0x140, 0x8145, 0x814f, 0x14a, 0x815b, 0x15e, 0x154, 0x8151, 0x8173, 0x176, 0x17c, 0x8179, - 0x168, 0x816d, 0x8167, 0x162, 0x8123, 0x126, 0x12c, 0x8129, 0x138, 0x813d, 0x8137, 0x132, - 0x110, 0x8115, 0x811f, 0x11a, 0x810b, 0x10e, 0x104, 0x8101, 0x8303, 0x306, 0x30c, 0x8309, - 0x318, 0x831d, 0x8317, 0x312, 0x330, 0x8335, 0x833f, 0x33a, 0x832b, 0x32e, 0x324, 0x8321, - 0x360, 0x8365, 0x836f, 0x36a, 0x837b, 0x37e, 0x374, 0x8371, 0x8353, 0x356, 0x35c, 0x8359, - 0x348, 0x834d, 0x8347, 0x342, 0x3c0, 0x83c5, 0x83cf, 0x3ca, 0x83db, 0x3de, 0x3d4, 0x83d1, - 0x83f3, 0x3f6, 0x3fc, 0x83f9, 0x3e8, 0x83ed, 0x83e7, 0x3e2, 0x83a3, 0x3a6, 0x3ac, 0x83a9, - 0x3b8, 0x83bd, 0x83b7, 0x3b2, 0x390, 0x8395, 0x839f, 0x39a, 0x838b, 0x38e, 0x384, 0x8381, - 0x280, 0x8285, 0x828f, 0x28a, 0x829b, 0x29e, 0x294, 0x8291, 0x82b3, 0x2b6, 0x2bc, 0x82b9, - 0x2a8, 0x82ad, 0x82a7, 0x2a2, 0x82e3, 0x2e6, 0x2ec, 0x82e9, 0x2f8, 0x82fd, 0x82f7, 0x2f2, - 0x2d0, 0x82d5, 0x82df, 0x2da, 0x82cb, 0x2ce, 0x2c4, 0x82c1, 0x8243, 0x246, 0x24c, 0x8249, - 0x258, 0x825d, 0x8257, 0x252, 0x270, 0x8275, 0x827f, 0x27a, 0x826b, 0x26e, 0x264, 0x8261, - 0x220, 0x8225, 0x822f, 0x22a, 0x823b, 0x23e, 0x234, 0x8231, 0x8213, 0x216, 0x21c, 0x8219 -}; - -const uint32_t Table_CRC_32bit_ANSI[] = { - 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, - 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, - 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, - 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, - 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, - 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, - 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, - 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, - 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, - 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13, 0x54bf6a4, 0x808d07d, 0xcc9cdca, - 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, - 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, - 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, - 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, - 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, - 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, - 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, - 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, - 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, - 0x315d626, 0x7d4cb91, 0xa97ed48, 0xe56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, - 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, - 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, - 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, - 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, - 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, - 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, - 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35, 0x65e2082, 0xb1d065b, 0xfdc1bec, - 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, - 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, - 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, - 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, - 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 -}; -} // namespace mbed +extern uint8_t Table_CRC_7Bit_SD[256]; +extern uint8_t Table_CRC_8bit_CCITT[256]; +extern uint16_t Table_CRC_16bit_CCITT[256]; +extern uint16_t Table_CRC_16bit_IBM[256]; +extern uint32_t Table_CRC_32bit_ANSI[256]; /** @}*/ +} // namespace mbed + #endif diff --git a/mbed.h b/mbed.h index 1e56e63640..f36010464e 100644 --- a/mbed.h +++ b/mbed.h @@ -70,6 +70,7 @@ #include "drivers/RawSerial.h" #include "drivers/UARTSerial.h" #include "drivers/FlashIAP.h" +#include "drivers/TableCRC.h" // mbed Internal components #include "drivers/Timer.h" From af0982295f010f3dd45ade36ddc9155a5f86289e Mon Sep 17 00:00:00 2001 From: deepikabhavnani Date: Tue, 20 Feb 2018 08:05:12 -0600 Subject: [PATCH 03/42] Moved specialized functions to CPP file Template specialized functions are moved to cpp file, to add MbedCRC.h in mbed.h. Else linker shall multiple definition error. --- drivers/MbedCRC.cpp | 115 ++++++++++++++++++++++++++++++++++++++++++++ drivers/MbedCRC.h | 88 --------------------------------- mbed.h | 2 +- 3 files changed, 116 insertions(+), 89 deletions(-) create mode 100644 drivers/MbedCRC.cpp diff --git a/drivers/MbedCRC.cpp b/drivers/MbedCRC.cpp new file mode 100644 index 0000000000..317cc8a78c --- /dev/null +++ b/drivers/MbedCRC.cpp @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "drivers/TableCRC.h" +#include "drivers/MbedCRC.h" + +namespace mbed { +/** \addtogroup drivers */ +/** @{*/ + +/* Default values for different types of polynomials +*/ +template +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), _crc_table(NULL) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_32bit_ANSI) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_8bit_CCITT) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_7Bit_SD) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_16bit_CCITT) +{ +} + +template<> +MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): + _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), + _crc_table((uint32_t *)Table_CRC_16bit_IBM) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true), + _crc_table((uint32_t *)Table_CRC_32bit_ANSI) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(true), _reflect_remainder(true), + _crc_table((uint32_t *)Table_CRC_16bit_IBM) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(~(0x0)), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_16bit_CCITT) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_7Bit_SD) +{ + mbed_crc_ctor(); +} + +template<> +MbedCRC::MbedCRC(): + _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), + _crc_table((uint32_t *)Table_CRC_8bit_CCITT) +{ + mbed_crc_ctor(); +} + +/** @}*/ +} // namespace mbed + diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index c63d03e520..cd9e873afa 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -404,94 +404,6 @@ private: } }; -/* Default values for different types of polynomials -*/ -template -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), _crc_table(NULL) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), - _crc_table((uint32_t *)Table_CRC_32bit_ANSI) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), - _crc_table((uint32_t *)Table_CRC_8bit_CCITT) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), - _crc_table((uint32_t *)Table_CRC_7Bit_SD) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), - _crc_table((uint32_t *)Table_CRC_16bit_CCITT) -{ -} - -template<> -MbedCRC::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder): - _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder), - _crc_table((uint32_t *)Table_CRC_16bit_IBM) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(): - _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true), - _crc_table((uint32_t *)Table_CRC_32bit_ANSI) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(): - _initial_value(0), _final_xor(0), _reflect_data(true), _reflect_remainder(true), - _crc_table((uint32_t *)Table_CRC_16bit_IBM) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(): - _initial_value(~(0x0)), _final_xor(0), _reflect_data(false), _reflect_remainder(false), - _crc_table((uint32_t *)Table_CRC_16bit_CCITT) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(): - _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), - _crc_table((uint32_t *)Table_CRC_7Bit_SD) -{ - mbed_crc_ctor(); -} - -template<> -MbedCRC::MbedCRC(): - _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false), - _crc_table((uint32_t *)Table_CRC_8bit_CCITT) -{ - mbed_crc_ctor(); -} - #if defined ( __CC_ARM ) #elif defined ( __GNUC__ ) #pragma GCC diagnostic pop diff --git a/mbed.h b/mbed.h index f36010464e..dec1d6f692 100644 --- a/mbed.h +++ b/mbed.h @@ -70,7 +70,7 @@ #include "drivers/RawSerial.h" #include "drivers/UARTSerial.h" #include "drivers/FlashIAP.h" -#include "drivers/TableCRC.h" +#include "drivers/MbedCRC.h" // mbed Internal components #include "drivers/Timer.h" From b2c71c0fce572e8926f3585f95118370312621fa Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Wed, 24 Jan 2018 18:19:17 -0600 Subject: [PATCH 04/42] Accept header configuration and reserve space --- tools/config/__init__.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tools/config/__init__.py b/tools/config/__init__.py index 0bbafa81e5..07a57343ac 100644 --- a/tools/config/__init__.py +++ b/tools/config/__init__.py @@ -41,6 +41,7 @@ except NameError: unicode = str PATH_OVERRIDES = set(["target.bootloader_img"]) BOOTLOADER_OVERRIDES = set(["target.bootloader_img", "target.restrict_size", + "target.header_format", "target.mbed_app_start", "target.mbed_app_size"]) # Base class for all configuration exceptions @@ -568,6 +569,29 @@ class Config(object): raise ConfigException( "Bootloader build requested but no bootlader configuration") + @staticmethod + def _header_size(format): + size_in_bytes = 0 + for _, _, subtype, _ in format: + try: + size_in_bytes += int(subtype) // 8 + except: + if subtype == "CRCITT32": + size_in_bytes += 32 // 8 + elif subtype == "SHA256": + size_in_bytes += 256 // 8 + else: + raise ValueError("target.header_format: subtype %s is not " + "understood" % subtype) + return size_in_bytes + + def _make_header_region(self, start, header_format): + size = self._header_size(header_format) + region = Region("application_header", start, size, False, None) + start += size + start = ((start + 7) // 8) * 8 + return (start, region) + def _generate_bootloader_build(self, rom_start, rom_size): start = rom_start rom_end = rom_start + rom_size @@ -588,11 +612,19 @@ class Config(object): yield Region("bootloader", rom_start, part_size, False, filename) start = rom_start + part_size + if self.target.header_format: + start, region = self._make_header_region( + start, self.target.header_format) + yield region if self.target.restrict_size is not None: new_size = int(self.target.restrict_size, 0) new_size = Config._align_floor(start + new_size, self.sectors) - start yield Region("application", start, new_size, True, None) start += new_size + if self.target.header_format: + start, region = self._make_header_region( + start, self.target.header_format) + yield region yield Region("post_application", start, rom_end - start, False, None) else: From 4c47f21cac92e37309dac0d9d4f6b748f0a79925 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Thu, 25 Jan 2018 15:57:48 -0600 Subject: [PATCH 05/42] Fill header in application --- tools/build_api.py | 67 +++++++++++++++++++++++++++++++++++++++- tools/config/__init__.py | 34 +++++++++++--------- 2 files changed, 85 insertions(+), 16 deletions(-) diff --git a/tools/build_api.py b/tools/build_api.py index c769dea202..9531967992 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -20,6 +20,9 @@ import re import tempfile import datetime import uuid +import struct +import zlib +import hashlib from shutil import rmtree from os.path import join, exists, dirname, basename, abspath, normpath, splitext from os.path import relpath @@ -339,8 +342,65 @@ def prepare_toolchain(src_paths, build_dir, target, toolchain_name, return toolchain +def _printihex(ihex): + import pprint + pprint.PrettyPrinter().pprint(ihex.todict()) + +def _real_region_size(region): + try: + part = intelhex_offset(region.filename, offset=region.start) + return (part.maxaddr() - part.minaddr()) + 1 + except AttributeError: + return region.size + +def _fill_header(region_list, current_region): + """Fill an application header region + + This is done it three steps: + * Fill the whole region with zeros + * Fill const, timestamp and size entries with their data + * Fill the digests using this header as the header region + """ + region_dict = {r.name: r for r in region_list} + header = IntelHex() + header.puts(current_region.start, b'\x00' * current_region.size) + start = current_region.start + for member in current_region.filename: + _, type, subtype, data = member + member_size = Config.header_member_size(member) + if type == "const": + fmt = {"8": " Date: Fri, 2 Feb 2018 16:21:48 -0600 Subject: [PATCH 06/42] Require endianness specification for ints > 8 bits --- tools/build_api.py | 16 +++++++++++----- tools/config/__init__.py | 4 ++-- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/tools/build_api.py b/tools/build_api.py index 9531967992..7d53f30a5d 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -369,13 +369,18 @@ def _fill_header(region_list, current_region): _, type, subtype, data = member member_size = Config.header_member_size(member) if type == "const": - fmt = {"8": "B", "16le": "H", "32be": ">L", "64be": ">Q" + }[subtype] header.puts(start, struct.pack(fmt, int(data, 0))) elif type == "timestamp": - fmt = {"32": "L", "64be": ">Q"}[subtype] header.puts(start, struct.pack(fmt, time())) elif type == "size": - fmt = {"32": "L", "64be": ">Q"}[subtype] size = sum(_real_region_size(region_dict[r]) for r in data) header.puts(start, struct.pack(fmt, size)) start += Config.header_member_size(member) @@ -387,8 +392,9 @@ def _fill_header(region_list, current_region): ih = header else: ih = intelhex_offset(region_dict[data].filename, offset=region_dict[data].start) - if subtype == "CRCITT32": - header.puts(start, struct.pack("l", "CRCITT32le": " Date: Fri, 2 Feb 2018 17:06:48 -0600 Subject: [PATCH 07/42] Calculate digests with header up to their start address --- tools/build_api.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tools/build_api.py b/tools/build_api.py index 7d53f30a5d..af5c4093bc 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -383,13 +383,9 @@ def _fill_header(region_list, current_region): "32be": ">L", "64be": ">Q"}[subtype] size = sum(_real_region_size(region_dict[r]) for r in data) header.puts(start, struct.pack(fmt, size)) - start += Config.header_member_size(member) - start = current_region.start - for member in current_region.filename: - _, type, subtype, data = member - if type == "digest": + elif type == "digest": if data == "header": - ih = header + ih = header[:start] else: ih = intelhex_offset(region_dict[data].filename, offset=region_dict[data].start) if subtype.startswith("CRCITT32"): From 9f99330be6ca6700fb1f76a34dbd844406c22895 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Mon, 5 Feb 2018 10:10:43 -0600 Subject: [PATCH 08/42] Allow overriding offsets with "app_offset" and "header_offset" --- tools/build_api.py | 5 +++-- tools/config/__init__.py | 28 +++++++++++++++++++++++++--- tools/utils.py | 8 ++++++++ 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/tools/build_api.py b/tools/build_api.py index af5c4093bc..7f192741f1 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -36,7 +36,7 @@ from jinja2.environment import Environment from .arm_pack_manager import Cache from .utils import (mkdir, run_cmd, run_cmd_ext, NotSupportedException, ToolException, InvalidReleaseTargetException, - intelhex_offset) + intelhex_offset, integer) from .paths import (MBED_CMSIS_PATH, MBED_TARGETS_PATH, MBED_LIBRARIES, MBED_HEADER, MBED_DRIVERS, MBED_PLATFORM, MBED_HAL, MBED_CONFIG_FILE, MBED_LIBRARIES_DRIVERS, @@ -353,6 +353,7 @@ def _real_region_size(region): except AttributeError: return region.size + def _fill_header(region_list, current_region): """Fill an application header region @@ -373,7 +374,7 @@ def _fill_header(region_list, current_region): "8le": ">B", "16le": "H", "32be": ">L", "64be": ">Q" }[subtype] - header.puts(start, struct.pack(fmt, int(data, 0))) + header.puts(start, struct.pack(fmt, integer(data, 0))) elif type == "timestamp": fmt = {"32le": "L", "64be": ">Q"}[subtype] diff --git a/tools/config/__init__.py b/tools/config/__init__.py index edef702c0b..f4b76bbf8a 100644 --- a/tools/config/__init__.py +++ b/tools/config/__init__.py @@ -30,7 +30,7 @@ from jinja2 import FileSystemLoader, StrictUndefined from jinja2.environment import Environment from jsonschema import Draft4Validator, RefResolver -from ..utils import json_file_to_dict, intelhex_offset +from ..utils import json_file_to_dict, intelhex_offset, integer from ..arm_pack_manager import Cache from ..targets import (CUMULATIVE_ATTRIBUTES, TARGET_MAP, generate_py_target, get_resolution_order, Target) @@ -41,9 +41,11 @@ except NameError: unicode = str PATH_OVERRIDES = set(["target.bootloader_img"]) BOOTLOADER_OVERRIDES = set(["target.bootloader_img", "target.restrict_size", - "target.header_format", + "target.header_format", "target.header_offset", + "target.app_offset", "target.mbed_app_start", "target.mbed_app_size"]) + # Base class for all configuration exceptions class ConfigException(Exception): """Config system only exception. Makes it easier to distinguish config @@ -589,13 +591,21 @@ class Config(object): def _header_size(format): return sum(Config.header_member_size(m) for m in format) - def _make_header_region(self, start, header_format): + def _make_header_region(self, start, header_format, offset=None): size = self._header_size(header_format) region = Region("header", start, size, False, None) start += size start = ((start + 7) // 8) * 8 return (start, region) + @staticmethod + def _assign_new_offset(rom_start, start, new_offset, region_name): + newstart = rom_start + integer(new_offset, 0) + if newstart < start: + raise ConfigException( + "Can not place % region inside previous region" % region_name) + return newstart + def _generate_bootloader_build(self, rom_start, rom_size): start = rom_start rom_end = rom_start + rom_size @@ -617,6 +627,9 @@ class Config(object): filename) start = rom_start + part_size if self.target.header_format: + if self.target.header_offset: + start = self._assign_new_offset( + rom_start, start, self.target.header_offset, "header") start, region = self._make_header_region( start, self.target.header_format) yield region._replace(filename=self.target.header_format) @@ -626,12 +639,21 @@ class Config(object): yield Region("application", start, new_size, True, None) start += new_size if self.target.header_format: + if self.target.header_offset: + start = self._assign_new_offset( + rom_start, start, self.target.header_offset, "header") start, region = self._make_header_region( start, self.target.header_format) yield region + if self.target.app_offset: + start = self._assign_new_offset( + rom_start, start, self.target.app_offset, "application") yield Region("post_application", start, rom_end - start, False, None) else: + if self.target.app_offset: + start = self._assign_new_offset( + rom_start, start, self.target.app_offset, "application") yield Region("application", start, rom_end - start, True, None) if start > rom_start + rom_size: diff --git a/tools/utils.py b/tools/utils.py index a952290c7a..2e92fc1e37 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -539,3 +539,11 @@ def intelhex_offset(filename, offset): raise ToolException("File %s does not have a known binary file type" % filename) return ih + + +def integer(maybe_string, base): + """Make an integer of a number or a string""" + if isinstance(maybe_string, int): + return maybe_string + else: + return int(maybe_string, base) From 5b8ff81e0214dda742f27dea3e3d76edc4429b9a Mon Sep 17 00:00:00 2001 From: "Galanakis, Minos" Date: Mon, 27 Nov 2017 09:46:30 +0000 Subject: [PATCH 09/42] CM3DS: fix a minor bug in the ethernet LWIP driver This patch fixes a memory bug. `eth_arch_enetif_init` method call would attempt to write to un-initialized area of memory. Change-Id: I9881de71d58fa14db609fe3e24617a210b896471 Signed-off-by: Galanakis, Minos --- .../lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c index 13a47fc671..20da174961 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/mps2_emac.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -316,16 +316,16 @@ err_t eth_arch_enetif_init(struct netif *netif) err_t error = ERR_OK; struct ethernetif *ethernetif; - ethernetif->is_enabled = 0; - LWIP_ASSERT("netif != NULL", (netif != NULL)); - ethernetif = mem_malloc(sizeof(struct ethernetif)); + if (ethernetif == NULL) { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); return ERR_MEM; } + ethernetif->is_enabled = 0; + #if LWIP_NETIF_HOSTNAME /* Initialize interface hostname */ netif->hostname = HOSTNAME_STRING; From ef7b16d9c54fe198bdc7660552347ff4678cb3bf Mon Sep 17 00:00:00 2001 From: Hugues de Valon Date: Thu, 4 Jan 2018 13:37:01 +0000 Subject: [PATCH 10/42] CM3DS: fix non aligned access in Ethernet driver This patch changes the way data is put in the TX_DATA_PORT register when sending packet over Ethernet. When this driver is compiled with release compilation profile (space optimization compiler options) with Arm compiler version 5, the line: SMSC9220->TX_DATA_PORT = *pktptr; generates the assembly instruction to get the pktptr pointed value: LDM r2!, {r3} with pktptr = r2 However, the code does not prevent the pktptr value from being unaligned (to a 32 bits boundary) in that zone and the LDM instruction causes a HardFault if this is the case. When the compiler option is not activated (debug and develop compilation profiles), the compiler generates LDR instruction instead which does not cause a HardFault. The ARM v7-M states page B3-601: "Unaligned load-store multiples and word or halfword exclusive accesses always fault." To face that problem, we check if the data pointer is aligned or not. If it is, we apply the same algorithm than before. If not, a local variable is created and we copy in it, byte per byte, the contents at the unaligned pointer. However, it will impact performances adding 8 instructions (one LD and one ST for each copied byte). Change-Id: I11f6e82ce5521960d2ecf499f718f76fec29c0b0 Signed-off-by: Hugues de Valon --- .../arch/TARGET_CM3DS_MPS2/lwipopts_conf.h | 20 ++++-- .../TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c | 66 ++++++++++++++++--- 2 files changed, 73 insertions(+), 13 deletions(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/lwipopts_conf.h index a6336e8f72..e1a95f2171 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/lwipopts_conf.h +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_CM3DS_MPS2/lwipopts_conf.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2017 ARM Limited +/* Copyright (c) 2017-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,12 +22,22 @@ /* size is 1522 bytes to accommodate the four-byte VLAN tag. */ #define ETH_MAX_FLEN 1522u /* recommended size for a VLAN frame */ - /* Maximum Transfer Unit - * The IEEE 802.3 specification limits the data portion of the 802.3 frame - * to a minimum of 46 and a maximum of 1500 bytes, this is on L3 level. - */ +/* + * Maximum Transfer Unit + * The IEEE 802.3 specification limits the data portion of the 802.3 frame + * to a minimum of 46 and a maximum of 1522 bytes, this is on L2 level. + */ #define ETH_L2_HEADER_LEN 22u #define ETH_MAX_PAYLOAD_LEN (ETH_MAX_FLEN - ETH_L2_HEADER_LEN) +/* + * Set this value to 2 to ensure that payload address of packet buffers is + * aligned on a 32 bits boundary. + * The padding is removed before passing the packet to the ethernet driver, + * hence defining this value to 2 will not prevent alignment issues inside the + * ethernet driver. + */ +#define ETH_PAD_SIZE 0 + #endif /* LWIPOPTS_CONF_H */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c index 5063052221..5c8c356004 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -426,6 +426,53 @@ static int smsc9220_check_id(void) return 0; } +/** + * \brief Fill the SMSC9220 TX FIFO with a number of words at an aligned + * address. + * + * \param[in] data Pointer to the aligned data that should be sent. + * \param[in] dwords_to_write Number of data words to write. + */ +static void fill_tx_fifo_aligned(unsigned int *data, + unsigned int dwords_to_write) +{ + while (dwords_to_write > 0) { + SMSC9220->TX_DATA_PORT = *data; + data++; + dwords_to_write--; + } +} + +/** + * \brief Fill the SMSC9220 TX FIFO with a number of words at an unaligned + * address. This function ensures that loading words at that address will + * not generate unaligned access which can trigger an exception to the + * processor. + * + * \param[in] data Pointer to the unaligned data that should be sent. + * \param[in] dwords_to_write Number of data words to write. + */ +static void fill_tx_fifo_unaligned(uint8_t *data, unsigned int dwords_to_write) +{ + /* + * Prevent unaligned word access from data pointer, 4 bytes are copied to + * this variable for each word that need to be sent. + */ + unsigned int tx_data_port_tmp = 0; + uint8_t *tx_data_port_tmp_ptr = (uint8_t *)&tx_data_port_tmp; + + while (dwords_to_write > 0) { + /* Keep the same endianness in data than in the temp variable */ + tx_data_port_tmp_ptr[0] = data[0]; + tx_data_port_tmp_ptr[1] = data[1]; + tx_data_port_tmp_ptr[2] = data[2]; + tx_data_port_tmp_ptr[3] = data[3]; + SMSC9220->TX_DATA_PORT = tx_data_port_tmp; + data += 4; + dwords_to_write--; + } +} + /*---------------------------------------------------------------------------- Public API *----------------------------------------------------------------------------*/ @@ -574,7 +621,6 @@ int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, int is_last_segment = 0; /* signing this is the last segment of the packet to be sent */ unsigned int txcmd_a, txcmd_b = 0; unsigned int dwords_to_write = 0; - unsigned int *pktptr = 0; unsigned int xmit_inf = 0; unsigned int tx_buffer_free_space = 0; volatile unsigned int xmit_stat = 0; @@ -602,7 +648,6 @@ int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, is_last_segment = 1; } - pktptr = (unsigned int *) data; txcmd_a = 0; txcmd_b = 0; @@ -616,11 +661,16 @@ int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, SMSC9220->TX_DATA_PORT = txcmd_b; dwords_to_write = (current_size + 3) >> 2; - /* PIO Copy to FIFO. Could replace this with DMA. */ - while(dwords_to_write > 0) { - SMSC9220->TX_DATA_PORT = *pktptr; - pktptr++; - dwords_to_write--; + /* + * Copy to TX FIFO + * The function to use depends on the alignment of the data pointer on a 32 + * bits boundary. + */ + if (((unsigned int)data % sizeof(uint32_t)) == 0) { + /* Cast is safe because we know data is aligned */ + fill_tx_fifo_aligned((unsigned int *)data, dwords_to_write); + } else { + fill_tx_fifo_unaligned((uint8_t *)data, dwords_to_write); } if (is_last_segment) { From 0efc876bb4c79ee327abe064867900141bcb3148 Mon Sep 17 00:00:00 2001 From: adustm Date: Tue, 20 Feb 2018 10:29:50 +0100 Subject: [PATCH 11/42] Call to specific _wrap_sbrk to support 2 region model for heap and stack --- platform/mbed_retarget.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index a71373e1a7..93362e82b6 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -1053,12 +1053,13 @@ extern "C" uint32_t __HeapLimit; extern "C" int errno; // Dynamic memory allocation related syscall. -#if defined(TARGET_NUVOTON) +#if (defined(TARGET_NUVOTON) || defined(TWO_RAM_REGIONS)) // Overwrite _sbrk() to support two region model (heap and stack are two distinct regions). // __wrap__sbrk() is implemented in: // TARGET_NUMAKER_PFM_NUC472 targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c // TARGET_NUMAKER_PFM_M453 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/m451_retarget.c +// TARGET_STM32L4 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4/l4_retarget.c extern "C" void *__wrap__sbrk(int incr); extern "C" caddr_t _sbrk(int incr) { return (caddr_t) __wrap__sbrk(incr); From 02b2b01a837d921d0fd2c0d14fc702d1fe3268e1 Mon Sep 17 00:00:00 2001 From: adustm Date: Tue, 20 Feb 2018 10:31:07 +0100 Subject: [PATCH 12/42] Change STM32L475/76/86 GCC_ARM linker files to have HEAP in SRAM1 and stack in SRAM2 (after the interrupt vector) --- .../device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld | 15 ++++++++++----- .../device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld | 15 ++++++++++----- .../device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld | 15 ++++++++++----- 3 files changed, 30 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld index ee234161e0..8e8e6db643 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld @@ -139,24 +139,29 @@ SECTIONS __end__ = .; end = __end__; *(.heap*) + . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .); __HeapLimit = .; } > SRAM1 - + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); + /* Check if data + heap exceeds RAM1 limit */ + ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow") /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ .stack_dummy (COPY): { *(.stack*) - } > SRAM1 + } > SRAM2 /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2); _estack = __StackTop; __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* Check if stack exceeds RAM2 limit */ + ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow") - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld index ee234161e0..8e8e6db643 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld @@ -139,24 +139,29 @@ SECTIONS __end__ = .; end = __end__; *(.heap*) + . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .); __HeapLimit = .; } > SRAM1 - + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); + /* Check if data + heap exceeds RAM1 limit */ + ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow") /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ .stack_dummy (COPY): { *(.stack*) - } > SRAM1 + } > SRAM2 /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2); _estack = __StackTop; __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* Check if stack exceeds RAM2 limit */ + ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow") - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld index d4f7965d54..9fc7632389 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld @@ -131,24 +131,29 @@ SECTIONS __end__ = .; end = __end__; *(.heap*) + . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .); __HeapLimit = .; } > SRAM1 - + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); + /* Check if data + heap exceeds RAM1 limit */ + ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow") /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ .stack_dummy (COPY): { *(.stack*) - } > SRAM1 + } > SRAM2 /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2); _estack = __StackTop; __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* Check if stack exceeds RAM2 limit */ + ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow") - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } From f551255ded5b3fa9d6d8e1c45fe7809fabb4dbbd Mon Sep 17 00:00:00 2001 From: adustm Date: Tue, 20 Feb 2018 10:32:49 +0100 Subject: [PATCH 13/42] Add support of separate memories for heap and stack region swith the use of TWO_RAM_REGIONS define --- .../TARGET_STM/TARGET_STM32L4/l4_retarget.c | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c new file mode 100644 index 0000000000..b56322b70f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c @@ -0,0 +1,68 @@ +/** + ****************************************************************************** + * @file l4_retarget.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for STM32L475xG + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(TWO_RAM_REGIONS) +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) + +#include +#include "stm32l4xx.h" +extern uint32_t __mbed_sbrk_start; +extern uint32_t __mbed_krbs_start; + +#define STM32L4_HEAP_ALIGN 32 +#define STM32L4_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1)) +/** + * The default implementation of _sbrk() (in platform/mbed_retarget.cpp) for GCC_ARM requires one-region model (heap and + * stack share one region), which doesn't fit two-region model (heap and stack are two distinct regions), for example, + * STM32L475xG locates heap on SRAM1 and stack on SRAM2. + * Define __wrap__sbrk() to override the default _sbrk(). It is expected to get called through gcc + * hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk(). + */ +void *__wrap__sbrk(int incr) +{ + static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start; + uint32_t heap_ind_old = STM32L4_ALIGN_UP(heap_ind, STM32L4_HEAP_ALIGN); + uint32_t heap_ind_new = STM32L4_ALIGN_UP(heap_ind_old + incr, STM32L4_HEAP_ALIGN); + + if (heap_ind_new > &__mbed_krbs_start) { + errno = ENOMEM; + return (void *) -1; + } + + heap_ind = heap_ind_new; + + return (void *) heap_ind_old; +} +#endif /* GCC_ARM toolchain */ +#endif /* TWO_RAM_REGIONS */ From 815be94197e61c3a3a4cc8e4ec2c4d8a92f0e114 Mon Sep 17 00:00:00 2001 From: adustm Date: Tue, 20 Feb 2018 11:38:28 +0100 Subject: [PATCH 14/42] Add defined for GCC_ARM to pass heap and stack tests --- targets/TARGET_STM/mbed_rtx.h | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index f208b87fd3..f81af15724 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -19,7 +19,15 @@ #ifndef INITIAL_SP -#if (defined(TARGET_STM32F051R8) ||\ +#if (defined(TARGET_STM32L475VG)) +/* only GCC_ARM and IAR toolchain have the stack on SRAM2 */ +#if (defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) || defined(__IAR_SYSTEMS_ICC__ )) +#define INITIAL_SP (0x10008000UL) +#else +#define INITIAL_SP (0x20018000UL) +#endif /* toolchains */ + +#elif (defined(TARGET_STM32F051R8) ||\ defined(TARGET_STM32F100RB) ||\ defined(TARGET_STM32L031K6) ||\ defined(TARGET_STM32L053C8) ||\ @@ -69,7 +77,6 @@ #define INITIAL_SP (0x20014000UL) #elif (defined(TARGET_STM32F401RE) ||\ - defined(TARGET_STM32L475VG) ||\ defined(TARGET_STM32L476RG) ||\ defined(TARGET_STM32L476JG) ||\ defined(TARGET_STM32L476VG) ||\ @@ -110,5 +117,17 @@ #endif #endif // INITIAL_SP +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) + extern uint32_t __StackLimit[]; + extern uint32_t __StackTop[]; + extern uint32_t __end__[]; + extern uint32_t __HeapLimit[]; + #define HEAP_START ((unsigned char*)__end__) + #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) + #define ISR_STACK_START ((unsigned char*)__StackLimit) + #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +#elif defined(__ICCARM__) + /* No region declarations needed */ +#endif #endif // MBED_MBED_RTX_H From 98657449b80724d50fba326e9b9f9f77c45fe3aa Mon Sep 17 00:00:00 2001 From: adustm Date: Thu, 22 Feb 2018 17:23:08 +0100 Subject: [PATCH 15/42] Use the TWO_RAM_REGIONS in targets.json for STM32L475 / STM32L476 and STM32L486 devices --- targets/targets.json | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 1561c94a7c..e8ec750100 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1552,7 +1552,7 @@ } }, "detect_code": ["0765"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L476RG", @@ -1571,7 +1571,7 @@ } }, "detect_code": ["0766"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["5"], "device_name": "STM32L476JG" @@ -1863,7 +1863,7 @@ }, "supported_form_factors": ["ARDUINO"], "detect_code": ["0764"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L475VG", @@ -1885,7 +1885,7 @@ } }, "detect_code": ["0820"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L476VG", From 67953251f963afefc3595c25003545d1880f8711 Mon Sep 17 00:00:00 2001 From: adustm Date: Fri, 23 Feb 2018 10:29:29 +0100 Subject: [PATCH 16/42] Use official toolchain defines --- targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c | 8 +++----- targets/TARGET_STM/mbed_rtx.h | 10 +++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c index b56322b70f..dbb446aa7a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c +++ b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c @@ -32,9 +32,7 @@ * ****************************************************************************** */ -#if defined(TWO_RAM_REGIONS) -#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) - +#if (defined(TWO_RAM_REGIONS) && defined(__GNUC__) && !defined(__CC_ARM)) #include #include "stm32l4xx.h" extern uint32_t __mbed_sbrk_start; @@ -64,5 +62,5 @@ void *__wrap__sbrk(int incr) return (void *) heap_ind_old; } -#endif /* GCC_ARM toolchain */ -#endif /* TWO_RAM_REGIONS */ +#endif /* GCC_ARM toolchain && TWO_RAM_REGIONS*/ + diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index f81af15724..d3bf003e53 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -20,8 +20,10 @@ #ifndef INITIAL_SP #if (defined(TARGET_STM32L475VG)) -/* only GCC_ARM and IAR toolchain have the stack on SRAM2 */ -#if (defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) || defined(__IAR_SYSTEMS_ICC__ )) +/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */ +#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\ + defined(__IAR_SYSTEMS_ICC__ )) &&\ + defined(TWO_RAM_REGIONS)) #define INITIAL_SP (0x10008000UL) #else #define INITIAL_SP (0x20018000UL) @@ -117,7 +119,7 @@ #endif #endif // INITIAL_SP -#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) +#if (defined(__GNUC__) && !defined(__CC_ARM)) extern uint32_t __StackLimit[]; extern uint32_t __StackTop[]; extern uint32_t __end__[]; @@ -126,8 +128,6 @@ #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) #define ISR_STACK_START ((unsigned char*)__StackLimit) #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) -#elif defined(__ICCARM__) - /* No region declarations needed */ #endif #endif // MBED_MBED_RTX_H From 28a43b55e738f5f58824dd7de46d35fdfb6c9e63 Mon Sep 17 00:00:00 2001 From: adustm Date: Fri, 23 Feb 2018 10:44:14 +0100 Subject: [PATCH 17/42] Add initial_sp value for STM32L476 and STM32L486 devices --- targets/TARGET_STM/mbed_rtx.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index d3bf003e53..8ef789369d 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -19,7 +19,11 @@ #ifndef INITIAL_SP -#if (defined(TARGET_STM32L475VG)) +#if (defined(TARGET_STM32L475VG) ||\ + defined(TARGET_STM32L476RG) ||\ + defined(TARGET_STM32L476JG) ||\ + defined(TARGET_STM32L476VG) ||\ + defined(TARGET_STM32L486RG)) /* only GCC_ARM and IAR toolchains have the stack on SRAM2 */ #if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\ defined(__IAR_SYSTEMS_ICC__ )) &&\ @@ -78,11 +82,7 @@ #elif defined(TARGET_STM32L152RE) #define INITIAL_SP (0x20014000UL) -#elif (defined(TARGET_STM32F401RE) ||\ - defined(TARGET_STM32L476RG) ||\ - defined(TARGET_STM32L476JG) ||\ - defined(TARGET_STM32L476VG) ||\ - defined(TARGET_STM32L486RG)) +#elif defined(TARGET_STM32F401RE) #define INITIAL_SP (0x20018000UL) #elif (defined(TARGET_STM32F207ZG) ||\ From eff848abea45ea2a8d4d68d8163207af0f8dea87 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 22 Feb 2018 13:34:34 -0600 Subject: [PATCH 18/42] LPC546XX: Update SDK driver to version 2.3 Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC546XX/drivers/fsl_adc.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_adc.h | 32 +- .../TARGET_LPC546XX/drivers/fsl_clock.c | 131 ++++- .../TARGET_LPC546XX/drivers/fsl_clock.h | 40 +- .../TARGET_LPC546XX/drivers/fsl_common.c | 144 ++---- .../TARGET_LPC546XX/drivers/fsl_common.h | 255 +++++---- .../TARGET_LPC546XX/drivers/fsl_crc.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_crc.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_ctimer.c | 40 +- .../TARGET_LPC546XX/drivers/fsl_ctimer.h | 43 +- .../TARGET_LPC546XX/drivers/fsl_dma.c | 158 +++--- .../TARGET_LPC546XX/drivers/fsl_dma.h | 189 ++++--- .../TARGET_LPC546XX/drivers/fsl_dmic.c | 18 +- .../TARGET_LPC546XX/drivers/fsl_dmic.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_dmic_dma.c | 9 +- .../TARGET_LPC546XX/drivers/fsl_dmic_dma.h | 35 +- .../TARGET_LPC546XX/drivers/fsl_eeprom.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_eeprom.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_emc.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_emc.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_enet.c | 24 +- .../TARGET_LPC546XX/drivers/fsl_enet.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_flashiap.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_flashiap.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_flexcomm.c | 61 ++- .../TARGET_LPC546XX/drivers/fsl_flexcomm.h | 12 +- .../TARGET_LPC546XX/drivers/fsl_fmc.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_fmc.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_fmeas.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_fmeas.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_gint.c | 46 +- .../TARGET_LPC546XX/drivers/fsl_gint.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_gpio.c | 20 +- .../TARGET_LPC546XX/drivers/fsl_gpio.h | 127 ++++- .../TARGET_LPC546XX/drivers/fsl_i2c.c | 103 +++- .../TARGET_LPC546XX/drivers/fsl_i2c.h | 55 +- .../TARGET_LPC546XX/drivers/fsl_i2c_dma.c | 8 +- .../TARGET_LPC546XX/drivers/fsl_i2c_dma.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_i2s.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_i2s.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_i2s_dma.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_i2s_dma.h | 21 +- .../TARGET_LPC546XX/drivers/fsl_inputmux.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_inputmux.h | 6 +- .../drivers/fsl_inputmux_connections.h | 37 +- .../TARGET_LPC546XX/drivers/fsl_iocon.h | 143 ++--- .../TARGET_LPC546XX/drivers/fsl_lcdc.c | 10 +- .../TARGET_LPC546XX/drivers/fsl_lcdc.h | 12 +- .../TARGET_LPC546XX/drivers/fsl_mcan.c | 26 +- .../TARGET_LPC546XX/drivers/fsl_mcan.h | 10 +- .../TARGET_LPC546XX/drivers/fsl_mrt.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_mrt.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_otp.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_phy.c | 18 +- .../TARGET_LPC546XX/drivers/fsl_phy.h | 8 +- .../TARGET_LPC546XX/drivers/fsl_pint.c | 62 ++- .../TARGET_LPC546XX/drivers/fsl_pint.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_power.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_power.h | 12 +- .../TARGET_LPC546XX/drivers/fsl_reset.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_reset.h | 12 +- .../TARGET_LPC546XX/drivers/fsl_rit.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_rit.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_rng.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_rtc.c | 8 +- .../TARGET_LPC546XX/drivers/fsl_rtc.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_sctimer.c | 11 +- .../TARGET_LPC546XX/drivers/fsl_sctimer.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_sdif.c | 201 ++++--- .../TARGET_LPC546XX/drivers/fsl_sdif.h | 103 ++-- .../TARGET_LPC546XX/drivers/fsl_sha.c | 489 ++++++++++++++++++ .../TARGET_LPC546XX/drivers/fsl_sha.h | 145 ++++++ .../TARGET_LPC546XX/drivers/fsl_spi.c | 164 +++++- .../TARGET_LPC546XX/drivers/fsl_spi.h | 139 ++++- .../TARGET_LPC546XX/drivers/fsl_spi_dma.c | 244 ++++++--- .../TARGET_LPC546XX/drivers/fsl_spi_dma.h | 21 +- .../TARGET_LPC546XX/drivers/fsl_spifi.c | 8 +- .../TARGET_LPC546XX/drivers/fsl_spifi.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_spifi_dma.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_spifi_dma.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_usart.c | 8 +- .../TARGET_LPC546XX/drivers/fsl_usart.h | 28 +- .../TARGET_LPC546XX/drivers/fsl_usart_dma.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_usart_dma.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_utick.c | 21 +- .../TARGET_LPC546XX/drivers/fsl_utick.h | 6 +- .../TARGET_LPC546XX/drivers/fsl_wwdt.c | 6 +- .../TARGET_LPC546XX/drivers/fsl_wwdt.h | 6 +- 88 files changed, 2917 insertions(+), 840 deletions(-) create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c index 2c8b2cb111..6b23b903fb 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h index 6db5030cd8..f5a416e9d5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,8 +50,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief ADC driver version 2.0.0. */ -#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief ADC driver version 2.1.0. */ +#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ /*! @@ -150,7 +154,7 @@ typedef enum _adc_trigger_polarity typedef enum _adc_priority { kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ - kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */ + kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ } adc_priority_t; /*! @@ -247,7 +251,7 @@ typedef struct _adc_conv_seq_config */ typedef struct _adc_result_info { - uint32_t result; /*!< Keey the conversion data value. */ + uint32_t result; /*!< Keep the conversion data value. */ adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ @@ -307,6 +311,7 @@ void ADC_GetDefaultConfig(adc_config_t *config); */ bool ADC_DoSelfCalibration(ADC_Type *base); +#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) /*! * @brief Enable the internal temperature sensor measurement. * @@ -327,7 +332,7 @@ static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); } } - +#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ /* @} */ /*! @@ -611,13 +616,24 @@ static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) } /*! - * @brief Enable the interrupt of shreshold compare event for each channel. + * @brief Enable the interrupt of threshold compare event for each channel. + * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt + */ +static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, + uint32_t channel, + adc_threshold_interrupt_mode_t mode) +{ + base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); +} + +/*! + * @brief Enable the interrupt of threshold compare event for each channel. * * @param base ADC peripheral base address. * @param channel Channel number. * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. */ -static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, +static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base, uint32_t channel, adc_threshold_interrupt_mode_t mode) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c index 90a32de9d3..de2e2971da 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016 - 2017 , NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -150,6 +154,10 @@ static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); +/* Convert the binary to fractional part */ +static double Binary2Fractional(uint32_t binaryPart); +/* Calculate the powerTimes' power of 2 */ +static uint32_t power2Cal(uint32_t powerTimes); /* Get the greatest common divisor */ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); /* Set PLL output based on desired output rate */ @@ -969,6 +977,25 @@ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) return mMult; } +/* Calculate the powerTimes' power of 2 */ +static uint32_t power2Cal(uint32_t powerTimes) +{ + if (powerTimes == 0) + return 1; + return 2 * power2Cal(powerTimes - 1); +} + +/* Convert the binary to fractional part */ +static double Binary2Fractional(uint32_t binaryPart) +{ + double fractional = 0; + for (uint32_t i = 0; i <= 14; i++) + { + fractional += (double)((binaryPart >> i) & 0x1U) / (double)power2Cal(15 - i); + } + return fractional; +} + /* Find greatest common divisor between m and n */ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) { @@ -1174,6 +1201,12 @@ static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup) s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup); } +/* Update AUDIO Fractional PLL rate variable */ +static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup) +{ + s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup); +} + /* Update USB PLL rate variable */ static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup) { @@ -1366,6 +1399,58 @@ uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) return (uint32_t)workRate; } +/* Return Audio PLL output clock rate from audio fractioanl setup structure */ +uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, inPllRate; + double workRate, mMultFactional; + + inPllRate = CLOCK_GetAudioPLLInClockRate(); + if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* + * 2. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + mMultFactional = (double)(pSetup->audpllfrac >> 15) + (double)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU); + workRate = (double)inPllRate * (double)mMultFactional; + + workRate = workRate / ((double)postdiv); + workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + /* Set the current PLL Rate */ void CLOCK_SetStoredPLLClockRate(uint32_t rate) { @@ -1609,6 +1694,48 @@ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) return kStatus_PLL_Success; } +/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */ +pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg) +{ + if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->AUDPLLCTRL = pSetup->pllctrl; + SYSCON->AUDPLLNDEC = pSetup->pllndec; + SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->AUDPLLPDEC = pSetup->pllpdec; + SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->AUDPLLMDEC = pSetup->pllmdec; + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */ + SYSCON->AUDPLLFRAC = pSetup->audpllfrac; + SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsAudioPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup); + + return kStatus_PLL_Success; +} + /* Set Audio PLL output based on the passed Audio PLL setup data */ pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) { @@ -1819,7 +1946,7 @@ pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup) } /* If configure the USB HOST clock, VD5 power for USB PHY should be enable - before the the PLL is working */ + before the PLL is working */ /* Turn on the ext clock for usb pll input */ CLOCK_Enable_SysOsc(true); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h index a602dc9fba..b21e9e43f5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016 - 2017 , NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,6 +50,12 @@ * Definitions *****************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! @brief Configure whether driver controls clock * * When set to 0, peripheral drivers will enable clock in initialize function @@ -119,7 +129,7 @@ /*! @brief Clock ip name array for GPIO. */ #define GPIO_CLOCKS \ { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ } /*! @brief Clock ip name array for PINT. */ #define PINT_CLOCKS \ @@ -670,12 +680,12 @@ typedef enum _clock_attach_id kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), - + kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), - + kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), @@ -988,10 +998,10 @@ __STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable) SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; } - + else { - SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; + SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; } @@ -1134,6 +1144,12 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); */ uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup); +/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup); + /*! @brief Return System USB PLL output clock rate from setup structure * @param pSetup : Pointer to a PLL setup structure * @return System PLL output clock rate the setup structure will generate @@ -1182,6 +1198,18 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); */ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); +/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency) + * @param pSetup : Pointer to populated PLL setup structure +* @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, + * and adjust system voltages to the new AUDIOPLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg); + /** * @brief Set PLL output from PLL setup structure (precise frequency) * @param pSetup : Pointer to populated PLL setup structure diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c index 18609460a9..4761130a3b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c @@ -1,78 +1,46 @@ /* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ +* The Clear BSD License +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP +* All rights reserved. +* +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ #include "fsl_common.h" -/* This is not needed for mbed */ -#if 0 -#include "fsl_debug_console.h" -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif(defined(__REDLIB__)) - -#if SDK_DEBUGCONSOLE -void __assertion_failed(char *_Expr) -{ - PRINTF("%s\n", _Expr); - for (;;) - { - __asm("bkpt #0"); - } -} -#endif - -#elif(defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ -#endif /* NDEBUG */ -#endif #ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) { /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined(__CC_ARM) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; extern uint32_t Image$$RW_m_data$$Base[]; @@ -112,11 +80,18 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) EnableGlobalIRQ(irqMaskValue); - return ret; -} +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); #endif -#ifndef CPU_QN908X + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#ifndef QN908XC_SERIES #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) void EnableDeepSleepIRQ(IRQn_Type interrupt) @@ -147,32 +122,5 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt) SYSCON->STARTERCLR[index] = 1u << intNumber; } #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#else -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - /* SYSCON->STARTERSET[index] = 1u << intNumber; */ - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ -} -#endif /*CPU_QN908X */ +#endif /* QN908XC_SERIES */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h index ead53ac46f..511dfb5ff6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -57,6 +61,12 @@ /*! @brief Construct the version number for drivers. */ #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.0. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /* Debug console type definition. */ #define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ #define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ @@ -65,6 +75,7 @@ #define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ #define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ #define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ /*! @brief Status group numbers. */ enum _status_groups @@ -96,6 +107,8 @@ enum _status_groups kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ @@ -120,11 +133,20 @@ enum _status_groups kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ }; /*! @brief Generic status return codes. */ @@ -168,7 +190,9 @@ typedef int32_t status_t; /* @} */ /*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif /*! @name UINT16_MAX/UINT32_MAX value */ /* @{ */ @@ -316,77 +340,102 @@ _Pragma("diag_suppress=Pm120") ******************************************************************************/ #if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable specific interrupt. - * - * Enable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void EnableIRQ(IRQn_Type interrupt) + extern "C" { - if (NotAvail_IRQn == interrupt) - { - return; - } - -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) #endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + #if defined(__GIC_PRIO_BITS) GIC_EnableIRQ(interrupt); #else NVIC_EnableIRQ(interrupt); #endif + return kStatus_Success; } -} -/*! - * @brief Disable specific interrupt. - * - * Disable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void DisableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) { - return; - } + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } #endif - { + #if defined(__GIC_PRIO_BITS) GIC_DisableIRQ(interrupt); #else - NVIC_DisableIRQ(interrupt); + NVIC_DisableIRQ(interrupt); #endif + return kStatus_Success; } -} -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { #if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - __disable_irq(); + __disable_irq(); - return cpsr; + return cpsr; #else uint32_t regPrimask = __get_PRIMASK(); @@ -394,66 +443,68 @@ static inline uint32_t DisableGlobalIRQ(void) return regPrimask; #endif -} + } -/*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { #if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); #else __set_PRIMASK(primask); #endif -} + } -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ #if defined(__cplusplus) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c index e413222dec..3a736bc59c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h index 5b1338d9b1..7baa918a08 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c index ac69e33344..5cea25715c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -302,7 +306,11 @@ void CTIMER_GenericIRQHandler(uint32_t index) } else { +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ { mask = 0x01 << i; /* For each status flag bit that was set call the callback function if it is valid */ @@ -312,6 +320,11 @@ void CTIMER_GenericIRQHandler(uint32_t index) } } } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /* IRQ handler functions overloading weak symbols in the startup */ @@ -319,6 +332,11 @@ void CTIMER_GenericIRQHandler(uint32_t index) void CTIMER0_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -326,6 +344,11 @@ void CTIMER0_DriverIRQHandler(void) void CTIMER1_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -333,6 +356,11 @@ void CTIMER1_DriverIRQHandler(void) void CTIMER2_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(2); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -340,6 +368,11 @@ void CTIMER2_DriverIRQHandler(void) void CTIMER3_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(3); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -347,6 +380,11 @@ void CTIMER3_DriverIRQHandler(void) void CTIMER4_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(4); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h index 6d4e9ae11a..9a10478251 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -54,7 +58,9 @@ typedef enum _ctimer_capture_channel kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ kCTIMER_Capture_1, /*!< Timer capture channel 1 */ kCTIMER_Capture_2, /*!< Timer capture channel 2 */ - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ } ctimer_capture_channel_t; /*! @brief List of capture edge options */ @@ -102,7 +108,9 @@ typedef enum _ctimer_interrupt_enable kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ } ctimer_interrupt_enable_t; /*! @brief List of Timer flags */ @@ -115,7 +123,9 @@ typedef enum _ctimer_status_flags kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ } ctimer_status_flags_t; typedef void (*ctimer_callback_t)(uint32_t flags); @@ -126,9 +136,9 @@ typedef void (*ctimer_callback_t)(uint32_t flags); */ typedef enum { - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture */ } ctimer_callback_type_t; @@ -306,10 +316,14 @@ void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctim static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) { /* Enable match interrupts */ - base->MCR |= mask; + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); /* Enable capture interrupts */ - base->CCR |= mask; + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); } /*! @@ -322,10 +336,14 @@ static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) { /* Disable match interrupts */ - base->MCR &= ~mask; + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); /* Disable capture interrupts */ - base->CCR &= ~mask; + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); } /*! @@ -342,11 +360,14 @@ static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) /* Get all the match interrupts enabled */ enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT); + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); /* Get all the capture interrupts enabled */ - enabledIntrs |= - base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT); + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); return enabledIntrs; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c index 99b9dd8a4c..dce88c396e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -111,11 +115,9 @@ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_t { assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger)); - uint32_t tmp = ( - DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK - ); + uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); tmp = base->CHANNEL[channel].CFG & (~tmp); tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); base->CHANNEL[channel].CFG = tmp; @@ -132,7 +134,7 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes * impossible to distinguish between: * - transfer finishes (represented by value '0x3FF') * - and remaining 1024 bytes to transfer (value 0x3FF) @@ -140,10 +142,9 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) * If you decide to use this function, please use 1023 transfers as maximal value */ /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ( - (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) - ) + if ((!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && + (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) { return 0; } @@ -152,12 +153,7 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) } static void DMA_SetupDescriptor( - dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcEndAddr, - void *dstEndAddr, - void *nextDesc -) + dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc) { desc->xfercfg = xfercfg; desc->srcEndAddr = srcEndAddr; @@ -166,10 +162,7 @@ static void DMA_SetupDescriptor( } /* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG( - dma_xfercfg_t *xfercfg, - uint32_t *xfercfg_addr -) +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) { assert(xfercfg != NULL); /* check source increment */ @@ -187,9 +180,9 @@ static void DMA_SetupXferCFG( /* set reload - allow link to next descriptor */ xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0); + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0); + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); /* set INTA */ xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); /* set INTB */ @@ -210,13 +203,7 @@ static void DMA_SetupXferCFG( *xfercfg_addr = xfer; } -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -) +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) { uint32_t xfercfg_reg = 0; @@ -229,11 +216,9 @@ void DMA_CreateDescriptor( DMA_SetupXferCFG(xfercfg, &xfercfg_reg); /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, - (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - nextDesc - ); + DMA_SetupDescriptor( + desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), + (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc); } void DMA_AbortTransfer(dma_handle_t *handle) @@ -242,7 +227,8 @@ void DMA_AbortTransfer(dma_handle_t *handle) DMA_DisableChannel(handle->base, handle->channel); while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel))) - { } + { + } handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel); DMA_EnableChannel(handle->base, handle->channel); } @@ -272,12 +258,12 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData } void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) { uint32_t xfer_count; assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); @@ -290,35 +276,35 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config, memset(config, 0, sizeof(*config)); switch (type) { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; + case kDMA_MemoryToMemory: + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + default: + return; } - config->dstAddr = (uint8_t*)dstAddr; - config->srcAddr = (uint8_t*)srcAddr; - config->nextDesc = (uint8_t*)nextDesc; + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; config->xfercfg.transferCount = xfer_count; config->xfercfg.byteWidth = byteWidth; config->xfercfg.intA = true; @@ -333,7 +319,7 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) /* Previous transfer has not finished */ if (DMA_ChannelIsActive(handle->base, handle->channel)) { - return kStatus_DMA_Busy; + return kStatus_DMA_Busy; } /* enable/disable peripheral request */ @@ -346,10 +332,8 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) DMA_DisableChannelPeriphRq(handle->base, handle->channel); } - DMA_CreateDescriptor( - &s_dma_descriptor_table[ handle->channel ], &config->xfercfg, - config->srcAddr, config->dstAddr, config->nextDesc - ); + DMA_CreateDescriptor(&s_dma_descriptor_table[handle->channel], &config->xfercfg, config->srcAddr, config->dstAddr, + config->nextDesc); return kStatus_Success; } @@ -364,18 +348,18 @@ void DMA_StartTransfer(dma_handle_t *handle) /* If HW trigger is enabled - disable SW trigger */ if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) { - s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); + s_dma_descriptor_table[handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); } /* Otherwise enable SW trigger */ else { - s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + s_dma_descriptor_table[handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; } /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg; - /* At this moment, the channel ACTIVE bit is set and application cannot modify - * or start another transfer using this channel. Channel ACTIVE bit is cleared by + handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[handle->channel].xfercfg; + /* At this moment, the channel ACTIVE bit is set and application cannot modify + * or start another transfer using this channel. Channel ACTIVE bit is cleared by * 'AbortTransfer' function or when the transfer finishes */ } @@ -416,6 +400,20 @@ void DMA0_DriverIRQHandler(void) (handle->callback)(handle, handle->userData, true, kDMA_IntB); } } + /* Error flag */ + if (handle->base->COMMON[channel_group].ERRINT & (1U << channel_index)) + { + /* Clear error flag */ + handle->base->COMMON[channel_group].ERRINT = 1U << channel_index; + if (handle->callback) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h index fbe7d007ab..01d435d169 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -56,17 +60,18 @@ /* Channel index in channel group. channel_index = (channel % 32) */ #define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F) - /*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor { - uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +typedef struct _dma_descriptor +{ + uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ } dma_descriptor_t; /*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg { +typedef struct _dma_xfercfg +{ bool valid; /*!< Descriptor is ready to transfer */ bool reload; /*!< Reload channel configuration register after current descriptor is exhausted */ @@ -82,55 +87,74 @@ typedef struct _dma_xfercfg { } dma_xfercfg_t; /*! @brief DMA channel priority */ -typedef enum _dma_priority { - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ } dma_priority_t; /*! @brief DMA interrupt flags */ -typedef enum _dma_int { - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ } dma_irq_t; /*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type { - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ } dma_trigger_type_t; /*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst { - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; /*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap { - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ } dma_burst_wrap_t; /*! @brief DMA transfer type */ @@ -143,27 +167,28 @@ typedef enum _dma_transfer_type } dma_transfer_type_t; /*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger { - dma_trigger_type_t type; - dma_trigger_burst_t burst; - dma_burst_wrap_t wrap; +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ } dma_channel_trigger_t; /*! @brief DMA transfer status */ enum _dma_transfer_status { - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ }; /*! @brief DMA transfer configuration */ typedef struct _dma_transfer_config { - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ } dma_transfer_config_t; /*! @brief Callback for DMA */ @@ -175,11 +200,11 @@ typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool tr /*! @brief DMA transfer handle structure */ typedef struct _dma_handle { - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ } dma_handle_t; /******************************************************************************* @@ -219,13 +244,13 @@ void DMA_Deinit(DMA_Type *base); * @{ */ - /*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ +/*! +* @brief Return whether DMA channel is processing transfer +* +* @param base DMA peripheral base address. +* @param channel DMA channel number. +* @return True for active state, false otherwise. +*/ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); @@ -333,7 +358,8 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) { assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); } /*! @@ -346,11 +372,12 @@ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) { assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); + return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); } /*! - * @brief Create application specific DMA descriptor + * @brief Create application specific DMA descriptor * to be used in a chain in transfer * * @param desc DMA descriptor address. @@ -359,13 +386,7 @@ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t cha * @param dstAddr Address of last item to receive. * @param nextDesc Address of next descriptor in chain. */ -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -); +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); /* @} */ @@ -379,7 +400,7 @@ void DMA_CreateDescriptor( * * This function aborts DMA transfer specified by handle. * - * @param handle DMA handle pointer. + * @param handle DMA handle pointer. */ void DMA_AbortTransfer(dma_handle_t *handle); @@ -425,12 +446,12 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData * source address error(SAE). */ void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); /*! * @brief Submits the DMA transfer request. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c index bf88fd76b9..0ee658a49a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -223,13 +227,23 @@ void DMIC0_DriverIRQHandler(void) { s_dmicCallback[0](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /*DMIC0 HWVAD IRQ handler */ -void HWVAD0_IRQHandler(void) +void HWVAD0_DriverIRQHandler(void) { if (s_dmicHwvadCallback[0] != NULL) { s_dmicHwvadCallback[0](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h index a97948d7df..72f8623470 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c index 8ac8ffffc4..adec7d73e4 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -120,6 +124,7 @@ status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, handle->userData = userData; handle->rxDmaHandle = rxDmaHandle; + handle->dataWidth = 2U; /* Set DMIC state to idle */ handle->state = kDMIC_Idle; @@ -157,7 +162,7 @@ status_t DMIC_TransferReceiveDMA(DMIC_Type *base, handle->transferSize = xfer->dataSize; /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t), + DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, handle->dataWidth, xfer->dataSize, kDMA_PeripheralToMemory, NULL); /* Submit transfer. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h index 8d3be059b0..65539e68d6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -51,6 +55,13 @@ typedef struct _dmic_transfer size_t dataSize; /*!< The byte count to be transfer. */ } dmic_transfer_t; +/*! @brief DMIC transfer structure. */ +typedef enum dmic_bitwidth +{ + kDMICBitWidth16Bits = 2U, /*!< 16 bits mode.*/ + kDMICBitWidth32Bits = 4U, /*!< 32 bits mode. */ +} dmic_bitwidth_t; + /* Forward declaration of the handle typedef. */ typedef struct _dmic_dma_handle dmic_dma_handle_t; @@ -68,6 +79,7 @@ struct _dmic_dma_handle DMIC_Type *base; /*!< DMIC peripheral base address. */ dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ dmic_dma_transfer_callback_t callback; /*!< Callback function. */ + uint8_t dataWidth; /*!< Data bit width */ void *userData; /*!< DMIC callback function parameter.*/ size_t transferSize; /*!< Size of the data to receive. */ volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ @@ -100,16 +112,33 @@ status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, void *userData, dma_handle_t *rxDmaHandle); +/*! + * @brief Configure the transfer data width. + * + * This function is optional to users, the default data width is set to 16 bits if not call this fuction. + * DMIC only support 16 bits and 32 bits setting. As DMA cannot support 24 bits directly, please set to 32 bits + * while need a 24 bits data. In 32 bit mode, the MSB 8 bits always 0, as the register can only have 24 bits valid bits. + * + * @param base DMIC peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param width DMIC width. See #dmic_bitwidth_t. + * @retval kStatus_Success + */ +static inline void DMIC_TransferSetBitWidthDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_bitwidth_t width) +{ + handle->dataWidth = width; +} + /*! * @brief Receives data using DMA. * * This function receives data using DMA. This is a non-blocking function, which returns * right away. When all data is received, the receive callback function is called. * - * @param base USART peripheral base address. + * @param base DMIC peripheral base address. * @param handle Pointer to usart_dma_handle_t structure. * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. - * @param dmic_channel DMIC channel + * @param dmic_channel DMIC channel * @retval kStatus_Success */ status_t DMIC_TransferReceiveDMA(DMIC_Type *base, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c index c8099b6dea..7c105badc5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h index 67f20df058..8fdfd228d5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c index 7ed4f64657..0861326d2f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h index 1afce0b6b8..7fcc0199d0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c index 8dfada5e4f..db893a2b32 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -919,8 +923,8 @@ status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer assert(config); assert(bufferConfig); - bool intTxEnable; - bool intRxEnable; + bool intTxEnable = false; + bool intRxEnable = false; bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false; uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2; uint8_t channel; @@ -928,12 +932,12 @@ status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer for (channel = 0; channel < ringNum; channel++) { intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false; + intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false; if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success) { return kStatus_Fail; } - intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false; if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success) { @@ -1244,7 +1248,7 @@ status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *l enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel]; enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - uint16_t index; + uint16_t index = rxBdRing->rxGenIdx; /* Reset the length to zero. */ *length = 0; @@ -1802,9 +1806,19 @@ void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle) } } #endif /* ENET_PTP1588FEATURE_REQUIRED */ + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void ETHERNET_DriverIRQHandler(void) { s_enetIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h index 631fd88121..dc59586db5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c index 862fd2d227..ea22b10466 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h index 3325ea7ce9..7a09589e1e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c index ffb240e064..b995b4f904 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -155,6 +159,11 @@ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *ha s_flexcommIrqHandler[instance] = NULL; s_flexcommHandle[instance] = handle; s_flexcommIrqHandler[instance] = handler; + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } /* IRQ handler functions overloading weak symbols in the startup */ @@ -163,6 +172,11 @@ void FLEXCOMM0_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[0]); s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -171,6 +185,11 @@ void FLEXCOMM1_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[1]); s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -179,6 +198,11 @@ void FLEXCOMM2_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[2]); s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -187,6 +211,11 @@ void FLEXCOMM3_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[3]); s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -195,6 +224,11 @@ void FLEXCOMM4_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[4]); s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -204,6 +238,11 @@ void FLEXCOMM5_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[5]); s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -212,6 +251,11 @@ void FLEXCOMM6_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[6]); s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -220,6 +264,11 @@ void FLEXCOMM7_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[7]); s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -228,6 +277,11 @@ void FLEXCOMM8_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[8]); s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -236,5 +290,10 @@ void FLEXCOMM9_DriverIRQHandler(void) { assert(s_flexcommIrqHandler[9]); s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h index 3e305dc620..866a370223 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -37,6 +41,12 @@ * @{ */ +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.0. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! @brief FLEXCOMM peripheral modes. */ typedef enum { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c index c985d323db..01f376ece2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h index 8c5ccd4beb..8553811be7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c index 6e6e7c0c66..7ec1984b58 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h index 354f513e97..0e14e3db9d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c index ac7c615df8..3bc8eaa284 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -176,6 +180,11 @@ void GINT0_DriverIRQHandler(void) { s_gintCallback[0](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -189,6 +198,11 @@ void GINT1_DriverIRQHandler(void) { s_gintCallback[1](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -202,6 +216,11 @@ void GINT2_DriverIRQHandler(void) { s_gintCallback[2](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -215,6 +234,11 @@ void GINT3_DriverIRQHandler(void) { s_gintCallback[3](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -228,6 +252,11 @@ void GINT4_DriverIRQHandler(void) { s_gintCallback[4](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -241,6 +270,11 @@ void GINT5_DriverIRQHandler(void) { s_gintCallback[5](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -254,6 +288,11 @@ void GINT6_DriverIRQHandler(void) { s_gintCallback[6](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -267,5 +306,10 @@ void GINT7_DriverIRQHandler(void) { s_gintCallback[7](); } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h index 499536c4ae..290c673da1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c index 3b70fb467b..2581df0f9b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,7 +37,10 @@ /******************************************************************************* * Variables ******************************************************************************/ - +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* * Prototypes ************ ******************************************************************/ @@ -41,6 +48,15 @@ /******************************************************************************* * Code ******************************************************************************/ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h index f92b60f332..b43140fc0a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,8 +50,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPC GPIO driver version 2.0.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief LPC GPIO driver version 2.1.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*@}*/ /*! @brief LPC GPIO direction definition */ @@ -80,6 +84,25 @@ extern "C" { /*! @name GPIO Configuration */ /*@{*/ +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes the GPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit. + */ +static inline void GPIO_Init(GPIO_Type *base, uint32_t port) +{ + GPIO_PortInit(base, port); +} + /*! * @brief Initializes a GPIO pin used by the board. * @@ -124,6 +147,15 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) { base->B[port][pin] = output; @@ -142,10 +174,19 @@ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t * - 0: corresponding pin input low-logic level. * - 1: corresponding pin input high-logic level. */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) { return (uint32_t)base->B[port][pin]; } + +/*! + * @brief Reads the current input value of the GPIO PIN. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return GPIO_PinRead(base, port, pin); +} /*@}*/ /*! @@ -155,11 +196,20 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_ * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->SET[port] = mask; } +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortSet(base, port, mask); +} + /*! * @brief Sets the output level of the multiple GPIO pins to the logic 0. * @@ -167,11 +217,20 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t m * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) { base->CLR[port] = mask; } +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortClear(base, port, mask); +} + /*! * @brief Reverses current output logic of the multiple GPIO pins. * @@ -179,10 +238,19 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) { base->NOT[port] = mask; } + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle. + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortToggle(base, port, mask); +} /*@}*/ /*! @@ -191,11 +259,20 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_ * @param base GPIO peripheral base pointer(Typically GPIO) * @param port GPIO port number */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->PIN[port]; } +/*! + * @brief Reads the current input value of the whole GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead + */ +static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortRead(base, port); +} + /*@}*/ /*! @name GPIO Mask Operations */ /*@{*/ @@ -207,11 +284,20 @@ static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->MASK[port] = mask; } +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet. + */ +static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortMaskedSet(base, port, mask); +} + /*! * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. * @@ -219,11 +305,20 @@ static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mas * @param port GPIO port number * @param output GPIO port output value. */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) { base->MPIN[port] = output; } +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite. + */ +static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +{ + GPIO_PortMaskedWrite(base, port, output); +} + /*! * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be * affected. @@ -232,11 +327,21 @@ static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t outp * @param port GPIO port number * @retval masked GPIO port value */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->MPIN[port]; } +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead. + */ +static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortMaskedRead(base, port); +} + /*@}*/ #if defined(__cplusplus) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c index ad519e4108..8f647983d4 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -159,10 +163,23 @@ static uint32_t I2C_PendingStatusWait(I2C_Type *base) { uint32_t status; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif + do { status = I2C_GetStatusFlags(base); +#if I2C_WAIT_TIMEOUT + } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); +#endif /* Clear controller state. */ I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); @@ -172,7 +189,12 @@ static uint32_t I2C_PendingStatusWait(I2C_Type *base) status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) { - I2C_PendingStatusWait(base); + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Write Address and RW bit to data register */ base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); @@ -184,7 +206,12 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct status_t I2C_MasterStop(I2C_Type *base) { - I2C_PendingStatusWait(base); + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; return kStatus_Success; @@ -204,6 +231,10 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi while (txSize) { status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } if (status & I2C_STAT_MSTARBLOSS_MASK) { @@ -245,6 +276,11 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) { if (!(flags & kI2C_TransferNoStopFlag)) @@ -252,6 +288,10 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi /* Initiate stop */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } @@ -282,6 +322,10 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin while (rxSize) { status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) { @@ -305,6 +349,10 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin /* initiate NAK and stop */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } break; @@ -483,7 +531,7 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, return kStatus_Success; } -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) { uint32_t status; uint32_t master_state; @@ -495,6 +543,10 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) /* Wait until module is ready */ status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Get the state of the I2C module */ master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; @@ -505,12 +557,17 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; /* Wait until the STOP is completed */ - I2C_PendingStatusWait(base); + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* Reset handle. */ handle->state = kIdleState; } + return kStatus_Success; } /*! @@ -842,10 +899,22 @@ static uint32_t I2C_SlavePollPending(I2C_Type *base) { uint32_t stat; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif do { stat = base->STAT; +#if I2C_WAIT_TIMEOUT + } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); + + if (waitTimes == 0u) + { + return kStatus_I2C_Timeout; + } +#else } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif return stat; } @@ -1099,6 +1168,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Get slave machine state */ slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); @@ -1118,6 +1191,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* send bytes up to txSize */ @@ -1145,6 +1222,10 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } @@ -1163,6 +1244,10 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } /* Get slave machine state */ slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); @@ -1182,6 +1267,10 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } /* receive bytes up to rxSize */ @@ -1209,6 +1298,10 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h index bda2d815f5..38e7da091a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -49,10 +53,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2C driver version 1.0.0. */ -#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief I2C driver version 2.0.1. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ +/*! @brief Timeout times for waiting flag. */ +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + /* definitions for MSTCODE bits in I2C Status register STAT */ #define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ #define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ @@ -77,10 +86,11 @@ enum _i2c_status kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ }; /*! @} */ @@ -98,8 +108,10 @@ enum _i2c_status enum _i2c_master_flags { kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ }; /*! @brief Direction of master and slave transfers. */ @@ -215,19 +227,21 @@ struct _i2c_master_handle * @{ */ - /*! - * @brief I2C slave peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ +/*! +* @brief I2C slave peripheral flags. +* +* @note These enums are meant to be OR'd together to form a bit mask. +*/ enum _i2c_slave_flags { kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ + kI2C_SlaveNotStretching = + I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ + kI2C_SaveDeselected = + I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ }; - + /*! @brief I2C slave address register. */ typedef enum _i2c_slave_address_register { @@ -621,7 +635,8 @@ static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, * @param base The I2C peripheral base address. * @param txBuff The pointer to the data to be transferred. * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag * @retval kStatus_Success Data was sent successfully. * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. @@ -635,7 +650,8 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi * @param base The I2C peripheral base address. * @param rxBuff The pointer to the data to be transferred. * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag * @retval kStatus_Success Data was received successfully. * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. @@ -712,9 +728,9 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, * @param base The I2C peripheral base address. * @param handle Pointer to the I2C master driver handle. * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); /*@}*/ @@ -786,7 +802,8 @@ status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, ui * This function writes new value to Slave Address register. * * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. * @param address The slave address to be stored to the address register for matching. * @param addressDisable Disable matching of the specified address register. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c index 17c0f3f509..22107e1af3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -316,7 +320,7 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - + DMA_StartTransfer(handle->dmaHandle); handle->remainingSubaddr = 0; if (transfer->dataSize) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h index 794e8ec0ba..ce7cb02a93 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c index 878f71e721..49c14fbe27 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h index d7bc3e1ba5..c79ff596ac 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c index 6501b16961..d07e33b652 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h index 72a39e4da6..8ac7bcac7b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,21 +50,6 @@ * @{ */ -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - /*! @brief Members not to be accessed / modified outside of the driver. */ typedef struct _i2s_dma_handle i2s_dma_handle_t; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c index 923585174b..2d2eab76e3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h index 3d298558bc..9a6bf6c018 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h index 1c8cf76343..be1453b6d6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h @@ -1,9 +1,13 @@ /* - * Copyright (c) 2013-2016, NXP Semiconductors. + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -90,8 +95,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_a = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_b = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), /*!< Pin Interrupt. */ kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), @@ -163,18 +168,18 @@ typedef enum _inputmux_connection_t kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h index f175e95902..860639c944 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -64,75 +68,76 @@ typedef struct _iocon_group * @brief IOCON function and mode selection definitions * @note See the User Manual for specific modes and functions supported by the various pins. */ - #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4) - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ - #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ - #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ - #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ - #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ - #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ - #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ - #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ - #define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 6) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #else - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) \ - ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #endif #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c index b3358a59a8..946e4bb2e7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -149,8 +153,8 @@ static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_ if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) || ((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) || ((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) || - ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) || - ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) || + ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 6U)) || + ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 6U)) || ((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U))) { return false; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h index 882038a5bf..57b5203f5a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -102,7 +106,7 @@ typedef enum _lcdc_display kLCDC_DisplayDualMonoSTN4Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */ kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK | - LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (8-bit bus interface). */ + LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (8-bit bus interface). */ kLCDC_DisplaySingleColorSTN8Bit = 0U, /*!< Single-panel color STN (8-bit bus interface). */ kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */ } lcdc_display_t; @@ -137,9 +141,9 @@ typedef struct _lcdc_config uint8_t lineEndDelay; /*!< The panel clocks between the last pixel of line and the start of line end. */ uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */ uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */ - lcdc_bpp_t bpp; /*!< LCD bits per pixel. */ + lcdc_bpp_t bpp; /*!< LCD bits per pixel. */ lcdc_data_format_t dataFormat; /*!< Data format. */ - bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */ + bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */ lcdc_display_t display; /*!< The display type. */ } lcdc_config_t; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c index 45b3059fe9..ad657ff497 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -835,6 +839,11 @@ void CAN0_IRQ0_DriverIRQHandler(void) assert(s_mcanHandle[0]); s_mcanIsr(CAN0, s_mcanHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void CAN0_IRQ1_DriverIRQHandler(void) @@ -842,6 +851,11 @@ void CAN0_IRQ1_DriverIRQHandler(void) assert(s_mcanHandle[0]); s_mcanIsr(CAN0, s_mcanHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -851,6 +865,11 @@ void CAN1_IRQ0_DriverIRQHandler(void) assert(s_mcanHandle[1]); s_mcanIsr(CAN1, s_mcanHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } void CAN1_IRQ1_DriverIRQHandler(void) @@ -858,5 +877,10 @@ void CAN1_IRQ1_DriverIRQHandler(void) assert(s_mcanHandle[1]); s_mcanIsr(CAN1, s_mcanHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h index 4a8a4bd727..07c17b8d98 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -43,8 +47,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief MCAN driver version 2.0.0. */ -#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief MCAN driver version 2.0.1. */ +#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief MCAN transfer status. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c index cd36ab2b4a..53d7f494f1 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h index 5638bf1675..d498d61a46 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h index 45242b1632..8d77574d02 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c index 98578cb590..6dac348d00 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -88,7 +92,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) while ((idReg != PHY_CONTROL_ID1) && (delay != 0)) { PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - delay --; + delay--; } if (!delay) @@ -118,7 +122,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) do { PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®); - delay --; + delay--; } while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0)); if (!delay) @@ -180,7 +184,7 @@ status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) { #if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0) - assert(dataPtr); + assert(dataPtr); uint32_t counter; @@ -216,7 +220,7 @@ status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t * ; *dataPtr = ENET_ReadSMIData(base); #endif - return kStatus_Success; + return kStatus_Success; } status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) @@ -236,7 +240,7 @@ status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) else { *status = false; - } + } } return result; } @@ -272,7 +276,7 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t * else { /* 10M speed. */ *speed = kPHY_Speed10M; - } + } } return result; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h index 22866c65b5..763f5d3ad3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -111,7 +115,7 @@ extern "C" { * * This function initialize the SMI interface and initialize PHY. * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. * * @param base ENET peripheral base address. * @param phyAddr The PHY address. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c index f76a000fa1..7572d6f462 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -303,6 +307,13 @@ void PIN_INT0_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) @@ -317,6 +328,13 @@ void PIN_INT1_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -332,6 +350,13 @@ void PIN_INT2_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -347,6 +372,13 @@ void PIN_INT3_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -362,6 +394,13 @@ void PIN_INT4_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -377,6 +416,13 @@ void PIN_INT5_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -392,6 +438,13 @@ void PIN_INT6_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif @@ -407,5 +460,12 @@ void PIN_INT7_DriverIRQHandler(void) { s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h index ae3ce30428..43929d53d0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c index 69b53d1f60..3e0e00f547 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h index ef1a5434bd..817585c3a7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -37,6 +41,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + #define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) #define PDRCFG0 0x0U #define PDRCFG1 0x1U diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c index 07a9ed9e2f..094b01b992 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h index 95dea0a97d..7666b00f46 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,6 +51,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! * @brief Enumeration for peripheral reset control bits * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c index 23c9c9257c..f9546537d2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h index e6f5e6be86..c36ec91570 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h index f08bdc4221..0ef0bebbd3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c index 4165af84e3..8ac0dcdb04 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -215,8 +219,10 @@ void RTC_Init(RTC_Type *base) /* Make sure the reset bit is cleared */ base->CTRL &= ~RTC_CTRL_SWRESET_MASK; +#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) /* Make sure the RTC OSC is powered up */ base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; +#endif } status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h index 83c5ba8549..6735ad724c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c index 22f9d3df13..68f84ba34f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -532,4 +536,9 @@ void SCTIMER_EventHandleIRQ(SCT_Type *base) void SCT0_IRQHandler(void) { s_sctimerIsr(SCT0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h index e799e1ecef..2dc4190761 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c index e15bf9b660..561fdf1035 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -37,6 +41,25 @@ /* Typedef for interrupt handler. */ typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); +/*! @brief convert the name here, due to RM use SDIO */ +#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler +/*! @brief define the controller support sd/sdio card version 2.0 */ +#define SDIF_SUPPORT_SD_VERSION (0x20) +/*! @brief define the controller support mmc card version 4.4 */ +#define SDIF_SUPPORT_MMC_VERSION (0x44) +/*! @brief define the timeout counter */ +#define SDIF_TIMEOUT_VALUE (65535U) +/*! @brief this value can be any value */ +#define SDIF_POLL_DEMAND_VALUE (0xFFU) +/*! @brief DMA descriptor buffer1 size */ +#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU) +/*! @brief DMA descriptor buffer2 size */ +#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) +/*! @brief RX water mark value */ +#define SDIF_RX_WATERMARK (15U) +/*! @brief TX water mark value */ +#define SDIF_TX_WATERMARK (16U) + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -141,9 +164,18 @@ static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); /* * @brief handle sdio interrupt * This function will call the SDIO interrupt callback +* @param SDIF base address * @param SDIF handle */ -static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle); +static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle); + +/* +* @brief handle card detect +* This function will call the cardInserted callback +* @param SDIF base addres +* @param SDIF handle +*/ +static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle); /******************************************************************************* * Variables @@ -288,19 +320,18 @@ static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) do { status = SDIF_GetInterruptStatus(base); - if ((status & - (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u) - { - SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | kSDIF_HardwareLockError)); - return kStatus_SDIF_SendCmdFail; - } } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone); - - /* clear the command done bit */ - SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone); - - return SDIF_ReadCommandResponse(base, command); + /* clear interrupt status flag first */ + SDIF_ClearInterruptStatus(base, status); + if ((status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != + 0u) + { + return kStatus_SDIF_SendCmdFail; + } + else + { + return SDIF_ReadCommandResponse(base, command); + } } status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) @@ -675,68 +706,35 @@ bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) { - /*config the clock delay and pharse shift - *should config the clk_in_drv, - *clk_in_sample to meet the min hold and - *setup time - */ - if (target_HZ <= kSDIF_Freq400KHZ) + uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; + + if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) { - /*min hold time:5ns - * min setup time: 5ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY); - } - else if (target_HZ >= kSDIF_Freq50MHZ) - { - /* - * user need to pay attention to this parameter - * can be change the setting for you card and board - * min hold time:2ns - * min setup time: 6ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY); - /* means the input clock = 2 * card clock, - * can use clock pharse shift tech - */ if (divider == 1U) { - SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180); +#if defined(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT) && (SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT != 0U) + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT); +#endif +#if defined(SDIF_HIGHSPEED_DRV_PHASE_SHIFT) && (SDIF_HIGHSPEED_DRV_PHASE_SHIFT != 0U) + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(SDIF_HIGHSPEED_DRV_PHASE_SHIFT); +#endif } - } - else - { - /* - * user need to pay attention to this parameter - * can be change the setting for you card and board - * min hold time:5ns - * min setup time: 5ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY); - /* means the input clock = 2 * card clock, - * can use clock pharse shift tech - */ - if (divider == 1U) + else { - SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90); +#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY); +#endif +#ifdef SDIF_HIGHSPEED_DRV_DELAY + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY); +#endif } } + + SYSCON->SDIOCLKCTRL = sdioClkCtrl; } uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) @@ -1098,7 +1096,7 @@ void SDIF_TransferCreateHandle(SDIF_Type *base, handle->callback.DMADesUnavailable = callback->DMADesUnavailable; handle->callback.CommandReload = callback->CommandReload; handle->callback.TransferComplete = callback->TransferComplete; - + handle->callback.cardInserted = callback->cardInserted; handle->userData = userData; /* Save the handle in global variables to support the double weak mechanism. */ @@ -1130,26 +1128,32 @@ static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, u { assert(handle->command); - /* transfer error */ - if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); - } /* cmd buffer full, in this condition user need re-send the command */ - else if (interruptFlags & kSDIF_HardwareLockError) + if (interruptFlags & kSDIF_HardwareLockError) { if (handle->callback.CommandReload) { - handle->callback.CommandReload(); + handle->callback.CommandReload(base, handle->userData); } } - /* transfer command success */ + /* transfer command done */ else { - SDIF_ReadCommandResponse(base, handle->command); - if (((handle->data) == NULL) && (handle->callback.TransferComplete)) + if ((kSDIF_CommandDone & interruptFlags) != 0U) { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + /* transfer error */ + if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); + } + else + { + SDIF_ReadCommandResponse(base, handle->command); + if (((handle->data) == NULL) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } } } } @@ -1217,7 +1221,7 @@ static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint3 { if (handle->callback.DMADesUnavailable) { - handle->callback.DMADesUnavailable(); + handle->callback.DMADesUnavailable(base, handle->userData); } } else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) && @@ -1232,11 +1236,29 @@ static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint3 } } -static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle) +static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) { if (handle->callback.SDIOInterrupt != NULL) { - handle->callback.SDIOInterrupt(); + handle->callback.SDIOInterrupt(base, handle->userData); + } +} + +static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) +{ + if (SDIF_DetectCardInsert(base, false)) + { + if ((handle->callback.cardInserted) != NULL) + { + handle->callback.cardInserted(base, handle->userData); + } + } + else + { + if ((handle->callback.cardRemoved) != NULL) + { + handle->callback.cardRemoved(base, handle->userData); + } } } @@ -1262,12 +1284,16 @@ static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) } if (interruptFlags & kSDIF_SDIOInterrupt) { - SDIF_TransferHandleSDIOInterrupt(handle); + SDIF_TransferHandleSDIOInterrupt(base, handle); } if (dmaInterruptFlags & kSDIF_DMAAllStatus) { SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); } + if (interruptFlags & kSDIF_CardDetect) + { + SDIF_TransferHandleCardDetect(base, handle); + } SDIF_ClearInterruptStatus(base, interruptFlags); SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); @@ -1289,5 +1315,10 @@ void SDIF_DriverIRQHandler(void) assert(s_sdifHandle[0]); s_sdifIsr(SDIF, s_sdifHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h index 6b1b7e8c08..e2602c6211 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -37,40 +41,56 @@ * @{ */ -/****************************************************************************** +/********************************** * Definitions. *****************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.0.1. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @brief Driver version 2.0.4. */ +#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U)) /*@}*/ -#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */ - -#define SDIF_SUPPORT_SD_VERSION (0x20) /*!< define the controller support sd/sdio card version 2.0 */ -#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */ - -#define SDIF_TIMEOUT_VALUE (65535U) /*!< define the timeout counter */ -#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */ - -#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU) /*!< DMA descriptor buffer1 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!STATUS & SDIF_STATUS_DATA_3_STATUS_MASK; + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; } else { - return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK; + return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U; } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.c new file mode 100644 index 0000000000..63600831bd --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.c @@ -0,0 +1,489 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sha.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*!< SHA-1 and SHA-256 block size */ +#define SHA_BLOCK_SIZE 64 + +/*!< Use standard C library memcpy */ +#define sha_memcpy memcpy + +/*! Internal states of the HASH creation process */ +typedef enum _sha_algo_state +{ + kSHA_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ + kSHA_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has been + written. */ +} sha_algo_state_t; + +/*! 64-byte block represented as byte array of 16 32-bit words */ +typedef union _sha_hash_block +{ + uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ + uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ +} sha_block_t; + +/*! internal sha context structure */ +typedef struct _sha_ctx_internal +{ + sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ + size_t blksz; /*!< number of valid bytes in memory buffer */ + sha_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ + sha_algo_state_t state; /*!< finite machine state of the hash software process */ + size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ +} sha_ctx_internal_t; + +/*!< SHA-1 and SHA-256 digest length in bytes */ +enum _sha_digest_len +{ + kSHA_OutLenSha1 = 20u, + kSHA_OutLenSha256 = 32u, +}; + +/*!< macro for checking build time condition. It is used to assure the sha_ctx_internal_t can fit into sha_ctx_t */ +#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief LDM to SHA engine INDATA and ALIAS registers. + * + * This function writes 16 words starting from the src address (must be word aligned) + * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). + * Src address increments to load 16 consecutive words. + * + * @param dst peripheral register address (word aligned) + * @param src address of the input 512-bit block (16 words) (word aligned) + * + */ +__STATIC_INLINE void sha_ldm_stm_16_words(volatile uint32_t *dst, const uint32_t *src) +{ + for (int i = 0; i < 8; i++) + { + dst[i] = src[i]; + } + src += 8u; + for (int i = 0; i < 8; i++) + { + dst[i] = src[i]; + } +} + +/*! + * @brief Swap bytes withing 32-bit word. + * + * This function changes endianess of a 32-bit word. + * + * @param in 32-bit unsigned integer + * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). + */ +static uint32_t swap_bytes(uint32_t in) +{ + return (((in & 0x000000ffu) << 24) | ((in & 0x0000ff00u) << 8) | ((in & 0x00ff0000u) >> 8) | + ((in & 0xff000000u) >> 24)); +} + +/*! + * @brief Check validity of algoritm. + * + * This function checks the validity of input argument. + * + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t sha_check_input_alg(sha_algo_t algo) +{ + if ((algo != kSHA_Sha1) && (algo != kSHA_Sha256)) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Check validity of input arguments. + * + * This function checks the validity of input arguments. + * + * @param base SHA peripheral base address. + * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t sha_check_input_args(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo) +{ + /* Check validity of input algorithm */ + if (kStatus_Success != sha_check_input_alg(algo)) + { + return kStatus_InvalidArgument; + } + + if ((NULL == ctx) || (NULL == base)) + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of internal software context. + * + * This function checks if the internal context structure looks correct. + * + * @param ctxInternal Internal context. + * @param message Input message address. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t sha_check_context(sha_ctx_internal_t *ctxInternal, const uint8_t *message) +{ + if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != sha_check_input_alg(ctxInternal->algo))) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Initialize the SHA engine for new hash. + * + * This function sets NEW and MODE fields in SHA Control register to start new hash. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + */ +static void sha_engine_init(SHA_Type *base, sha_ctx_internal_t *ctxInternal) +{ + uint32_t shaCtrl; + + if (kSHA_Sha1 == ctxInternal->algo) + { + shaCtrl = SHA_CTRL_MODE(1) | SHA_CTRL_NEW(1); + } + else + { + shaCtrl = SHA_CTRL_MODE(2) | SHA_CTRL_NEW(1); + } + base->CTRL = shaCtrl; +} + +/*! + * @brief Load 512-bit block (16 words) into SHA engine. + * + * This function aligns the input block and moves it into SHA engine INDATA. + * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. + * + * @param base SHA peripheral base address. + * @param blk 512-bit block + */ +static void sha_one_block(SHA_Type *base, const uint8_t *blk) +{ + uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; + const uint32_t *actBlk; + + /* make sure the 512-bit block is word aligned */ + if ((uintptr_t)blk & 0x3u) + { + sha_memcpy(temp, blk, SHA_BLOCK_SIZE); + actBlk = (const uint32_t *)(uintptr_t)temp; + } + else + { + actBlk = (const uint32_t *)(uintptr_t)blk; + } + + /* poll waiting. */ + while (0 == (base->STATUS & SHA_STATUS_WAITING_MASK)) + { + } + /* feed INDATA (and ALIASes). use STM instruction. */ + sha_ldm_stm_16_words(&base->INDATA, actBlk); +} + +/*! + * @brief Adds message to current hash. + * + * This function merges the message to fill the internal buffer, empties the internal buffer if + * it becomes full, then process all remaining message data. + * + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @param message Input message. + * @param messageSize Size of input message in bytes. + * @return kStatus_Success. + */ +static status_t sha_process_message_data(SHA_Type *base, + sha_ctx_internal_t *ctxInternal, + const uint8_t *message, + size_t messageSize) +{ + /* first fill the internal buffer to full block */ + size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; + sha_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + message += toCopy; + messageSize -= toCopy; + + /* process full internal block */ + sha_one_block(base, &ctxInternal->blk.b[0]); + + /* process all full blocks in message[] */ + while (messageSize >= SHA_BLOCK_SIZE) + { + sha_one_block(base, message); + message += SHA_BLOCK_SIZE; + messageSize -= SHA_BLOCK_SIZE; + } + + /* copy last incomplete message bytes into internal block */ + sha_memcpy(&ctxInternal->blk.b[0], message, messageSize); + ctxInternal->blksz = messageSize; + return kStatus_Success; +} + +/*! + * @brief Finalize the running hash to make digest. + * + * This function empties the internal buffer, adds padding bits, and generates final digest. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @return kStatus_Success. + */ +static status_t sha_finalize(SHA_Type *base, sha_ctx_internal_t *ctxInternal) +{ + sha_block_t lastBlock; + + memset(&lastBlock, 0, sizeof(sha_block_t)); + + /* this is last call, so need to flush buffered message bytes along with padding */ + if (ctxInternal->blksz <= 55u) + { + /* last data is 440 bits or less. */ + sha_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); + lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; + lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + sha_one_block(base, &lastBlock.b[0]); + } + else + { + if (ctxInternal->blksz < SHA_BLOCK_SIZE) + { + ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; + for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) + { + ctxInternal->blk.b[i] = 0; + } + } + else + { + lastBlock.b[0] = (uint8_t)0x80U; + } + + sha_one_block(base, &ctxInternal->blk.b[0]); + lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + sha_one_block(base, &lastBlock.b[0]); + } + /* poll wait for final digest */ + while (0 == (base->STATUS & SHA_STATUS_DIGEST_MASK)) + { + } + return kStatus_Success; +} + +/*! + * @brief Read DIGEST registers. + * + * This function copies DIGEST to output buffer. + * + * @param base SHA peripheral base address. + * @param[out] output Output buffer. + * @param Number of bytes to copy. + * @return kStatus_Success. + */ +static void sha_get_digest(SHA_Type *base, uint8_t *output, size_t outputSize) +{ + uint32_t digest[8]; + + for (int i = 0; i < 8; i++) + { + digest[i] = swap_bytes(base->DIGEST[i]); + } + + if (outputSize > sizeof(digest)) + { + outputSize = sizeof(digest); + } + sha_memcpy(output, digest, outputSize); +} + +status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo) +{ + status_t status; + + sha_ctx_internal_t *ctxInternal; + /* compile time check for the correct structure size */ + BUILD_ASSERT(sizeof(sha_ctx_t) >= sizeof(sha_ctx_internal_t), sha_ctx_t_size); + uint32_t i; + + status = sha_check_input_args(base, ctx, algo); + if (status != kStatus_Success) + { + return status; + } + + /* set algorithm in context struct for later use */ + ctxInternal = (sha_ctx_internal_t *)ctx; + ctxInternal->algo = algo; + ctxInternal->blksz = 0u; + for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) + { + ctxInternal->blk.w[0] = 0u; + } + ctxInternal->state = kSHA_HashInit; + ctxInternal->fullMessageSize = 0; + return status; +} + +status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize) +{ + bool isUpdateState; + status_t status; + sha_ctx_internal_t *ctxInternal; + size_t blockSize; + + if (messageSize == 0) + { + return kStatus_Success; + } + + ctxInternal = (sha_ctx_internal_t *)ctx; + status = sha_check_context(ctxInternal, message); + if (kStatus_Success != status) + { + return status; + } + + ctxInternal->fullMessageSize += messageSize; + blockSize = SHA_BLOCK_SIZE; + /* if we are still less than 64 bytes, keep only in context */ + if ((ctxInternal->blksz + messageSize) <= blockSize) + { + sha_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, message, messageSize); + ctxInternal->blksz += messageSize; + return status; + } + else + { + isUpdateState = ctxInternal->state == kSHA_HashUpdate; + if (!isUpdateState) + { + /* start NEW hash */ + sha_engine_init(base, ctxInternal); + ctxInternal->state = kSHA_HashUpdate; + } + } + + /* process message data */ + status = sha_process_message_data(base, ctxInternal, message, messageSize); + return status; +} + +status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize) +{ + size_t algOutSize = 0; + status_t status; + sha_ctx_internal_t *ctxInternal; + uint32_t *ctxW; + uint32_t i; + + ctxInternal = (sha_ctx_internal_t *)ctx; + status = sha_check_context(ctxInternal, output); + if (kStatus_Success != status) + { + return status; + } + + if (ctxInternal->state == kSHA_HashInit) + { + sha_engine_init(base, ctxInternal); + } + + size_t outSize = 0u; + + /* compute algorithm output length */ + switch (ctxInternal->algo) + { + case kSHA_Sha1: + outSize = kSHA_OutLenSha1; + break; + case kSHA_Sha256: + outSize = kSHA_OutLenSha256; + break; + default: + break; + } + algOutSize = outSize; + + /* flush message last incomplete block, if there is any, and add padding bits */ + status = sha_finalize(base, ctxInternal); + + if (outputSize) + { + if (algOutSize < *outputSize) + { + *outputSize = algOutSize; + } + else + { + algOutSize = *outputSize; + } + } + + sha_get_digest(base, &output[0], algOutSize); + + ctxW = (uint32_t *)ctx; + for (i = 0; i < SHA_CTX_SIZE; i++) + { + ctxW[i] = 0u; + } + return status; +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.h new file mode 100644 index 0000000000..d8b46df490 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.h @@ -0,0 +1,145 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SHA_H_ +#define _FSL_SHA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sha + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines LPC SHA driver version 2.0.0. + * + * Change log: + * - Version 2.0.0 + * - initial version + */ +#define FSL_SHA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! Supported cryptographic block cipher functions for HASH creation */ +typedef enum _sha_algo_t +{ + kSHA_Sha1, /*!< SHA_1 */ + kSHA_Sha256, /*!< SHA_256 */ +} sha_algo_t; + +/*! @brief SHA Context size. */ +#define SHA_CTX_SIZE 20 + +/*! @brief Storage type used to save hash context. */ +typedef struct _sha_ctx_t +{ + uint32_t x[SHA_CTX_SIZE]; +} sha_ctx_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SHA Functional Operation + * @{ + */ + +/*! + * @addtogroup sha_algorithm_level_api + * @{ + */ +/*! +* @brief Initialize HASH context +* +* This function initializes new hash context. +* +* @param base SHA peripheral base address +* @param[out] ctx Output hash context +* @param algo Underlaying algorithm to use for hash computation. Either SHA-1 or SHA-256. +* @return Status of initialization +*/ +status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo); + +/*! + * @brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. + * + * @param base SHA peripheral base address + * @param[in,out] ctx HASH context + * @param message Input message + * @param messageSize Size of input message in bytes + * @return Status of the hash update operation + */ +status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize); + +/*! + * @brief Finalize hashing + * + * Outputs the final hash and erases the context. SHA-1 or SHA-256 padding bits are automatically added by this + * function. + * + * @param base SHA peripheral base address + * @param[in,out] ctx HASH context + * @param[out] output Output hash data + * @param[in,out] outputSize On input, determines the size of bytes of the output array. On output, tells how many bytes + * have been written to output. + * @return Status of the hash finish operation + */ +status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize); +/*! + *@} + */ /* sha_algorithm_level_api */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ +/*! @}*/ /* end of group sha */ + +#endif /* _FSL_SHA_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c index c205e95a07..1f1a4589df 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -41,6 +45,7 @@ * range <0,15>. Range <8,15> represents 2B transfer */ #define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) #define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) /******************************************************************************* * Variables @@ -54,6 +59,8 @@ static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS /*! @brief IRQ name array */ static const IRQn_Type s_spiIRQ[] = SPI_IRQS; +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; /******************************************************************************* * Code ******************************************************************************/ @@ -75,6 +82,12 @@ uint32_t SPI_GetInstance(SPI_Type *base) return 0; } +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + void *SPI_GetConfig(SPI_Type *base) { int32_t instance; @@ -100,6 +113,11 @@ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) config->sselNum = kSPI_Ssel0; config->txWatermark = kSPI_TxFifo0; config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; } status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) @@ -134,7 +152,8 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 /* configure SPI mode */ tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK); + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); /* phase */ tmp |= SPI_CFG_CPHA(config->phase); /* polarity */ @@ -145,6 +164,8 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 tmp |= SPI_CFG_MASTER(1); /* loopback */ tmp |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); base->CFG = tmp; /* store configuration */ @@ -161,6 +182,11 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 /* set FIFOTRIG */ base->FIFOTRIG = tmp; + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + SPI_Enable(base, config->enableMaster); return kStatus_Success; } @@ -176,6 +202,7 @@ void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) config->dataWidth = kSPI_Data8Bits; config->txWatermark = kSPI_TxFifo0; config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; } status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) @@ -201,13 +228,16 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) /* configure SPI mode */ tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK); + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | + SPI_SSELPOL_MASK); /* phase */ tmp |= SPI_CFG_CPHA(config->phase); /* polarity */ tmp |= SPI_CFG_CPOL(config->polarity); /* direction */ tmp |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); base->CFG = tmp; /* store configuration */ @@ -223,6 +253,8 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) /* set FIFOTRIG */ base->FIFOTRIG = tmp; + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + SPI_Enable(base, config->enableSlave); return kStatus_Success; } @@ -402,10 +434,10 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); /* set width of data - range asserted at entry */ tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* end of transfer */ last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* last index of loop */ while (txRemainingBytes || rxRemainingBytes || toReceiveCount) { @@ -450,7 +482,7 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) } else { - tmp32 = SPI_DUMMYDATA; + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); /* last transfer */ if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) { @@ -513,6 +545,118 @@ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *hand return kStatus_Success; } +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) { assert(NULL != handle); @@ -552,6 +696,8 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; bool loopContinue; uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); /* check params */ assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); @@ -561,10 +707,10 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); /* set width of data */ tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; /* end of transfer */ last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; do { loopContinue = false; @@ -619,7 +765,7 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h } else { - tmp32 = SPI_DUMMYDATA; + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); /* last transfer */ if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h index e444774a7b..37eafa1d51 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -46,11 +50,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief USART driver version 2.0.0. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief SPI driver version 2.0.1. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ -#define SPI_DUMMYDATA (0xFFFF) +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + #define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) #define SPI_CTRLMASK (0xFFFF0000) @@ -64,25 +72,29 @@ #define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) /*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option { +typedef enum _spi_xfer_option +{ kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */ kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */ } spi_xfer_option_t; /*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction { +typedef enum _spi_shift_direction +{ kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ } spi_shift_direction_t; /*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity { +typedef enum _spi_clock_polarity +{ kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ } spi_clock_polarity_t; /*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase { +typedef enum _spi_clock_phase +{ kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first * cycle of a data transfer. */ kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the @@ -90,7 +102,8 @@ typedef enum _spi_clock_phase { } spi_clock_phase_t; /*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark { +typedef enum _spi_txfifo_watermark +{ kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ @@ -102,7 +115,8 @@ typedef enum _spi_txfifo_watermark { } spi_txfifo_watermark_t; /*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark { +typedef enum _spi_rxfifo_watermark +{ kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ @@ -114,7 +128,8 @@ typedef enum _spi_rxfifo_watermark { } spi_rxfifo_watermark_t; /*! @brief Transfer data width */ -typedef enum _spi_data_width { +typedef enum _spi_data_width +{ kSPI_Data4Bits = 3, /*!< 4 bits data width */ kSPI_Data5Bits = 4, /*!< 5 bits data width */ kSPI_Data6Bits = 5, /*!< 6 bits data width */ @@ -131,13 +146,41 @@ typedef enum _spi_data_width { } spi_data_width_t; /*! @brief Slave select */ -typedef enum _spi_ssel { +typedef enum _spi_ssel +{ kSPI_Ssel0 = 0, /*!< Slave select 0 */ kSPI_Ssel1 = 1, /*!< Slave select 1 */ kSPI_Ssel2 = 2, /*!< Slave select 2 */ kSPI_Ssel3 = 3, /*!< Slave select 3 */ } spi_ssel_t; +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + /*! @brief SPI master user configure structure.*/ typedef struct _spi_master_config { @@ -149,8 +192,10 @@ typedef struct _spi_master_config uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ spi_data_width_t dataWidth; /*!< Width of the data */ spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ } spi_master_config_t; /*! @brief SPI slave user configure structure.*/ @@ -161,6 +206,7 @@ typedef struct _spi_slave_config spi_clock_phase_t phase; /*!< Clock phase */ spi_shift_direction_t direction; /*!< MSB or LSB */ spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ } spi_slave_config_t; @@ -200,6 +246,19 @@ typedef struct _spi_transfer size_t dataSize; /*!< Transfer bytes */ } spi_transfer_t; +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + /*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ typedef struct _spi_config { @@ -468,6 +527,28 @@ static inline uint32_t SPI_ReadData(SPI_Type *base) return base->FIFORD; } +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + /*! @} */ /*! @@ -513,6 +594,36 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); */ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + /*! * @brief Gets the master transfer count. * @@ -591,7 +702,7 @@ static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_ha */ static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) { - return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count); + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); } /*! @@ -604,7 +715,7 @@ static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handl */ static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) { - SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle); + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); } /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c index 4ac9007952..f02e4d0519 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -97,10 +101,13 @@ __attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_S #if defined(__ICCARM__) #pragma data_alignment = 4 static uint16_t s_rxDummy; +static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT]; #elif defined(__CC_ARM) __attribute__((aligned(4))) static uint16_t s_rxDummy; +__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT]; #elif defined(__GNUC__) __attribute__((aligned(4))) static uint16_t s_rxDummy; +__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT]; #endif #if defined(__ICCARM__) @@ -112,6 +119,8 @@ __attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_ __attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0}; #endif +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; /******************************************************************************* * Code ******************************************************************************/ @@ -129,31 +138,31 @@ static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); } -static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl) +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) { - assert(!(fifo == NULL)); - if (fifo == NULL) + if (config->dataWidth > kSPI_Data8Bits) { - return; + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); } - /* CS deassert and CS delay are relevant only for last word */ - uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK)); - uint32_t i = 0; - for (; i + 1 < count; i++) + else { - fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U); - } - if (i < count) - { - fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U); + *txLastWord = xfer->txData[xfer->dataSize - 1]; } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); } -static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) { - *dummy = SPI_DUMMYDATA; - XferToFifoWR(xfer, dummy); - SpiConfigToFifoWR(spi_config_p, dummy); + uint32_t instance = SPI_GetInstance(base); + dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (uint32_t)(~kSPI_FrameAssert); } status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, @@ -212,21 +221,10 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra { return kStatus_InvalidArgument; } - /* txData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))); - if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* rxData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))); - if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* byte size is zero or not aligned to sizeof(uint32_t) */ - assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))); - if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))) + + /* Byte size is zero. */ + assert(!(xfer->dataSize == 0)); + if (xfer->dataSize == 0) { return kStatus_InvalidArgument; } @@ -256,13 +254,15 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra SPI_EnableRxDMA(base, true); if (xfer->rxData) { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); + DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); } else { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize, - kDMA_StaticToStatic, NULL); + DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); } DMA_SubmitTransfer(handle->rxHandle, &xferConfig); handle->rxInProgress = true; @@ -270,21 +270,21 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra /* transmit */ SPI_EnableTxDMA(base, true); + + if (xfer->configFlags & kSPI_FrameAssert) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + if (xfer->txData) { - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); - PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp); - DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - else - { - if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t))) + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) { - dma_xfercfg_t tmp_xfercfg = { 0 }; + dma_xfercfg_t tmp_xfercfg = {0}; tmp_xfercfg.valid = true; tmp_xfercfg.swtrig = true; tmp_xfercfg.intA = true; @@ -292,17 +292,16 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra tmp_xfercfg.srcInc = 0; tmp_xfercfg.dstInc = 0; tmp_xfercfg.transferCount = 1; - /* create chained descriptor to transmit last word */ - SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p); - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)&base->FIFOWR, NULL); - /* use common API to setup first descriptor */ - SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic, - &s_spi_descriptor_table[instance]); - /* disable interrupts for first descriptor - * to avoid calling callback twice */ + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + (void *)&base->FIFOWR, NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ xferConfig.xfercfg.intA = false; xferConfig.xfercfg.intB = false; result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); @@ -313,9 +312,52 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra } else { - SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize, kDMA_StaticToStatic, NULL); + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (uint32_t *)&base->FIFOWR, NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); if (result != kStatus_Success) { @@ -323,13 +365,89 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra } } } + handle->txInProgress = true; + tmp = 0; + XferToFifoWR(xfer, &tmp); + SpiConfigToFifoWR(spi_config_p, &tmp); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmp &= (uint32_t)(~kSPI_FrameAssert); + *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U); + } + DMA_StartTransfer(handle->txHandle); } return result; } +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) { spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h index d4bdf8b16c..37f9bde8e5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -111,6 +115,21 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, */ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + /*! * @brief Initialize the SPI slave DMA handle. * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c index 60176a2c9c..a3469218bb 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -87,7 +91,7 @@ void SPIFI_GetDefaultConfig(spifi_config_t *config) config->disableCachePrefech = false; config->isFeedbackClock = true; config->spiMode = kSPIFI_SPISckLow; - config->isReadFullClockCycle = false; + config->isReadFullClockCycle = true; config->dualMode = kSPIFI_QuadMode; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h index 39890b9fe5..f6ce803206 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c index 6fcafb2136..0dedcae27e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h index 89b3a09b6a..3e95162581 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c index 7e276d3091..91c3d1cc08 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -71,7 +75,7 @@ uint32_t USART_GetInstance(USART_Type *base) return 0; } -static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) { size_t size; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h index 3fea97e6ec..fd1f3423f0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -366,7 +370,19 @@ static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) */ static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) { - base->FIFOINTENSET = ~(mask & 0xF); + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; } /*! @@ -540,6 +556,14 @@ void USART_TransferStartRingBuffer(USART_Type *base, */ void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + /*! * @brief Aborts the interrupt-driven data transmit. * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c index 129419eace..f9f0986cf0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h index e28692cf3f..46137ba214 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c index b1b208e856..42b33ee4dc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -139,17 +143,32 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) void UTICK0_DriverIRQHandler(void) { s_utickIsr(UTICK0, s_utickHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if defined(UTICK1) void UTICK1_DriverIRQHandler(void) { s_utickIsr(UTICK1, s_utickHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif #if defined(UTICK2) void UTICK2_DriverIRQHandler(void) { s_utickIsr(UTICK2, s_utickHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h index 6aa617d933..3d674f05cc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c index 43c44de667..ef64264908 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h index 02916aa2f2..651f482957 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE From d1e6e8f1281f584de40a685326ec1b70302d457e Mon Sep 17 00:00:00 2001 From: adustm Date: Fri, 23 Feb 2018 17:40:09 +0100 Subject: [PATCH 19/42] Allow jenkins script to pass --- targets/TARGET_STM/mbed_rtx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index 8ef789369d..b405a29d3d 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -119,7 +119,7 @@ #endif #endif // INITIAL_SP -#if (defined(__GNUC__) && !defined(__CC_ARM)) +#if (defined(__GNUC__) && !defined(__CC_ARM) && defined(TWO_RAM_REGIONS)) extern uint32_t __StackLimit[]; extern uint32_t __StackTop[]; extern uint32_t __end__[]; From 56bc7fb391c15bcf67d9ab8c0eda3186643eadbf Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 26 Feb 2018 11:33:17 +0000 Subject: [PATCH 20/42] Platform: Improve mbed_sleep.h * Qualify inclusion of sleep_api.h * use standard `inline` qualification instead of the non standard `__INLINE` --- platform/mbed_sleep.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/mbed_sleep.h b/platform/mbed_sleep.h index 23fa5150f4..7473135681 100644 --- a/platform/mbed_sleep.h +++ b/platform/mbed_sleep.h @@ -24,7 +24,7 @@ #ifndef MBED_SLEEP_H #define MBED_SLEEP_H -#include "sleep_api.h" +#include "hal/sleep_api.h" #include "mbed_toolchain.h" #include @@ -128,7 +128,7 @@ void sleep_manager_sleep_auto(void); * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be * able to access the LocalFileSystem */ -__INLINE static void sleep(void) +static inline void sleep(void) { #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) #if DEVICE_SLEEP @@ -158,7 +158,7 @@ __INLINE static void sleep(void) */ MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()") -__INLINE static void deepsleep(void) +static inline void deepsleep(void) { #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) #if DEVICE_SLEEP From 2fe32236126168076e6aeff8ecd3a6d79ce35bf3 Mon Sep 17 00:00:00 2001 From: Rob Meades Date: Fri, 23 Feb 2018 11:00:12 +0000 Subject: [PATCH 21/42] Make MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP default in mbed_lib.json while ensuring that, if there is a user-specified APN, it is still used. --- .../PPPCellularInterface.cpp | 46 +++++++++++-------- .../generic_modem_driver/mbed_lib.json | 2 +- 2 files changed, 27 insertions(+), 21 deletions(-) diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp index 996e78b2d4..4d22eb2b8b 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp @@ -53,7 +53,6 @@ #endif //MBED_CONF_PPP_CELL_IFACE_AT_PARSER_TIMEOUT static bool initialized; -static bool set_credentials_api_used; static bool set_sim_pin_check_request; static bool change_pin; static device_info dev_info; @@ -257,7 +256,7 @@ PPPCellularInterface::PPPCellularInterface(FileHandle *fh, bool debug) _new_pin = NULL; _pin = NULL; _at = NULL; - _apn = "internet"; + _apn = NULL; _uname = NULL; _pwd = NULL; _fh = fh; @@ -500,16 +499,13 @@ retry_without_dual_stack: } void PPPCellularInterface::set_credentials(const char *apn, const char *uname, - const char *pwd) + const char *pwd) { _apn = apn; _uname = uname; _pwd = pwd; - set_credentials_api_used = true; } - - void PPPCellularInterface::setup_at_parser() { if (_at) { @@ -542,20 +538,15 @@ nsapi_error_t PPPCellularInterface::connect(const char *sim_pin, const char *apn return NSAPI_ERROR_PARAMETER; } - if (apn) { - _apn = apn; - } - - if (uname && pwd) { - _uname = uname; - _pwd = pwd; - } else { - _uname = NULL; - _pwd = NULL; - } - _pin = sim_pin; + if (apn) { + if (pwd && !uname) { + return NSAPI_ERROR_PARAMETER; + } + set_credentials(apn, uname, pwd); + } + return connect(); } @@ -565,7 +556,21 @@ nsapi_error_t PPPCellularInterface::connect() bool success; bool did_init = false; const char *apn_config = NULL; + bool user_specified_apn = false; + /* If the user has specified the APN then use that or, + * if we are not using the APN database, set _apn to + * "internet" as a best guess + */ + if (_apn) { + user_specified_apn = true; + } else { +#ifndef MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP + _apn = "internet"; + user_specified_apn = true; +#endif + } + if (is_connected()) { return NSAPI_ERROR_IS_CONNECTED; } else if (_connect_status == NSAPI_STATUS_CONNECTING) { @@ -580,7 +585,6 @@ nsapi_error_t PPPCellularInterface::connect() do { retry_init: - retcode = NSAPI_ERROR_OK; /* setup AT parser */ @@ -643,7 +647,7 @@ nsapi_error_t PPPCellularInterface::connect() } #if MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP - if (apn_config) { + if (!user_specified_apn && apn_config) { _apn = _APN_GET(apn_config); _uname = _APN_GET(apn_config); _pwd = _APN_GET(apn_config); @@ -672,6 +676,8 @@ nsapi_error_t PPPCellularInterface::connect() success = _at->send("AT") && _at->recv("OK"); } + tr_info("The APN being used is %s.\n", _apn); + /* Attempt to enter data mode */ success = set_atd(_at); //enter into Data mode with the modem if (!success) { diff --git a/features/netsocket/cellular/generic_modem_driver/mbed_lib.json b/features/netsocket/cellular/generic_modem_driver/mbed_lib.json index 267aee66e2..542221e609 100644 --- a/features/netsocket/cellular/generic_modem_driver/mbed_lib.json +++ b/features/netsocket/cellular/generic_modem_driver/mbed_lib.json @@ -2,7 +2,7 @@ "name": "ppp-cell-iface", "config": { "baud-rate": 115200, - "apn-lookup": false, + "apn-lookup": true, "at-parser-buffer-size": 256, "at-parser-timeout": 8000 } From 8cc71dda75c5524adf74541f7eea8e0cd62b6547 Mon Sep 17 00:00:00 2001 From: Tamas Kaman Date: Mon, 26 Feb 2018 16:30:40 +0100 Subject: [PATCH 22/42] Build issue for M33 core Fix typo in irq_armv8mml.S Signed-off-by: Tamas Kaman --- .../rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S index 12062b6e19..3cbab2ad8b 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S @@ -27,7 +27,7 @@ .file "irq_armv8mml.S" .syntax unified -+#ifndef __DOMAIN_NS +#ifndef __DOMAIN_NS .equ __DOMAIN_NS, 0 #endif From 43bad7c0ddbfa57b705383aec52a062921f3aa5a Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Fri, 23 Feb 2018 15:56:50 -0600 Subject: [PATCH 23/42] Travis: Tore out python3 testing to get CI working again Temporary solution, python3 will be added back later Travis doesn't recognize version matrices when inside a matrix include job. Instead, it breaks in a way that isn't reported as an error. --- .travis.yml | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/.travis.yml b/.travis.yml index 9de3c6c155..2e83469542 100644 --- a/.travis.yml +++ b/.travis.yml @@ -10,7 +10,7 @@ env: --data @- << DATA\n{ "state": "$0", "description": "$1", - "context": "travis-ci/$NAME/$(python --version)", + "context": "travis-ci/$NAME", "target_url": "https://travis-ci.org/$TRAVIS_REPO_SLUG/jobs/$TRAVIS_JOB_ID" }\nDATA' @@ -74,10 +74,6 @@ matrix: - env: - NAME=tools - python: - - '2.7' - - '3.5' - - '3.6' install: # Install dependencies - sudo apt-get install gcc-arm-embedded @@ -89,7 +85,7 @@ matrix: script: # Run local testing on tools - PYTHONPATH=. coverage run -a -m pytest tools/test - - python2 tools/test/pylint.py + - python tools/test/pylint.py - coverage run -a tools/project.py -S | sed -n '/^Total/p' - coverage html after_success: @@ -199,8 +195,3 @@ matrix: env: NAME=mbed2-NUVOTON - <<: *mbed-2 env: NAME=mbed2-RENESAS - # Change python version here only because 3x the other jobs does not add any more coverage - python: - - '2.7' - - '3.5' - - '3.6' From 5a108166f02a856207c3fcee2ff07525f8920191 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Mon, 26 Feb 2018 17:04:03 -0600 Subject: [PATCH 24/42] tools: Fixed small unicode issue in config tests --- tools/test/config/invalid_key/test_data.json | 2 +- tools/test/config/invalid_key_lib/test_data.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/test/config/invalid_key/test_data.json b/tools/test/config/invalid_key/test_data.json index c86542f1aa..8c17e13f91 100644 --- a/tools/test/config/invalid_key/test_data.json +++ b/tools/test/config/invalid_key/test_data.json @@ -1,5 +1,5 @@ { "K64F": { - "exception_msg": "Additional properties are not allowed ('unknown_key' was unexpected)" + "exception_msg": "Additional properties are not allowed (u'unknown_key' was unexpected)" } } diff --git a/tools/test/config/invalid_key_lib/test_data.json b/tools/test/config/invalid_key_lib/test_data.json index c86542f1aa..8c17e13f91 100644 --- a/tools/test/config/invalid_key_lib/test_data.json +++ b/tools/test/config/invalid_key_lib/test_data.json @@ -1,5 +1,5 @@ { "K64F": { - "exception_msg": "Additional properties are not allowed ('unknown_key' was unexpected)" + "exception_msg": "Additional properties are not allowed (u'unknown_key' was unexpected)" } } From efe4600cee823029989c652b1312b3ea8a6f5e61 Mon Sep 17 00:00:00 2001 From: Shrikant Tudavekar Date: Mon, 26 Feb 2018 18:03:08 -0600 Subject: [PATCH 25/42] measure the time over a longer range --- TESTS/mbed_hal/flash/functional_tests/main.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index 0170d2255e..af101b7232 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -27,8 +27,8 @@ using namespace utest::v1; -#define TEST_CYCLES 1000000 -#define ALLOWED_DRIFT_PPM 5000 //0.5% +#define TEST_CYCLES 10000000 +#define ALLOWED_DRIFT_PPM (1000000/5000) //0.5% /* return values to be checked are documented at: @@ -269,7 +269,7 @@ void flash_buffer_alignment_test() void flash_clock_and_cache_test() { const int timer_diff_end = time_cpu_cycles(TEST_CYCLES); - const int acceptable_range = timer_diff_start / (1000000 / ALLOWED_DRIFT_PPM); + const int acceptable_range = timer_diff_start / (ALLOWED_DRIFT_PPM); TEST_ASSERT_UINT32_WITHIN(acceptable_range, timer_diff_start, timer_diff_end); } From b6ff40e94dfc67c5b63818263f196680e6b92081 Mon Sep 17 00:00:00 2001 From: cyliangtw Date: Tue, 27 Feb 2018 11:38:29 +0800 Subject: [PATCH 26/42] [M451/M480/NANO100/NUC472] Define SERIAL and I2C pin name for compatiblity --- .../TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h | 7 ++++++- .../TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h | 5 +++++ .../TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h | 7 ++++++- .../TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h | 9 +++++++-- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h index 8712c3faa8..4599c86ca9 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h @@ -104,13 +104,18 @@ typedef enum { D13 = PC_5, D14 = PE_5, D15 = PE_4, + + I2C_SCL = D15, + I2C_SDA = D14, - // FIXME: other board-specific naming + // NOTE: board-specific naming // UART naming USBTX = PA_8, USBRX = PA_9, STDIO_UART_TX = USBTX, STDIO_UART_RX = USBRX, + SERIAL_TX = USBTX, + SERIAL_RX = USBRX, // LED naming LED1 = PD_2, LED2 = PD_3, diff --git a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h index 9116c5c757..6539843296 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h @@ -105,12 +105,17 @@ typedef enum { D14 = PG_3, D15 = PG_2, + I2C_SCL = D15, + I2C_SDA = D14, + // Note: board-specific // UART naming USBTX = PD_3, USBRX = PD_2, STDIO_UART_TX = USBTX, STDIO_UART_RX = USBRX, + SERIAL_TX = USBTX, + SERIAL_RX = USBRX, // LED naming LED_RED = PH_0, LED_YELLOW = PH_1, diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h index 57661d2639..b443dabd38 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h @@ -102,13 +102,18 @@ typedef enum { D13 = PC_1, D14 = PC_8, D15 = PC_9, - + + I2C_SCL = D15, + I2C_SDA = D14, + // NOTE: other board-specific naming // UART naming USBTX = PB_1, USBRX = PB_0, STDIO_UART_TX = USBTX, STDIO_UART_RX = USBRX, + SERIAL_TX = USBTX, + SERIAL_RX = USBRX, // LED naming LED1 = PE_11, LED2 = PE_10, diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h index 4715ef11b2..4beecb4b88 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h @@ -107,13 +107,18 @@ typedef enum { D13 = PD_0, D14 = PD_12, D15 = PD_10, - - // FIXME: other board-specific naming + + I2C_SCL = D15, + I2C_SDA = D14, + + // NOTE: other board-specific naming // UART naming USBTX = PD_5, USBRX = PD_4, STDIO_UART_TX = USBTX, STDIO_UART_RX = USBRX, + SERIAL_TX = USBTX, + SERIAL_RX = USBRX, // LED naming LED1 = PD_9, LED2 = PA_4, From 45cbdc889ff1f80e257f7db1eb1146765f633336 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 26 Feb 2018 17:41:01 +0100 Subject: [PATCH 27/42] STM32 RTC : update free function - LSI specific implementation is removed - Remove RTC clock disable --- targets/TARGET_STM/rtc_api.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 76cad5d18b..2ee3782247 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -144,28 +144,8 @@ void rtc_init(void) void rtc_free(void) { -#if !MBED_CONF_TARGET_LSE_AVAILABLE - // Enable Power clock - __HAL_RCC_PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - // Disable access to Backup domain HAL_PWR_DisableBkUpAccess(); -#endif - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); } /* From 961c8da51c8b518cc9d1aa34407b127e30d02f48 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 27 Feb 2018 11:02:49 +0100 Subject: [PATCH 28/42] STM32F1 RTC : Date read after reset F1 is the only STM32 family where RTC date is not saved into registers --- targets/TARGET_STM/rtc_api.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 2ee3782247..1d04db7b88 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -189,7 +189,8 @@ So by moving it 68 years forward from 1970, it become 1969-2067 which include 19 68 is also a multiple of 4 so it let the leap year synchronized. Information about STM32F1: -32bit register is used (no BCD format) for the seconds and a software structure to store dates. +32bit register is used (no BCD format) for the seconds. +For date, there is no specific register, only a software structure. It is then not a problem to not use shifts. */ @@ -206,16 +207,25 @@ time_t rtc_read(void) HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN); HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN); +#if TARGET_STM32F1 + /* date information is null before first write procedure */ + /* set 01/01/1970 as default values */ + if (dateStruct.Year == 0) { + dateStruct.Year = 2 ; + dateStruct.Month = 1 ; + dateStruct.Date = 1 ; + } +#endif + // Setup a tm structure based on the RTC - /* tm_wday information is ignored by mktime */ + /* tm_wday information is ignored by _rtc_maketime */ + /* tm_isdst information is ignored by _rtc_maketime */ timeinfo.tm_mon = dateStruct.Month - 1; timeinfo.tm_mday = dateStruct.Date; timeinfo.tm_year = dateStruct.Year + 68; timeinfo.tm_hour = timeStruct.Hours; timeinfo.tm_min = timeStruct.Minutes; timeinfo.tm_sec = timeStruct.Seconds; - // Daylight Saving Time information is not available - timeinfo.tm_isdst = -1; // Convert to timestamp time_t t; From b0027c1e816cfdf3105c3d313ad1302a82ead2be Mon Sep 17 00:00:00 2001 From: Hugues de Valon Date: Mon, 26 Feb 2018 18:02:59 +0000 Subject: [PATCH 29/42] Fix a bug using ELF as output extension When overriding the OUTPUT_EXT variable in compilation configuration, bugs appear: * The bin variable is not None as the 'elf' string is not interned. * When that is fixed, the function returns None instead of returning the path of the ELF file. Signed-off-by: Hugues de Valon --- tools/toolchains/__init__.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index c73ca5457c..600b617f91 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -1129,8 +1129,10 @@ class mbedToolchain: mkdir(new_path) filename = name+'.'+ext + # Absolute path of the final linked file + full_path = join(tmp_path, filename) elf = join(tmp_path, name + '.elf') - bin = None if ext is 'elf' else join(tmp_path, filename) + bin = None if ext == 'elf' else full_path map = join(tmp_path, name + '.map') r.objects = sorted(set(r.objects)) @@ -1154,7 +1156,7 @@ class mbedToolchain: self.var("compile_succeded", True) self.var("binary", filename) - return bin, needed_update + return full_path, needed_update # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY From f0cc00ef3bcfa3e14fc2d1976092ea2679f7636f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tero=20J=C3=A4=C3=A4sk=C3=B6?= Date: Wed, 13 Dec 2017 13:22:11 +0200 Subject: [PATCH 30/42] nanostack-hal: add alternative critical section implementation The nanostack hal's critical section uses a mutex for mutual exclusion, which is nice for many use cases. But when one needs to use the critical section from interrupts, the RTX will have a assertion failure and panic. Add a configurable for mbed_lib, which can be used to enable a alternative version of critical section, which uses the underlying OS primitives, which disables the interrupts. Note: the default behavior is not changed, one needs to override the "nanostack-hal.critical-section-usable-from-interrupt" to have "true". Reason for this change is that there is a need for sending events using nanostack event queue from interrupt context, eg. from a socket callback. --- .../arm_hal_interrupt.c | 29 +++++++++++++++++++ .../mbed_lib.json | 4 +++ 2 files changed, 33 insertions(+) diff --git a/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c b/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c index 91485d1a14..fa13de658d 100644 --- a/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c +++ b/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c @@ -4,10 +4,25 @@ #include "arm_hal_interrupt.h" #include "arm_hal_interrupt_private.h" + +#if MBED_CONF_NANOSTACK_HAL_CRITICAL_SECTION_USABLE_FROM_INTERRUPT +#include "platform/mbed_critical.h" +#else #include "cmsis_os2.h" #include "mbed_rtos_storage.h" +#endif + #include + +// The critical section has two alternative implementations, the default which uses mutex +// as locking primitive and the optional, which will bluntly disable interrupts +// for the critical section. The mutex version will not cause issues by delaying +// interrupts, but it has a down side that it can not be used from the interrupt +// service routines. The IRQ-safe version will do the mutual exclusion by temporarily +// disabling the interrupts, so it will have effect on interrupt latency. +#if !MBED_CONF_NANOSTACK_HAL_CRITICAL_SECTION_USABLE_FROM_INTERRUPT + static uint8_t sys_irq_disable_counter; static mbed_rtos_storage_mutex_t critical_mutex; @@ -19,20 +34,34 @@ static const osMutexAttr_t critical_mutex_attr = { }; static osMutexId_t critical_mutex_id; +#endif + void platform_critical_init(void) { +#if MBED_CONF_NANOSTACK_HAL_CRITICAL_SECTION_USABLE_FROM_INTERRUPT + // nothing to do here +#else critical_mutex_id = osMutexNew(&critical_mutex_attr); MBED_ASSERT(critical_mutex_id); +#endif } void platform_enter_critical(void) { +#if MBED_CONF_NANOSTACK_HAL_CRITICAL_SECTION_USABLE_FROM_INTERRUPT + core_util_critical_section_enter(); +#else osMutexAcquire(critical_mutex_id, osWaitForever); sys_irq_disable_counter++; +#endif } void platform_exit_critical(void) { +#if MBED_CONF_NANOSTACK_HAL_CRITICAL_SECTION_USABLE_FROM_INTERRUPT + core_util_critical_section_exit(); +#else --sys_irq_disable_counter; osMutexRelease(critical_mutex_id); +#endif } diff --git a/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/mbed_lib.json b/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/mbed_lib.json index 8dfb2faec2..408bb7627f 100644 --- a/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/mbed_lib.json +++ b/features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/mbed_lib.json @@ -8,6 +8,10 @@ "event_loop_thread_stack_size": { "help": "Define event-loop thread stack size.", "value": 6144 + }, + "critical-section-usable-from-interrupt": { + "help": "Make critical section API usable from interrupt context. Else a mutex is used as locking primitive. Consult arm_hal_interrupt.c for possible side effects on interrupt latency.", + "value": false } , "event-loop-dispatch-from-application": { From b60eb1d00123b817f5ad5b93e7b72ad7237b4139 Mon Sep 17 00:00:00 2001 From: deepikabhavnani Date: Mon, 26 Feb 2018 10:59:58 -0600 Subject: [PATCH 31/42] Updated table to be const and small fixes --- drivers/MbedCRC.h | 11 ++++++++--- drivers/TableCRC.cpp | 11 ++++++----- drivers/TableCRC.h | 12 +++++++----- 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index cd9e873afa..3c2ad433d9 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -20,6 +20,13 @@ #include "drivers/TableCRC.h" #include "platform/mbed_assert.h" +/* This is invalid warning from the compiler for below section of code +if ((width < 8) && (NULL == _crc_table)) { + p_crc = (uint32_t)(p_crc << (8 - width)); +} +Compiler warns of the shift operation with width as it is width=(std::uint8_t), +but we check for ( width < 8) before performing shift, so it should not be an issue. +*/ #if defined ( __CC_ARM ) #pragma diag_suppress 62 // Shift count is negative #elif defined ( __GNUC__ ) @@ -57,7 +64,6 @@ typedef enum crc_polynomial { * @code * * #include "mbed.h" - * #include "drivers/MbedCRC.h" * * int main() { * MbedCRC ct; @@ -77,7 +83,6 @@ typedef enum crc_polynomial { * @code * * #include "mbed.h" - * #include "drivers/MbedCRC.h" * int main() { * MbedCRC ct; * @@ -263,7 +268,7 @@ private: */ uint32_t get_crc_mask(void) const { - return (width < 8 ? ((1u << 8)-1) : (uint32_t)((uint64_t)(1ull << width) - 1)); + return (width < 8 ? ((1u << 8) - 1) : (uint32_t)((uint64_t)(1ull << width) - 1)); } /** Final value of CRC is reflected diff --git a/drivers/TableCRC.cpp b/drivers/TableCRC.cpp index c3380cfd40..b63cfcaaf7 100644 --- a/drivers/TableCRC.cpp +++ b/drivers/TableCRC.cpp @@ -15,12 +15,13 @@ */ #include +#include "drivers/TableCRC.h" namespace mbed { /** \addtogroup drivers */ /** @{*/ -uint8_t Table_CRC_7Bit_SD[256] = { +extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE] = { 0x0, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee, 0x32, 0x20, 0x16, 0x4, 0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc, 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8, 0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a, @@ -39,7 +40,7 @@ uint8_t Table_CRC_7Bit_SD[256] = { 0x1c, 0xe, 0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2 }; -uint8_t Table_CRC_8bit_CCITT[256] = { +extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE] = { 0x0, 0x7, 0xe, 0x9, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, @@ -58,7 +59,7 @@ uint8_t Table_CRC_8bit_CCITT[256] = { 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 }; -uint16_t Table_CRC_16bit_CCITT[256] = { +extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE] = { 0x0, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420, 0x1401, @@ -83,7 +84,7 @@ uint16_t Table_CRC_16bit_CCITT[256] = { 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 }; -uint16_t Table_CRC_16bit_IBM[256] = { +extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE] = { 0x0, 0x8005, 0x800f, 0xa, 0x801b, 0x1e, 0x14, 0x8011, 0x8033, 0x36, 0x3c, 0x8039, 0x28, 0x802d, 0x8027, 0x22, 0x8063, 0x66, 0x6c, 0x8069, 0x78, 0x807d, 0x8077, 0x72, 0x50, 0x8055, 0x805f, 0x5a, 0x804b, 0x4e, 0x44, 0x8041, 0x80c3, 0xc6, 0xcc, 0x80c9, @@ -107,7 +108,7 @@ uint16_t Table_CRC_16bit_IBM[256] = { 0x220, 0x8225, 0x822f, 0x22a, 0x823b, 0x23e, 0x234, 0x8231, 0x8213, 0x216, 0x21c, 0x8219 }; -uint32_t Table_CRC_32bit_ANSI[256] = { +extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE] = { 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, diff --git a/drivers/TableCRC.h b/drivers/TableCRC.h index 106ad72635..224e14e532 100644 --- a/drivers/TableCRC.h +++ b/drivers/TableCRC.h @@ -23,11 +23,13 @@ namespace mbed { /** \addtogroup drivers */ /** @{*/ -extern uint8_t Table_CRC_7Bit_SD[256]; -extern uint8_t Table_CRC_8bit_CCITT[256]; -extern uint16_t Table_CRC_16bit_CCITT[256]; -extern uint16_t Table_CRC_16bit_IBM[256]; -extern uint32_t Table_CRC_32bit_ANSI[256]; +#define MBED_CRC_TABLE_SIZE 256 + +extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE]; +extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE]; +extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE]; +extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE]; +extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE]; /** @}*/ } // namespace mbed From 24bb55612779791b15be83b2d30452616575e458 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Mon, 26 Feb 2018 17:21:42 -0600 Subject: [PATCH 32/42] tools: Removed outdated (and broken) toolchain initialization test Also moved the access of build_dir into condition on secure in ARMC6 per theotherjimmy --- tools/test/toolchains/api_test.py | 7 ------- tools/toolchains/arm.py | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/tools/test/toolchains/api_test.py b/tools/test/toolchains/api_test.py index d98b1cef1b..228d6b1f08 100644 --- a/tools/test/toolchains/api_test.py +++ b/tools/test/toolchains/api_test.py @@ -15,13 +15,6 @@ from tools.toolchains import TOOLCHAIN_CLASSES, LEGACY_TOOLCHAIN_NAMES,\ Resources, TOOLCHAIN_PATHS, mbedToolchain from tools.targets import TARGET_MAP -def test_instantiation(): - """Test that all exported toolchain may be instantiated""" - for name, tc_class in TOOLCHAIN_CLASSES.items(): - cls = tc_class(TARGET_MAP["K64F"]) - assert name == cls.name or\ - name == LEGACY_TOOLCHAIN_NAMES[cls.name] - ALPHABET = [char for char in printable if char not in [u'.', u'/']] @given(fixed_dictionaries({ diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 39ea318210..2df0bfac10 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -309,7 +309,6 @@ class ARMC6(ARM_STD): raise NotSupportedException( "this compiler does not support the core %s" % target.core) - build_dir = kwargs['build_dir'] if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)): raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build") @@ -349,6 +348,7 @@ class ARMC6(ARM_STD): # Create Secure library if target.core == "Cortex-M23" or self.target.core == "Cortex-M33": + build_dir = kwargs['build_dir'] secure_file = join(build_dir, "cmse_lib.o") self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file] From 668f4d316a03574c2121c6dc9a10e8ca55453a12 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 27 Feb 2018 15:40:24 +0000 Subject: [PATCH 33/42] pull request: add required info Please use these 2 sections for describing a pull request. They should be part of every pull request. The type specifies what is expected from the pull request and when it can be released. For instance a feature pull request can't be expected to go to the patch release. Important: do not mix pull request types ! Changed also the heading type, to make it smaller. --- .github/pull_request_template.md | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 48e258a26d..80506a0647 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,11 +1,21 @@ -# Description +### Description -> Detailed changes summary | testing | dependencies -> Good example: https://os.mbed.com/docs/latest/reference/guidelines.html#workflow (Pull request template) + -# Pull request type + +### Pull request type + + - [ ] Fix - [ ] Refactor -- [ ] New Target +- [ ] New target - [ ] Feature +- [ ] Breaking change From 1054277c659394d24d92a57931bc4cd33473a34d Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Wed, 27 Sep 2017 15:47:58 +0200 Subject: [PATCH 34/42] RTOS: SysTimer: Extract RtosTimer as SysTimer RtosTimer class introduced with tickless support in #4991 had to be renamed because that name was already present in rtos namespace. --- rtos/TARGET_CORTEX/SysTimer.cpp | 112 +++++++++++++++++++++++++++ rtos/TARGET_CORTEX/SysTimer.h | 110 ++++++++++++++++++++++++++ rtos/TARGET_CORTEX/mbed_rtx_idle.cpp | 104 +------------------------ 3 files changed, 226 insertions(+), 100 deletions(-) create mode 100644 rtos/TARGET_CORTEX/SysTimer.cpp create mode 100644 rtos/TARGET_CORTEX/SysTimer.h diff --git a/rtos/TARGET_CORTEX/SysTimer.cpp b/rtos/TARGET_CORTEX/SysTimer.cpp new file mode 100644 index 0000000000..41a8a2157e --- /dev/null +++ b/rtos/TARGET_CORTEX/SysTimer.cpp @@ -0,0 +1,112 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2012 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "rtos/TARGET_CORTEX/SysTimer.h" + +#if DEVICE_LOWPOWERTIMER + +#include "hal/lp_ticker_api.h" +#include "rtx_core_cm.h" +extern "C" { +#include "rtx_lib.h" +} + +#if (defined(NO_SYSTICK)) +/** + * Return an IRQ number that can be used in the absence of SysTick + * + * @return Free IRQ number that can be used + */ +extern "C" IRQn_Type mbed_get_m0_tick_irqn(void); +#endif + +namespace rtos { +namespace internal { + +SysTimer::SysTimer() : + TimerEvent(get_lp_ticker_data()), _start_time(0), _tick(0) +{ + _start_time = ticker_read_us(_ticker_data); +#if (defined(NO_SYSTICK)) + NVIC_SetVector(mbed_get_m0_tick_irqn(), (uint32_t)SysTick_Handler); + NVIC_SetPriority(mbed_get_m0_tick_irqn(), 0xFF); /* RTOS requires lowest priority */ + NVIC_EnableIRQ(mbed_get_m0_tick_irqn()); +#else + // Ensure SysTick has the correct priority as it is still used + // to trigger software interrupts on each tick. The period does + // not matter since it will never start counting. + OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER); +#endif +} + +void SysTimer::schedule_tick(uint32_t delta) +{ + insert_absolute(_start_time + (_tick + delta) * 1000000ULL / OS_TICK_FREQ); +} + +void SysTimer::cancel_tick() +{ + remove(); +} + +uint32_t SysTimer::get_tick() +{ + return _tick & 0xFFFFFFFF; +} + +uint32_t SysTimer::update_tick() +{ + uint64_t new_tick = ticker_read_us(_ticker_data) * OS_TICK_FREQ / 1000000; + if (new_tick > _tick) { + // Don't update to the current tick. Instead, update to the + // previous tick and let the SysTick handler increment it + // to the current value. This allows scheduling restart + // successfully after the OS is resumed. + new_tick--; + } + uint32_t elapsed_ticks = new_tick - _tick; + _tick = new_tick; + return elapsed_ticks; +} + +us_timestamp_t SysTimer::get_time() +{ + return ticker_read_us(_ticker_data); +} + +SysTimer::~SysTimer() +{ +} + +void SysTimer::handler() +{ +#if (defined(NO_SYSTICK)) + NVIC_SetPendingIRQ(mbed_get_m0_tick_irqn()); +#else + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; +#endif + _tick++; +} + +} +} + +#endif diff --git a/rtos/TARGET_CORTEX/SysTimer.h b/rtos/TARGET_CORTEX/SysTimer.h new file mode 100644 index 0000000000..c902629481 --- /dev/null +++ b/rtos/TARGET_CORTEX/SysTimer.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2012 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_SYS_TIMER_H +#define MBED_SYS_TIMER_H + +#if defined(DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY) + +#include "platform/NonCopyable.h" +#include "drivers/TimerEvent.h" + +namespace rtos { +namespace internal { + +/** + * @cond RTOS_INTERNAL + * + * @addtogroup rtos + * @{ + * + * @defgroup rtos_SysTimer SysTimer class + * @{ + */ + +/** + * The SysTimer class is used exclusively by RTX idle loop in TICKLESS mode. + * + * @note SysTimer is not the part of Mbed RTOS API. + */ +class SysTimer: private mbed::TimerEvent, private mbed::NonCopyable { +public: + + SysTimer(); + virtual ~SysTimer(); + + /** + * Schedule an os tick to fire + * + * @param delta Tick to fire at relative to current tick + * + * @warning If a tick is already scheduled it needs to be cancelled first! + */ + void schedule_tick(uint32_t delta = 1); + + /** + * Prevent any scheduled ticks from triggering + */ + void cancel_tick(); + + /** Get the current tick count + * + * @return The number of ticks since timer creation. For the os_timer this + * should match RTX's tick count (the number of ticks since boot). + */ + uint32_t get_tick(); + + /** + * Update the internal tick count + * + * @return The number of ticks incremented + * + * @note Due to a scheduling issue, the number of ticks returned is decremented + * by 1 so that a handler can be called and update to the current value. + * This allows scheduling restart successfully after the OS is resumed. + */ + uint32_t update_tick(); + + /** + * Get the time + * + * @return Current time in microseconds + */ + us_timestamp_t get_time(); + +protected: + virtual void handler(); + us_timestamp_t _start_time; + uint64_t _tick; +}; + +/** + * @} + * @} + * @endcond + */ + +} +} + +#endif + +#endif diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index 23830a8f5d..c027552864 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -36,113 +36,17 @@ using namespace mbed; #ifdef MBED_TICKLESS -#if (defined(NO_SYSTICK)) -/** - * Return an IRQ number that can be used in the absence of SysTick - * - * @return Free IRQ number that can be used - */ -extern "C" IRQn_Type mbed_get_m0_tick_irqn(void); -#endif +#include "rtos/TARGET_CORTEX/SysTimer.h" -class RtosTimer : private TimerEvent { -public: - RtosTimer(): TimerEvent(get_lp_ticker_data()), _start_time(0), _tick(0) { - _start_time = ticker_read_us(_ticker_data); -#if (defined(NO_SYSTICK)) - NVIC_SetVector(mbed_get_m0_tick_irqn(), (uint32_t)SysTick_Handler); - NVIC_SetPriority(mbed_get_m0_tick_irqn(), 0xFF); /* RTOS requires lowest priority */ - NVIC_EnableIRQ(mbed_get_m0_tick_irqn()); -#else - // Ensure SysTick has the correct priority as it is still used - // to trigger software interrupts on each tick. The period does - // not matter since it will never start counting. - OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER); -#endif - }; - - /** - * Schedule an os tick to fire - * - * @param delta Tick to fire at relative to current tick - */ - void schedule_tick(uint32_t delta=1) { - insert_absolute(_start_time + (_tick + delta) * 1000000 / OS_TICK_FREQ); - } - - - /** - * Prevent any scheduled ticks from triggering - */ - void cancel_tick() { - remove(); - } - - /** - * Get the current tick count - * - * @return The number of ticks since boot. This should match RTX's tick count - */ - uint32_t get_tick() { - return _tick & 0xFFFFFFFF; - } - - /** - * Update the internal tick count - * - * @return The number of ticks incremented - */ - uint32_t update_tick() { - uint64_t new_tick = ticker_read_us(_ticker_data) * OS_TICK_FREQ / 1000000; - if (new_tick > _tick) { - // Don't update to the current tick. Instead, update to the - // previous tick and let the SysTick handler increment it - // to the current value. This allows scheduling restart - // successfully after the OS is resumed. - new_tick--; - } - uint32_t elapsed_ticks = new_tick - _tick; - _tick = new_tick; - return elapsed_ticks; - } - - /** - * Get the time - * - * @return Current time in microseconds - */ - us_timestamp_t get_time() { - return ticker_read_us(_ticker_data); - } - - ~RtosTimer() { - - }; - -protected: - - void handler() { -#if (defined(NO_SYSTICK)) - NVIC_SetPendingIRQ(mbed_get_m0_tick_irqn()); -#else - SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; -#endif - _tick++; - } - - us_timestamp_t _start_time; - uint64_t _tick; -}; - -static RtosTimer *os_timer; -static uint64_t os_timer_data[sizeof(RtosTimer) / 8]; +static rtos::internal::SysTimer *os_timer; +static uint64_t os_timer_data[sizeof(rtos::internal::SysTimer) / 8]; /// Enable System Timer. int32_t OS_Tick_Enable (void) { // Do not use SingletonPtr since this relies on the RTOS if (NULL == os_timer) { - os_timer = new (os_timer_data) RtosTimer(); + os_timer = new (os_timer_data) rtos::internal::SysTimer(); } // set to fire interrupt on next tick From d098cd6757a02a4b58411bbd7c0749d2ba02294e Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 21 Nov 2017 14:54:02 +0100 Subject: [PATCH 35/42] RTOS: SysTimer: Split methods for testing --- rtos/TARGET_CORTEX/SysTimer.cpp | 16 +++++++++++++++- rtos/TARGET_CORTEX/SysTimer.h | 7 +++++++ rtos/TARGET_CORTEX/mbed_rtx_idle.cpp | 1 + 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/rtos/TARGET_CORTEX/SysTimer.cpp b/rtos/TARGET_CORTEX/SysTimer.cpp index 41a8a2157e..3f56ac36f7 100644 --- a/rtos/TARGET_CORTEX/SysTimer.cpp +++ b/rtos/TARGET_CORTEX/SysTimer.cpp @@ -45,6 +45,10 @@ SysTimer::SysTimer() : TimerEvent(get_lp_ticker_data()), _start_time(0), _tick(0) { _start_time = ticker_read_us(_ticker_data); +} + +void SysTimer::setup_irq() +{ #if (defined(NO_SYSTICK)) NVIC_SetVector(mbed_get_m0_tick_irqn(), (uint32_t)SysTick_Handler); NVIC_SetPriority(mbed_get_m0_tick_irqn(), 0xFF); /* RTOS requires lowest priority */ @@ -96,16 +100,26 @@ SysTimer::~SysTimer() { } -void SysTimer::handler() +void SysTimer::set_irq_pending() { #if (defined(NO_SYSTICK)) NVIC_SetPendingIRQ(mbed_get_m0_tick_irqn()); #else SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; #endif +} + +void SysTimer::increment_tick() +{ _tick++; } +void SysTimer::handler() +{ + set_irq_pending(); + increment_tick(); +} + } } diff --git a/rtos/TARGET_CORTEX/SysTimer.h b/rtos/TARGET_CORTEX/SysTimer.h index c902629481..2af7c8ec33 100644 --- a/rtos/TARGET_CORTEX/SysTimer.h +++ b/rtos/TARGET_CORTEX/SysTimer.h @@ -51,6 +51,11 @@ public: SysTimer(); virtual ~SysTimer(); + /** + * Enable an IRQ/SysTick with the correct priority. + */ + static void setup_irq(); + /** * Schedule an os tick to fire * @@ -92,6 +97,8 @@ public: protected: virtual void handler(); + void increment_tick(); + static void set_irq_pending(); us_timestamp_t _start_time; uint64_t _tick; }; diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index c027552864..ac0ad4c53b 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -47,6 +47,7 @@ int32_t OS_Tick_Enable (void) // Do not use SingletonPtr since this relies on the RTOS if (NULL == os_timer) { os_timer = new (os_timer_data) rtos::internal::SysTimer(); + os_timer->setup_irq(); } // set to fire interrupt on next tick From 74e0f95cd61a2abcd44836389c0da5a9804ea77c Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 21 Nov 2017 14:54:39 +0100 Subject: [PATCH 36/42] RTOS: SysTimer: Add tests --- TESTS/mbedmicro-rtos-mbed/systimer/main.cpp | 274 ++++++++++++++++++++ 1 file changed, 274 insertions(+) create mode 100644 TESTS/mbedmicro-rtos-mbed/systimer/main.cpp diff --git a/TESTS/mbedmicro-rtos-mbed/systimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/systimer/main.cpp new file mode 100644 index 0000000000..51a85cea96 --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/systimer/main.cpp @@ -0,0 +1,274 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if !MBED_TICKLESS +#error [NOT_SUPPORTED] Tickless mode not supported for this target. +#endif + +#if !DEVICE_LOWPOWERTIMER +#error [NOT_SUPPORTED] Current SysTimer implementation requires lp ticker support. +#endif + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +extern "C" { +#include "rtx_lib.h" +} +#include "rtos/TARGET_CORTEX/SysTimer.h" + +#define TEST_TICKS 42UL +#define DELAY_DELTA_US 2500ULL + +using namespace utest::v1; + +const us_timestamp_t DELAY_US = 1000000ULL * TEST_TICKS / OS_TICK_FREQ; + +// Override the handler() -- the SysTick interrupt must not be set as pending by the test code. +class SysTimerTest: public rtos::internal::SysTimer { +private: + Semaphore _sem; + virtual void handler() + { + increment_tick(); + _sem.release(); + } + +public: + SysTimerTest() : + SysTimer(), _sem(0, 1) + { + } + + virtual ~SysTimerTest() + { + } + + int32_t sem_wait(uint32_t millisec) + { + return _sem.wait(millisec); + } +}; + +/** Test tick count is zero upon creation + * + * Given a SysTimer + * When the timer is created + * Then tick count is zero + */ +void test_created_with_zero_tick_count(void) +{ + SysTimerTest st; + TEST_ASSERT_EQUAL_UINT32(0, st.get_tick()); +} + +/** Test tick count is updated correctly + * + * Given a SysTimer + * When @a update_tick method is called immediately after creation + * Then the tick count is not updated + * When @a update_tick is called again after a delay + * Then the tick count is updated + * and the number of ticks incremented is equal TEST_TICKS - 1 + * When @a update_tick is called again without a delay + * Then the tick count is not updated + */ +void test_update_tick(void) +{ + SysTimerTest st; + TEST_ASSERT_EQUAL_UINT32(0, st.update_tick()); + TEST_ASSERT_EQUAL_UINT32(0, st.get_tick()); + us_timestamp_t test_ticks_elapsed_ts = st.get_time() + DELAY_US; + + while (st.get_time() <= test_ticks_elapsed_ts) {} + TEST_ASSERT_EQUAL_UINT32(TEST_TICKS - 1, st.update_tick()); + TEST_ASSERT_EQUAL_UINT32(TEST_TICKS - 1, st.get_tick()); + + TEST_ASSERT_EQUAL_UINT32(0, st.update_tick()); + TEST_ASSERT_EQUAL_UINT32(TEST_TICKS - 1, st.get_tick()); +} + +/** Test get_time returns correct time + * + * Given a SysTimer + * When @a get_time method is called before and after a delay + * Then time difference is equal the delay + */ +void test_get_time(void) +{ + SysTimerTest st; + us_timestamp_t t1 = st.get_time(); + + wait_us(DELAY_US); + us_timestamp_t t2 = st.get_time(); + TEST_ASSERT_UINT64_WITHIN(DELAY_DELTA_US, DELAY_US, t2 - t1); +} + +/** Test cancel_tick + * + * Given a SysTimer with a scheduled tick + * When @a cancel_tick is called before the given number of ticks elapse + * Then the handler is never called + * and the tick count is not incremented + */ +void test_cancel_tick(void) +{ + SysTimerTest st; + st.cancel_tick(); + st.schedule_tick(TEST_TICKS); + + st.cancel_tick(); + int32_t sem_slots = st.sem_wait((DELAY_US + DELAY_DELTA_US) / 1000ULL); + TEST_ASSERT_EQUAL_INT32(0, sem_slots); + TEST_ASSERT_EQUAL_UINT32(0, st.get_tick()); +} + +/** Test schedule zero + * + * Given a SysTimer + * When a tick is scheduled with delta = 0 ticks + * Then the handler is called instantly + */ +void test_schedule_zero(void) +{ + SysTimerTest st; + + st.schedule_tick(0UL); + int32_t sem_slots = st.sem_wait(0UL); + TEST_ASSERT_EQUAL_INT32(1, sem_slots); +} + +/** Test handler called once + * + * Given a SysTimer with a tick scheduled with delta = TEST_TICKS + * When the handler is called + * Then the tick count is incremented by 1 + * and elapsed time is equal 1000000ULL * TEST_TICKS / OS_TICK_FREQ; + * When more time elapses + * Then the handler is not called again + */ +void test_handler_called_once(void) +{ + SysTimerTest st; + st.schedule_tick(TEST_TICKS); + us_timestamp_t t1 = st.get_time(); + int32_t sem_slots = st.sem_wait(0); + TEST_ASSERT_EQUAL_INT32(0, sem_slots); + + sem_slots = st.sem_wait(osWaitForever); + us_timestamp_t t2 = st.get_time(); + TEST_ASSERT_EQUAL_INT32(1, sem_slots); + TEST_ASSERT_EQUAL_UINT32(1, st.get_tick()); + TEST_ASSERT_UINT64_WITHIN(DELAY_DELTA_US, DELAY_US, t2 - t1); + + sem_slots = st.sem_wait((DELAY_US + DELAY_DELTA_US) / 1000ULL); + TEST_ASSERT_EQUAL_INT32(0, sem_slots); + TEST_ASSERT_EQUAL_UINT32(1, st.get_tick()); +} + +/** Test wake up from sleep + * + * Given a SysTimer with a tick scheduled in the future + * and a core in sleep mode + * When given time elapses + * Then the uC is woken up from sleep + * and the tick handler is called + * and measured time matches requested delay + */ +void test_sleep(void) +{ + Timer timer; + SysTimerTest st; + + sleep_manager_lock_deep_sleep(); + timer.start(); + st.schedule_tick(TEST_TICKS); + + TEST_ASSERT_FALSE_MESSAGE(sleep_manager_can_deep_sleep(), "Deep sleep should be disallowed"); + while (st.sem_wait(0) != 1) { + sleep(); + } + timer.stop(); + sleep_manager_unlock_deep_sleep(); + + TEST_ASSERT_UINT64_WITHIN(DELAY_DELTA_US, DELAY_US, timer.read_high_resolution_us()); +} + +#if DEVICE_LOWPOWERTIMER +/** Test wake up from deepsleep + * + * Given a SysTimer with a tick scheduled in the future + * and a core in deepsleep mode + * When given time elapses + * Then the uC is woken up from deepsleep + * and the tick handler is called + * and measured time matches requested delay + */ +void test_deepsleep(void) +{ + /* + * Since deepsleep() may shut down the UART peripheral, we wait for 10ms + * to allow for hardware serial buffers to completely flush. + + * This should be replaced with a better function that checks if the + * hardware buffers are empty. However, such an API does not exist now, + * so we'll use the wait_ms() function for now. + */ + wait_ms(10); + + // Regular Timer might be disabled during deepsleep. + LowPowerTimer lptimer; + SysTimerTest st; + + lptimer.start(); + st.schedule_tick(TEST_TICKS); + TEST_ASSERT_TRUE_MESSAGE(sleep_manager_can_deep_sleep(), "Deep sleep should be allowed"); + while (st.sem_wait(0) != 1) { + sleep(); + } + lptimer.stop(); + + TEST_ASSERT_UINT64_WITHIN(DELAY_DELTA_US, DELAY_US, lptimer.read_high_resolution_us()); +} +#endif + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(5, "default_auto"); + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Tick count is zero upon creation", test_created_with_zero_tick_count), + Case("Tick count is updated correctly", test_update_tick), + Case("Time is updated correctly", test_get_time), + Case("Tick can be cancelled", test_cancel_tick), + Case("Schedule zero ticks", test_schedule_zero), + Case("Handler called once", test_handler_called_once), + Case("Wake up from sleep", test_sleep), +#if DEVICE_LOWPOWERTIMER + Case("Wake up from deep sleep", test_deepsleep), +#endif + +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} From d83ed63a3149639ea96163a43530bb85f63dde3a Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Thu, 9 Nov 2017 16:42:55 +0100 Subject: [PATCH 37/42] RTOS: SysTimer: Fix update_tick --- rtos/TARGET_CORTEX/SysTimer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtos/TARGET_CORTEX/SysTimer.cpp b/rtos/TARGET_CORTEX/SysTimer.cpp index 3f56ac36f7..fc2e06bc36 100644 --- a/rtos/TARGET_CORTEX/SysTimer.cpp +++ b/rtos/TARGET_CORTEX/SysTimer.cpp @@ -78,7 +78,7 @@ uint32_t SysTimer::get_tick() uint32_t SysTimer::update_tick() { - uint64_t new_tick = ticker_read_us(_ticker_data) * OS_TICK_FREQ / 1000000; + uint64_t new_tick = (ticker_read_us(_ticker_data) - _start_time) * OS_TICK_FREQ / 1000000; if (new_tick > _tick) { // Don't update to the current tick. Instead, update to the // previous tick and let the SysTick handler increment it From 4cb47df40af0026042860f01918dfa4e612d8823 Mon Sep 17 00:00:00 2001 From: Bartek Szatkowski Date: Tue, 27 Feb 2018 15:25:16 +0000 Subject: [PATCH 38/42] Add system_reset() function to Mbed OS --- drivers/CAN.cpp | 2 +- drivers/I2C.cpp | 2 +- drivers/PwmOut.h | 2 +- drivers/SPI.cpp | 2 +- drivers/SerialBase.cpp | 2 +- drivers/Ticker.h | 2 +- drivers/Timeout.h | 2 +- drivers/Timer.h | 2 +- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 2 +- hal/mbed_sleep_manager.c | 2 +- mbed.h | 2 +- platform/DeepSleepLock.h | 2 +- platform/mbed_interface.c | 3 +- platform/mbed_power_mgmt.h | 185 ++++++++++++++++++ platform/mbed_sleep.h | 177 ++--------------- platform/mbed_wait_api_rtos.cpp | 2 +- platform/sleep.h | 4 +- rtos/TARGET_CORTEX/mbed_rtx_idle.cpp | 2 +- .../TARGET_SAM_CortexM4/drivers/pmc/sleep.c | 2 +- targets/TARGET_NUVOTON/nu_timer.h | 2 +- targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c | 2 +- .../TARGET_EFM32/i2c_api.c | 2 +- .../TARGET_EFM32/pwmout_api.c | 2 +- .../TARGET_EFM32/serial_api.c | 2 +- .../TARGET_EFM32/spi_api.c | 2 +- 25 files changed, 222 insertions(+), 189 deletions(-) create mode 100644 platform/mbed_power_mgmt.h diff --git a/drivers/CAN.cpp b/drivers/CAN.cpp index b84d6082ce..a5e8e4266b 100644 --- a/drivers/CAN.cpp +++ b/drivers/CAN.cpp @@ -18,7 +18,7 @@ #if DEVICE_CAN #include "cmsis.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" namespace mbed { diff --git a/drivers/I2C.cpp b/drivers/I2C.cpp index c912e3f9e5..8be7a529fc 100644 --- a/drivers/I2C.cpp +++ b/drivers/I2C.cpp @@ -18,7 +18,7 @@ #if DEVICE_I2C #if DEVICE_I2C_ASYNCH -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #endif namespace mbed { diff --git a/drivers/PwmOut.h b/drivers/PwmOut.h index c94b8584fd..5f7bb478ae 100644 --- a/drivers/PwmOut.h +++ b/drivers/PwmOut.h @@ -21,7 +21,7 @@ #if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY) #include "hal/pwmout_api.h" #include "platform/mbed_critical.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" namespace mbed { /** \addtogroup drivers */ diff --git a/drivers/SPI.cpp b/drivers/SPI.cpp index e21922b258..7bb94018d1 100644 --- a/drivers/SPI.cpp +++ b/drivers/SPI.cpp @@ -17,7 +17,7 @@ #include "platform/mbed_critical.h" #if DEVICE_SPI_ASYNCH -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #endif #if DEVICE_SPI diff --git a/drivers/SerialBase.cpp b/drivers/SerialBase.cpp index 5ec47ff83a..ba5f9db3f2 100644 --- a/drivers/SerialBase.cpp +++ b/drivers/SerialBase.cpp @@ -16,7 +16,7 @@ #include "drivers/SerialBase.h" #include "platform/mbed_wait_api.h" #include "platform/mbed_critical.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #if DEVICE_SERIAL diff --git a/drivers/Ticker.h b/drivers/Ticker.h index 16d552ea7a..646f8261c8 100644 --- a/drivers/Ticker.h +++ b/drivers/Ticker.h @@ -20,7 +20,7 @@ #include "platform/Callback.h" #include "platform/mbed_toolchain.h" #include "platform/NonCopyable.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #include "hal/lp_ticker_api.h" #include "platform/mbed_critical.h" diff --git a/drivers/Timeout.h b/drivers/Timeout.h index 8d9a19327e..e3a92cc3be 100644 --- a/drivers/Timeout.h +++ b/drivers/Timeout.h @@ -18,7 +18,7 @@ #include "drivers/Ticker.h" #include "platform/NonCopyable.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" namespace mbed { /** \addtogroup drivers */ diff --git a/drivers/Timer.h b/drivers/Timer.h index a8758005d4..9fafad945a 100644 --- a/drivers/Timer.h +++ b/drivers/Timer.h @@ -19,7 +19,7 @@ #include "platform/platform.h" #include "hal/ticker_api.h" #include "platform/NonCopyable.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" namespace mbed { /** \addtogroup drivers */ diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 75c3af2d9b..8418d2892c 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -18,7 +18,7 @@ #include #include "mbed.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "ns_types.h" #include "platform/arm_hal_interrupt.h" #include "nanostack/platform/arm_hal_phy.h" diff --git a/hal/mbed_sleep_manager.c b/hal/mbed_sleep_manager.c index 58cf23a685..8efd7bcc8e 100644 --- a/hal/mbed_sleep_manager.c +++ b/hal/mbed_sleep_manager.c @@ -14,7 +14,7 @@ * limitations under the License. */ -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "mbed_critical.h" #include "sleep_api.h" #include "mbed_error.h" diff --git a/mbed.h b/mbed.h index 4a3d291ae3..1e6eec446c 100644 --- a/mbed.h +++ b/mbed.h @@ -82,7 +82,7 @@ #include "drivers/InterruptIn.h" #include "platform/mbed_wait_api.h" #include "hal/sleep_api.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #include "platform/mbed_rtc_time.h" #include "platform/mbed_poll.h" #include "platform/ATCmdParser.h" diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h index 6b64022fc0..78fa962732 100644 --- a/platform/DeepSleepLock.h +++ b/platform/DeepSleepLock.h @@ -17,7 +17,7 @@ #define MBED_DEEPSLEEPLOCK_H #include -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #include "platform/mbed_critical.h" namespace mbed { diff --git a/platform/mbed_interface.c b/platform/mbed_interface.c index 84ab20cd8a..99c7c4891b 100644 --- a/platform/mbed_interface.c +++ b/platform/mbed_interface.c @@ -71,7 +71,8 @@ int mbed_interface_powerdown(void) { } } -// for backward compatibility +MBED_DEPRECATED_SINCE("mbed-os-5.9", "This function shouldn't be used in new code." + "For system reset funcionality use system_reset()") void mbed_reset(void) { mbed_interface_reset(); } diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h new file mode 100644 index 0000000000..9efbaca411 --- /dev/null +++ b/platform/mbed_power_mgmt.h @@ -0,0 +1,185 @@ +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_power_mgmt Power management functions + * @{ + */ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_POWER_MGMT_H +#define MBED_POWER_MGMT_H + +#include "hal/sleep_api.h" +#include "mbed_toolchain.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Sleep manager API + * The sleep manager provides API to automatically select sleep mode. + * + * There are two sleep modes: + * - sleep + * - deepsleep + * + * Use locking/unlocking deepsleep for drivers that depend on features that + * are not allowed (=disabled) during the deepsleep. For instance, high frequency + * clocks. + * + * Example: + * @code + * + * void driver::handler() + * { + * if (_sensor.get_event()) { + * // any event - we are finished, unlock the deepsleep + * sleep_manager_unlock_deep_sleep(); + * _callback(); + * } + * } + * + * int driver::measure(event_t event, callback_t& callback) + * { + * _callback = callback; + * sleep_manager_lock_deep_sleep(); + * // start async transaction, we are waiting for an event + * return _sensor.start(event, callback); + * } + * @endcode + */ + +/** Lock the deep sleep mode + * + * This locks the automatic deep mode selection. + * sleep_manager_sleep_auto() will ignore deepsleep mode if + * this function is invoked at least once (the internal counter is non-zero) + * + * Use this locking mechanism for interrupt driven API that are + * running in the background and deepsleep could affect their functionality + * + * The lock is a counter, can be locked up to USHRT_MAX + * This function is IRQ and thread safe + */ +void sleep_manager_lock_deep_sleep(void); + +/** Unlock the deep sleep mode + * + * Use unlocking in pair with sleep_manager_lock_deep_sleep(). + * + * The lock is a counter, should be equally unlocked as locked + * This function is IRQ and thread safe + */ +void sleep_manager_unlock_deep_sleep(void); + +/** Get the status of deep sleep allowance for a target + * + * @return true if a target can go to deepsleep, false otherwise + */ +bool sleep_manager_can_deep_sleep(void); + +/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based + * on the deepsleep locking counter + * + * This function is IRQ and thread safe + * + * @note + * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger + * to be active for debug modes. + * + */ +void sleep_manager_sleep_auto(void); + +/** Send the microcontroller to sleep + * + * @note This function can be a noop if not implemented by the platform. + * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined). + * @note This function will be a noop while uVisor is in use. + * @note This function will be a noop if the following conditions are met: + * - The RTOS is present + * - The processor turn off the Systick clock during sleep + * - The target does not implement tickless mode + * + * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + */ +static inline void sleep(void) +{ +#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) +#if DEVICE_SLEEP +#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) + sleep_manager_sleep_auto(); +#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */ +#endif /* DEVICE_SLEEP */ +#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */ +} + +/** Send the microcontroller to deep sleep + * + * @note This function can be a noop if not implemented by the platform. + * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined) + * @note This function will be a noop while uVisor is in use. + * + * This processor is setup ready for deep sleep, and sent to sleep. This mode + * has the same sleep features as sleep plus it powers down peripherals and clocks. All state + * is still maintained. + * + * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + */ + +MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()") +static inline void deepsleep(void) +{ +#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) +#if DEVICE_SLEEP + sleep_manager_sleep_auto(); +#endif /* DEVICE_SLEEP */ +#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */ +} + +/** Resets the processor and most of the sub-system + * + * @note Does not affect the debug sub-system + */ +static inline void system_reset(void) +{ + NVIC_SystemReset(); +} + +#ifdef __cplusplus +} +#endif + +#endif + +/** @}*/ +/** @}*/ diff --git a/platform/mbed_sleep.h b/platform/mbed_sleep.h index 7473135681..c29549f331 100644 --- a/platform/mbed_sleep.h +++ b/platform/mbed_sleep.h @@ -1,177 +1,24 @@ - -/** \addtogroup platform */ -/** @{*/ -/** - * \defgroup platform_sleep Sleep functions - * @{ - */ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef MBED_SLEEP_H -#define MBED_SLEEP_H -#include "hal/sleep_api.h" -#include "mbed_toolchain.h" -#include +#ifndef MBED_MBED_SLEEP_H +#define MBED_MBED_SLEEP_H -#ifdef __cplusplus -extern "C" { -#endif - -/** Sleep manager API - * The sleep manager provides API to automatically select sleep mode. - * - * There are two sleep modes: - * - sleep - * - deepsleep - * - * Use locking/unlocking deepsleep for drivers that depend on features that - * are not allowed (=disabled) during the deepsleep. For instance, high frequency - * clocks. - * - * Example: - * @code - * - * void driver::handler() - * { - * if (_sensor.get_event()) { - * // any event - we are finished, unlock the deepsleep - * sleep_manager_unlock_deep_sleep(); - * _callback(); - * } - * } - * - * int driver::measure(event_t event, callback_t& callback) - * { - * _callback = callback; - * sleep_manager_lock_deep_sleep(); - * // start async transaction, we are waiting for an event - * return _sensor.start(event, callback); - * } - * @endcode - */ - -/** Lock the deep sleep mode - * - * This locks the automatic deep mode selection. - * sleep_manager_sleep_auto() will ignore deepsleep mode if - * this function is invoked at least once (the internal counter is non-zero) - * - * Use this locking mechanism for interrupt driven API that are - * running in the background and deepsleep could affect their functionality - * - * The lock is a counter, can be locked up to USHRT_MAX - * This function is IRQ and thread safe - */ -void sleep_manager_lock_deep_sleep(void); - -/** Unlock the deep sleep mode - * - * Use unlocking in pair with sleep_manager_lock_deep_sleep(). - * - * The lock is a counter, should be equally unlocked as locked - * This function is IRQ and thread safe - */ -void sleep_manager_unlock_deep_sleep(void); - -/** Get the status of deep sleep allowance for a target - * - * @return true if a target can go to deepsleep, false otherwise - */ -bool sleep_manager_can_deep_sleep(void); - -/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based - * on the deepsleep locking counter - * - * This function is IRQ and thread safe - * - * @note - * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger - * to be active for debug modes. - * - */ -void sleep_manager_sleep_auto(void); - -/** Send the microcontroller to sleep - * - * @note This function can be a noop if not implemented by the platform. - * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined). - * @note This function will be a noop while uVisor is in use. - * @note This function will be a noop if the following conditions are met: - * - The RTOS is present - * - The processor turn off the Systick clock during sleep - * - The target does not implement tickless mode - * - * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the - * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates - * dynamic power used by the processor, memory systems and buses. The processor, peripheral and - * memory state are maintained, and the peripherals continue to work and can generate interrupts. - * - * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. - * - * @note - * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. - * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be - * able to access the LocalFileSystem - */ -static inline void sleep(void) -{ -#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) -#if DEVICE_SLEEP -#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) - sleep_manager_sleep_auto(); -#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */ -#endif /* DEVICE_SLEEP */ -#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */ -} - -/** Send the microcontroller to deep sleep - * - * @note This function can be a noop if not implemented by the platform. - * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined) - * @note This function will be a noop while uVisor is in use. - * - * This processor is setup ready for deep sleep, and sent to sleep. This mode - * has the same sleep features as sleep plus it powers down peripherals and clocks. All state - * is still maintained. - * - * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. - * - * @note - * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. - * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be - * able to access the LocalFileSystem - */ - -MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()") -static inline void deepsleep(void) -{ -#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) -#if DEVICE_SLEEP - sleep_manager_sleep_auto(); -#endif /* DEVICE_SLEEP */ -#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */ -} - -#ifdef __cplusplus -} -#endif +#warning mbed_sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] +#include "platform/mbed_power_mgmt.h" #endif - -/** @}*/ -/** @}*/ diff --git a/platform/mbed_wait_api_rtos.cpp b/platform/mbed_wait_api_rtos.cpp index d89b139cf2..3c082f2fe6 100644 --- a/platform/mbed_wait_api_rtos.cpp +++ b/platform/mbed_wait_api_rtos.cpp @@ -22,7 +22,7 @@ #include "hal/us_ticker_api.h" #include "rtos/rtos.h" #include "platform/mbed_critical.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" void wait(float s) { wait_us(s * 1000000.0f); diff --git a/platform/sleep.h b/platform/sleep.h index ac3e84b777..f900bcf6e3 100644 --- a/platform/sleep.h +++ b/platform/sleep.h @@ -18,7 +18,7 @@ #ifndef MBED_OLD_SLEEP_H #define MBED_OLD_SLEEP_H -#warning sleep.h has been replaced by mbed_sleep.h, please update to mbed_sleep.h [since mbed-os-5.3] -#include "platform/mbed_sleep.h" +#warning sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] +#include "platform/mbed_power_mgmt.h" #endif diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index 23830a8f5d..180f5489a3 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -21,7 +21,7 @@ */ #include "rtos/rtos_idle.h" -#include "platform/mbed_sleep.h" +#include "platform/mbed_power_mgmt.h" #include "TimerEvent.h" #include "lp_ticker_api.h" #include "mbed_critical.h" diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c index 87f1b4d1fe..0e79bf2d72 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c @@ -45,7 +45,7 @@ */ #include -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" /* SAM3 and SAM4 series */ #if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ diff --git a/targets/TARGET_NUVOTON/nu_timer.h b/targets/TARGET_NUVOTON/nu_timer.h index 08683370fc..7342fe92b5 100644 --- a/targets/TARGET_NUVOTON/nu_timer.h +++ b/targets/TARGET_NUVOTON/nu_timer.h @@ -20,7 +20,7 @@ #include #include #include "cmsis.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "mbed_critical.h" #include "ticker_api.h" #include "us_ticker_api.h" diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c index 31c9a5f720..41be2fea41 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c @@ -31,7 +31,7 @@ * */ #if DEVICE_SLEEP -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "sleep_api.h" #include "cmsis_nvic.h" diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c index 608c5c7c2e..f9adc69bfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c @@ -28,7 +28,7 @@ #if DEVICE_I2C #include "mbed_assert.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "i2c_api.h" #include "PeripheralPins.h" #include "pinmap_function.h" diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c index 5ad3b9714c..759c1533d3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c @@ -26,7 +26,7 @@ #if DEVICE_PWMOUT #include "mbed_assert.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "pwmout_api.h" #include "pinmap.h" #include "PeripheralPins.h" diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index 987ee98375..3c4bc21945 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -26,7 +26,7 @@ #if DEVICE_SERIAL #include "mbed_assert.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "serial_api.h" #include "serial_api_HAL.h" #include diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index e832536ed2..3a2c9df896 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -26,7 +26,7 @@ #if DEVICE_SPI #include "mbed_assert.h" -#include "mbed_sleep.h" +#include "mbed_power_mgmt.h" #include "PeripheralPins.h" #include "pinmap.h" #include "pinmap_function.h" From 73b054601d8fdea4b8194775e225ae91963b473d Mon Sep 17 00:00:00 2001 From: Bartek Szatkowski Date: Tue, 27 Feb 2018 15:25:59 +0000 Subject: [PATCH 39/42] Add tests for system_reset() --- TESTS/host_tests/system_reset.py | 76 +++++++++++++++++++++++ TESTS/mbed_platform/system_reset/main.cpp | 51 +++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 TESTS/host_tests/system_reset.py create mode 100644 TESTS/mbed_platform/system_reset/main.cpp diff --git a/TESTS/host_tests/system_reset.py b/TESTS/host_tests/system_reset.py new file mode 100644 index 0000000000..7899e3783e --- /dev/null +++ b/TESTS/host_tests/system_reset.py @@ -0,0 +1,76 @@ +""" +Copyright (c) 2018 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" +import time +from mbed_host_tests import BaseHostTest +from mbed_host_tests.host_tests_runner.host_test_default import DefaultTestSelector + +DEFAULT_CYCLE_PERIOD = 1.0 + +MSG_VALUE_DUMMY = '0' + +MSG_KEY_DEVICE_READY = 'ready' +MSG_KEY_DEVICE_RESET = 'reset' +MSG_KEY_SYNC = '__sync' + +class SystemResetTest(BaseHostTest): + """Test for the system_reset API. + + Given a device running code + When the device is restarted using @a system_reset() + Then the device is restarted + """ + + def __init__(self): + super(SystemResetTest, self).__init__() + self.reset = False + cycle_s = self.get_config_item('program_cycle_s') + self.program_cycle_s = cycle_s if cycle_s is not None else DEFAULT_CYCLE_PERIOD + + self.test_steps_sequence = self.test_steps() + # Advance the coroutine to it's first yield statement. + self.test_steps_sequence.send(None) + + def setup(self): + self.register_callback(MSG_KEY_DEVICE_READY, self.cb_device_ready) + + def cb_device_ready(self, key, value, timestamp): + """Acknowledge device rebooted correctly and feed the test execution + """ + self.reset = True + + try: + if self.test_steps_sequence.send(value): + self.notify_complete(True) + except (StopIteration, RuntimeError) as exc: + self.notify_complete(False) + + def test_steps(self): + """Reset the device and check the status + """ + system_reset = yield + + self.reset = False + self.send_kv(MSG_KEY_DEVICE_RESET, MSG_VALUE_DUMMY) + time.sleep(self.program_cycle_s) + self.send_kv(MSG_KEY_SYNC, MSG_VALUE_DUMMY) + + system_reset = yield + + if self.reset == False: + raise RuntimeError('Platform did not reset as expected.') + + # The sequence is correct -- test passed. + yield True \ No newline at end of file diff --git a/TESTS/mbed_platform/system_reset/main.cpp b/TESTS/mbed_platform/system_reset/main.cpp new file mode 100644 index 0000000000..637735e472 --- /dev/null +++ b/TESTS/mbed_platform/system_reset/main.cpp @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" + +#define MSG_VALUE_DUMMY "0" +#define MSG_VALUE_LEN 16 +#define MSG_KEY_LEN 16 + +#define MSG_KEY_DEVICE_READY "ready" +#define MSG_KEY_DEVICE_RESET "reset" + +void test_system_reset() +{ + // Report readiness + greentea_send_kv(MSG_KEY_DEVICE_READY, MSG_VALUE_DUMMY); + + static char _key[MSG_KEY_LEN + 1] = { }; + static char _value[MSG_VALUE_LEN + 1] = { }; + + greentea_parse_kv(_key, _value, MSG_KEY_LEN, MSG_VALUE_LEN); + if (strcmp(_key, MSG_KEY_DEVICE_RESET) == 0) { + system_reset(); + TEST_ASSERT_MESSAGE(0, "system_reset() did not reset the device as expected."); + } + + TEST_ASSERT_MESSAGE(0, "Unexpected message key."); +} + +int main(void) +{ + GREENTEA_SETUP(2, "system_reset"); + test_system_reset(); + GREENTEA_TESTSUITE_RESULT(0); // Fail on any error. + + return 0; +} \ No newline at end of file From 2b83b69f90d781f334079142f07b12199f9ccb92 Mon Sep 17 00:00:00 2001 From: Bartek Szatkowski Date: Wed, 28 Feb 2018 20:02:24 +0000 Subject: [PATCH 40/42] Remove conflictinng system_reset() from Atmel drivers --- .../drivers/system/reset/TARGET_SAMD21/reset.h | 12 ------------ .../drivers/system/reset/TARGET_SAML21/reset.h | 12 ------------ .../drivers/system/reset/TARGET_SAMR21/reset.h | 12 ------------ 3 files changed, 36 deletions(-) diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h index 698ec7d364..75216c4842 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h @@ -83,18 +83,6 @@ enum system_reset_cause { * @{ */ -/** - * \brief Reset the MCU. - * - * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources, - * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set). - * - */ -static inline void system_reset(void) -{ - NVIC_SystemReset(); -} - /** * \brief Return the reset cause. * diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h index e8200b54bf..0dde18a18d 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h @@ -121,18 +121,6 @@ enum system_wakeup_debounce_count { * @{ */ -/** - * \brief Reset the MCU. - * - * Resets the MCU and all associated peripherals and registers, except RTC, - * OSC32KCTRL, RSTC, GCLK (if WRTLOCK is set), and I/O retention state of PM. - * - */ -static inline void system_reset(void) -{ - NVIC_SystemReset(); -} - /** * \brief Get the reset cause. * diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h index 698ec7d364..75216c4842 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h @@ -83,18 +83,6 @@ enum system_reset_cause { * @{ */ -/** - * \brief Reset the MCU. - * - * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources, - * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set). - * - */ -static inline void system_reset(void) -{ - NVIC_SystemReset(); -} - /** * \brief Return the reset cause. * From 477b947b22898838cbdad2202d7dcfb689253e9b Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Wed, 28 Feb 2018 13:59:57 -0600 Subject: [PATCH 41/42] Improve json schema validation errors --- tools/config/__init__.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/tools/config/__init__.py b/tools/config/__init__.py index 0bbafa81e5..7bdbd41238 100644 --- a/tools/config/__init__.py +++ b/tools/config/__init__.py @@ -384,6 +384,13 @@ class Config(object): app_config_location = full_path return app_config_location + def format_validation_error(self, error, path): + if error.context: + return self.format_validation_error(error.context[0], path) + else: + return "in {} element {}: {}".format( + path, str(".".join(error.absolute_path)), error.message) + def __init__(self, tgt, top_level_dirs=None, app_config=None): """Construct a mbed configuration @@ -430,7 +437,9 @@ class Config(object): errors = sorted(validator.iter_errors(self.app_config_data)) if errors: - raise ConfigException(",".join(x.message for x in errors)) + raise ConfigException("; ".join( + self.format_validation_error(x, self.app_config_location) + for x in errors)) # Update the list of targets with the ones defined in the application # config, if applicable @@ -494,7 +503,9 @@ class Config(object): errors = sorted(validator.iter_errors(cfg)) if errors: - raise ConfigException(",".join(x.message for x in errors)) + raise ConfigException("; ".join( + self.format_validation_error(x, config_file) + for x in errors)) cfg["__config_path"] = full_path From 0f15633d37698b038ef2956c1c181729ca1d085c Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Thu, 1 Feb 2018 10:28:32 -0600 Subject: [PATCH 42/42] Work around Arm Compiler 6 stdvector perfomance cliff --- tools/profiles/debug.json | 2 +- tools/profiles/develop.json | 2 +- tools/profiles/release.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json index ff8d9ed056..b5229e2e1a 100644 --- a/tools/profiles/debug.json +++ b/tools/profiles/debug.json @@ -19,7 +19,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD"], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"], diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 8bf0db68a7..7858826722 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -18,7 +18,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD"], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index 1fa503836d..42bc2cfeb4 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -18,7 +18,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD"], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"],