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Added support for Nordic parts with 32K of RAM

pull/480/head
Bogdan Marinescu 2014-09-08 16:27:53 +01:00
parent eec7671fa0
commit 82ec8c2c4d
7 changed files with 368 additions and 3 deletions
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0
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/nRF51822.sct → libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct
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0
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/startup_nRF51822.s → libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.s
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27
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct Normal file
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@ -0,0 +1,27 @@
;WITHOUT SOFTDEVICE:
;LR_IROM1 0x00000000 0x00040000 {
; ER_IROM1 0x00000000 0x00040000 {
; *.o (RESET, +First)
; *(InRoot$$Sections)
; .ANY (+RO)
; }
; RW_IRAM1 0x20000000 0x00004000 {
; .ANY (+RW +ZI)
; }
;}
;
;WITH SOFTDEVICE:
LR_IROM1 0x16000 0x002A000 {
ER_IROM1 0x16000 0x002A000 {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20002000 0x00006000 {
.ANY (+RW +ZI)
}
}

187
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s Normal file
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@ -0,0 +1,187 @@
; mbed Microcontroller Library
; Copyright (c) 2013 Nordic Semiconductor.
;Licensed under the Apache License, Version 2.0 (the "License");
;you may not use this file except in compliance with the License.
;You may obtain a copy of the License at
;http://www.apache.org/licenses/LICENSE-2.0
;Unless required by applicable law or agreed to in writing, software
;distributed under the License is distributed on an "AS IS" BASIS,
;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;See the License for the specific language governing permissions and
;limitations under the License.
; Description message
__initial_sp EQU 0x20008000
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_COMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_COMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
END

0
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/NRF51822.ld → libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld
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151
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld Normal file
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@ -0,0 +1,151 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000
RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x6000
}
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.Vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

6
workspace_tools/targets.py
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@ -431,7 +431,7 @@ class NRF51822(Target):
def __init__(self):
Target.__init__(self)
self.core = "Cortex-M0"
self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822"]
self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"]
self.supported_toolchains = ["ARM", "GCC_ARM"]
self.is_disk_virtual = True
@ -544,14 +544,14 @@ class XADOW_M0(LPCTarget):
class ARCH_BLE(NRF51822):
def __init__(self):
NRF51822.__init__(self)
self.extra_labels = ['NORDIC', 'MCU_NRF51822']
self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K']
self.macros = ['TARGET_NRF51822']
self.supported_form_factors = ["ARDUINO"]
class NRF51_DK(NRF51822):
def __init__(self):
NRF51822.__init__(self)
self.extra_labels = ['NORDIC', 'MCU_NRF51822']
self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K']
self.macros = ['TARGET_NRF51822']
self.supported_form_factors = ["ARDUINO"]