From 8273e371dfd8cf54bf718a815ea88b1b920d5549 Mon Sep 17 00:00:00 2001 From: bcostm Date: Thu, 17 Aug 2017 10:55:18 +0200 Subject: [PATCH] STM32L053x8: Align system_clock.c files --- .../TARGET_NUCLEO_L053R8/system_clock.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c index 0aa0cc6987..f2e0635a30 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c @@ -132,7 +132,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; /* Used to gain time after DeepSleep in case HSI is used */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { @@ -163,6 +162,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } + /* Select HSI48 as USB clock source */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz @@ -173,12 +180,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - /* Output clock on MCO1 pin(PA8) for debugging purpose */ //if (bypass == 0) // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz