From 1325d8c8c2480862d7f50a56b9be6f07906d0de3 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 28 Jan 2016 16:31:12 +0100
Subject: [PATCH 01/78] [B96B_F446VE] Add CAN Feature

---
 libraries/mbed/hal/can_api.h                  |   3 +-
 .../TARGET_STM32F4/PeripheralPins.h           |   4 +
 .../TARGET_B96B_F446VE/PeripheralNames.h      |   7 +-
 .../TARGET_B96B_F446VE/PeripheralPins.c       |  21 +
 .../TARGET_B96B_F446VE/device.h               |   2 +
 .../TARGET_B96B_F446VE/objects.h              |   5 +
 .../hal/TARGET_STM/TARGET_STM32F4/can_api.c   | 554 ++++++++++++++++++
 7 files changed, 594 insertions(+), 2 deletions(-)
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c

diff --git a/libraries/mbed/hal/can_api.h b/libraries/mbed/hal/can_api.h
index 2f51cea9e3..be205e3f44 100644
--- a/libraries/mbed/hal/can_api.h
+++ b/libraries/mbed/hal/can_api.h
@@ -37,7 +37,8 @@ typedef enum {
     IRQ_PASSIVE,
     IRQ_ARB,
     IRQ_BUS,
-    IRQ_READY
+    IRQ_READY,
+    IRQ_RX1
 } CanIrqType;
 
 
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/PeripheralPins.h
index cc2fcaaf11..e6077cf110 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/PeripheralPins.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/PeripheralPins.h
@@ -63,4 +63,8 @@ extern const PinMap PinMap_SPI_MISO[];
 extern const PinMap PinMap_SPI_SCLK[];
 extern const PinMap PinMap_SPI_SSEL[];
 
+//*** CAN ***
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+
 #endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralNames.h
index 43a3a507be..d0c091eb51 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralNames.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralNames.h
@@ -38,7 +38,7 @@ extern "C" {
 
 typedef enum {
     ADC_1 = (int)ADC1_BASE,
-    ADC_3 = (int)ADC3_BASE,
+    ADC_3 = (int)ADC3_BASE
 } ADCName;
 
 typedef enum {
@@ -92,6 +92,11 @@ typedef enum {
     PWM_14 = (int)TIM14_BASE
 } PWMName;
 
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c
index b36a155c15..28133033fd 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c
@@ -267,3 +267,24 @@ const PinMap PinMap_SPI_SSEL[] = {
     {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
     {NC,    NC,    0}
 };
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+ // {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP73 to use it
+ // {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP36 to use it
+ // {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs
+ // {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ // {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP74 to use it
+ // {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP43 to use it
+ // {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs
+ // {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PD_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h
index c4ba64b581..403a0c74e3 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h
@@ -57,6 +57,8 @@
 
 #define DEVICE_SLEEP            1
 
+#define DEVICE_CAN              1
+
 //=======================================
 
 #define DEVICE_SEMIHOST         0
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
index 0116da688c..b997be405b 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
@@ -104,6 +104,11 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct can_s {
+    CANName can;
+    int index; // Used by irq	
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
new file mode 100644
index 0000000000..4fe1567406
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
@@ -0,0 +1,554 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include <math.h>
+#include <string.h>
+
+#define CAN_NUM    2
+static CAN_HandleTypeDef CanHandle;
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+void can_init(can_t *obj, PinName rd, PinName td) 
+{
+    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->can = (CANName)pinmap_merge(can_rd, can_td);
+    MBED_ASSERT((int)obj->can != NC);    
+
+    if(obj->can == CAN_1) {
+        __HAL_RCC_CAN1_CLK_ENABLE();
+        obj->index = 0;
+    } else {
+        __HAL_RCC_CAN2_CLK_ENABLE();
+        obj->index = 0;
+    }
+
+    // Configure the CAN pins
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+    if (rd != NC) {
+        pin_mode(rd, PullUp);
+    }
+    if (td != NC) {
+        pin_mode(td, PullUp);
+    }
+
+    CanHandle.Instance = (CAN_TypeDef *)(obj->can);
+
+    CanHandle.Init.TTCM = DISABLE;
+    CanHandle.Init.ABOM = DISABLE;
+    CanHandle.Init.AWUM = DISABLE;
+    CanHandle.Init.NART = DISABLE;
+    CanHandle.Init.RFLM = DISABLE;
+    CanHandle.Init.TXFP = DISABLE;
+    CanHandle.Init.Mode = CAN_MODE_NORMAL;
+    CanHandle.Init.SJW = CAN_SJW_1TQ;
+    CanHandle.Init.BS1 = CAN_BS1_6TQ;
+    CanHandle.Init.BS2 = CAN_BS2_8TQ;
+    CanHandle.Init.Prescaler = 2;
+
+    if (HAL_CAN_Init(&CanHandle) != HAL_OK) {
+       error("Cannot initialize CAN");
+    }
+    can_filter(obj, 0, 0, CANStandard, 0);
+}
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) 
+{
+    irq_handler = handler;
+    can_irq_ids[obj->index] = id;    
+}
+
+void can_irq_free(can_t *obj) 
+{
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+  
+    can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
+                  CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
+    can_irq_ids[obj->can] = 0;
+}
+
+void can_free(can_t *obj) 
+{
+    // Reset CAN and disable clock
+    if (obj->can == CAN_1) {
+        __HAL_RCC_CAN1_FORCE_RESET();
+        __HAL_RCC_CAN1_RELEASE_RESET();
+        __HAL_RCC_CAN1_CLK_DISABLE();
+    }
+
+    if (obj->can == CAN_2) {
+        __HAL_RCC_CAN2_FORCE_RESET();
+        __HAL_RCC_CAN2_RELEASE_RESET();
+        __HAL_RCC_CAN2_CLK_DISABLE();
+    }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+    {0x0, 0x0},      // 2,  50%
+    {0x1, 0x0},      // 3,  67%
+    {0x2, 0x0},      // 4,  75%
+    {0x3, 0x0},      // 5,  80%
+    {0x3, 0x1},      // 6,  67%
+    {0x4, 0x1},      // 7,  71%
+    {0x5, 0x1},      // 8,  75%
+    {0x6, 0x1},      // 9,  78%
+    {0x6, 0x2},      // 10, 70%
+    {0x7, 0x2},      // 11, 73%
+    {0x8, 0x2},      // 12, 75%
+    {0x9, 0x2},      // 13, 77%
+    {0x9, 0x3},      // 14, 71%
+    {0xA, 0x3},      // 15, 73%
+    {0xB, 0x3},      // 16, 75%
+    {0xC, 0x3},      // 17, 76%
+    {0xD, 0x3},      // 18, 78%
+    {0xD, 0x4},      // 19, 74%
+    {0xE, 0x4},      // 20, 75%
+    {0xF, 0x4},      // 21, 76%
+    {0xF, 0x5},      // 22, 73%
+    {0xF, 0x6},      // 23, 70%
+    {0xF, 0x7},      // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) 
+{
+    uint32_t    btr;
+    uint16_t    brp = 0;
+    uint32_t    calcbit;
+    uint32_t    bitwidth;
+    int         hit = 0;
+    int         bits;
+    
+    bitwidth = (pclk / cclk);
+    
+    brp = bitwidth / 0x18;
+    while ((!hit) && (brp < bitwidth / 4)) {
+        brp++;
+        for (bits = 22; bits > 0; bits--) {
+            calcbit = (bits + 3) * (brp + 1);
+            if (calcbit == bitwidth) {
+                hit = 1;
+                break;
+            }
+        }
+    }
+    
+    if (hit) {
+        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+            | ((timing_pts[bits][0] << 16) & 0x000F0000)
+            | ((psjw                << 24) & 0x0000C000)
+            | ((brp                 <<  0) & 0x000003FF);
+    } else {
+        btr = 0xFFFFFFFF;
+    }
+    
+    return btr;
+
+}
+
+int can_frequency(can_t *obj, int f) 
+{
+    int pclk ; //= PeripheralClock;
+    int btr = can_speed(pclk, (unsigned int)f, 1);
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+
+    if (btr > 0) {
+        can->MCR |= CAN_MCR_INRQ ;
+        while((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+        }
+        can->BTR = btr;
+        can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+        while((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+        }
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) 
+{
+    uint32_t  transmitmailbox = 5;
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+
+    /* Select one empty transmit mailbox */
+    if ((can->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) {
+        transmitmailbox = 0;
+    } else if ((can->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) {
+        transmitmailbox = 1;
+    } else if ((can->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) {
+        transmitmailbox = 2;
+    } else {
+        transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+    }
+
+    if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) {
+    can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+    if (!(msg.format))
+    {
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type);
+    }
+    else
+    {
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type);
+    }
+
+    /* Set up the DLC */
+    can->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    can->sTxMailBox[transmitmailbox].TDTR |= (msg.len & (uint8_t)0x0000000F);
+
+    /* Set up the data field */
+    can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) | 
+                                             ((uint32_t)msg.data[2] << 16) |
+                                             ((uint32_t)msg.data[1] << 8) | 
+                                             ((uint32_t)msg.data[0]));
+    can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) | 
+                                             ((uint32_t)msg.data[6] << 16) |
+                                             ((uint32_t)msg.data[5] << 8) |
+                                             ((uint32_t)msg.data[4]));
+    /* Request transmission */
+    can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+  }
+
+  return 1;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) 
+{
+    //handle is the FIFO number
+
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);    
+    
+    /* Get the Id */
+    msg->format = (CANFormat)((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR);
+    if (!msg->format) {
+        msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21);
+    } else {
+        msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3);
+    }
+      
+    msg->type = (CANType)((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR);
+    /* Get the DLC */
+    msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR;
+//  /* Get the FMI */
+//  msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8);
+    /* Get the data field */
+    msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR;
+    msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8);
+    msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16);
+    msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24);
+    msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR;
+    msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8);
+    msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16);
+    msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24);
+    
+    /* Release the FIFO */
+    if(handle == CAN_FIFO0) {
+        /* Release FIFO0 */
+        can->RF0R = CAN_RF0R_RFOM0;
+    } else { /* FIFONumber == CAN_FIFO1 */
+      /* Release FIFO1 */
+      can->RF1R = CAN_RF1R_RFOM1;
+    }
+
+    return 1;
+}
+
+void can_reset(can_t *obj) 
+{
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+
+    can->MCR |= CAN_MCR_RESET;  
+    can->ESR = 0x0;
+}
+
+unsigned char can_rderror(can_t *obj) 
+{
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);    
+    return (can->ESR >> 24) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) 
+{
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);    
+    return (can->ESR >> 16) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) 
+{
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);        
+    
+    can->MCR |= CAN_MCR_INRQ ;
+    while((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+    }
+    if (silent) {
+        can->BTR |= ((uint32_t)1 << 31);
+    } else {
+        can->BTR &= ~((uint32_t)1 << 31);
+    }
+    can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+    while((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+    }
+}
+
+int can_mode(can_t *obj, CanMode mode) 
+{
+    int success = 0;
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);            
+    can->MCR |= CAN_MCR_INRQ ;
+    while((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+    }
+    switch (mode) {
+        case MODE_NORMAL:
+            can->BTR &= ~(((uint32_t)1 << 31) | ((uint32_t)1 << 30));
+            success = 1;
+            break;
+        case MODE_SILENT:
+            can->BTR |= ((uint32_t)1 << 31);
+                    can->BTR &= ~((uint32_t)1 << 30);
+            success = 1;
+            break;
+        case MODE_TEST_GLOBAL:
+            can->BTR |= ((uint32_t)1 << 30);
+            can->BTR &= ~((uint32_t)1 << 31);
+            success = 1;
+            break;
+        case MODE_TEST_SILENT:
+            can->BTR |= (((uint32_t)1 << 31) | ((uint32_t)1 << 30));
+            success = 1;
+            break;
+        default:
+            success = 0;
+            break;
+    }
+    can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+    while((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+    }
+    return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) 
+{
+    CanHandle.Instance = (CAN_TypeDef *)(obj->can);    
+    CAN_FilterConfTypeDef  sFilterConfig;
+    
+    sFilterConfig.FilterNumber = handle;
+    sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
+    sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
+    sFilterConfig.FilterIdHigh = (uint8_t) (id >> 8);
+    sFilterConfig.FilterIdLow = (uint8_t) id;
+    sFilterConfig.FilterMaskIdHigh = (uint8_t) (mask >> 8);
+    sFilterConfig.FilterMaskIdLow = (uint8_t) mask;
+    sFilterConfig.FilterFIFOAssignment = 0;
+    sFilterConfig.FilterActivation = ENABLE;
+    sFilterConfig.BankNumber = 14 + handle;
+  
+    HAL_CAN_ConfigFilter(&CanHandle, &sFilterConfig);
+      
+    return 0;
+}
+
+static void can_irq(CANName name, int id) 
+{
+    uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;    
+    CanHandle.Instance = (CAN_TypeDef *)name;
+    
+    if(__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
+        tmp1 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_0);
+        tmp2 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_1);
+        tmp3 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_2);
+        if(tmp1 || tmp2 || tmp3)  
+        {
+            irq_handler(can_irq_ids[id], IRQ_TX);
+        }
+    }
+  
+    tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
+  
+    if((tmp1 != 0) && tmp2) {
+         irq_handler(can_irq_ids[id], IRQ_RX);
+    }
+  
+    tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO1);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP1);
+  
+    if((tmp1 != 0) && tmp2) {
+         irq_handler(can_irq_ids[id], IRQ_RX1);
+    }
+      
+  
+    tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR); 
+  
+    if(tmp1 && tmp2 && tmp3) {
+         irq_handler(can_irq_ids[id], IRQ_PASSIVE);
+    }
+  
+    tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF);
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);  
+    if(tmp1 && tmp2 && tmp3) {
+        irq_handler(can_irq_ids[id], IRQ_BUS);
+    }
+  
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);  
+    if(tmp1 && tmp2 && tmp3) {
+        irq_handler(can_irq_ids[id], IRQ_ERROR);
+    }  
+}
+
+void CAN1_RX0_IRQHandler(void) 
+{
+    can_irq(CAN_1, 0);
+}
+
+void CAN1_RX1_IRQHandler(void) 
+{
+    can_irq(CAN_1, 0);
+}
+
+void CAN1_TX_IRQHandler(void) 
+{
+    can_irq(CAN_1, 0);
+}
+
+void CAN1_SCE_IRQHandler(void) 
+{
+    can_irq(CAN_1, 0);
+}
+
+void CAN2_RX0_IRQHandler(void) 
+{
+    can_irq(CAN_2, 1);
+}
+
+void CAN2_RX1_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+
+void CAN2_TX_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+
+void CAN2_SCE_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
+{
+
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;    
+    uint32_t ier;
+
+    if(obj->can == CAN_1) {
+        switch (type) {
+            case IRQ_RX:
+                ier = CAN_IT_FMP0;
+                irq_n = CAN1_RX0_IRQn;
+                vector = (uint32_t)&CAN1_RX0_IRQHandler;
+                break;
+            case IRQ_RX1:      
+                ier = CAN_IT_FMP1;
+                irq_n = CAN1_RX1_IRQn;
+                vector = (uint32_t)&CAN1_RX1_IRQHandler;
+                break;                
+            case IRQ_TX:      
+                ier = CAN_IT_TME;
+                irq_n = CAN1_TX_IRQn;
+                vector = (uint32_t)&CAN1_TX_IRQHandler;
+                break;
+            case IRQ_ERROR:   
+                ier = CAN_IT_ERR;
+                irq_n = CAN1_SCE_IRQn;
+                vector = (uint32_t)&CAN1_SCE_IRQHandler;
+                break;
+            case IRQ_PASSIVE:
+                ier = CAN_IT_EPV;
+                irq_n = CAN1_SCE_IRQn;
+                vector = (uint32_t)&CAN1_SCE_IRQHandler;
+                break;
+            case IRQ_BUS:
+                ier = CAN_IT_BOF;
+                irq_n = CAN1_SCE_IRQn;
+                vector = (uint32_t)&CAN1_SCE_IRQHandler;
+                break;
+            default: return;
+        }
+    } else {
+        switch (type) {
+              case IRQ_RX:
+                  ier = CAN_IT_FMP0;
+                  irq_n = CAN2_RX0_IRQn;
+                  vector = (uint32_t)&CAN2_RX0_IRQHandler;
+                  break;
+              case IRQ_RX1:
+                  ier = CAN_IT_FMP1;
+                  irq_n = CAN2_RX1_IRQn;
+                  vector = (uint32_t)&CAN2_RX1_IRQHandler;
+                  break;
+              case IRQ_TX:      
+                  ier = CAN_IT_TME;
+                  irq_n = CAN2_TX_IRQn;
+                  vector = (uint32_t)&CAN2_TX_IRQHandler;
+                  break;
+              case IRQ_ERROR:   
+                  ier = CAN_IT_ERR;
+                  irq_n = CAN2_SCE_IRQn;
+                  vector = (uint32_t)&CAN2_SCE_IRQHandler;
+                  break;
+              case IRQ_PASSIVE:
+                  ier = CAN_IT_EPV;
+                  irq_n = CAN2_SCE_IRQn;
+                  vector = (uint32_t)&CAN2_SCE_IRQHandler;
+                  break;
+              case IRQ_BUS:
+                  ier = CAN_IT_BOF;
+                  irq_n = CAN2_SCE_IRQn;
+                  vector = (uint32_t)&CAN2_SCE_IRQHandler;
+                  break;
+              default: return;
+        }
+    }
+
+    if(enable) {
+        can->IER |= ier;
+    } else {
+        can->IER &= ~ier;
+    }
+
+    NVIC_SetVector(irq_n, vector);
+    NVIC_EnableIRQ(irq_n);
+}
+
+#endif // DEVICE_CAN
+

From 6ff8955d58503827af6156871177607586cc3649 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 29 Jan 2016 14:09:25 +0100
Subject: [PATCH 02/78] [B96B_F446VE] Add Can test files + bug fix in can_api.c

---
 .../hal/TARGET_STM/TARGET_STM32F4/can_api.c     | 17 +++++++++--------
 libraries/tests/mbed/can_interrupt/main.cpp     |  7 +++++--
 libraries/tests/mbed/can_loopback/main.cpp      |  2 ++
 workspace_tools/tests.py                        |  6 +++---
 4 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
index 4fe1567406..57712c76cd 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
@@ -317,27 +317,28 @@ void can_monitor(can_t *obj, int silent)
 int can_mode(can_t *obj, CanMode mode) 
 {
     int success = 0;
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);            
+    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
     can->MCR |= CAN_MCR_INRQ ;
     while((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
     }
     switch (mode) {
         case MODE_NORMAL:
-            can->BTR &= ~(((uint32_t)1 << 31) | ((uint32_t)1 << 30));
+            can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
             success = 1;
             break;
         case MODE_SILENT:
-            can->BTR |= ((uint32_t)1 << 31);
-                    can->BTR &= ~((uint32_t)1 << 30);
+            can->BTR |= CAN_BTR_SILM;
+            can->BTR &= ~CAN_BTR_LBKM;
             success = 1;
             break;
         case MODE_TEST_GLOBAL:
-            can->BTR |= ((uint32_t)1 << 30);
-            can->BTR &= ~((uint32_t)1 << 31);
+        case MODE_TEST_LOCAL:
+            can->BTR |= CAN_BTR_LBKM;
+            can->BTR &= ~CAN_BTR_SILM;
             success = 1;
             break;
         case MODE_TEST_SILENT:
-            can->BTR |= (((uint32_t)1 << 31) | ((uint32_t)1 << 30));
+            can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
             success = 1;
             break;
         default:
@@ -352,7 +353,7 @@ int can_mode(can_t *obj, CanMode mode)
 
 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) 
 {
-    CanHandle.Instance = (CAN_TypeDef *)(obj->can);    
+    CanHandle.Instance = (CAN_TypeDef *)(obj->can);
     CAN_FilterConfTypeDef  sFilterConfig;
     
     sFilterConfig.FilterNumber = handle;
diff --git a/libraries/tests/mbed/can_interrupt/main.cpp b/libraries/tests/mbed/can_interrupt/main.cpp
index 3fad7ff625..17d129a46b 100644
--- a/libraries/tests/mbed/can_interrupt/main.cpp
+++ b/libraries/tests/mbed/can_interrupt/main.cpp
@@ -7,6 +7,9 @@ DigitalOut led2(LED2);
 #if defined(TARGET_LPC1549)
 // LPC1549 support only single CAN channel
 CAN can1(D2, D3);
+#elif defined(TARGET_B96B_F446VE)
+// B96B_F446VE support only single CAN channel
+CAN can1(PD_0, PD_1);
 #else
 CAN can1(p9, p10);
 #endif
@@ -36,7 +39,7 @@ void send() {
     led1 = !led1;
 }
 
-#if !defined (TARGET_LPC1549)
+#if (!defined (TARGET_LPC1549) && !defined(TARGET_B96B_F446VE))
 void read() {
     CANMessage msg;
     printf("rx()\n");
@@ -50,7 +53,7 @@ void read() {
 int main() {
     printf("main()\n");
     ticker.attach(&send, 1);
-#if !defined (TARGET_LPC1549)
+#if (!defined (TARGET_LPC1549) && !defined(TARGET_B96B_F446VE))
     can2.attach(&read);
 #endif
     while(1) {
diff --git a/libraries/tests/mbed/can_loopback/main.cpp b/libraries/tests/mbed/can_loopback/main.cpp
index 3ac87f1281..cf786597c9 100644
--- a/libraries/tests/mbed/can_loopback/main.cpp
+++ b/libraries/tests/mbed/can_loopback/main.cpp
@@ -5,6 +5,8 @@
 CAN can1(D9, D8);
 #elif defined(TARGET_LPC1768) || defined(TARGET_LPC4088)
 CAN can1(p9, p10);
+#elif defined(TARGET_B96B_F446VE)
+CAN can1(PD_0, PD_1);
 #endif
 
 #define TEST_ITERATIONS     127
diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py
index b400f63896..2e21e91ca6 100644
--- a/workspace_tools/tests.py
+++ b/workspace_tools/tests.py
@@ -283,7 +283,7 @@ TESTS = [
         "automated": True,
         "duration": 20,
         "peripherals": ["can_transceiver"],
-        "mcu": ["LPC1549", "LPC1768"],
+        "mcu": ["LPC1549", "LPC1768","B96B_F446VE"],
     },
     {
         "id": "MBED_BLINKY", "description": "Blinky",
@@ -554,13 +554,13 @@ TESTS = [
         "id": "MBED_29", "description": "CAN network test",
         "source_dir": join(TEST_DIR, "mbed", "can"),
         "dependencies": [MBED_LIBRARIES],
-        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H"]
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE"]
     },
     {
         "id": "MBED_30", "description": "CAN network test using interrupts",
         "source_dir": join(TEST_DIR, "mbed", "can_interrupt"),
         "dependencies": [MBED_LIBRARIES],
-        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H"]
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE"]
     },
     {
         "id": "MBED_31", "description": "PWM LED test",

From a58480e9eb2e26ec348d1c3e929cc6c9231460b5 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 29 Jan 2016 14:20:51 +0100
Subject: [PATCH 03/78] [B96B_F446VE] Add the target for can test

---
 libraries/tests/mbed/can/main.cpp | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/libraries/tests/mbed/can/main.cpp b/libraries/tests/mbed/can/main.cpp
index a05321a907..56ebc1f694 100644
--- a/libraries/tests/mbed/can/main.cpp
+++ b/libraries/tests/mbed/can/main.cpp
@@ -7,6 +7,9 @@ DigitalOut led2(LED2);
 #if defined(TARGET_LPC1549)
 // LPC1549 support only single CAN channel
 CAN can1(D2, D3);
+#elif defined(TARGET_B96B_F446VE)
+// B96B_F446VE support only single CAN channel
+CAN can1(PD_0, PD_1);
 #else
 CAN can1(p9, p10);
 #endif
@@ -41,8 +44,8 @@ int main() {
     ticker.attach(&send, 1);
     CANMessage msg;
     while(1) {
-#if !defined(TARGET_LPC1549)
-        printf("loop()\n");
+#if (!defined (TARGET_LPC1549) && !defined(TARGET_B96B_F446VE))
+      printf("loop()\n");
         if(can2.read(msg)) {
             printmsg("Rx message:", &msg);
             led2 = !led2;

From c11325e11bf00fd0a8de3fc535baa3218ef7627d Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 1 Feb 2016 10:13:29 +0100
Subject: [PATCH 04/78] [B96B_F446VE] add IRQ_RX1 interrupt

Can contains 2 fifos. Both generates its own interrupt.
IRQ_RX occurs when a message has arrived in FIFO-0 , FIFO-0 is full or
overrun.
IRQ_RX1 occurs when a message has arrived in FIFO-1 , FIFO-1 is full or
overrun.
---
 libraries/mbed/hal/can_api.h                                   | 2 +-
 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/hal/can_api.h b/libraries/mbed/hal/can_api.h
index be205e3f44..bdf259a35d 100644
--- a/libraries/mbed/hal/can_api.h
+++ b/libraries/mbed/hal/can_api.h
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
+ * Copyright (c) 2006-2016 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
index 57712c76cd..e931c290bf 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
+ * Copyright (c) 2006-2016 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

From 27caef30a468dc69cd11d64ba026a97af9ac56e9 Mon Sep 17 00:00:00 2001
From: tomoyuki yamanaka <tomoyuki.yamanaka.xd@renesas.com>
Date: Mon, 15 Feb 2016 14:49:31 +0900
Subject: [PATCH 05/78] Support of export function to the IAR.

We modified the following to support the export function to the IAR.
- In tools files, add RZ_A1H to the target of IAR.
- In tools files, add the tmpl files.
---
 .../inc/devdrv_usb_function_api.h             |    4 +-
 libraries/USBHost/USBHost/USBEndpoint.cpp     |    4 +-
 libraries/USBHost/USBHost/USBHost.cpp         |    2 +-
 libraries/USBHost/USBHost/USBHostTypes.h      |    4 +-
 .../TARGET_RZ_A1H/TOOLCHAIN_IAR/MBRZA1H.icf   |   62 +
 .../TOOLCHAIN_IAR/startup_RZA1H.s             |  505 +++
 .../TARGET_RZ_A1H/mbed_sf_boot.c              |    2 +
 .../TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c         |   51 +
 .../TARGET_RZ_A1H/system_MBRZA1H.c            |   34 +
 .../TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s     |   97 +
 libraries/mbed/targets/cmsis/core_ca9.h       |    5 +
 libraries/mbed/targets/cmsis/core_caFunc.h    |  243 +-
 .../TARGET_RZ_A1H/ethernet_api.c              |   23 +-
 .../TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c |   36 +
 .../TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c  |    4 +
 .../rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h     |  147 +-
 .../TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c   |   46 +
 .../TOOLCHAIN_IAR/HAL_CA9_asm.s               |  480 +++
 .../TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S |   57 +
 libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h |    2 +-
 .../rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h      |   24 +-
 .../rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c      |    9 +
 .../rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h     |   17 +
 workspace_tools/export/iar.py                 |    1 +
 workspace_tools/export/iar_rz_a1h.ewd.tmpl    | 2733 +++++++++++++++++
 workspace_tools/export/iar_rz_a1h.ewp.tmpl    | 1840 +++++++++++
 workspace_tools/export_test.py                |    1 +
 workspace_tools/targets.py                    |    2 +-
 28 files changed, 6411 insertions(+), 24 deletions(-)
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/MBRZA1H.icf
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/startup_RZA1H.s
 create mode 100644 libraries/mbed/targets/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
 create mode 100644 libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c
 create mode 100644 libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
 create mode 100644 libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S
 create mode 100644 workspace_tools/export/iar_rz_a1h.ewd.tmpl
 create mode 100644 workspace_tools/export/iar_rz_a1h.ewp.tmpl

diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
index d319e60f30..2d1b0495f3 100644
--- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
+++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
@@ -334,8 +334,8 @@ void     usb1_function_Vendor4(uint16_t type, uint16_t req, uint16_t value, uint
 void     usb1_function_Vendor5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
 void     usb1_function_ResetDescriptor(uint16_t mode);
 
-uint16_t Userdef_USB_usb1_function_d0fifo_dmaintid(void);
-uint16_t Userdef_USB_usb1_function_d1fifo_dmaintid(void);
+IRQn_Type Userdef_USB_usb1_function_d0fifo_dmaintid(void);
+IRQn_Type Userdef_USB_usb1_function_d1fifo_dmaintid(void);
 void     Userdef_USB_usb1_function_attach(void);
 void     Userdef_USB_usb1_function_detach(void);
 void     Userdef_USB_usb1_function_delay_1ms(void);
diff --git a/libraries/USBHost/USBHost/USBEndpoint.cpp b/libraries/USBHost/USBHost/USBEndpoint.cpp
index fc372232f3..6e07421855 100644
--- a/libraries/USBHost/USBHost/USBEndpoint.cpp
+++ b/libraries/USBHost/USBHost/USBEndpoint.cpp
@@ -140,7 +140,7 @@ void USBEndpoint::queueTransfer()
 
     //Now add this free TD at this end of the queue
     state = USB_TYPE_PROCESSING;
-    td_current->nextTD = td_next;
+    td_current->nextTD = (hcTd*)td_next;
     hced->tailTD = td_next;
 }
 
@@ -158,5 +158,5 @@ void USBEndpoint::unqueueTransfer(volatile HCTD * td)
 void USBEndpoint::queueEndpoint(USBEndpoint * ed)
 {
     nextEp = ed;
-    hced->nextED = (ed == NULL) ? 0 : ed->getHCED();
+    hced->nextED = (ed == NULL) ? 0 : (hcEd*)(ed->getHCED());
 }
diff --git a/libraries/USBHost/USBHost/USBHost.cpp b/libraries/USBHost/USBHost/USBHost.cpp
index d05486db91..d8b5c450e9 100644
--- a/libraries/USBHost/USBHost/USBHost.cpp
+++ b/libraries/USBHost/USBHost/USBHost.cpp
@@ -304,7 +304,7 @@ void USBHost::transferCompleted(volatile uint32_t addr)
     do {
         volatile HCTD* td = (volatile HCTD*)addr;
         addr = (uint32_t)td->nextTD; //Dequeue from physical list
-        td->nextTD = tdList; //Enqueue into reversed list
+        td->nextTD = (hcTd*)tdList; //Enqueue into reversed list
         tdList = td;
     } while(addr);
 
diff --git a/libraries/USBHost/USBHost/USBHostTypes.h b/libraries/USBHost/USBHost/USBHostTypes.h
index c4462aa052..23daefaf55 100644
--- a/libraries/USBHost/USBHost/USBHostTypes.h
+++ b/libraries/USBHost/USBHost/USBHostTypes.h
@@ -136,10 +136,10 @@ enum ENDPOINT_TYPE {
 #define CONFIGURATION_DESCRIPTOR_LENGTH     0x09
 
 // ------------ HostController Transfer Descriptor ------------
-typedef struct HCTD {
+typedef struct hcTd {
     __IO  uint32_t   control;        // Transfer descriptor control
     __IO  uint8_t *  currBufPtr;    // Physical address of current buffer pointer
-    __IO  HCTD *     nextTD;         // Physical pointer to next Transfer Descriptor
+    __IO  hcTd *     nextTD;         // Physical pointer to next Transfer Descriptor
     __IO  uint8_t *  bufEnd;        // Physical address of end of buffer
     void * ep;                      // ep address where a td is linked in
     uint32_t dummy[3];              // padding
diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/MBRZA1H.icf b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/MBRZA1H.icf
new file mode 100644
index 0000000000..ebe95c51ec
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/MBRZA1H.icf
@@ -0,0 +1,62 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x18004000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x18000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x187FFFFF;
+define symbol __ICFEDIT_region_TTB_start__   = 0x20000000;
+define symbol __ICFEDIT_region_TTB_end__     = 0x2001FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20020000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x209FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x00004000;
+define symbol __ICFEDIT_size_svcstack__ = 0x00008000;
+define symbol __ICFEDIT_size_irqstack__ = 0x00008000;
+define symbol __ICFEDIT_size_fiqstack__ = 0x00000100;
+define symbol __ICFEDIT_size_undstack__ = 0x00000100;
+define symbol __ICFEDIT_size_abtstack__ = 0x00000100;
+define symbol __ICFEDIT_size_heap__     = 0x00080000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__       = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__         = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__    = 0x60900000;
+define symbol __ICFEDIT_region_MirrorRAM_end__      = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__   = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region ROM_region          = mem:[from __ICFEDIT_region_ROM_start__          to __ICFEDIT_region_ROM_end__];
+define region RAM_region          = mem:[from __ICFEDIT_region_RAM_start__          to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region       = mem:[from __ICFEDIT_region_RetRAM_start__       to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region    = mem:[from __ICFEDIT_region_MirrorRAM_start__    to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { section MMU_TT };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in RAM_region     { readwrite,
+                          block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                          block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region       { section .retram };
+place in MirrorRAM_region    { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/startup_RZA1H.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/startup_RZA1H.s
new file mode 100644
index 0000000000..451f8e032f
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/startup_RZA1H.s
@@ -0,0 +1,505 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION SVC_STACK:DATA:NOROOT(3)
+        SECTION IRQ_STACK:DATA:NOROOT(3)
+        SECTION ABT_STACK:DATA:NOROOT(3)
+        SECTION FIQ_STACK:DATA:NOROOT(3)
+        SECTION UND_STACK:DATA:NOROOT(3)
+        SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        PUBLIC  __vector
+        PUBLIC  __iar_program_start
+        PUBLIC  Undefined_Handler
+        EXTERN  SWI_Handler
+        PUBLIC  Prefetch_Handler
+        PUBLIC  Abort_Handler
+        PUBLIC  IRQ_Handler
+        PUBLIC  FIQ_Handler
+        EXTERN  VbarInit
+        EXTERN  SetLowVectors
+        EXTERN  init_TTB
+        EXTERN  enable_mmu
+        EXTERN  Peripheral_BasicInit
+        EXTERN  initsct
+        EXTERN  PowerON_Reset
+        PUBLIC  FPUEnable
+        
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+__vector:                       ; Make this a DATA label, so that stack usage
+                                ; analysis doesn't consider it an uncalled fun
+
+        ARM
+
+        ; All default exception handlers (except reset) are
+        ; defined as weak symbol definitions.
+        ; If a handler is defined by the application it will take precedence.
+        LDR     PC,Reset_Addr           ; Reset
+        LDR     PC,Undefined_Addr       ; Undefined instructions
+        LDR     PC,SWI_Addr             ; Software interrupt (SWI/SVC)
+        LDR     PC,Prefetch_Addr        ; Prefetch abort
+        LDR     PC,Abort_Addr           ; Data abort
+        DCD     0                       ; RESERVED
+        LDR     PC,IRQ_Addr             ; IRQ
+        LDR     PC,FIQ_Addr             ; FIQ
+
+        DATA
+
+Reset_Addr:     DCD   __iar_program_start
+Undefined_Addr: DCD   Undefined_Handler
+SWI_Addr:       DCD   SWI_Handler
+Prefetch_Addr:  DCD   Prefetch_Handler
+Abort_Addr:     DCD   Abort_Handler
+IRQ_Addr:       DCD   IRQ_Handler
+FIQ_Addr:       DCD   FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+        SECTION .text:CODE:NOROOT(2)
+        EXTERN  RZ_A1_SetSramWriteEnable
+        EXTERN  create_translation_table
+        EXTERN  SystemInit
+        EXTERN  InitMemorySubsystem
+        EXTERN  __cmain
+        REQUIRE __vector
+        EXTWEAK __iar_init_core
+        EXTWEAK __iar_init_vfp
+
+
+        ARM
+
+__iar_program_start:
+?cstartup:
+
+
+;;;    @ Put any cores other than 0 to sleep
+    mrc     p15, 0, r0, c0, c0, 5   ;;; @ Read MPIDR
+    ands    r0, r0, #3
+    
+goToSleep:
+    wfine
+    bne     goToSleep
+
+
+//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 
+//@ Enables Full Access i.e. in both privileged and non privileged modes 
+    mrc     p15, 0, r0, c1, c0, 2       ;@ Read Coprocessor Access Control Register (CPACR) 
+    orr     r0, r0, #(0xF << 20)        ;@ Enable access to CP 10 & 11 
+    mcr     p15, 0, r0, c1, c0, 2       ;@ Write Coprocessor Access Control Register (CPACR) 
+    isb
+   
+   
+;; Switch on the VFP and NEON hardware 
+    mov     r0, #0x40000000
+    vmsr    fpexc, r0                   ;@ Write FPEXC register, EN bit set 
+
+    mrc     p15, 0, r0, c1, c0, 0       ;@ Read CP15 System Control register 
+    bic     r0, r0, #(0x1 << 12)        ;@ Clear I bit 12 to disable I Cache 
+    bic     r0, r0, #(0x1 <<  2)        ;@ Clear C bit  2 to disable D Cache 
+    bic     r0, r0, #0x1                ;@ Clear M bit  0 to disable MMU 
+    bic     r0, r0, #(0x1 << 11)        ;@ Clear Z bit 11 to disable branch prediction 
+    bic     r0, r0, #(0x1 << 13)        ;@ Clear V bit 13 to disable hivecs 
+    mcr     p15, 0, r0, c1, c0, 0       ;@ Write value back to CP15 System Control register 
+    isb
+  
+  
+;; Set Vector Base Address Register (VBAR) to point to this application's vector table
+    ldr     r0, =__vector
+    mcr     p15, 0, r0, c12, c0, 0
+    
+    
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F            ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10            ; User mode
+#define FIQ_MODE 0x11            ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12            ; Interrupt Request mode
+#define SVC_MODE 0x13            ; Supervisor mode
+#define ABT_MODE 0x17            ; Abort mode
+#define UND_MODE 0x1B            ; Undefined Instruction mode
+#define SYS_MODE 0x1F            ; System mode
+
+#define Mode_SVC  0x13
+#define Mode_ABT  0x17
+#define Mode_UND  0x1B
+#define GICI_BASE 0xe8202000
+#define ICCIAR_OFFSET   0x0000000C
+#define ICCEOIR_OFFSET  0x00000010
+#define ICCHPIR_OFFSET  0x00000018
+#define GICD_BASE       0xe8201000
+#define GIC_ERRATA_CHECK_1 0x000003FE 
+#define GIC_ERRATA_CHECK_2 0x000003FF 
+#define ICDABR0_OFFSET  0x00000300
+#define ICDIPR0_OFFSET  0x00000400
+#define T_Bit           0x20     ; when T bit is set, core is in Thumb state 
+
+        MRS     r0, cpsr                ; Original PSR value
+
+        ;; Set up the SVC stack pointer.        
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #SVC_MODE       ; Set SVC mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(SVC_STACK)     ; End of SVC_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the fast interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #FIQ_MODE       ; Set FIR mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(FIQ_STACK)     ; End of FIQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+
+        ;; Set up the ABT stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #ABT_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(ABT_STACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+
+        ;; Set up the UDF stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #UND_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(UND_STACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+        
+        ;; Set up the normal stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #SYS_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(CSTACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+;;;
+
+    isb
+    ldr     r0, =RZ_A1_SetSramWriteEnable
+    blx     r0
+
+    bl      create_translation_table 
+
+;  USR/SYS stack pointer will be set during kernel init
+    ldr     r0, =SystemInit
+    blx     r0
+    ldr     r0, =InitMemorySubsystem
+    blx     r0
+
+; fp_init
+    mov      r0, #0x3000000
+    vmsr     fpscr, r0
+    
+    
+
+;;; Continue to __cmain for C-level initialization.
+
+          FUNCALL __iar_program_start, __cmain
+        B       __cmain
+
+
+    ldr     r0, sf_boot     ;@ dummy to keep boot loader area
+loop_here:
+    b       loop_here
+
+sf_boot: 
+    DC32   0x00000001
+
+Undefined_Handler:
+                EXTERN CUndefHandler
+                SRSDB   SP!, #Mode_UND
+                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
+
+                MRS     R0, SPSR
+                TST     R0, #T_Bit                /* Check mode */
+                MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
+                MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
+                SUB     R0, LR, R1
+                LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
+                BEQ     undef_cont
+
+                /* Thumb instruction */
+                /* Determine if it is a 32-bit Thumb instruction */
+                LDRH    R0, [R0]
+                MOV     R2, #0x1c
+                CMP     R2, R0, LSR #11
+                BHS     undef_cont                /* 16-bit Thumb instruction */
+
+                /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
+                LDRH    R2, [LR]
+                ORR     R0, R2, R0, LSL #16
+undef_cont:
+                MOV     R2, LR                    /* Set LR to third argument */
+                
+/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
+                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               /* Adjust stack */
+                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
+
+                /* R0 Offending instruction */
+                /* R1 =2 (Thumb) or =4 (ARM) */
+                BL      CUndefHandler
+
+                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
+                ADD     SP, SP, R12               /* Unadjust stack */
+
+                LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
+                SUB     LR, LR, R0
+                LDR     R0, [SP, #28]             /* Restore stacked SPSR */
+                MSR     SPSR_cxsf, R0
+                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
+                ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
+                MOVS    PC, LR
+ 
+Prefetch_Handler:
+                EXTERN CPAbtHandler
+                SUB     LR, LR, #4                /* Pre-adjust LR */
+                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
+                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
+                MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
+                MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
+
+                MOV     R2, LR                    /* Set LR to third argument */
+
+/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
+                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               /* Adjust stack */
+                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
+
+                BL      CPAbtHandler
+
+                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
+                ADD     SP, SP, R12               /* Unadjust stack */
+
+                POP     {R0-R4, R12}              /* Restore stack APCS registers */
+                RFEFD   SP!                       /* Return from exception */
+
+Abort_Handler:
+                EXTERN CDAbtHandler
+                SUB     LR, LR, #8                /* Pre-adjust LR */
+                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
+                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
+                CLREX                             /* State of exclusive monitors unknown after taken data abort */
+                MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
+                MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
+
+                MOV     R2, LR                    /* Set LR to third argument */
+
+/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
+                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               /* Adjust stack */
+                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
+
+                BL      CDAbtHandler
+
+                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
+                ADD     SP, SP, R12               /* Unadjust stack */
+
+                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
+                RFEFD   SP!                       /* Return from exception */
+
+FIQ_Handler:
+    /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+     * so if a real FIQ Handler is implemented, this will be needed before returning:
+     */
+    /* LDR     R1, =GICI_BASE
+    LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+     */
+    B       .
+ 
+    EXTERN SVC_Handler                 /* refer RTX function */
+
+IRQ_Handler: 
+                EXTERN IRQCount
+                EXTERN IRQTable
+                EXTERN IRQNestLevel
+
+                /* prologue */
+                SUB     LR, LR, #4                  /* Pre-adjust LR */
+                SRSDB   SP!, #Mode_SVC              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
+                CPS     #Mode_SVC                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
+                PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
+
+/*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
+                MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
+                AND     R1, R3, #4
+                SUB     SP, SP, R1                  /* Adjust stack */
+                PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
+
+                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
+                LDR     R1, [R0]
+                ADD     R1, R1, #1                  /* Increment nesting counter */
+                STR     R1, [R0]
+
+                /* identify and acknowledge interrupt */
+                LDR     R1, =GICI_BASE
+                LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
+                LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
+                DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
+
+                /* Workaround GIC 390 errata 733075
+                 * If the ID is not 0, then service the interrupt as normal.
+                 * If the ID is 0 and active, then service interrupt ID 0 as normal.
+                 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+                 *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
+                 */
+                LDR     R2, =GICD_BASE
+                LDR     R3, =GIC_ERRATA_CHECK_1
+                CMP     R0, R3
+                BEQ     unlock_cpu
+                LDR     R3, =GIC_ERRATA_CHECK_2
+                CMP     R0, R3
+                BEQ     unlock_cpu
+                CMP     R0, #0
+                BNE     int_active                  /* If the ID is not 0, then service the interrupt */
+                LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
+                TST     R3, #1
+                BNE     int_active                  /* If active, then service the interrupt */
+unlock_cpu:
+                LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
+                STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
+                DSB                                 /* Ensure the write completes before continuing */
+                B       ret_irq                     /* Do not service the spurious interrupt */
+                /* End workaround */
+
+int_active:
+                LDR     R2, =IRQCount               /* Read number of IRQs */
+                LDR     R2, [R2]
+                CMP     R0, R2                      /* Clean up and return if no handler */
+                BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
+                LDR     R2, =IRQTable               /* Get address of handler */
+                LDR     R2, [R2, R0, LSL #2]
+                CMP     R2, #0                      /* Clean up and return if handler address is 0 */
+                BEQ     ret_irq
+                PUSH    {R0,R1}
+
+                CPSIE   i                           /* Now safe to re-enable interrupts */
+                BLX     R2                          /* Call handler. R0 will be IRQ number */
+                CPSID   i                           /* Disable interrupts again */
+
+                /* write EOIR (GIC CPU Interface register) */
+                POP     {R0,R1}
+                DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
+ret_irq:
+                /* epilogue */
+                STR     R0, [R1, #ICCEOIR_OFFSET]
+
+                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
+                LDR     R1, [R0]
+                SUB     R1, R1, #1                  /* Decrement nesting counter */
+                STR     R1, [R0]
+
+                POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
+                ADD     SP, SP, R1                  /* Unadjust stack */
+
+                POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
+                RFEFD   SP!                         /* Return from exception */
+;;;
+;;; Add more initialization here
+;;;
+FPUEnable:
+        ARM
+
+        //Permit access to VFP registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Enable VFP
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP registers to 0
+        MOV     R2,#0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+
+  END
diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
index 59e3da598e..4d254a21c4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
+++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
@@ -30,6 +30,8 @@
 #pragma arm section rodata = "BOOT_LOADER"
 const char boot_loader[]  __attribute__((used)) =
 
+#elif defined (__ICCARM__)
+__root const char boot_loader[] @ 0x18000000 =
 #else
 const char boot_loader[]  __attribute__ ((section(".boot_loader"), used)) =
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
index 16c0cc0c8e..5ef7ab3658 100644
--- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
+++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
@@ -71,8 +71,12 @@ extern uint32_t Image$$VECTORS$$Base;
 extern uint32_t Image$$RO_DATA$$Base;
 extern uint32_t Image$$RW_DATA$$Base;
 extern uint32_t Image$$ZI_DATA$$Base;
+#if !defined ( __ICCARM__ )
 extern uint32_t Image$$TTB$$ZI$$Base;
+#endif 
+
 #if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
 #else
 extern uint32_t Image$$RW_DATA_NC$$Base;
 extern uint32_t Image$$ZI_DATA_NC$$Base;
@@ -88,10 +92,18 @@ extern uint32_t Image$$RW_DATA_NC$$Limit;
 extern uint32_t Image$$ZI_DATA_NC$$Limit;
 #endif
 
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE    (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
+#else
 #define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
 #define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
 #define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
 #define ZI_DATA_SIZE    (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
+#endif
+
 #if defined( __CC_ARM )
 #else
 #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
@@ -112,10 +124,37 @@ static uint32_t Page_L1_64k = 0x0;  //generic
 static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
 
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$ZI_DATA$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$ZI_DATA$$Limit;
+#endif
+
 void create_translation_table(void)
 {
     mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
 
+    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
+    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+    Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");  
+    Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
     /*
      * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
      *
@@ -157,13 +196,25 @@ void create_translation_table(void)
     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
 
+#if defined( __ICCARM__ )
+    //Define Image
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#else
     //Define Image
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#endif
+
 #if defined( __CC_ARM )
     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ ) 
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
+
 #else
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
index 37fc9196c9..a07f8c4bc8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
+++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
@@ -133,6 +133,40 @@ void InitMemorySubsystem(void) {
        PL310_Enable(); 
     } 
 } 
+#elif defined ( __ICCARM__ )
+
+void InitMemorySubsystem(void) { 
+ 
+    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
+     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
+     * You are not required to invalidate the main TLB, even though it is recommended for safety 
+     * reasons. This ensures compatibility with future revisions of the processor. */ 
+ 
+    unsigned int l2_id; 
+ 
+    /* Invalidate undefined data */ 
+    __ca9u_inv_tlb_all(); 
+    __v7_inv_icache_all(); 
+    __v7_inv_dcache_all(); 
+    __v7_inv_btac(); 
+ 
+    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
+     * invalidate in order to flush the valid data to the next level cache. 
+     */ 
+    __enable_mmu();
+ 
+    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
+    __enable_caches(); 
+    __enable_btac(); 
+ 
+    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
+    l2_id = PL310_GetID(); 
+    if (l2_id) 
+    { 
+       PL310_InvAllByWay(); 
+       PL310_Enable(); 
+    } 
+} 
 #else 
 
 #endif 
diff --git a/libraries/mbed/targets/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s b/libraries/mbed/targets/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
new file mode 100644
index 0000000000..00352787a2
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
@@ -0,0 +1,97 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    SECTION `.text`:CODE:NOROOT(2)
+    arm 
+    PUBLIC __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+
+__v7_all_cache:
+
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+ 
diff --git a/libraries/mbed/targets/cmsis/core_ca9.h b/libraries/mbed/targets/cmsis/core_ca9.h
index bae5f6508e..c7c402d750 100644
--- a/libraries/mbed/targets/cmsis/core_ca9.h
+++ b/libraries/mbed/targets/cmsis/core_ca9.h
@@ -89,6 +89,11 @@
   #define __STATIC_INLINE  static inline
   #define __STATIC_ASM     static __asm
 
+#include <stdint.h>
+inline uint32_t __get_PSR(void) {
+	__ASM("mrs r0, cpsr");
+}
+
 #elif defined ( __TMS470__ )
   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
   #define __STATIC_INLINE  static inline
diff --git a/libraries/mbed/targets/cmsis/core_caFunc.h b/libraries/mbed/targets/cmsis/core_caFunc.h
index 76cf80bace..9c1a37536a 100644
--- a/libraries/mbed/targets/cmsis/core_caFunc.h
+++ b/libraries/mbed/targets/cmsis/core_caFunc.h
@@ -570,7 +570,248 @@ __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
 
 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
 
-#error IAR Compiler support not implemented for Cortex-A
+#define __inline inline
+
+inline static uint32_t __disable_irq_iar() {
+  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
+  __disable_irq();
+  return irq_dis;
+}
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_PSP(uint32_t topOfProcStack) {
+__asm(
+  "    ARM\n"
+//  "    PRESERVE8\n"
+
+  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
+  "    MRS     R1, CPSR \n"
+  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
+  "    MOV     SP, R0 \n"
+  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
+  "    ISB \n"
+  "    BX      LR \n");
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_CPS_USR(void) {
+__asm(
+  "    ARM \n"
+
+  "    CPS  #0x10  \n"                  // MODE_USR
+  "    BX   LR\n");
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+
+/******************************** Cache and BTAC enable  ****************************************************/
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+// from __enable_mmu()
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
+    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+// from __enable_mmu()
+__STATIC_INLINE uint32_t __get_SCTLR() {
+	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
+	return __regSCTLR;
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_caches(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_btac(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_btac(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_icache_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+// from __v7_inv_dcache_all()
+__arm static inline void __v7_all_cache(uint32_t op) {
+__asm(
+	"        ARM \n"
+
+	"        PUSH    {R4-R11} \n"
+
+	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
+	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
+	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
+	"        BEQ     Finished\n"                   // If 0, no need to clean
+
+	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
+    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
+	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
+	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
+	"        CMP     R1, #2 \n"
+	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
+
+	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
+	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
+	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
+	"        AND     R2, R1, #7 \n"                // Extract the line length field
+	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
+	"        movw    R4, #0x3FF \n"
+	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
+	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
+	"        movw    R7, #0x7FFF \n"
+	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
+
+	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
+
+	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
+	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
+	"        CMP     R0, #0 \n"
+	"        BNE     Dccsw \n"
+	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
+	"        B       cont \n"
+	"Dccsw:   CMP     R0, #1 \n"
+	"        BNE     Dccisw \n"
+	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
+	"        B       cont \n"
+	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
+	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
+	"        BGE     Loop3 \n"
+	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
+	"        BGE     Loop2 \n"
+	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
+	"        CMP     R3, R10 \n"
+	"        BGT     Loop1 \n"
+
+	"Finished: \n"
+	"        DSB \n"
+	"        POP    {R4-R11} \n"
+	"        BX     lr \n" );
+}
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+#include "core_ca_mmu.h"
 
 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c
index 471b10ddfa..7c9b8add96 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c
@@ -60,7 +60,7 @@
 #define PHY_READ                (2)
 #define MDC_WAIT                (6)        /* 400ns/4 */
 #define BASIC_STS_MSK_LINK      (0x0004)   /* Link Status */
-#define BASIC_STS_MSK_AUTO_CMP  (0x0010)   /* Auto-Negotiate Complete */
+#define BASIC_STS_MSK_AUTO_CMP  (0x0020)   /* Auto-Negotiate Complete */
 #define M_PHY_ID                (0xFFFFFFF0)
 #define PHY_ID_LAN8710A         (0x0007C0F0)
 /* ETHERPIR0 */
@@ -106,11 +106,20 @@ typedef struct tag_edmac_recv_desc {
 /* memory */
 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
-static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+#if defined(__ICCARM__)
+#pragma data_alignment=16
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]  //16 bytes aligned!
+                                 @ ".mirrorram";
+#else
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
                                  (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
                                  (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
                                  (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
                                  __attribute((section("NC_BSS"),aligned(16)));  //16 bytes aligned!
+#endif
 static int32_t            rx_read_offset;   /* read offset */
 static int32_t            tx_wite_offset;   /* write offset */
 static uint32_t           send_top_index;
@@ -208,7 +217,7 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
     if (p_ethcfg->ether_mac != NULL) {
         (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
     } else {
-		ethernet_address(mac_addr); /* Get MAC Address */
+        ethernet_address(mac_addr); /* Get MAC Address */
     }
 
     return 0;
@@ -401,7 +410,7 @@ int ethernet_read(char *data, int dlen) {
 
 void ethernet_address(char *mac) {
     if (mac != NULL) {
-		mbed_mac_address(mac); /* Get MAC Address */
+        mbed_mac_address(mac); /* Get MAC Address */
     }
 }
 
@@ -427,8 +436,8 @@ void ethernet_set_link(int speed, int duplex) {
     if ((speed < 0) || (speed > 1)) {
         data = 0x1000;      /* Auto-Negotiation Enable */
         phy_reg_write(BASIC_MODE_CONTROL_REG, data);
-        data = phy_reg_read(BASIC_MODE_STATUS_REG);
         for (i = 0; i < 1000; i++) {
+            data = phy_reg_read(BASIC_MODE_STATUS_REG);
             if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
                 break;
             }
@@ -486,8 +495,8 @@ static void lan_desc_create(void) {
     int32_t i;
     uint8_t *p_memory_top;
 
-    (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory));
-    p_memory_top = ehernet_nc_memory;
+    (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
+    p_memory_top = ethernet_nc_memory;
 
     /* Descriptor area configuration */
     p_eth_desc_dsend  = (edmac_send_desc_t *)p_memory_top;
diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
index 56c306e70a..1c95b190f9 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
@@ -512,7 +512,11 @@ int serial_getc(serial_t *obj) {
     int data;
     int was_masked;
 
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     if (obj->uart->SCFSR & 0x93) {
         err_read = obj->uart->SCFSR;
         obj->uart->SCFSR = (err_read & ~0x93);
@@ -529,7 +533,11 @@ int serial_getc(serial_t *obj) {
     while (!serial_readable(obj));
     data = obj->uart->SCFRDR & 0xff;
 
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     err_read = obj->uart->SCFSR;
     obj->uart->SCFSR = (err_read & 0xfffD);     // Clear RDF
     if (!was_masked) {
@@ -546,14 +554,22 @@ void serial_putc(serial_t *obj, int c) {
     uint16_t dummy_read;
     int was_masked;
 
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     obj->uart->SCSCR |= 0x0080;     // Set TIE
     if (!was_masked) {
         __enable_irq();
     }
     while (!serial_writable(obj));
     obj->uart->SCFTDR = c;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     dummy_read = obj->uart->SCFSR;
     obj->uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
     if (!was_masked) {
@@ -572,7 +588,11 @@ int serial_writable(serial_t *obj) {
 
 void serial_clear(serial_t *obj) {
     int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
 
     obj->uart->SCFCR |=  0x06;          // TFRST = 1, RFRST = 1
     obj->uart->SCFCR &= ~0x06;          // TFRST = 0, RFRST = 0
@@ -589,7 +609,11 @@ void serial_pinout_tx(PinName tx) {
 
 void serial_break_set(serial_t *obj) {
     int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     // TxD Output(L)
     obj->uart->SCSPTR &= ~0x0001u;  // SPB2DT = 0
     obj->uart->SCSCR &= ~0x0020u;   // TE = 0 (Output disable)
@@ -600,7 +624,11 @@ void serial_break_set(serial_t *obj) {
 
 void serial_break_clear(serial_t *obj) {
     int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
     was_masked = __disable_irq();
+#endif /* __ICCARM__ */
     obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
     obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
     if (!was_masked) {
@@ -615,7 +643,11 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
     serial_flow_irq_set(obj, 0);
 
     if (type == FlowControlRTSCTS) {
+#if defined ( __ICCARM__ )
+        was_masked = __disable_irq_iar();
+#else
         was_masked = __disable_irq();
+#endif /* __ICCARM__ */
         obj->uart->SCFCR = 0x0008u;   // CTS/RTS enable
         if (!was_masked) {
             __enable_irq();
@@ -623,7 +655,11 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
         pinmap_pinout(rxflow, PinMap_UART_RTS);
         pinmap_pinout(txflow, PinMap_UART_CTS);
     } else {
+#if defined ( __ICCARM__ )
+        was_masked = __disable_irq_iar();
+#else
         was_masked = __disable_irq();
+#endif /* __ICCARM__ */
         obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
         if (!was_masked) {
             __enable_irq();
diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c
index 46ff8cefb0..70be974cd9 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c
@@ -85,7 +85,11 @@ uint32_t us_ticker_read() {
     uint64_t us_val64;
     int check_irq_masked;
 
+#if defined ( __ICCARM__)
+    check_irq_masked = __disable_irq_iar();
+#else
     check_irq_masked = __disable_irq();
+#endif /* __ICCARM__ */
 
     cnt_val64        = ticker_read_counter64();
     us_val64         = (cnt_val64 / count_clock);
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
index 13cee6613f..79a4adf8bb 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
@@ -76,6 +76,62 @@ extern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);
 OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex)                   __svc_indirect(0);
 OS_RESULT _os_mut_wait    (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);
 
+#elif defined (__ICCARM__)
+
+typedef void    *OS_ID;
+typedef uint32_t OS_TID;
+typedef uint32_t OS_MUT[4];
+typedef uint32_t OS_RESULT;
+
+#define runtask_id()    rt_tsk_self()
+#define mutex_init(m)   rt_mut_init(m)
+#define mutex_del(m)    os_mut_delete(m)
+#define mutex_wait(m)   os_mut_wait(m,0xFFFF)
+#define mutex_rel(m)    os_mut_release(m)
+
+extern OS_TID    rt_tsk_self    (void);
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_delete  (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_delete  (OS_ID mutex);
+
+static inline OS_RESULT os_mut_delete(OS_ID mutex)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_delete) : "r12" );
+    return _os_mut_delete(mutex);
+}
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_release (OS_ID mutex);
+
+static inline OS_RESULT os_mut_release(OS_ID mutex)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_release) : "r12" );
+    return _os_mut_release(mutex);
+}
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+static inline OS_RESULT os_mut_wait(OS_ID mutex, uint16_t timeout)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_wait) : "r12" );
+    return _os_mut_wait(mutex, timeout);
+}
+
+#include <yvals.h> /* for include DLib_Thread.h */
+
+void __iar_system_Mtxinit(__iar_Rmtx *);
+void __iar_system_Mtxdst(__iar_Rmtx *);
+void __iar_system_Mtxlock(__iar_Rmtx *);
+void __iar_system_Mtxunlock(__iar_Rmtx *);
+
+
+
+
 #endif
 
 
@@ -174,6 +230,14 @@ uint16_t const mp_tmr_size = 0;
  static OS_MUT   std_libmutex[OS_MUTEXCNT];
  static uint32_t nr_mutex;
  extern void  *__libspace_start;
+#elif defined (__ICCARM__)
+typedef struct os_mut_array {
+    OS_MUT   mutex;
+    uint32_t used;
+} os_mut_array_t;
+
+static os_mut_array_t std_libmutex[OS_MUTEXCNT];/* must be Zero clear */
+static uint32_t nr_mutex = 0;
 #endif
 
 
@@ -247,6 +311,82 @@ __attribute__((used)) void _mutex_release (OS_ID *mutex) {
   }
 }
 
+#elif defined (__ICCARM__)
+
+/*--------------------------- __iar_system_Mtxinit --------------------------*/
+
+void __iar_system_Mtxinit(__iar_Rmtx *mutex)
+{
+    /* Allocate and initialize a system mutex. */
+    int32_t idx;
+
+    for (idx = 0; idx < OS_MUTEXCNT; idx++)
+    {
+        if (std_libmutex[idx].used == 0)
+        {
+            std_libmutex[idx].used = 1;
+            *mutex = &std_libmutex[idx].mutex;
+            nr_mutex++;
+            break;
+        }
+    }
+    if (nr_mutex >= OS_MUTEXCNT)
+    {
+        /* If you are here, you need to increase the number OS_MUTEXCNT. */
+        for (;;);
+    }
+  
+    mutex_init (*mutex);
+}
+
+/*--------------------------- __iar_system_Mtxdst ---------------------------*/
+
+void __iar_system_Mtxdst(__iar_Rmtx *mutex)
+{
+    /* Free a system mutex. */
+    int32_t idx;
+
+    if (nr_mutex == 0)
+    {
+        for (;;);
+    }
+
+    idx = ((((uint32_t)mutex) - ((uint32_t)&std_libmutex[0].mutex))
+           / sizeof(os_mut_array_t));
+
+    if (idx >= OS_MUTEXCNT)
+    {
+        for (;;);
+    }
+
+    mutex_del (*mutex);
+    std_libmutex[idx].used = 0;
+}
+
+/*--------------------------- __iar_system_Mtxlock --------------------------*/
+
+void __iar_system_Mtxlock(__iar_Rmtx *mutex)
+{
+    /* Acquire a system mutex, lock stdlib resources. */
+    if (runtask_id ())
+    {
+        /* RTX running, acquire a mutex. */
+        mutex_wait (*mutex);
+    }
+}
+
+/*--------------------------- __iar_system_Mtxunlock ------------------------*/
+
+void __iar_system_Mtxunlock(__iar_Rmtx *mutex)
+{
+    /* Release a system mutex, unlock stdlib resources. */
+    if (runtask_id ())
+    {
+        /* RTX running, release a mutex. */
+        mutex_rel (*mutex);
+    }
+}
+
 #endif
 
 
@@ -388,14 +528,13 @@ __attribute__((naked)) void software_init_hook (void) {
 
 extern int  __low_level_init(void);
 extern void __iar_data_init3(void);
+extern void __iar_dynamic_initialization(void);
+extern void mbed_sdk_init(void);
 extern void exit(int arg);
 
-__noreturn __stackless void __cmain(void) {
+void mbed_main(void) {
   int a;
 
-  if (__low_level_init() != 0) {
-    __iar_data_init3();
-  }
   osKernelInitialize();
   osThreadCreate(&os_thread_def_main, NULL);
   a = osKernelStart();
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c
new file mode 100644
index 0000000000..b12326ab23
--- /dev/null
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c
@@ -0,0 +1,46 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CA9.c
+ *      Purpose: Hardware Abstraction Layer for Cortex-A9
+ *      Rev.:    23 March 2015
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2012 - 2015 ARM Limited
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+//unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+/* Functions move to HAL_CA9_asm.S */
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
new file mode 100644
index 0000000000..456f9e0a97
--- /dev/null
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
@@ -0,0 +1,480 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CA9.c
+ *      Purpose: Hardware Abstraction Layer for Cortex-A9
+ *      Rev.:    8 April 2015
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2012 - 2015 ARM Limited
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+        PUBLIC rt_set_PSP
+        PUBLIC rt_get_PSP
+        PUBLIC _alloc_box
+        PUBLIC _free_box
+        PUBLIC SWI_Handler
+        PUBLIC PendSV_Handler
+        PUBLIC OS_Tick_Handler
+
+/* macro defines form rt_HAL_CA.h */
+#define CPSR_T_BIT      0x20
+#define CPSR_I_BIT      0x80
+#define CPSR_F_BIT      0x40
+
+#define MODE_USR        0x10
+#define MODE_FIQ        0x11
+#define MODE_IRQ        0x12
+#define MODE_SVC        0x13
+#define MODE_ABT        0x17
+#define MODE_UND        0x1B
+#define MODE_SYS        0x1F
+
+/* macro defines form rt_TypeDef.h */
+#define TCB_TID          3        /* 'task id' offset                        */
+#define TCB_STACKF      37        /* 'stack_frame' offset                    */
+#ifndef __LARGE_PRIV_STACK
+#define TCB_TSTACK      40        /* 'tsk_stack' offset                      */
+#else
+#define TCB_TSTACK      44        /* 'tsk_stack' offset for LARGE_STACK      */
+#endif
+
+
+        IMPORT rt_alloc_box
+        IMPORT rt_free_box
+        IMPORT os_tsk
+        IMPORT GICInterface_BASE
+        IMPORT rt_pop_req
+        IMPORT os_tick_irqack
+        IMPORT rt_systick
+
+        SECTION `.text`:CODE:ROOT(2)
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+//For A-class, set USR/SYS stack
+//__asm void rt_set_PSP (U32 stack) {
+rt_set_PSP:
+        ARM
+
+        MRS     R1, CPSR
+        CPS     #MODE_SYS   ;no effect in USR mode
+        ISB
+        MOV     SP, R0
+        MSR     CPSR_c, R1  ;no effect in USR mode
+        ISB
+        BX      LR
+
+//}
+
+//For A-class, get USR/SYS stack
+//__asm U32 rt_get_PSP (void) {
+rt_get_PSP:
+        ARM
+
+        MRS     R1, CPSR
+        CPS     #MODE_SYS   ;no effect in USR mode
+        ISB
+        MOV     R0, SP
+        MSR     CPSR_c, R1  ;no effect in USR mode
+        ISB
+        BX      LR
+//}
+
+/*--------------------------- _alloc_box ------------------------------------*/
+//__asm void *_alloc_box (void *box_mem) {
+_alloc_box:
+    /* Function wrapper for Unprivileged/Privileged mode. */
+        ARM
+
+        LDR     R12,=(rt_alloc_box)
+        MRS     R2, CPSR
+        LSLS    R2, R2,#28
+        BXNE    R12
+        SVC     0
+        BX      LR
+//}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+//__asm int _free_box (void *box_mem, void *box) {
+_free_box:
+   /* Function wrapper for Unprivileged/Privileged mode. */
+
+        LDR     R12,=(rt_free_box)
+        MRS     R2, CPSR
+        LSLS    R2, R2,#28
+        BXNE    R12
+        SVC     0
+        BX      LR
+
+//}
+
+/*-------------------------- SWI_Handler -----------------------------------*/
+
+//#pragma push
+//#pragma arm
+//__asm void SWI_Handler (void) {
+SWI_Handler:
+        PRESERVE8
+        ARM
+
+        IMPORT  rt_tsk_lock
+        IMPORT  rt_tsk_unlock
+        IMPORT  SVC_Count
+        IMPORT  SVC_Table
+        IMPORT  rt_stk_check
+        IMPORT  FPUEnable
+        IMPORT  scheduler_suspended    ; flag set by rt_suspend, cleared by rt_resume, read by SWI_Handler
+
+Mode_SVC        EQU     0x13
+
+        SRSDB   #Mode_SVC!             ; Push LR_SVC and SPRS_SVC onto SVC mode stack
+        STR     R4,[SP,#-0x4]!         ; Push R4 so we can use it as a temp
+
+        MRS     R4,SPSR                ; Get SPSR
+        TST     R4,#CPSR_T_BIT         ; Check Thumb Bit
+        LDRNEH  R4,[LR,#-2]            ; Thumb: Load Halfword
+        BICNE   R4,R4,#0xFF00          ;        Extract SVC Number
+        LDREQ   R4,[LR,#-4]            ; ARM:   Load Word
+        BICEQ   R4,R4,#0xFF000000      ;        Extract SVC Number
+
+        /* Lock out systick and re-enable interrupts */
+        STMDB   SP!,{R0-R3,R12,LR}
+
+        AND     R12, SP, #4            ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12            ; Adjust stack
+        STMDB   SP!,{R12, LR}          ; Store stack adjustment and dummy LR to SVC stack
+
+        BLX     rt_tsk_lock
+        CPSIE   i
+
+        LDMIA   SP!,{R12,LR}           ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12            ; Unadjust stack
+
+        LDMIA   SP!,{R0-R3,R12,LR}
+
+        CMP     R4,#0
+        BNE     SVC_User
+
+        MRS     R4,SPSR
+        STR     R4,[SP,#-0x4]!         ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        STMDB   SP!,{R4, LR}            ; Store stack adjustment and dummy LR
+        BLX     R12
+        LDMIA   SP!,{R4, LR}            ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        LDR     R4,[SP],#0x4            ; Restore R4
+        MSR     SPSR_CXSF,R4
+
+        /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
+Sys_Switch:
+        LDR     LR,=(os_tsk)
+        LDMIA   LR,{R4,LR}              ; os_tsk.run, os_tsk.new
+        CMP     R4,LR
+        BNE     switching
+
+        STMDB   SP!,{R0-R3,R12,LR}
+
+        AND     R12, SP, #4             ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12             ; Adjust stack
+        STMDB   SP!,{R12,LR}            ; Store stack adjustment and dummy LR to SVC stack
+
+        CPSID   i
+        ; Do not unlock scheduler if it has just been suspended by rt_suspend()
+        LDR     R1,=scheduler_suspended
+        LDRB    R0, [R1]
+        CMP     R0, #1
+        BEQ     dont_unlock
+        BLX     rt_tsk_unlock
+dont_unlock:
+
+        LDMIA   SP!,{R12,LR}            ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12             ; Unadjust stack
+
+        LDMIA   SP!,{R0-R3,R12,LR}
+        LDR     R4,[SP],#0x4
+        RFEFD   SP!                     ; Return from exception, no task switch
+
+switching:
+        CLREX
+        CMP     R4,#0
+        ADDEQ   SP,SP,#12               ; Original R4, LR & SPSR do not need to be popped when we are paging in a different task
+        BEQ     SVC_Next                ; Runtask deleted?
+
+
+        STMDB   SP!,{R8-R11} //R4 and LR already stacked
+        MOV     R10,R4                  ; Preserve os_tsk.run
+        MOV     R11,LR                  ; Preserve os_tsk.new
+
+        ADD     R8,SP,#16               ; Unstack R4,LR
+        LDMIA   R8,{R4,LR}
+
+        SUB     SP,SP,#4                ; Make space on the stack for the next instn
+        STMIA   SP,{SP}^                ; Put User SP onto stack
+        LDR     R8,[SP],#0x4            ; Pop User SP into R8
+
+        MRS     R9,SPSR
+        STMDB   R8!,{R9}                ; User CPSR
+        STMDB   R8!,{LR}                ; User PC
+        STMDB   R8,{LR}^                ; User LR
+        SUB     R8,R8,#4                ; No writeback for store of User LR
+        STMDB   R8!,{R0-R3,R12}         ; User R0-R3,R12
+        MOV     R3,R10                  ; os_tsk.run
+        MOV     LR,R11                  ; os_tsk.new
+        LDMIA   SP!,{R9-R12}
+        ADD     SP,SP,#12               ; Fix up SP for unstack of R4, LR & SPSR
+        STMDB   R8!,{R4-R7,R9-R12}      ; User R4-R11
+
+        //If applicable, stack VFP/NEON state
+        MRC     p15,0,R1,c1,c0,2        ; VFP/NEON access enabled? (CPACR)
+        AND     R2,R1,#0x00F00000
+        CMP     R2,#0x00F00000
+        BNE     no_outgoing_vfp
+        VMRS    R2,FPSCR
+        STMDB   R8!,{R2,R4}             ; Push FPSCR, maintain 8-byte alignment
+  //IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        VSTMDB  R8!,{D0-D15}
+        VSTMDB  R8!,{D16-D31}
+        LDRB    R2,[R3,#TCB_STACKF]     ; Record in TCB that NEON/D32 state is stacked
+        ORR     R2,R2,#4
+        STRB    R2,[R3,#TCB_STACKF]
+  //ENDIF
+
+no_outgoing_vfp:
+        STR     R8,[R3,#TCB_TSTACK]
+        MOV     R4,LR
+
+        STR     R4,[SP,#-0x4]!          ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        STMDB   SP!,{R4, LR}            ; Store stack adjustment and dummy LR to SVC stack
+
+        BLX     rt_stk_check
+
+        LDMIA   SP!,{R4, LR}            ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        LDR     R4,[SP],#0x4            ; Restore R4
+
+        MOV     LR,R4
+
+SVC_Next:  //R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible
+        LDR     R1,=(os_tsk)            ; os_tsk.run = os_tsk.new
+        STR     LR,[R1]
+        LDRB    R1,[LR,#TCB_TID]        ; os_tsk.run->task_id
+        LSL     R1,R1,#8                ; Store PROCID
+        MCR     p15,0,R1,c13,c0,1       ; Write CONTEXTIDR
+
+        LDR     R0,[LR,#TCB_TSTACK]     ; os_tsk.run->tsk_stack
+
+        //Does incoming task have VFP/NEON state in stack?
+        LDRB    R3,[LR,#TCB_STACKF]
+        ANDS    R3, R3, #0x6
+        MRC     p15,0,R1,c1,c0,2        ; Read CPACR
+        BICEQ   R1,R1,#0x00F00000       ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
+        ORRNE   R1,R1,#0x00F00000       ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
+        MCR     p15,0,R1,c1,c0,2        ; Write CPACR
+        BEQ     no_incoming_vfp
+        ISB                             ; We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway
+  //IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        VLDMIA  R0!,{D16-D31}
+  //ENDIF
+        VLDMIA  R0!,{D0-D15}
+        LDR     R2,[R0]
+        VMSR    FPSCR,R2
+        ADD     R0,R0,#8
+
+no_incoming_vfp:
+        LDR     R1,[R0,#60]             ; Restore User CPSR
+        MSR     SPSR_CXSF,R1
+        LDMIA   R0!,{R4-R11}            ; Restore User R4-R11
+        ADD     R0,R0,#4                ; Restore User R1-R3,R12
+        LDMIA   R0!,{R1-R3,R12}
+        LDMIA   R0,{LR}^                ; Restore User LR
+        ADD     R0,R0,#4                ; No writeback for load to user LR
+        LDMIA   R0!,{LR}                ; Restore User PC
+        ADD     R0,R0,#4                ; Correct User SP for unstacked user CPSR
+
+        STR     R0,[SP,#-0x4]!          ; Push R0 onto stack
+        LDMIA   SP,{SP}^                ; Get R0 off stack into User SP
+        ADD     SP,SP,#4                ; Put SP back
+
+        LDR     R0,[R0,#-32]            ; Restore R0
+
+        STMDB   SP!,{R0-R3,R12,LR}
+
+        AND     R12, SP, #4             ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12             ; Adjust stack
+        STMDB   sp!,{R12, LR}           ; Store stack adjustment and dummy LR to SVC stack
+
+        CPSID   i
+        BLX     rt_tsk_unlock
+
+        LDMIA   sp!,{R12, LR}           ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12             ; Unadjust stack
+
+        LDMIA   SP!,{R0-R3,R12,LR}
+
+        MOVS    PC,LR                   ; Return from exception
+
+
+        /*------------------- User SVC -------------------------------*/
+
+SVC_User:
+        LDR     R12,=SVC_Count
+        LDR     R12,[R12]
+        CMP     R4,R12                  ; Check for overflow
+        BHI     SVC_Done
+
+        LDR     R12,=SVC_Table-4
+        LDR     R12,[R12,R4,LSL #2]     ; Load SVC Function Address
+        MRS     R4,SPSR                 ; Save SPSR
+        STR     R4,[SP,#-0x4]!          ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        STMDB   SP!,{R4, LR}            ; Store stack adjustment and dummy LR
+        BLX     R12                     ; Call SVC Function
+        LDMIA   SP!,{R4, LR}            ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        LDR     R4,[SP],#0x4            ; Restore R4
+        MSR     SPSR_CXSF,R4            ; Restore SPSR
+
+SVC_Done:
+        STMDB   sp!,{R0-R3,R12,LR}
+
+        STR     R4,[sp,#-0x4]!          ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        STMDB   SP!,{R4, LR}            ; Store stack adjustment and dummy LR
+
+        CPSID   i
+        BLX     rt_tsk_unlock
+
+        LDMIA   SP!,{R4, LR}            ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        LDR     R4,[SP],#0x4            ; Restore R4
+
+        LDMIA   SP!,{R0-R3,R12,LR}
+        LDR     R4,[SP],#0x4
+        RFEFD   SP!                     ; Return from exception
+//}
+//#pragma pop
+
+//#pragma push
+//#pragma arm
+//__asm void PendSV_Handler (U32 IRQn) {
+PendSV_Handler:
+    ARM
+
+    IMPORT  rt_tsk_lock
+    IMPORT  IRQNestLevel                ; Flag indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR.
+    IMPORT  seen_id0_active             ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
+
+    ADD     SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
+
+    //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
+    STMDB   SP!,{R0, R1}
+    BLX     rt_tsk_lock
+    LDMIA   SP!,{R0, R1}
+    LDR     R1,=(GICInterface_BASE)
+    LDR     R1, [R1, #0]
+    STR     R0, [R1, #0x10]
+
+    ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
+    CMP     R0, #0
+    LDREQ   R1, =seen_id0_active
+    STRBEQ  R0, [R1]                    ; Clear the seen flag, using R0 (which is 0), to save loading another register
+
+    LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+    LDR     R1, [R0]
+    SUB     R1, R1, #1                  ; Decrement nesting counter
+    STR     R1, [R0]
+
+    BLX     (rt_pop_req)
+
+    LDMIA   SP!,{R1, LR}            ; Get stack adjustment & discard dummy LR
+    ADD     SP, SP, R1              ; Unadjust stack
+
+    LDR     R0,[SP,#24]
+    MSR     SPSR_CXSF,R0
+    LDMIA   SP!,{R0-R3,R12}         ; Leave SPSR & LR on the stack
+    STR     R4,[SP,#-0x4]!
+    B       Sys_Switch
+//}
+//#pragma pop
+
+
+//#pragma push
+//#pragma arm
+//__asm void OS_Tick_Handler (U32 IRQn) {
+OS_Tick_Handler:
+    ARM
+
+    IMPORT  rt_tsk_lock
+    IMPORT  IRQNestLevel                ; Flag indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR.
+    IMPORT  seen_id0_active             ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
+
+    ADD     SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
+
+    STMDB   SP!,{R0, R1}
+    BLX     rt_tsk_lock
+    LDMIA   SP!,{R0, R1}
+    LDR     R1, =(GICInterface_BASE)
+    LDR     R1, [R1, #0]
+    STR     R0, [R1, #0x10]
+
+    ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
+    CMP     R0, #0
+    LDREQ   R1, =seen_id0_active
+    STRBEQ  R0, [R1]                    ; Clear the seen flag, using R0 (which is 0), to save loading another register
+
+    LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+    LDR     R1, [R0]
+    SUB     R1, R1, #1                  ; Decrement nesting counter
+    STR     R1, [R0]
+
+    BLX     (os_tick_irqack)
+    BLX     (rt_systick)
+
+    LDMIA   SP!,{R1, LR}            ; Get stack adjustment & discard dummy LR
+    ADD     SP, SP, R1              ; Unadjust stack
+
+    LDR     R0,[SP,#24]
+    MSR     SPSR_CXSF,R0
+    LDMIA   SP!,{R0-R3,R12}         ; Leave SPSR & LR on the stack
+    STR     R4,[SP,#-0x4]!
+    B       Sys_Switch
+//}
+//#pragma pop
+
+
+  END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S
new file mode 100644
index 0000000000..b7f2cc8bdb
--- /dev/null
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S
@@ -0,0 +1,57 @@
+;/*----------------------------------------------------------------------------
+; *      RL-ARM - RTX
+; *----------------------------------------------------------------------------
+; *      Name:    SVC_TABLE.S
+; *      Purpose: Pre-defined SVC Table for Cortex-M
+; *      Rev.:    V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *  - Redistributions of source code must retain the above copyright
+; *    notice, this list of conditions and the following disclaimer.
+; *  - Redistributions in binary form must reproduce the above copyright
+; *    notice, this list of conditions and the following disclaimer in the
+; *    documentation and/or other materials provided with the distribution.
+; *  - Neither the name of ARM  nor the names of its contributors may be used 
+; *    to endorse or promote products derived from this software without 
+; *    specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+                SECTION SVC_TABLE:CODE:ROOT(2)
+
+                EXPORT  SVC_Count
+
+SVC_Cnt         EQU    (SVC_End-SVC_Table)/4
+SVC_Count       DCD     SVC_Cnt
+
+; Import user SVC functions here.
+;                IMPORT  __SVC_1
+
+                EXPORT  SVC_Table
+SVC_Table
+; Insert user SVC functions here. SVC 0 used by RTL Kernel.
+;                DCD     __SVC_1                 ; InitMemorySubsystem
+
+SVC_End
+
+                END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h b/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
index ae679afa7f..5ead34c993 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
@@ -143,7 +143,7 @@ used throughout the whole project.
 #define CMSIS_OS_RTX_CA          /* new define for Coretex-A */
 
 // The stack space occupied is mainly dependent on the underling C standard library
-#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD)
+#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) || defined(TOOLCHAIN_IAR)
 #    define WORDS_STACK_SIZE   512
 #elif defined(TOOLCHAIN_ARM_MICRO)
 #    define WORDS_STACK_SIZE   128
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
index 1a5fdf5cc9..a1f41223f6 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
@@ -75,8 +75,6 @@
 
 #elif defined (__ICCARM__)      /* IAR Compiler */
 
-#error IAR Compiler support not implemented for Cortex-A
-
 #endif
 
 static U8 priority = 0xff;
@@ -99,6 +97,15 @@ extern const U32 GICInterface_BASE;
 #define SGI_PENDSV_BIT  ((U32)(1 << (SGI_PENDSV & 0xf)))
 
 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
+#if defined (__ICCARM__)
+#define OS_LOCK() int irq_dis = __disable_irq_iar();\
+                  priority = GICI_ICCPMR; \
+                  GICI_ICCPMR = 0xff; \
+                  GICI_ICCPMR = GICI_ICCPMR - 1; \
+                  __DSB();\
+                  if(!irq_dis) __enable_irq(); \
+
+#else
 #define OS_LOCK() int irq_dis = __disable_irq();\
                   priority = GICI_ICCPMR; \
                   GICI_ICCPMR = 0xff; \
@@ -106,6 +113,8 @@ extern const U32 GICInterface_BASE;
                   __DSB();\
                   if(!irq_dis) __enable_irq(); \
 
+#endif
+
 //Restore priority filter. Re-enable timer and PendSV signaling
 #define OS_UNLOCK() __DSB(); \
                     GICI_ICCPMR = priority; \
@@ -133,10 +142,15 @@ extern const U32 GICInterface_BASE;
 #ifdef __USE_EXCLUSIVE_ACCESS
  #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
  #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
+#else
+#if defined (__ICCARM__)
+ #define rt_inc(p)     { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
+ #define rt_dec(p)     { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
 #else
  #define rt_inc(p)     { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
  #define rt_dec(p)     { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
-#endif
+#endif /* __ICCARM__ */
+#endif /* __USE_EXCLUSIVE_ACCESS */
 
 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
   U32 cnt,c2;
@@ -152,7 +166,11 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
   } while (__strex(c2, first));
 #else
   int irq_dis;
+ #if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+ #else
   irq_dis = __disable_irq();
+ #endif /* __ICCARM__ */
   if ((cnt = *count) < size) {
     *count = cnt+1;
     c2 = (cnt = *first) + 1;
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
index 5d0388ebbf..105d3e23b4 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
@@ -101,7 +101,12 @@ void *rt_alloc_box (void *box_mem) {
 #ifndef __USE_EXCLUSIVE_ACCESS
   int  irq_dis;
 
+
+#if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+#else
   irq_dis = __disable_irq ();
+#endif /* __ICCARM__ */
   free = ((P_BM) box_mem)->free;
   if (free) {
     ((P_BM) box_mem)->free = *free;
@@ -152,7 +157,11 @@ int rt_free_box (void *box_mem, void *box) {
   }
 
 #ifndef __USE_EXCLUSIVE_ACCESS
+#if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+#else
   irq_dis = __disable_irq ();
+#endif /* __ICCARM__ */
   *((void **)box) = ((P_BM) box_mem)->free;
   ((P_BM) box_mem)->free = box;
   if (!irq_dis) __enable_irq ();
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
index 18b45b9169..832f9ad008 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
@@ -69,8 +69,17 @@ typedef struct OS_TCB {
 
   /* Hardware dependant part: specific for Cortex processor                  */
   U8     stack_frame;             /* Stack frame: 0x0 Basic, 0x1 Extended, 0x2 VFP/D16 stacked, 0x4 NEON/D32 stacked */
+#if defined (__ICCARM__)
+#ifndef __LARGE_PRIV_STACK
+  U16    priv_stack;              /* Private stack size, 0= system assigned  */
+#else
   U16    reserved;                /* Reserved (padding)                      */
   U32    priv_stack;              /* Private stack size for LARGE_STACK, 0= system assigned  */
+#endif /* __LARGE_PRIV_STACK */
+#else
+  U16    reserved;                /* Reserved (padding)                      */
+  U32    priv_stack;              /* Private stack size for LARGE_STACK, 0= system assigned  */
+#endif
   U32    tsk_stack;               /* Current task Stack pointer (R13)        */
   U32    *stack;                  /* Pointer to Task Stack memory block      */
 
@@ -79,7 +88,15 @@ typedef struct OS_TCB {
 } *P_TCB;
 #define TCB_TID          3        /* 'task id' offset                        */
 #define TCB_STACKF      37        /* 'stack_frame' offset                    */
+#if defined (__ICCARM__)
+#ifndef __LARGE_PRIV_STACK
+#define TCB_TSTACK      40        /* 'tsk_stack' offset                      */
+#else
 #define TCB_TSTACK      44        /* 'tsk_stack' offset for LARGE_STACK      */
+#endif /* __LARGE_PRIV_STACK */
+#else
+#define TCB_TSTACK      44        /* 'tsk_stack' offset for LARGE_STACK      */
+#endif
 
 typedef struct OS_PSFE {          /* Post Service Fifo Entry                 */
   void  *id;                      /* Object Identification                   */
diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 87b9cb3739..50d64f5a6e 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -87,6 +87,7 @@ class IAREmbeddedWorkbench(Exporter):
         'ARCH_BLE',
         'MOTE_L152RC',
         'EFM32PG_STK3401',
+        'RZ_A1H',
     ]
 
     def generate(self):
diff --git a/workspace_tools/export/iar_rz_a1h.ewd.tmpl b/workspace_tools/export/iar_rz_a1h.ewd.tmpl
new file mode 100644
index 0000000000..baa751f071
--- /dev/null
+++ b/workspace_tools/export/iar_rz_a1h.ewd.tmpl
@@ -0,0 +1,2733 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC1768.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.30.4.8186</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>CMSISDAP_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>7.30.4.8186</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC512K_Cortex.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>5</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.30.4.8186</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>ARMSIM_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>5</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
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+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
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+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
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+          <name>CatchNOCPERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
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+          <name>CatchHARDERR</name>
+          <state>1</state>
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+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+      </data>
+    </settings>
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+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
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+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
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+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
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+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
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+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
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+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
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+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
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+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
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+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
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+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
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+          <name>CCCatchCORERESET</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
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+          <name>CCCatchCHRERR</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>CCCatchBUSERR</name>
+          <state>0</state>
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+          <name>CCCatchINTERR</name>
+          <state>0</state>
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+          <name>CCCatchHARDERR</name>
+          <state>0</state>
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+          <name>CCCatchDummy</name>
+          <state>0</state>
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+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
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+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
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+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
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+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
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+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
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+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
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+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
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+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
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+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/workspace_tools/export/iar_rz_a1h.ewp.tmpl b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
new file mode 100644
index 0000000000..6a9dbe0950
--- /dev/null
+++ b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
@@ -0,0 +1,1840 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>19</version>
+          <state>37</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>3</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.30.6.53380</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>R7S721001	Renesas R7S721001</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>19</version>
+          <state>37</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>19</version>
+          <state>37</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+          {% for s in symbols %}
+            <state>{{s}}</state>
+          {% endfor %}
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        {% for path in include_paths %}
+          <state>$PROJ_DIR$\{{path}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
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+        <option>
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+          <state>$FILE_BNAME$.o</state>
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+          <state>100</state>
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+          <state>1</state>
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+          <state></state>
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+          <name>AExtraOptionsV2</name>
+          <state></state>
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+      <archiveVersion>0</archiveVersion>
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+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
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+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>{{name}}.bin</state>
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+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
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+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
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+      </data>
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+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\{{linker_script}}</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state>--skip_dynamic_initialization</state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+        {% for library in libraries %}
+          <state>$PROJ_DIR$\{{library}}</state>
+        {% endfor %}
+        {% for object in object_files %}
+          <state>$PROJ_DIR$\{{object}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
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+          <name>DoFill</name>
+          <state>0</state>
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+          <state>0xFF</state>
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+          <state>0x0</state>
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+          <version>0</version>
+          <state>1</state>
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+          <name>CrcAlign</name>
+          <state>1</state>
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+          <name>CrcAlgo</name>
+          <state>1</state>
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+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+          <version>0</version>
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+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+  </configuration>
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+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Release\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>Release\Obj</state>
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+        <option>
+          <name>ListPath</name>
+          <state>Release\List</state>
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+        <option>
+          <name>Variant</name>
+          <version>19</version>
+          <state>0</state>
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+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
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+          <version>3</version>
+          <state>1</state>
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+          <state>Full formatting.</state>
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+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
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+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
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+          <name>GOutputBinary</name>
+          <state>0</state>
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+          <version>3</version>
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+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <state>5.10.0.159</state>
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+          <name>OGChipSelectEditMenu</name>
+          <state>R7S721001	Renesas R7S721001</state>
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+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
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+        <option>
+          <name>GEndianModeBE</name>
+          <state>0</state>
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+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+          <name>GenStdoutInterface</name>
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+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <state>0</state>
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+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>19</version>
+          <state>0</state>
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+          <name>GBECoreSlave</name>
+          <version>19</version>
+          <state>0</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      <archiveVersion>2</archiveVersion>
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+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCDefines</name>
+          <state>NDEBUG</state>
+          {% for s in symbols %}
+            <state>{{s}}</state>
+          {% endfor %}
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
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+          <state>0</state>
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+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+          <name>CCListAssFile</name>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        {% for path in include_paths %}
+          <state>$PROJ_DIR$\{{path}}</state>
+        {% endfor %}
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>1</state>
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+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
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+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
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+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>5.srec</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\{{linker_script}}</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state>--skip_dynamic_initialization</state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+        {% for library in libraries %}
+          <state>$PROJ_DIR$\{{library}}</state>
+        {% endfor %}
+        {% for object in object_files %}
+          <state>$PROJ_DIR$\{{object}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlgo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  {{source_files}}
+</project>
+
+
diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py
index f6a4058ed7..32ef26b494 100644
--- a/workspace_tools/export_test.py
+++ b/workspace_tools/export_test.py
@@ -271,6 +271,7 @@ if __name__ == '__main__':
             ('iar', 'MAXWSNENV'),
             ('iar', 'MAX32600MBED'),
             ('iar', 'MOTE_L152RC'),
+            ('iar', 'RZ_A1H'),
 
             # ('sw4stm32', 'DISCO_F051R8'),
             # ('sw4stm32', 'DISCO_F100RB'),
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index b40b238bca..eca69fd6bc 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -1630,7 +1630,7 @@ class RZ_A1H(Target):
         Target.__init__(self)
         self.core = "Cortex-A9"
         self.extra_labels = ['RENESAS', 'MBRZA1H']
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
+        self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"]
         self.supported_form_factors = ["ARDUINO"]
         self.default_toolchain = "ARM"
 

From 44df3e5bd7f63394fc0629e7a3785951c8148233 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Tue, 16 Feb 2016 15:48:00 +0000
Subject: [PATCH 06/78] mbed lib revision - 114

---
 libraries/mbed/api/mbed.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h
index 466b4a3433..f5a9056516 100644
--- a/libraries/mbed/api/mbed.h
+++ b/libraries/mbed/api/mbed.h
@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 113
+#define MBED_LIBRARY_VERSION 114
 
 #include "platform.h"
 

From 8b042490286c9ad5ac1468c067ff4dd1bc315e6c Mon Sep 17 00:00:00 2001
From: dbestm <dbe.stm13@gmail.com>
Date: Tue, 16 Feb 2016 17:30:54 +0100
Subject: [PATCH 07/78] [NUCLEO_L476RG] RTC+LSE

make the RTC works properly with LSE and add the possibility to use the
LSI (internal clock)
---
 .../TARGET_STM32L4/stm32l4xx_hal_rcc.h        |  2 +-
 .../TARGET_DISCO_L476VG/device.h              |  1 +
 .../hal/TARGET_STM/TARGET_STM32L4/rtc_api.c   | 51 ++++++++++++-------
 3 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h
index 5409a64c8f..27f03456b6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h
@@ -159,7 +159,7 @@ typedef struct
   * @{
   */
 #define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)100)
-#define RCC_LSE_TIMEOUT_VALUE          ((uint32_t)100)
+#define RCC_LSE_TIMEOUT_VALUE          ((uint32_t)5000)
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h
index f842633cf8..8b1f3d7ca2 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h
@@ -48,6 +48,7 @@
 #define DEVICE_SPISLAVE         1
 
 #define DEVICE_RTC              1
+#define DEVICE_RTC_LSI          0
 
 #define DEVICE_PWMOUT           1
 
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
index 61dfd2bb5e..cde22774e1 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
@@ -33,7 +33,9 @@
 
 #include "mbed_error.h"
 
+#if DEVICE_RTC_LSI
 static int rtc_inited = 0;
+#endif
 
 static RTC_HandleTypeDef RtcHandle;
 
@@ -43,8 +45,10 @@ void rtc_init(void)
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
     uint32_t rtc_freq = 0;
 
+#if DEVICE_RTC_LSI
     if (rtc_inited) return;
     rtc_inited = 1;
+#endif
 
     RtcHandle.Instance = RTC;
 
@@ -58,6 +62,7 @@ void rtc_init(void)
     __HAL_RCC_BACKUPRESET_FORCE();
     __HAL_RCC_BACKUPRESET_RELEASE();
 
+#if !DEVICE_RTC_LSI
     // Enable LSE Oscillator
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
@@ -69,24 +74,27 @@ void rtc_init(void)
         PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
         HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
         rtc_freq = LSE_VALUE;
-    } else { // LSE didn't start, try with LSI
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("Cannot initialize RTC with LSI\n");
-        }
-        // Connect LSI to RTC
-        PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
-        PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
-        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
-            error("Cannot initialize RTC with LSI\n");
-        }
-        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
-        rtc_freq = 40000;
+    } else {
+	    error("Cannot initialize RTC with LSE\n");
     }
+#else	
+	// Enable LSI clock
+	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+	RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+	RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+	RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+		error("Cannot initialize RTC with LSI\n");
+	}
+	// Connect LSI to RTC
+	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+	PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+	if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+		error("Cannot initialize RTC with LSI\n");
+	}
+	// This value is LSI typical value. To be measured precisely using a timer input capture for example.
+	rtc_freq = 40000;
+#endif
 
     // Check if RTC is already initialized
     if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return;
@@ -129,12 +137,19 @@ void rtc_free(void)
     RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
     HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
+#if DEVICE_RTC_LSI
     rtc_inited = 0;
+#endif	
 }
 
 int rtc_isenabled(void)
 {
-    return rtc_inited;
+#if DEVICE_RTC_LSI
+  return rtc_inited;
+#else
+  if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return 1;
+  else return 0;
+#endif
 }
 
 /*

From 60b7accf2231acf5ed944b767c11ddebd897ff22 Mon Sep 17 00:00:00 2001
From: tomoyuki yamanaka <tomoyuki.yamanaka.xd@renesas.com>
Date: Wed, 17 Feb 2016 11:39:01 +0900
Subject: [PATCH 08/78] Additional changes to support of export function to the
 IAR.

In support of export function to the IAR, delete unnecessary extern declaration.
---
 libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
index 79a4adf8bb..4cff2443f2 100644
--- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
@@ -526,10 +526,6 @@ __attribute__((naked)) void software_init_hook (void) {
 
 #elif defined (__ICCARM__)
 
-extern int  __low_level_init(void);
-extern void __iar_data_init3(void);
-extern void __iar_dynamic_initialization(void);
-extern void mbed_sdk_init(void);
 extern void exit(int arg);
 
 void mbed_main(void) {

From b9d78a005f68c1fa7aab0bfeee579a0312ef1398 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Thu, 18 Feb 2016 09:07:45 +0000
Subject: [PATCH 09/78] Export - remove codesourcery tool

---
 workspace_tools/export/__init__.py | 3 +--
 workspace_tools/export_test.py     | 3 ---
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py
index 226d841079..9daf998988 100755
--- a/workspace_tools/export/__init__.py
+++ b/workspace_tools/export/__init__.py
@@ -19,7 +19,7 @@ from os.path import join, exists, basename
 from shutil import copytree, rmtree, copy
 
 from workspace_tools.utils import mkdir
-from workspace_tools.export import uvision4, codesourcery, codered, gccarm, ds5_5, iar, emblocks, coide, kds, zip, simplicityv3, atmelstudio, sw4stm32
+from workspace_tools.export import uvision4, codered, gccarm, ds5_5, iar, emblocks, coide, kds, zip, simplicityv3, atmelstudio, sw4stm32
 from workspace_tools.export.exporters import zip_working_directory_and_clean_up, OldLibrariesException
 from workspace_tools.targets import TARGET_NAMES, EXPORT_MAP, TARGET_MAP
 
@@ -28,7 +28,6 @@ from project_generator_definitions.definitions import ProGenDef
 EXPORTERS = {
     'uvision': uvision4.Uvision4,
     'lpcxpresso': codered.CodeRed,
-    'codesourcery': codesourcery.CodeSourcery,
     'gcc_arm': gccarm.GccArm,
     'ds5_5': ds5_5.DS5_5,
     'iar': iar.IAREmbeddedWorkbench,
diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py
index f6a4058ed7..3347e5681d 100644
--- a/workspace_tools/export_test.py
+++ b/workspace_tools/export_test.py
@@ -168,9 +168,6 @@ if __name__ == '__main__':
             ('lpcxpresso', 'LPCCAPPUCCINO'),
             ('lpcxpresso', 'LPC1549'),
             ('lpcxpresso', 'LPC11U68'),
-            # Linux path: /home/emimon01/bin/gcc-cs/bin/
-            # Windows path: "C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin/"
-            ('codesourcery', 'LPC1768'),
 
             # Linux path: /home/emimon01/bin/gcc-arm/bin/
             # Windows path: C:/arm-none-eabi-gcc-4_7/bin/

From b78542d10ea58dcbfe0551c8d89daa9bf613a3c6 Mon Sep 17 00:00:00 2001
From: modtronix-com <git1@modtronix.com>
Date: Mon, 15 Feb 2016 12:50:09 +1100
Subject: [PATCH 10/78] Changed target name from NZ32SC151 to NZ32_SC151

---
 .../TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S               | 0
 .../TOOLCHAIN_ARM_MICRO/stm32l151rc.sct                     | 0
 .../TOOLCHAIN_ARM_MICRO/sys.cpp                             | 0
 .../TOOLCHAIN_ARM_STD/startup_stm32l151xc.S                 | 0
 .../TOOLCHAIN_ARM_STD/stm32l151rc.sct                       | 0
 .../TOOLCHAIN_ARM_STD/sys.cpp                               | 0
 .../TOOLCHAIN_GCC_ARM/STM32L151XC.ld                        | 0
 .../TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S                 | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis.h         | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis_nvic.c    | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis_nvic.h    | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/hal_tick.c      | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/hal_tick.h      | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/stm32l151xc.h   | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/stm32l1xx.h     | 0
 .../stm32l1xx_hal_conf.h                                    | 0
 .../system_stm32l1xx.c                                      | 0
 .../system_stm32l1xx.h                                      | 0
 .../PeripheralNames.h                                       | 0
 .../PeripheralPins.c                                        | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PinNames.h      | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PortNames.h     | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/device.h        | 0
 .../{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/objects.h       | 0
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h             | 2 +-
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c            | 6 +++---
 workspace_tools/export/coide.py                             | 2 +-
 ...e_nz32sc151.coproj.tmpl => coide_nz32_sc151.coproj.tmpl} | 0
 .../{gcc_arm_nz32sc151.tmpl => gcc_arm_nz32_sc151.tmpl}     | 0
 workspace_tools/export/gccarm.py                            | 2 +-
 workspace_tools/export/uvision4.py                          | 4 ++--
 ..._nz32sc151.uvopt.tmpl => uvision4_nz32_sc151.uvopt.tmpl} | 2 +-
 ...z32sc151.uvproj.tmpl => uvision4_nz32_sc151.uvproj.tmpl} | 4 ++--
 workspace_tools/targets.py                                  | 4 ++--
 34 files changed, 13 insertions(+), 13 deletions(-)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_MICRO/sys.cpp (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_STD/stm32l151rc.sct (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_ARM_STD/sys.cpp (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_GCC_ARM/STM32L151XC.ld (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis_nvic.c (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/cmsis_nvic.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/hal_tick.c (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/hal_tick.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/stm32l151xc.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/stm32l1xx.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/stm32l1xx_hal_conf.h (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/system_stm32l1xx.c (100%)
 rename libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/system_stm32l1xx.h (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PeripheralNames.h (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PeripheralPins.c (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PinNames.h (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/PortNames.h (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/device.h (100%)
 rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/{TARGET_NZ32SC151 => TARGET_NZ32_SC151}/objects.h (100%)
 rename workspace_tools/export/{coide_nz32sc151.coproj.tmpl => coide_nz32_sc151.coproj.tmpl} (100%)
 rename workspace_tools/export/{gcc_arm_nz32sc151.tmpl => gcc_arm_nz32_sc151.tmpl} (100%)
 rename workspace_tools/export/{uvision4_nz32sc151.uvopt.tmpl => uvision4_nz32_sc151.uvopt.tmpl} (99%)
 rename workspace_tools/export/{uvision4_nz32sc151.uvproj.tmpl => uvision4_nz32_sc151.uvproj.tmpl} (99%)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/sys.cpp
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/sys.cpp
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/sys.cpp
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/sys.cpp
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis_nvic.c
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.c
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis_nvic.c
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis_nvic.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/cmsis_nvic.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/hal_tick.c
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.c
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/hal_tick.c
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/hal_tick.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/hal_tick.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l151xc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l151xc.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx_hal_conf.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.c
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h
similarity index 100%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.h
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralNames.h
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralPins.c
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PinNames.h
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PortNames.h
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PortNames.h
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PortNames.h
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/device.h
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h
similarity index 100%
rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/objects.h
rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
index 981a456a9d..e6e754b883 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
@@ -322,7 +322,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
 #elif defined(TARGET_STM32L152RE)
 #define INITIAL_SP            (0x20014000UL)
 
-#elif defined(TARGET_NZ32SC151)
+#elif defined(TARGET_NZ32_SC151)
 #define INITIAL_SP            (0x20008000UL)
 
 #elif (defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE)) 
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
index 2fbc5337cb..d73002c179 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
@@ -57,7 +57,7 @@
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL26Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
    || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \
-   || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32SC151) \
+   || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
    || defined(TARGET_SSCI824)  || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
 #    define OS_TASKCNT         6
 #  else
@@ -74,7 +74,7 @@
 #      define OS_SCHEDULERSTKSIZE    256
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)  || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL26Z)        || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
-   || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32SC151) \
+   || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
    || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
 #      define OS_SCHEDULERSTKSIZE    128
 #  elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) ||  defined(TARGET_STM32F303K8) ||  defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8)
@@ -184,7 +184,7 @@
 #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
 #    define OS_CLOCK       24000000
 
-#elif defined(TARGET_NZ32SC151)
+#elif defined(TARGET_NZ32_SC151)
 #    define OS_CLOCK       32000000
 
 #elif defined(TARGET_STM32L152RE)
diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py
index 60e4c288ce..50ecc38105 100755
--- a/workspace_tools/export/coide.py
+++ b/workspace_tools/export/coide.py
@@ -57,7 +57,7 @@ class CoIDE(Exporter):
         'MTS_MDOT_F405RG',
         'MTS_MDOT_F411RE',
         'MOTE_L152RC',
-        'NZ32SC151',
+        'NZ32_SC151',
     ]
 
     # seems like CoIDE currently supports only one type
diff --git a/workspace_tools/export/coide_nz32sc151.coproj.tmpl b/workspace_tools/export/coide_nz32_sc151.coproj.tmpl
similarity index 100%
rename from workspace_tools/export/coide_nz32sc151.coproj.tmpl
rename to workspace_tools/export/coide_nz32_sc151.coproj.tmpl
diff --git a/workspace_tools/export/gcc_arm_nz32sc151.tmpl b/workspace_tools/export/gcc_arm_nz32_sc151.tmpl
similarity index 100%
rename from workspace_tools/export/gcc_arm_nz32sc151.tmpl
rename to workspace_tools/export/gcc_arm_nz32_sc151.tmpl
diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py
index 8183dfd4a2..0d030ccac6 100755
--- a/workspace_tools/export/gccarm.py
+++ b/workspace_tools/export/gccarm.py
@@ -105,7 +105,7 @@ class GccArm(Exporter):
         'EFM32ZG_STK3200',
         'EFM32HG_STK3400',
         'EFM32PG_STK3401',
-        'NZ32SC151',
+        'NZ32_SC151',
         'SAMR21G18A',
         'TEENSY3_1',
         'SAMD21J18A',
diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index e8bbf9c4df..031a5cbc65 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -93,7 +93,7 @@ class Uvision4(Exporter):
         'MAXWSNENV',
         'MAX32600MBED',
         'MOTE_L152RC',
-        'NZ32SC151',
+        'NZ32_SC151',
         'SAMR21G18A',
         'SAMD21J18A',
         'SAMD21G18A',
@@ -142,7 +142,7 @@ class Uvision4(Exporter):
         'KL05Z',
         'LPC11U37H_401',
         'MOTE_L152RC',
-        'NZ32SC151',
+        'NZ32_SC151',
         'SAMR21G18A',
         'SAMD21J18A',
         'SAMD21G18A',
diff --git a/workspace_tools/export/uvision4_nz32sc151.uvopt.tmpl b/workspace_tools/export/uvision4_nz32_sc151.uvopt.tmpl
similarity index 99%
rename from workspace_tools/export/uvision4_nz32sc151.uvopt.tmpl
rename to workspace_tools/export/uvision4_nz32_sc151.uvopt.tmpl
index 3e0672ce0c..729a112271 100644
--- a/workspace_tools/export/uvision4_nz32sc151.uvopt.tmpl
+++ b/workspace_tools/export/uvision4_nz32_sc151.uvopt.tmpl
@@ -21,7 +21,7 @@
   </DaveTm>
 
   <Target>
-    <TargetName>mbed NZ32SC151</TargetName>
+    <TargetName>mbed NZ32_SC151</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
diff --git a/workspace_tools/export/uvision4_nz32sc151.uvproj.tmpl b/workspace_tools/export/uvision4_nz32_sc151.uvproj.tmpl
similarity index 99%
rename from workspace_tools/export/uvision4_nz32sc151.uvproj.tmpl
rename to workspace_tools/export/uvision4_nz32_sc151.uvproj.tmpl
index dfea264ce4..01333d96d6 100644
--- a/workspace_tools/export/uvision4_nz32sc151.uvproj.tmpl
+++ b/workspace_tools/export/uvision4_nz32_sc151.uvproj.tmpl
@@ -7,7 +7,7 @@
 
   <Targets>
     <Target>
-      <TargetName>mbed NZ32SC151</TargetName>
+      <TargetName>mbed NZ32_SC151</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
@@ -76,7 +76,7 @@
           <AfterMake>
             <RunUserProg1>1</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>fromelf --bin -o build\{{name}}_NZ32SC151.bin build\{{name}}.axf</UserProg1Name>
+            <UserProg1Name>fromelf --bin -o build\{{name}}_NZ32_SC151.bin build\{{name}}.axf</UserProg1Name>
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index cf2212a0b0..e27c8446e2 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -1046,7 +1046,7 @@ class UBLOX_C029(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
 
-class NZ32SC151(Target):
+class NZ32_SC151(Target):
     def __init__(self):
         Target.__init__(self)
         self.core = "Cortex-M3"
@@ -1881,7 +1881,7 @@ TARGETS = [
     MTS_DRAGONFLY_F411RE(),
     DISCO_F401VC(),
     UBLOX_C029(),       # STM32F439
-    NZ32SC151(),        # STM32L151
+    NZ32_SC151(),       # STM32L151
 
     ### Nordic ###
     NRF51822(),             # nRF51_16K

From a4cf4782400139f95f93a2747bc96d7c79b5c13a Mon Sep 17 00:00:00 2001
From: bcostm <bco.stm@gmail.com>
Date: Fri, 19 Feb 2016 10:09:08 +0100
Subject: [PATCH 11/78] Set NVIC_RAM_VECTOR_ADDRESS to 0x10000000

---
 .../TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/cmsis_nvic.c  | 2 +-
 .../TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/cmsis_nvic.c
index 9263c748e7..a8a6a487a5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/cmsis_nvic.c
@@ -30,7 +30,7 @@
  */ 
 #include "cmsis_nvic.h"
 
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of SRAM2
 #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
 
 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c
index 9263c748e7..a8a6a487a5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c
@@ -30,7 +30,7 @@
  */ 
 #include "cmsis_nvic.h"
 
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of SRAM2
 #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
 
 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {

From 2722a2f62d105991710f2333003bcb24c3167182 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Fri, 19 Feb 2016 15:59:54 -0600
Subject: [PATCH 12/78] Allow build report data structure to be passed to
 SingleTestRunner

---
 workspace_tools/test_api.py | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py
index 530e113c86..95bf1f8838 100644
--- a/workspace_tools/test_api.py
+++ b/workspace_tools/test_api.py
@@ -162,6 +162,8 @@ class SingleTestRunner(object):
                  _opts_report_html_file_name=None,
                  _opts_report_junit_file_name=None,
                  _opts_report_build_file_name=None,
+                 _opts_build_report={},
+                 _opts_build_properties={},
                  _test_spec={},
                  _opts_goanna_for_mbed_sdk=None,
                  _opts_goanna_for_tests=None,
@@ -185,7 +187,8 @@ class SingleTestRunner(object):
                  _opts_waterfall_test=None,
                  _opts_consolidate_waterfall_test=None,
                  _opts_extend_test_timeout=None,
-                 _opts_auto_detect=None):
+                 _opts_auto_detect=None,
+                 _opts_include_non_automated=False):
         """ Let's try hard to init this object
         """
         from colorama import init
@@ -241,6 +244,10 @@ class SingleTestRunner(object):
         self.opts_extend_test_timeout = _opts_extend_test_timeout
         self.opts_clean = _clean
         self.opts_auto_detect = _opts_auto_detect
+        self.opts_include_non_automated = _opts_include_non_automated
+
+        self.build_report = _opts_build_report
+        self.build_properties = _opts_build_properties
 
         # File / screen logger initialization
         self.logger = CLITestLogger(file_name=self.opts_log_file_name)  # Default test logger
@@ -382,7 +389,7 @@ class SingleTestRunner(object):
                     self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options()))
                     self.db_logger.disconnect();
 
-            valid_test_map_keys = self.get_valid_tests(test_map_keys, target, toolchain, test_ids)
+            valid_test_map_keys = self.get_valid_tests(test_map_keys, target, toolchain, test_ids, self.opts_include_non_automated)
             skipped_test_map_keys = self.get_skipped_tests(test_map_keys, valid_test_map_keys)
 
             for skipped_test_id in skipped_test_map_keys:
@@ -560,8 +567,6 @@ class SingleTestRunner(object):
         if self.opts_shuffle_test_seed is not None and self.is_shuffle_seed_float():
             self.shuffle_random_seed = round(float(self.opts_shuffle_test_seed), self.SHUFFLE_SEED_ROUND)
 
-        build_report = {}
-        build_properties = {}
 
         if self.opts_parallel_test_exec:
             ###################################################################
@@ -575,7 +580,7 @@ class SingleTestRunner(object):
             # get information about available MUTs (per target).
             for target, toolchains in self.test_spec['targets'].iteritems():
                 self.test_suite_properties_ext[target] = {}
-                t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids, build_report, build_properties))
+                t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids, self.build_report, self.build_properties))
                 t.daemon = True
                 t.start()
                 execute_threads.append(t)
@@ -588,7 +593,7 @@ class SingleTestRunner(object):
                 if target not in self.test_suite_properties_ext:
                     self.test_suite_properties_ext[target] = {}
 
-                self.execute_thread_slice(q, target, toolchains, clean, test_ids, build_report, build_properties)
+                self.execute_thread_slice(q, target, toolchains, clean, test_ids, self.build_report, self.build_properties)
                 q.get()
 
         if self.db_logger:
@@ -597,9 +602,9 @@ class SingleTestRunner(object):
                 self.db_logger.update_build_id_info(self.db_logger_build_id, _status_fk=self.db_logger.BUILD_ID_STATUS_COMPLETED)
                 self.db_logger.disconnect();
 
-        return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext, build_report, build_properties
+        return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext, self.build_report, self.build_properties
 
-    def get_valid_tests(self, test_map_keys, target, toolchain, test_ids):
+    def get_valid_tests(self, test_map_keys, target, toolchain, test_ids, include_non_automated):
         valid_test_map_keys = []
 
         for test_id in test_map_keys:
@@ -626,7 +631,12 @@ class SingleTestRunner(object):
                     print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target))
                 continue
 
-            if test.automated and test.is_supported(target, toolchain):
+            if not include_non_automated and not test.automated:
+                if self.opts_verbose_skipped_tests:
+                    print self.logger.log_line(self.logger.LogType.INFO, 'Non automated test skipped for target %s'% (target))
+                continue
+
+            if test.is_supported(target, toolchain):
                 if test.peripherals is None and self.opts_only_build_tests:
                     # When users are using 'build only flag' and test do not have
                     # specified peripherals we can allow test building by default

From b020cbe758a0b8daab090c38bd8718811e3f4cfa Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Fri, 19 Feb 2016 16:00:11 -0600
Subject: [PATCH 13/78] Allow build_release.py to build tests

---
 workspace_tools/build_release.py | 123 +++++++++++++++++++++++++------
 1 file changed, 100 insertions(+), 23 deletions(-)

diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py
index d968404e21..7e4ee32cc8 100644
--- a/workspace_tools/build_release.py
+++ b/workspace_tools/build_release.py
@@ -17,8 +17,9 @@ limitations under the License.
 """
 import sys
 from time import time
-from os.path import join, abspath, dirname
+from os.path import join, abspath, dirname, normpath
 from optparse import OptionParser
+import json
 
 # Be sure that the tools directory is in the search path
 ROOT = abspath(join(dirname(__file__), ".."))
@@ -28,6 +29,10 @@ from workspace_tools.build_api import build_mbed_libs
 from workspace_tools.build_api import write_build_report
 from workspace_tools.targets import TARGET_MAP
 from workspace_tools.test_exporters import ReportExporter, ResultExporterType
+from workspace_tools.test_api import SingleTestRunner
+from workspace_tools.test_api import singletest_in_cli_mode
+from workspace_tools.paths import TEST_DIR
+from workspace_tools.tests import TEST_MAP
 
 OFFICIAL_MBED_LIBRARY_BUILD = (
     ('LPC11U24',     ('ARM', 'uARM', 'GCC_ARM', 'IAR')),
@@ -153,51 +158,123 @@ if __name__ == '__main__':
 
     parser.add_option("-p", "--platforms", dest="platforms", default="", help="Build only for the platform namesseparated by comma")
 
+    parser.add_option("-L", "--list-config", action="store_true", dest="list_config",
+                      default=False, help="List the platforms and toolchains in the release in JSON")
+
     parser.add_option("", "--report-build", dest="report_build_file_name", help="Output the build results to an junit xml file")
 
+    parser.add_option("", "--build-tests", dest="build_tests", help="Build all tests in the given directories (relative to /libraries/tests)")
+
 
     options, args = parser.parse_args()
+
+
+
+    if options.list_config:
+        print json.dumps(OFFICIAL_MBED_LIBRARY_BUILD, indent=4)
+        sys.exit()
+
     start = time()
-    report = {}
-    properties = {}
+    build_report = {}
+    build_properties = {}
 
     platforms = None
     if options.platforms != "":
         platforms = set(options.platforms.split(","))
 
-    for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD:
-        if platforms is not None and not target_name in platforms:
-            print("Excluding %s from release" % target_name)
-            continue
+    if options.build_tests:
+        # Get all paths
+        directories = options.build_tests.split(',')
+        for i in range(len(directories)):
+            directories[i] = normpath(join(TEST_DIR, directories[i]))
 
-        if options.official_only:
-            toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),)
-        else:
-            toolchains = toolchain_list
+        test_names = []
 
-        if options.toolchains:
-            print "Only building using the following toolchains: %s" % (options.toolchains)
-            toolchainSet = set(toolchains)
-            toolchains = toolchainSet.intersection(set((options.toolchains).split(',')))
+        for test_id in TEST_MAP.keys():
+            # Prevents tests with multiple source dirs from being checked
+            if isinstance( TEST_MAP[test_id].source_dir, basestring):
+                test_path = normpath(TEST_MAP[test_id].source_dir)
+                for directory in directories:
+                    if directory in test_path:
+                        test_names.append(test_id)
 
-        for toolchain in toolchains:
-            id = "%s::%s" % (target_name, toolchain)
+        mut_counter = 1
+        mut = {}
+        test_spec = {
+            "targets": {}
+        }
 
-            try:
-                built_mbed_lib = build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs, report=report, properties=properties)
+        for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD:
+            toolchains = None
+            if platforms is not None and not target_name in platforms:
+                print("Excluding %s from release" % target_name)
+                continue
 
-            except Exception, e:
-                print str(e)
+            if options.official_only:
+                toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),)
+            else:
+                toolchains = toolchain_list
+
+            if options.toolchains:
+                print "Only building using the following toolchains: %s" % (options.toolchains)
+                toolchainSet = set(toolchains)
+                toolchains = toolchainSet.intersection(set((options.toolchains).split(',')))
+
+            mut[str(mut_counter)] = {
+                "mcu": target_name
+            }
+
+            mut_counter += 1
+
+            test_spec["targets"][target_name] = toolchains
+
+            single_test = SingleTestRunner(_muts=mut,
+                                           _opts_report_build_file_name=options.report_build_file_name,
+                                           _test_spec=test_spec,
+                                           _opts_test_by_names=",".join(test_names),
+                                           _opts_verbose=options.verbose,
+                                           _opts_only_build_tests=True,
+                                           _opts_suppress_summary=True,
+                                           _opts_jobs=options.jobs,
+                                           _opts_include_non_automated=True,
+                                           _opts_build_report=build_report,
+                                           _opts_build_properties=build_properties)
+            # Runs test suite in CLI mode
+            test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext, new_build_report, new_build_properties = single_test.execute()
+    else:
+        for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD:
+            if platforms is not None and not target_name in platforms:
+                print("Excluding %s from release" % target_name)
+                continue
+
+            if options.official_only:
+                toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),)
+            else:
+                toolchains = toolchain_list
+
+            if options.toolchains:
+                print "Only building using the following toolchains: %s" % (options.toolchains)
+                toolchainSet = set(toolchains)
+                toolchains = toolchainSet.intersection(set((options.toolchains).split(',')))
+
+            for toolchain in toolchains:
+                id = "%s::%s" % (target_name, toolchain)
+
+                try:
+                    built_mbed_lib = build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs, report=build_report, properties=build_properties)
+
+                except Exception, e:
+                    print str(e)
 
     # Write summary of the builds
     if options.report_build_file_name:
         file_report_exporter = ReportExporter(ResultExporterType.JUNIT, package="build")
-        file_report_exporter.report_to_file(report, options.report_build_file_name, test_suite_properties=properties)
+        file_report_exporter.report_to_file(build_report, options.report_build_file_name, test_suite_properties=build_properties)
 
     print "\n\nCompleted in: (%.2f)s" % (time() - start)
 
     print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
-    status = print_report_exporter.report(report)
+    status = print_report_exporter.report(build_report)
 
     if not status:
         sys.exit(1)

From 9211a3afea66e2cdeda256616535f2d4fb0ef629 Mon Sep 17 00:00:00 2001
From: mtkrtk <mtkrtk@gmail.com>
Date: Sat, 20 Feb 2016 10:17:51 +0900
Subject: [PATCH 14/78] Enable SPI_3

---
 .../hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h       | 1 +
 .../mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c  | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h
index a5a29a5e66..a1a385b36d 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h
@@ -127,6 +127,7 @@ typedef enum {
     SPI_0 = 0,
     SPI_1,
     SPI_2,
+    SPI_3,
 } SPIName;
 
 typedef enum {
diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c
index b1e6727266..78da487328 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c
@@ -27,6 +27,7 @@ static const PinMap PinMap_SPI_SCLK[] = {
     {P4_4  , SPI_1, 2},
     {P11_12, SPI_1, 2},
     {P8_3  , SPI_2, 3},
+    {P5_0  , SPI_3, 8},
     {NC    , NC   , 0}
 };
 
@@ -35,6 +36,7 @@ static const PinMap PinMap_SPI_SSEL[] = {
     {P4_5  , SPI_1, 2},
     {P11_13, SPI_1, 2},
     {P8_4  , SPI_2, 3},
+    {P5_1  , SPI_3, 8},
     {NC    , NC   , 0}
 };
 
@@ -43,6 +45,7 @@ static const PinMap PinMap_SPI_MOSI[] = {
     {P4_6  , SPI_1, 2},
     {P11_14, SPI_1, 2},
     {P8_5  , SPI_2, 3},
+    {P5_2  , SPI_3, 8},
     {NC    , NC   , 0}
 };
 
@@ -51,6 +54,7 @@ static const PinMap PinMap_SPI_MISO[] = {
     {P4_7  , SPI_1, 2},
     {P11_15, SPI_1, 2},
     {P8_6  , SPI_2, 3},
+    {P5_3  , SPI_3, 8},
     {NC    , NC   , 0}
 };
 
@@ -82,6 +86,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
         case SPI_0: CPGSTBCR10 &= ~(0x80); break;
         case SPI_1: CPGSTBCR10 &= ~(0x40); break;
         case SPI_2: CPGSTBCR10 &= ~(0x20); break;
+        case SPI_3: CPGSTBCR10 &= ~(0x10); break;
     }
     dummy = CPGSTBCR10;
 

From 788e1c62eb18554a6cc2094a918fac51bb8af275 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Sat, 20 Feb 2016 21:48:17 +0000
Subject: [PATCH 15/78] Export - remove iar templates

Shall be replaced by progen, which contains generic template. Any new target for
IAR, please check [project generator definitions](https://github.com/project-generator/project_generator_definitions).
---
 workspace_tools/export/iar.eww.tmpl           |    8 -
 workspace_tools/export/iar_arch_ble.ewd.tmpl  | 1370 --------
 workspace_tools/export/iar_arch_ble.ewp.tmpl  |  956 ------
 workspace_tools/export/iar_arch_pro.ewd.tmpl  | 2733 ---------------
 workspace_tools/export/iar_arch_pro.ewp.tmpl  | 1829 ----------
 .../export/iar_b96b_f446ve.ewd.tmpl           | 2977 -----------------
 .../export/iar_b96b_f446ve.ewp.tmpl           | 1927 -----------
 .../export/iar_delta_dfcm_nnn40.ewd.tmpl      | 1370 --------
 .../export/iar_delta_dfcm_nnn40.ewp.tmpl      |  956 ------
 .../export/iar_disco_f334c8.ewd.tmpl          | 2733 ---------------
 .../export/iar_disco_f334c8.ewp.tmpl          | 1899 -----------
 .../export/iar_disco_f429zi.ewd.tmpl          | 2977 -----------------
 .../export/iar_disco_f429zi.ewp.tmpl          | 1927 -----------
 .../export/iar_disco_f469ni.ewd.tmpl          | 2977 -----------------
 .../export/iar_disco_f469ni.ewp.tmpl          | 1927 -----------
 .../export/iar_disco_f746ng.ewd.tmpl          | 2976 ----------------
 .../export/iar_disco_f746ng.ewp.tmpl          | 1927 -----------
 .../export/iar_disco_l053c8.ewd.tmpl          | 2733 ---------------
 .../export/iar_disco_l053c8.ewp.tmpl          | 1899 -----------
 .../export/iar_disco_l476vg.ewd.tmpl          | 2975 ----------------
 .../export/iar_disco_l476vg.ewp.tmpl          | 1927 -----------
 .../export/iar_efm32pg_stk3401.ewd.tmpl       | 1403 --------
 .../export/iar_efm32pg_stk3401.ewp.tmpl       |  954 ------
 workspace_tools/export/iar_hrm1017.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_hrm1017.ewp.tmpl   |  956 ------
 workspace_tools/export/iar_k20d50m.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_k20d50m.ewp.tmpl   |  954 ------
 workspace_tools/export/iar_k22f.ewd.tmpl      | 1370 --------
 workspace_tools/export/iar_k22f.ewp.tmpl      |  954 ------
 workspace_tools/export/iar_k64f.ewd.tmpl      | 1370 --------
 workspace_tools/export/iar_k64f.ewp.tmpl      |  954 ------
 workspace_tools/export/iar_kl05z.ewd.tmpl     | 1370 --------
 workspace_tools/export/iar_kl05z.ewp.tmpl     |  954 ------
 workspace_tools/export/iar_kl25z.ewd.tmpl     | 1370 --------
 workspace_tools/export/iar_kl25z.ewp.tmpl     |  954 ------
 workspace_tools/export/iar_kl46z.ewd.tmpl     | 1370 --------
 workspace_tools/export/iar_kl46z.ewp.tmpl     |  954 ------
 workspace_tools/export/iar_lpc1114.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_lpc1114.ewp.tmpl   |  954 ------
 workspace_tools/export/iar_lpc11u24.ewd.tmpl  | 1370 --------
 workspace_tools/export/iar_lpc11u24.ewp.tmpl  |  954 ------
 .../export/iar_lpc11u35_401.ewd.tmpl          | 1370 --------
 .../export/iar_lpc11u35_401.ewp.tmpl          |  954 ------
 .../export/iar_lpc11u35_501.ewd.tmpl          | 1370 --------
 .../export/iar_lpc11u35_501.ewp.tmpl          |  954 ------
 workspace_tools/export/iar_lpc1347.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_lpc1347.ewp.tmpl   |  959 ------
 workspace_tools/export/iar_lpc1549.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_lpc1549.ewp.tmpl   |  954 ------
 workspace_tools/export/iar_lpc1768.ewd.tmpl   | 2733 ---------------
 workspace_tools/export/iar_lpc1768.ewp.tmpl   | 1829 ----------
 workspace_tools/export/iar_lpc4088.ewd.tmpl   | 1370 --------
 workspace_tools/export/iar_lpc4088.ewp.tmpl   |  954 ------
 .../export/iar_lpc4088_dm.ewd.tmpl            | 1370 --------
 .../export/iar_lpc4088_dm.ewp.tmpl            |  954 ------
 workspace_tools/export/iar_lpc812.ewd.tmpl    | 1370 --------
 workspace_tools/export/iar_lpc812.ewp.tmpl    |  954 ------
 workspace_tools/export/iar_lpc824.ewd.tmpl    | 1370 --------
 workspace_tools/export/iar_lpc824.ewp.tmpl    |  954 ------
 .../export/iar_lpccappuccino.ewp.tmpl         |  954 ------
 .../export/iar_max32600mbed.ewd.tmpl          | 1370 --------
 .../export/iar_max32600mbed.ewp.tmpl          |  957 ------
 workspace_tools/export/iar_maxwsnenv.ewd.tmpl | 1370 --------
 workspace_tools/export/iar_maxwsnenv.ewp.tmpl |  957 ------
 .../export/iar_mote_l152rc.ewp.tmpl           | 1903 -----------
 .../export/iar_mts_dragonfly_f411re.ewd.tmpl  | 2733 ---------------
 .../export/iar_mts_dragonfly_f411re.ewp.tmpl  | 1899 -----------
 .../export/iar_mts_mdot_f405rg.ewd.tmpl       | 2733 ---------------
 .../export/iar_mts_mdot_f405rg.ewp.tmpl       | 1899 -----------
 .../export/iar_mts_mdot_f411re.ewd.tmpl       | 2733 ---------------
 .../export/iar_mts_mdot_f411re.ewp.tmpl       | 1899 -----------
 workspace_tools/export/iar_nrf51822.ewd.tmpl  | 1370 --------
 workspace_tools/export/iar_nrf51822.ewp.tmpl  |  956 ------
 workspace_tools/export/iar_nrf51_dk.ewd.tmpl  | 1370 --------
 workspace_tools/export/iar_nrf51_dk.ewp.tmpl  |  956 ------
 .../export/iar_nrf51_dongle.ewd.tmpl          | 1370 --------
 .../export/iar_nrf51_dongle.ewp.tmpl          |  956 ------
 .../export/iar_nucleo_f030r8.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f030r8.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f031k6.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f031k6.ewp.tmpl         | 1901 -----------
 .../export/iar_nucleo_f042k6.ewd.tmpl         | 2977 -----------------
 .../export/iar_nucleo_f042k6.ewp.tmpl         | 1927 -----------
 .../export/iar_nucleo_f070rb.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f070rb.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f072rb.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f072rb.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f091rc.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f091rc.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f103rb.ewd.tmpl         | 1370 --------
 .../export/iar_nucleo_f103rb.ewp.tmpl         |  954 ------
 .../export/iar_nucleo_f302r8.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f302r8.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f303k8.ewd.tmpl         | 2977 -----------------
 .../export/iar_nucleo_f303k8.ewp.tmpl         | 1871 -----------
 .../export/iar_nucleo_f303re.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f303re.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f334r8.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f334r8.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f401re.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f401re.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f410rb.ewd.tmpl         | 2977 -----------------
 .../export/iar_nucleo_f410rb.ewp.tmpl         | 1927 -----------
 .../export/iar_nucleo_f411re.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_f411re.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_f446re.ewd.tmpl         | 2977 -----------------
 .../export/iar_nucleo_f446re.ewp.tmpl         | 1927 -----------
 .../export/iar_nucleo_l053r8.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_l053r8.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_l073rz.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_l073rz.ewp.tmpl         | 1903 -----------
 .../export/iar_nucleo_l152re.ewd.tmpl         | 2733 ---------------
 .../export/iar_nucleo_l152re.ewp.tmpl         | 1899 -----------
 .../export/iar_nucleo_l476rg.ewd.tmpl         | 2975 ----------------
 .../export/iar_nucleo_l476rg.ewp.tmpl         | 1927 -----------
 .../export/iar_seeed_tiny_ble.ewd.tmpl        | 1370 --------
 .../export/iar_seeed_tiny_ble.ewp.tmpl        |  956 ------
 workspace_tools/export/iar_stm32f407.ewp.tmpl |  954 ------
 .../export/iar_ublox_c027.ewd.tmpl            | 2733 ---------------
 .../export/iar_ublox_c027.ewp.tmpl            | 1829 ----------
 120 files changed, 212672 deletions(-)
 delete mode 100644 workspace_tools/export/iar.eww.tmpl
 delete mode 100644 workspace_tools/export/iar_arch_ble.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_arch_ble.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_arch_pro.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_arch_pro.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_b96b_f446ve.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_b96b_f446ve.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_delta_dfcm_nnn40.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_delta_dfcm_nnn40.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f334c8.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f334c8.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f429zi.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f429zi.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f469ni.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f469ni.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f746ng.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_f746ng.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_l053c8.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_l053c8.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_l476vg.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_disco_l476vg.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_efm32pg_stk3401.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_efm32pg_stk3401.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_hrm1017.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_hrm1017.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_k20d50m.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_k20d50m.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_k22f.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_k22f.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_k64f.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_k64f.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_kl05z.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_kl05z.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_kl25z.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_kl25z.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_kl46z.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_kl46z.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1114.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1114.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u24.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u24.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u35_401.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u35_401.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u35_501.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc11u35_501.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1347.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1347.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1549.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1549.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1768.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc1768.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc4088.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc4088.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc4088_dm.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc4088_dm.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc812.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc812.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc824.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_lpc824.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_lpccappuccino.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_max32600mbed.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_max32600mbed.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_maxwsnenv.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_maxwsnenv.ewp.tmpl
 delete mode 100755 workspace_tools/export/iar_mote_l152rc.ewp.tmpl
 delete mode 100644 workspace_tools/export/iar_mts_dragonfly_f411re.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl
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diff --git a/workspace_tools/export/iar.eww.tmpl b/workspace_tools/export/iar.eww.tmpl
deleted file mode 100644
index 37a7826e77..0000000000
--- a/workspace_tools/export/iar.eww.tmpl
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
-  <project>
-    <path>$WS_DIR$\{{name}}.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
diff --git a/workspace_tools/export/iar_arch_ble.ewd.tmpl b/workspace_tools/export/iar_arch_ble.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_arch_ble.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
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-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
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-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
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-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
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-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NordicSemi\nRF51822-QFAA.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
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-          <name>CExtraOptions</name>
-          <state></state>
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-          <name>CFpuProcessor</name>
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-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
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-          <name>OCDownloadSuppressDownload</name>
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-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
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-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
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-          <state>CMSISDAP_ID</state>
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-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
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-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NordicSemi\FlashNRF51822.board</state>
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-          <name>OCImagesUse2</name>
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-          <name>OCAllMTBOptions</name>
-          <state>1</state>
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-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
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-          <name>OCMulticoreSlaveConfiguration</name>
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-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
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-          <name>OCSimPspConfigFile</name>
-          <state></state>
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-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>CCAngelHeartbeat</name>
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-          <state>1</state>
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-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
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-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
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-          <state>200</state>
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-          <name>CMSISDAPDoLogfile</name>
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-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-          <name>CMSISDAPInterfaceRadio</name>
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-          <name>CMSISDAPInterfaceCmdLine</name>
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-          <name>CMSISDAPMultiTarget</name>
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-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
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-          <name>CMSISDAPRestoreBreakpointsCheck</name>
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-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
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-          <name>RDICatchReset</name>
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-          <name>RDICatchUndef</name>
-          <state>1</state>
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-          <name>RDICatchData</name>
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-        <option>
-          <name>RDICatchIRQ</name>
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-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
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-        <option>
-          <name>CatchCORERESET</name>
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-        <option>
-          <name>CatchMMERR</name>
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-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchBUSERR</name>
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-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
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-          <name>CMSISDAPMultiCPUNumber</name>
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-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
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-          <name>ICpuName</name>
-          <state></state>
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-          <name>OCJetEmuParams</name>
-          <state>1</state>
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-      <name>GDBSERVER_ID</name>
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-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-          <state>$PROJ_DIR$\cspycomm.log</state>
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-      <archiveVersion>2</archiveVersion>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>CRomLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-      <name>IJET_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>5</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-        <option>
-          <name>IjetCpuClockEdit</name>
-          <state>72.0</state>
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-          <name>IjetSwoPrescalerList</name>
-          <version>1</version>
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-          <state>_call_main</state>
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-        <option>
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-        </option>
-        <option>
-          <name>RDICatchData</name>
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-        <option>
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-          <state>1</state>
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-        <option>
-          <name>RDICatchIRQ</name>
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-        <option>
-          <name>RDICatchFIQ</name>
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-          <state>0</state>
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-        <option>
-          <name>CatchMMERR</name>
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-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IjetProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetSelectedCPUBehaviour</name>
-          <state>0</state>
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-        <option>
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-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetPreferETB</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetTraceSettingsList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetTraceSizeList</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>15</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>JLinkSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJLinkHWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>JLinkInitialSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCDoJlinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_arch_ble.ewp.tmpl b/workspace_tools/export/iar_arch_ble.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_arch_ble.ewp.tmpl
+++ /dev/null
@@ -1,956 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
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-      <data>
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-          <state>###Unitialized###</state>
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-    <settings>
-      <name>BILINK</name>
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-      <data/>
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-  {{source_files}}
-</project>
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-
diff --git a/workspace_tools/export/iar_arch_pro.ewd.tmpl b/workspace_tools/export/iar_arch_pro.ewd.tmpl
deleted file mode 100644
index baa751f071..0000000000
--- a/workspace_tools/export/iar_arch_pro.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-<project>
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-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_arch_pro.ewp.tmpl b/workspace_tools/export/iar_arch_pro.ewp.tmpl
deleted file mode 100644
index 5cb39e3f45..0000000000
--- a/workspace_tools/export/iar_arch_pro.ewp.tmpl
+++ /dev/null
@@ -1,1829 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>21</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>6.30.6.53380</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>LPC1768	NXP LPC1768</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>28</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
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-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
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-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
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-        <option>
-          <name>CCDiagRemark</name>
-          <state></state>
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-        <option>
-          <name>CCDiagWarning</name>
-          <state></state>
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-        <option>
-          <name>CCDiagError</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
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diff --git a/workspace_tools/export/iar_b96b_f446ve.ewd.tmpl b/workspace_tools/export/iar_b96b_f446ve.ewd.tmpl
deleted file mode 100644
index 7d9fe6bb7f..0000000000
--- a/workspace_tools/export/iar_b96b_f446ve.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_b96b_f446ve.ewp.tmpl b/workspace_tools/export/iar_b96b_f446ve.ewp.tmpl
deleted file mode 100644
index 5320986168..0000000000
--- a/workspace_tools/export/iar_b96b_f446ve.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.40.3.8937</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F446VE	ST STM32F446VE</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
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diff --git a/workspace_tools/export/iar_delta_dfcm_nnn40.ewd.tmpl b/workspace_tools/export/iar_delta_dfcm_nnn40.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_delta_dfcm_nnn40.ewd.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_delta_dfcm_nnn40.ewp.tmpl b/workspace_tools/export/iar_delta_dfcm_nnn40.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_delta_dfcm_nnn40.ewp.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_disco_f334c8.ewd.tmpl b/workspace_tools/export/iar_disco_f334c8.ewd.tmpl
deleted file mode 100644
index 1b9216e2ee..0000000000
--- a/workspace_tools/export/iar_disco_f334c8.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-          <state>0</state>
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-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
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-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
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-      </data>
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-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>2</version>
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-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
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-        <option>
-          <name>TIPackage</name>
-          <state></state>
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-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_disco_f334c8.ewp.tmpl b/workspace_tools/export/iar_disco_f334c8.ewp.tmpl
deleted file mode 100644
index 7f267e6463..0000000000
--- a/workspace_tools/export/iar_disco_f334c8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
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-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
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-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>40</state>
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-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
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-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
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-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
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-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
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-          <name>OGLastSavedByProductVersion</name>
-          <state>7.30.1.7765</state>
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-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F334x8	ST STM32F334x8</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-          <name>GenStdoutInterface</name>
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-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-          <name>GFPUCoreSlave</name>
-          <version>21</version>
-          <state>40</state>
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-          <name>GBECoreSlave</name>
-          <version>21</version>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
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-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-      <name>ICCARM</name>
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-        <version>31</version>
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-        <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
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-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-          <name>CCListCMessages</name>
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diff --git a/workspace_tools/export/iar_disco_f429zi.ewd.tmpl b/workspace_tools/export/iar_disco_f429zi.ewd.tmpl
deleted file mode 100644
index 4d70381145..0000000000
--- a/workspace_tools/export/iar_disco_f429zi.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
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-          <state>0</state>
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-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
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-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
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-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
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-          <state>0</state>
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-          <state>2000</state>
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-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
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-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
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-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
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-        <option>
-          <name>CCLmiftdiDoLogfile</name>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-          <state>0</state>
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-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
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-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
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-        <option>
-          <name>EmuMultiTarget</name>
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-          <name>EmuHWReset</name>
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-          <version>0</version>
-          <state>4</state>
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-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
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-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_disco_f429zi.ewp.tmpl b/workspace_tools/export/iar_disco_f429zi.ewp.tmpl
deleted file mode 100644
index 594dd19798..0000000000
--- a/workspace_tools/export/iar_disco_f429zi.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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diff --git a/workspace_tools/export/iar_disco_f469ni.ewd.tmpl b/workspace_tools/export/iar_disco_f469ni.ewd.tmpl
deleted file mode 100644
index 3c6396c651..0000000000
--- a/workspace_tools/export/iar_disco_f469ni.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-        <option>
-          <name>RDICatchData</name>
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-        <option>
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-        <option>
-          <name>OCProbeCfgOverride</name>
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-        <option>
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-        <option>
-          <name>IjetMultiCPUEnable</name>
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-        <option>
-          <name>IjetMultiCPUNumber</name>
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-        <option>
-          <name>IjetSelectedCPUBehaviour</name>
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-        <option>
-          <name>ICpuName</name>
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-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
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-        <option>
-          <name>IjetPreferETB</name>
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-        <option>
-          <name>IjetTraceSettingsList</name>
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-        <option>
-          <name>IjetTraceSizeList</name>
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-        <option>
-          <name>FlashBoardPathSlave</name>
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-        </option>
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-        <option>
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-        <option>
-          <name>CCJLinkLogFile</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>JLinkInitialSpeed</name>
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-        <option>
-          <name>CCDoJlinkMultiTarget</name>
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-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
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-        <option>
-          <name>CCJLinkMultiTarget</name>
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-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
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-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
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-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
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-        <option>
-          <name>CCUSBDevice</name>
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-        <option>
-          <name>CCRDICatchReset</name>
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-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
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-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
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-        <option>
-          <name>CCJLinkBreakpointRadio</name>
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-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCJLinkInterfaceRadio</name>
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-        <option>
-          <name>OCJLinkAttachSlave</name>
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-        <option>
-          <name>CCJLinkResetList</name>
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-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
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-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
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-      <name>LMIFTDI_ID</name>
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-        <wantNonLocal>1</wantNonLocal>
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-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
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-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
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-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoLogfile</name>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
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-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
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-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>UnusedAddr</name>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
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-        <option>
-          <name>CCJTagBreakpointRadio</name>
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-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
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-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>OCPEMicroAttachSlave</name>
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-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
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-        <option>
-          <name>CCPEMicroJtagSpeed</name>
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-        <option>
-          <name>CCJPEMicroShowSettings</name>
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-        </option>
-        <option>
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-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
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-          <state>0</state>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
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-        </option>
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-    <settings>
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-        <debug>1</debug>
-        <option>
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-        <option>
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-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
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-        <option>
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-        <option>
-          <name>CCRDICatchReset</name>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
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-        <option>
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-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
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-        <option>
-          <name>CCCpuClockEdit</name>
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-        <option>
-          <name>CCSwoClockAuto</name>
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-        <option>
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-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
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-          <name>OCDriverInfo</name>
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-          <name>TIPackage</name>
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-        <option>
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-        <option>
-          <name>LogFile</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCXds100CatchReset</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCXds100CatchIRQ</name>
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-        <option>
-          <name>CCXds100CatchFIQ</name>
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-        </option>
-        <option>
-          <name>IjetRestoreBreakpointsCheck</name>
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-        </option>
-        <option>
-          <name>IjetUpdateBreakpointsEdit</name>
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-        </option>
-        <option>
-          <name>RDICatchReset</name>
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-        </option>
-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchSWI</name>
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-        </option>
-        <option>
-          <name>RDICatchData</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchCORERESET</name>
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-        </option>
-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchCHKERR</name>
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-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IjetProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetSelectedCPUBehaviour</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetPreferETB</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetTraceSettingsList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetTraceSizeList</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>FlashBoardPathSlave</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>JLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>15</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>JLinkSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJLinkHWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>JLinkInitialSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCDoJlinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
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-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
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-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
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-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
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-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
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-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
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-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
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-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
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diff --git a/workspace_tools/export/iar_disco_f469ni.ewp.tmpl b/workspace_tools/export/iar_disco_f469ni.ewp.tmpl
deleted file mode 100644
index 471874d804..0000000000
--- a/workspace_tools/export/iar_disco_f469ni.ewp.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_disco_f746ng.ewd.tmpl b/workspace_tools/export/iar_disco_f746ng.ewd.tmpl
deleted file mode 100644
index 43dd4bb5bb..0000000000
--- a/workspace_tools/export/iar_disco_f746ng.ewd.tmpl
+++ /dev/null
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
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-        <option>
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diff --git a/workspace_tools/export/iar_disco_f746ng.ewp.tmpl b/workspace_tools/export/iar_disco_f746ng.ewp.tmpl
deleted file mode 100644
index f500439554..0000000000
--- a/workspace_tools/export/iar_disco_f746ng.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
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diff --git a/workspace_tools/export/iar_disco_l053c8.ewd.tmpl b/workspace_tools/export/iar_disco_l053c8.ewd.tmpl
deleted file mode 100644
index da36da6931..0000000000
--- a/workspace_tools/export/iar_disco_l053c8.ewd.tmpl
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diff --git a/workspace_tools/export/iar_disco_l053c8.ewp.tmpl b/workspace_tools/export/iar_disco_l053c8.ewp.tmpl
deleted file mode 100644
index c9c4362ada..0000000000
--- a/workspace_tools/export/iar_disco_l053c8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
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diff --git a/workspace_tools/export/iar_disco_l476vg.ewd.tmpl b/workspace_tools/export/iar_disco_l476vg.ewd.tmpl
deleted file mode 100644
index 8bce922e01..0000000000
--- a/workspace_tools/export/iar_disco_l476vg.ewd.tmpl
+++ /dev/null
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-    <settings>
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-          <name>CCXds100CatchFIQ</name>
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-          <version>0</version>
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-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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diff --git a/workspace_tools/export/iar_disco_l476vg.ewp.tmpl b/workspace_tools/export/iar_disco_l476vg.ewp.tmpl
deleted file mode 100644
index e3df8a4ccd..0000000000
--- a/workspace_tools/export/iar_disco_l476vg.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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diff --git a/workspace_tools/export/iar_efm32pg_stk3401.ewd.tmpl b/workspace_tools/export/iar_efm32pg_stk3401.ewd.tmpl
deleted file mode 100644
index eff75f6c8f..0000000000
--- a/workspace_tools/export/iar_efm32pg_stk3401.ewd.tmpl
+++ /dev/null
@@ -1,1403 +0,0 @@
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-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>main</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARROM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRomLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CRomCommunication</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomCommBaud</name>
-          <version>0</version>
-          <state>7</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>JLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>10</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>JLinkSpeed</name>
-          <state>32</state>
-        </option>
-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJLinkHWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>JLinkInitialSpeed</name>
-          <state>32</state>
-        </option>
-        <option>
-          <name>CCDoJlinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>2</version>
-          <state>7</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDIUseETM</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_efm32pg_stk3401.ewp.tmpl b/workspace_tools/export/iar_efm32pg_stk3401.ewp.tmpl
deleted file mode 100644
index cf92e168c0..0000000000
--- a/workspace_tools/export/iar_efm32pg_stk3401.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>EFM32PG1B200F256GM48	SiliconLaboratories EFM32PG1B200F256GM48</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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diff --git a/workspace_tools/export/iar_hrm1017.ewd.tmpl b/workspace_tools/export/iar_hrm1017.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_hrm1017.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_hrm1017.ewp.tmpl b/workspace_tools/export/iar_hrm1017.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_hrm1017.ewp.tmpl
+++ /dev/null
@@ -1,956 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>nRF51822-QFAA	NordicSemi nRF51822-QFAA</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
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diff --git a/workspace_tools/export/iar_k20d50m.ewd.tmpl b/workspace_tools/export/iar_k20d50m.ewd.tmpl
deleted file mode 100644
index 7a232db1f2..0000000000
--- a/workspace_tools/export/iar_k20d50m.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <state>1</state>
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-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_k20d50m.ewp.tmpl b/workspace_tools/export/iar_k20d50m.ewp.tmpl
deleted file mode 100644
index 24b15f9f69..0000000000
--- a/workspace_tools/export/iar_k20d50m.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
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-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>39</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
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-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
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-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MK20DX128xxx5	Freescale MK20DX128xxx5</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-          <name>GenStdoutInterface</name>
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-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>39</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>39</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
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-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-          <name>CCListCMnemonics</name>
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-          <name>CCListCMessages</name>
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-          <name>CCListAssFile</name>
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-          <name>CCListAssSource</name>
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-          <name>CCEnableRemarks</name>
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diff --git a/workspace_tools/export/iar_k22f.ewd.tmpl b/workspace_tools/export/iar_k22f.ewd.tmpl
deleted file mode 100644
index 632b082bf6..0000000000
--- a/workspace_tools/export/iar_k22f.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_k22f.ewp.tmpl b/workspace_tools/export/iar_k22f.ewp.tmpl
deleted file mode 100644
index bfaee1dbb9..0000000000
--- a/workspace_tools/export/iar_k22f.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
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-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
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-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MK22FN512xxx12	Freescale MK22FN512xxx12</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>40</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>40</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-      </data>
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-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocComments</name>
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-          <state>0</state>
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-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssFile</name>
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-          <name>CCListAssSource</name>
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-          <name>CCEnableRemarks</name>
-          <state>0</state>
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-          <name>CCDiagSuppress</name>
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-          <name>CCDiagRemark</name>
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-          <name>CCDiagWarning</name>
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-        <option>
-          <name>CCDiagError</name>
-          <state></state>
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-          <version>1</version>
-          <state>11111110</state>
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diff --git a/workspace_tools/export/iar_k64f.ewd.tmpl b/workspace_tools/export/iar_k64f.ewd.tmpl
deleted file mode 100644
index a64b6d80ed..0000000000
--- a/workspace_tools/export/iar_k64f.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_k64f.ewp.tmpl b/workspace_tools/export/iar_k64f.ewp.tmpl
deleted file mode 100644
index 0a7408568c..0000000000
--- a/workspace_tools/export/iar_k64f.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MK64FN1M0xxx12	Freescale MK64FN1M0xxx12</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
-        </option>
-        <option>
-          <name>CCDiagRemark</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCDiagWarning</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCDiagError</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
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-        <option>
-          <name>CCAllowList</name>
-          <version>1</version>
-          <state>11111110</state>
-        </option>
-        <option>
-          <name>CCDebugInfo</name>
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-          <state>1</state>
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-        <option>
-          <name>IProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IExtraOptionsCheck</name>
-          <state>0</state>
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-        <option>
-          <name>IExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCLangConformance</name>
-          <state>0</state>
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-        <option>
-          <name>CCSignedPlainChar</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRequirePrototypes</name>
-          <state>0</state>
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diff --git a/workspace_tools/export/iar_kl05z.ewd.tmpl b/workspace_tools/export/iar_kl05z.ewd.tmpl
deleted file mode 100644
index 29993f220c..0000000000
--- a/workspace_tools/export/iar_kl05z.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_kl05z.ewp.tmpl b/workspace_tools/export/iar_kl05z.ewp.tmpl
deleted file mode 100644
index ed7f6f9950..0000000000
--- a/workspace_tools/export/iar_kl05z.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MKL05Z32xxx4	Freescale MKL05Z32xxx4</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
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-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
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-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
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-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
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-        <option>
-          <name>CCDiagRemark</name>
-          <state></state>
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-        <option>
-          <name>CCDiagWarning</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCDiagError</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
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-        <option>
-          <name>CCAllowList</name>
-          <version>1</version>
-          <state>11111110</state>
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-        <option>
-          <name>CCDebugInfo</name>
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-        <option>
-          <name>IProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IExtraOptionsCheck</name>
-          <state>0</state>
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-        <option>
-          <name>IExtraOptions</name>
-          <state></state>
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-        <option>
-          <name>CCSignedPlainChar</name>
-          <state>1</state>
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-          <name>CCRequirePrototypes</name>
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-          <state>0</state>
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-          <name>CCDiagWarnAreErr</name>
-          <state>0</state>
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-        <option>
-          <name>CCCompilerRuntimeInfo</name>
-          <state>0</state>
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-        <option>
-          <name>IFpuProcessor</name>
-          <state>1</state>
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-        <option>
-          <name>OutputFile</name>
-          <state>$FILE_BNAME$.o</state>
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-          <name>CCLibConfigHeader</name>
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diff --git a/workspace_tools/export/iar_kl25z.ewd.tmpl b/workspace_tools/export/iar_kl25z.ewd.tmpl
deleted file mode 100644
index c86f117391..0000000000
--- a/workspace_tools/export/iar_kl25z.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_kl25z.ewp.tmpl b/workspace_tools/export/iar_kl25z.ewp.tmpl
deleted file mode 100644
index 8a197ba65c..0000000000
--- a/workspace_tools/export/iar_kl25z.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MKL25Z128xxx4	Freescale MKL25Z128xxx4</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
-        </option>
-        <option>
-          <name>CCDiagRemark</name>
-          <state></state>
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-        <option>
-          <name>CCDiagWarning</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCDiagError</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
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-        <option>
-          <name>CCAllowList</name>
-          <version>1</version>
-          <state>11111110</state>
-        </option>
-        <option>
-          <name>CCDebugInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IEndianMode</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCLangConformance</name>
-          <state>0</state>
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-        <option>
-          <name>CCSignedPlainChar</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRequirePrototypes</name>
-          <state>0</state>
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-        <option>
-          <name>CCMultibyteSupport</name>
-          <state>0</state>
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-        <option>
-          <name>CCDiagWarnAreErr</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCompilerRuntimeInfo</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OutputFile</name>
-          <state>$FILE_BNAME$.o</state>
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-        <option>
-          <name>CCLibConfigHeader</name>
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-          <name>PreInclude</name>
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-        <option>
-          <name>CompilerMisraOverride</name>
-          <state>0</state>
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-        <option>
-          <name>CCIncludePath2</name>
-        {% for path in include_paths %}
-          <state>$PROJ_DIR$\{{path}}</state>
-        {% endfor %}
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-        <option>
-          <name>CCStdIncCheck</name>
-          <state>0</state>
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-        <option>
-          <name>CCCodeSection</name>
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diff --git a/workspace_tools/export/iar_kl46z.ewd.tmpl b/workspace_tools/export/iar_kl46z.ewd.tmpl
deleted file mode 100644
index a799d24d96..0000000000
--- a/workspace_tools/export/iar_kl46z.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_kl46z.ewp.tmpl b/workspace_tools/export/iar_kl46z.ewp.tmpl
deleted file mode 100644
index f47b9295fe..0000000000
--- a/workspace_tools/export/iar_kl46z.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>MKL46Z256xxx4	Freescale MKL46Z256xxx4</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
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-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>35</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>35</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-      </data>
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-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>30</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPreprocComments</name>
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-          <name>CCPreprocLine</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssSource</name>
-          <state>0</state>
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-        <option>
-          <name>CCEnableRemarks</name>
-          <state>0</state>
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-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
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-        <option>
-          <name>CCDiagRemark</name>
-          <state></state>
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-          <name>CCDiagWarning</name>
-          <state></state>
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-        <option>
-          <name>CCDiagError</name>
-          <state></state>
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-        <option>
-          <name>CCObjPrefix</name>
-          <state>1</state>
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-          <name>CCAllowList</name>
-          <version>1</version>
-          <state>11111110</state>
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-          <name>CCDebugInfo</name>
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-          <state>1</state>
-        </option>
-        <option>
-          <name>IExtraOptionsCheck</name>
-          <state>0</state>
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-        <option>
-          <name>IExtraOptions</name>
-          <state></state>
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-        <option>
-          <name>CCSignedPlainChar</name>
-          <state>1</state>
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-          <name>CCRequirePrototypes</name>
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-          <name>CCDiagWarnAreErr</name>
-          <state>0</state>
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-        <option>
-          <name>CCCompilerRuntimeInfo</name>
-          <state>0</state>
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-        <option>
-          <name>IFpuProcessor</name>
-          <state>1</state>
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-          <state>$FILE_BNAME$.o</state>
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-        <option>
-          <name>CCIncludePath2</name>
-        {% for path in include_paths %}
-          <state>$PROJ_DIR$\{{path}}</state>
-        {% endfor %}
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-          <state>0</state>
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diff --git a/workspace_tools/export/iar_lpc1114.ewd.tmpl b/workspace_tools/export/iar_lpc1114.ewd.tmpl
deleted file mode 100644
index e40702430a..0000000000
--- a/workspace_tools/export/iar_lpc1114.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-      </data>
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-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc1114.ewp.tmpl b/workspace_tools/export/iar_lpc1114.ewp.tmpl
deleted file mode 100644
index b5bfc8a2ee..0000000000
--- a/workspace_tools/export/iar_lpc1114.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
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-    <toolchain>
-      <name>ARM</name>
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-    <debug>1</debug>
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-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
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-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>FPU</name>
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-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-        <option>
-          <name>OGProductVersion</name>
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-          <name>OGLastSavedByProductVersion</name>
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-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
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-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>LPC1114FN28_102	NXP LPC1114FN28_102</state>
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-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
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-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <name>OGUseCmsis</name>
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-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-          <name>GRuntimeLibThreads</name>
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-          <name>CCDefines</name>
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-          {% endfor %}
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diff --git a/workspace_tools/export/iar_lpc11u24.ewd.tmpl b/workspace_tools/export/iar_lpc11u24.ewd.tmpl
deleted file mode 100644
index 4ea416f0c6..0000000000
--- a/workspace_tools/export/iar_lpc11u24.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc11u24.ewp.tmpl b/workspace_tools/export/iar_lpc11u24.ewp.tmpl
deleted file mode 100644
index e41acb7fe2..0000000000
--- a/workspace_tools/export/iar_lpc11u24.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
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-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
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-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
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-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
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-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>LPC11U24FBD64_401	NXP LPC11U24FBD64_401</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-        <option>
-          <name>OGBufferedTerminalOutput</name>
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-          <name>GenStdoutInterface</name>
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-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <state>34</state>
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-          <version>20</version>
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-          <name>OGUseCmsis</name>
-          <state>0</state>
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-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-          <name>CCDefines</name>
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-            <state>{{s}}</state>
-          {% endfor %}
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-          <name>CCListCMnemonics</name>
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diff --git a/workspace_tools/export/iar_lpc11u35_401.ewd.tmpl b/workspace_tools/export/iar_lpc11u35_401.ewd.tmpl
deleted file mode 100644
index fe09cc7327..0000000000
--- a/workspace_tools/export/iar_lpc11u35_401.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc11u35_401.ewp.tmpl b/workspace_tools/export/iar_lpc11u35_401.ewp.tmpl
deleted file mode 100644
index a4ff036a5b..0000000000
--- a/workspace_tools/export/iar_lpc11u35_401.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc11u35_501.ewd.tmpl b/workspace_tools/export/iar_lpc11u35_501.ewd.tmpl
deleted file mode 100644
index b095d950b1..0000000000
--- a/workspace_tools/export/iar_lpc11u35_501.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc11u35_501.ewp.tmpl b/workspace_tools/export/iar_lpc11u35_501.ewp.tmpl
deleted file mode 100644
index b223a20367..0000000000
--- a/workspace_tools/export/iar_lpc11u35_501.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc1347.ewd.tmpl b/workspace_tools/export/iar_lpc1347.ewd.tmpl
deleted file mode 100644
index 2dc3d97717..0000000000
--- a/workspace_tools/export/iar_lpc1347.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc1347.ewp.tmpl b/workspace_tools/export/iar_lpc1347.ewp.tmpl
deleted file mode 100644
index d612df1a87..0000000000
--- a/workspace_tools/export/iar_lpc1347.ewp.tmpl
+++ /dev/null
@@ -1,959 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
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-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
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-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>ExePath</name>
-          <state>debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>38</state>
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-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
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-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
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-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <name>OGProductVersion</name>
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-          <name>OGLastSavedByProductVersion</name>
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-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>LPC1347	NXP LPC1347</state>
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-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-          <name>GenStdoutInterface</name>
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-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
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-          <name>GeneralMisraRules04</name>
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-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-          <name>GFPUCoreSlave</name>
-          <version>21</version>
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-          <name>GRuntimeLibThreads</name>
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-          <name>CCDefines</name>
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-          {% endfor %}
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-      <archiveVersion>2</archiveVersion>
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-        <version>9</version>
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-        <option>
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-        <option>
-          <name>AWarnEnable</name>
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-        <option>
-          <name>AWarnWhat</name>
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-          <name>AWarnOne</name>
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-          <state></state>
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diff --git a/workspace_tools/export/iar_lpc1549.ewd.tmpl b/workspace_tools/export/iar_lpc1549.ewd.tmpl
deleted file mode 100644
index 1cec388eea..0000000000
--- a/workspace_tools/export/iar_lpc1549.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <state>0</state>
-        </option>
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-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-          <state>2000</state>
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-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
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-          <name>CThirdPartyLogFileCheck</name>
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-          <name>CThirdPartyLogFileEditB</name>
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-        <version>2</version>
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-        <debug>1</debug>
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-          <name>OCXDS100AttachSlave</name>
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-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
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-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc1549.ewp.tmpl b/workspace_tools/export/iar_lpc1549.ewp.tmpl
deleted file mode 100644
index 2a3442135b..0000000000
--- a/workspace_tools/export/iar_lpc1549.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-      <name>ARM</name>
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-          <state>Debug\Exe</state>
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-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-          <name>ListPath</name>
-          <state>Debug\List</state>
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-          <state>38</state>
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-          <state>1</state>
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-          <name>Input description</name>
-          <state>Full formatting.</state>
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-          <version>2</version>
-          <state>1</state>
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-          <name>Output description</name>
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-          <name>FPU</name>
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-          <name>OGCoreOrChip</name>
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-          <name>GRuntimeLibSelectSlave</name>
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-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <state>0</state>
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-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
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-          <name>OGChipSelectEditMenu</name>
-          <state>LPC1549	NXP LPC1549</state>
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-          <name>GenLowLevelInterface</name>
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-          <name>GEndianModeBE</name>
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diff --git a/workspace_tools/export/iar_lpc1768.ewd.tmpl b/workspace_tools/export/iar_lpc1768.ewd.tmpl
deleted file mode 100644
index baa751f071..0000000000
--- a/workspace_tools/export/iar_lpc1768.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc1768.ewp.tmpl b/workspace_tools/export/iar_lpc1768.ewp.tmpl
deleted file mode 100644
index 5cb39e3f45..0000000000
--- a/workspace_tools/export/iar_lpc1768.ewp.tmpl
+++ /dev/null
@@ -1,1829 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpc4088.ewd.tmpl b/workspace_tools/export/iar_lpc4088.ewd.tmpl
deleted file mode 100644
index 7bef97b9f7..0000000000
--- a/workspace_tools/export/iar_lpc4088.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCCatchNOCPERR</name>
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-        <option>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
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-        <option>
-          <name>CCCatchDummy</name>
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-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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diff --git a/workspace_tools/export/iar_lpc4088.ewp.tmpl b/workspace_tools/export/iar_lpc4088.ewp.tmpl
deleted file mode 100644
index e1ffe051f1..0000000000
--- a/workspace_tools/export/iar_lpc4088.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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-        <option>
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-        <option>
-          <name>IlinkLogVeneer</name>
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-        <option>
-          <name>IlinkIcfOverride</name>
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-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
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-          <state></state>
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-          <name>IlinkEnableRemarks</name>
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-          <name>IlinkSuppressDiags</name>
-          <state></state>
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-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
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-          <name>IlinkTreatAsWarn</name>
-          <state></state>
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-        <option>
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-          <state></state>
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-          <name>IlinkWarningsAreErrors</name>
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-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
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-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
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-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
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-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
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-        <option>
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-          <name>IlinkProgramEntryLabelSelect</name>
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-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
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-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
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-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
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-          <name>DoCrc</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
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-          <name>IlinkBufferedTerminalOutput</name>
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-          <name>IlinkStdoutInterfaceSlave</name>
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-          <name>CrcFullSize</name>
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-          <name>IlinkLogAutoLibSelect</name>
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-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
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-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
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-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
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-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
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-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc4088_dm.ewd.tmpl b/workspace_tools/export/iar_lpc4088_dm.ewd.tmpl
deleted file mode 100644
index 20414c43df..0000000000
--- a/workspace_tools/export/iar_lpc4088_dm.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
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-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
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-    <settings>
-      <name>C-SPY</name>
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-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>CInput</name>
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-        <option>
-          <name>CEndian</name>
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-          <name>CProcessor</name>
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-          <name>OCVariant</name>
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-        <option>
-          <name>MacOverride</name>
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-        <option>
-          <name>MacFile</name>
-          <state></state>
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-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
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-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC4088.ddf</state>
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-          <name>RunToEnable</name>
-          <state>1</state>
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-        <option>
-          <name>RunToName</name>
-          <state>main</state>
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-          <name>CExtraOptionsCheck</name>
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-          <name>OCDownloadVerifyAll</name>
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-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
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-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
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-          <name>UseFlashLoader</name>
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-          <name>CLowLevel</name>
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-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
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-        <option>
-          <name>MacFile2</name>
-          <state></state>
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-        <option>
-          <name>CDevice</name>
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-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC40x8.board</state>
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-          <name>OCImagesPath1</name>
-          <state></state>
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-          <name>OCImagesPath2</name>
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-          <name>OverrideDefFlashBoard</name>
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-      <name>ANGEL_ID</name>
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diff --git a/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl b/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl
deleted file mode 100644
index e1ffe051f1..0000000000
--- a/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
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-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc812.ewd.tmpl b/workspace_tools/export/iar_lpc812.ewd.tmpl
deleted file mode 100644
index 862e1acbeb..0000000000
--- a/workspace_tools/export/iar_lpc812.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC812M101.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC16K1K_Cortex.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
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-        <option>
-          <name>OCDeviceConfigMacroFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDebuggerExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
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-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
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-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
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-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
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-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
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-          <name>CMSISDAPMultiTarget</name>
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-          <name>CMSISDAPJtagSpeedList</name>
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-          <state>0</state>
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-        <option>
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-        <option>
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-        <option>
-          <name>RDICatchUndef</name>
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-        <option>
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-        <option>
-          <name>RDICatchFIQ</name>
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-        <option>
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-          <state>1</state>
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-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
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-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state></state>
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-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
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-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCJTagBreakpointRadio</name>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
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-          <name>CCJTagUpdateBreakpoints</name>
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-    <settings>
-      <name>IJET_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>5</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>IjetAttachSlave</name>
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-          <name>OCIarProbeScriptFile</name>
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-        <option>
-          <name>IjetResetList</name>
-          <version>1</version>
-          <state>10</state>
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-          <name>IjetHWResetDuration</name>
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diff --git a/workspace_tools/export/iar_lpc812.ewp.tmpl b/workspace_tools/export/iar_lpc812.ewp.tmpl
deleted file mode 100644
index e84ba4b48f..0000000000
--- a/workspace_tools/export/iar_lpc812.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_lpc824.ewd.tmpl b/workspace_tools/export/iar_lpc824.ewd.tmpl
deleted file mode 100644
index 862e1acbeb..0000000000
--- a/workspace_tools/export/iar_lpc824.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC812M101.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC16K1K_Cortex.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDeviceConfigMacroFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDebuggerExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiTargetEnable</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPRestoreBreakpointsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>RDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchData</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
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-        <option>
-          <name>RDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state></state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
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-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-      <data>
-        <version>1</version>
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-        <debug>1</debug>
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-        <option>
-          <name>CRomLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
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-          <name>CRomCommPort</name>
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-          <state>0</state>
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-          <version>0</version>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>IJET_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>5</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetAttachSlave</name>
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-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetResetList</name>
-          <version>1</version>
-          <state>10</state>
-        </option>
-        <option>
-          <name>IjetHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>IjetHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>IjetPowerFromProbe</name>
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-        <option>
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-        <option>
-          <name>IjetLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>IjetInterfaceRadio</name>
-          <state>0</state>
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diff --git a/workspace_tools/export/iar_lpc824.ewp.tmpl b/workspace_tools/export/iar_lpc824.ewp.tmpl
deleted file mode 100644
index bdb393af54..0000000000
--- a/workspace_tools/export/iar_lpc824.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
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diff --git a/workspace_tools/export/iar_lpccappuccino.ewp.tmpl b/workspace_tools/export/iar_lpccappuccino.ewp.tmpl
deleted file mode 100644
index ddf5d8decc..0000000000
--- a/workspace_tools/export/iar_lpccappuccino.ewp.tmpl
+++ /dev/null
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-          <name>OOCOutputFile</name>
-          <state>{{name}}.bin</state>
-        </option>
-        <option>
-          <name>OOCCommandLineProducer</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OOCObjCopyEnable</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CUSTOM</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <extensions></extensions>
-        <cmdline></cmdline>
-      </data>
-    </settings>
-    <settings>
-      <name>BICOMP</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-    <settings>
-      <name>BUILDACTION</name>
-      <archiveVersion>1</archiveVersion>
-      <data>
-        <prebuild></prebuild>
-        <postbuild></postbuild>
-      </data>
-    </settings>
-    <settings>
-      <name>ILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>16</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IlinkLibIOConfig</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>XLinkMisraHandler</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkInputFileSlave</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOutputFile</name>
-          <state>{{name}}.out</state>
-        </option>
-        <option>
-          <name>IlinkDebugInfoEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkKeepSymbols</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySymbol</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_max32600mbed.ewd.tmpl b/workspace_tools/export/iar_max32600mbed.ewd.tmpl
deleted file mode 100644
index c99d125078..0000000000
--- a/workspace_tools/export/iar_max32600mbed.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\Maxim\MAX32600x85.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\Maxim\FlashMAX32600x85.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDeviceConfigMacroFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDebuggerExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiTargetEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPRestoreBreakpointsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>RDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchData</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
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-        <option>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_max32600mbed.ewp.tmpl b/workspace_tools/export/iar_max32600mbed.ewp.tmpl
deleted file mode 100644
index be7d8093e3..0000000000
--- a/workspace_tools/export/iar_max32600mbed.ewp.tmpl
+++ /dev/null
@@ -1,957 +0,0 @@
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-      <name>BICOMP</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-    <settings>
-      <name>BUILDACTION</name>
-      <archiveVersion>1</archiveVersion>
-      <data>
-        <prebuild></prebuild>
-        <postbuild></postbuild>
-      </data>
-    </settings>
-    <settings>
-      <name>ILINK</name>
-      <archiveVersion>0</archiveVersion>
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-        <version>16</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>IlinkLibIOConfig</name>
-          <state>1</state>
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-        <option>
-          <name>XLinkMisraHandler</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkInputFileSlave</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkOutputFile</name>
-          <state>cpp.out</state>
-        </option>
-        <option>
-          <name>IlinkDebugInfoEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkKeepSymbols</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile</name>
-          <state></state>
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-        <option>
-          <name>IlinkRawBinarySymbol</name>
-          <state></state>
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-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>1</state>
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-        <option>
-          <name>IlinkLogFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
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-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
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-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
diff --git a/workspace_tools/export/iar_maxwsnenv.ewd.tmpl b/workspace_tools/export/iar_maxwsnenv.ewd.tmpl
deleted file mode 100644
index c99d125078..0000000000
--- a/workspace_tools/export/iar_maxwsnenv.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\Maxim\MAX32600x85.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
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-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
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-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
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-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
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-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
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-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
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-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
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-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\Maxim\FlashMAX32600x85.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesSuppressCheck3</name>
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-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
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-          <name>OverrideDefFlashBoard</name>
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-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
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-          <name>OCImagesOffset3</name>
-          <state></state>
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-          <name>OCImagesUse1</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
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-        <option>
-          <name>OCDeviceConfigMacroFile</name>
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-          <name>OCDebuggerExtraOption</name>
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-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
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-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
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-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
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-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
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-      <name>ARMSIM_ID</name>
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-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
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-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
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-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceCmdLine</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPMultiTargetEnable</name>
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-        </option>
-        <option>
-          <name>CMSISDAPMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPRestoreBreakpointsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>RDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>RDICatchData</name>
-          <state>1</state>
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-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
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-        <option>
-          <name>RDICatchIRQ</name>
-          <state>0</state>
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-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state></state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>RDICatchSWI</name>
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-        <option>
-          <name>RDICatchData</name>
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-        <option>
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-        <option>
-          <name>RDICatchIRQ</name>
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-        <option>
-          <name>RDICatchFIQ</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CatchDummy</name>
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-        <option>
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-        <option>
-          <name>OCProbeConfig</name>
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-        <option>
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-        </option>
-        <option>
-          <name>IjetMultiCPUEnable</name>
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-        </option>
-        <option>
-          <name>IjetMultiCPUNumber</name>
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-        </option>
-        <option>
-          <name>IjetSelectedCPUBehaviour</name>
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-        </option>
-        <option>
-          <name>ICpuName</name>
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-        <option>
-          <name>OCJetEmuParams</name>
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-        </option>
-        <option>
-          <name>IjetPreferETB</name>
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-        <option>
-          <name>IjetTraceSettingsList</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetTraceSizeList</name>
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-          <state>2</state>
-        </option>
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-        <wantNonLocal>1</wantNonLocal>
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-          <name>JLinkSpeed</name>
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-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>CCJLinkLogFile</name>
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-        <option>
-          <name>CCJLinkHWResetDelay</name>
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-        </option>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>JLinkInitialSpeed</name>
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-        <option>
-          <name>CCDoJlinkMultiTarget</name>
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-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
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-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
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-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
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-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
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-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
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-        </option>
-        <option>
-          <name>CCUSBDevice</name>
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-        <option>
-          <name>CCRDICatchReset</name>
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-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
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-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
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-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
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-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
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-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
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-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
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-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>LmiftdiSpeed</name>
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-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
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-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
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-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoLogfile</name>
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-        </option>
-        <option>
-          <name>LogFile</name>
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-        <option>
-          <name>DoEmuMultiTarget</name>
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-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
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-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
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-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>UnusedAddr</name>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
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-        <option>
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-        </option>
-        <option>
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-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
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-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
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-        </option>
-        <option>
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-        <option>
-          <name>CCJPEMicroShowSettings</name>
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-        </option>
-        <option>
-          <name>DoLogfile</name>
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-        </option>
-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
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-          <state>0</state>
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-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
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-        <option>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
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-    <settings>
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-        <debug>1</debug>
-        <option>
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-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-    <settings>
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-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
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-        <option>
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-        <option>
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-    <settings>
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-        <option>
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-        <option>
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-        <option>
-          <name>OCDriverInfo</name>
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diff --git a/workspace_tools/export/iar_maxwsnenv.ewp.tmpl b/workspace_tools/export/iar_maxwsnenv.ewp.tmpl
deleted file mode 100644
index be7d8093e3..0000000000
--- a/workspace_tools/export/iar_maxwsnenv.ewp.tmpl
+++ /dev/null
@@ -1,957 +0,0 @@
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diff --git a/workspace_tools/export/iar_mote_l152rc.ewp.tmpl b/workspace_tools/export/iar_mote_l152rc.ewp.tmpl
deleted file mode 100755
index cb4c55d0c9..0000000000
--- a/workspace_tools/export/iar_mote_l152rc.ewp.tmpl
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diff --git a/workspace_tools/export/iar_mts_dragonfly_f411re.ewd.tmpl b/workspace_tools/export/iar_mts_dragonfly_f411re.ewd.tmpl
deleted file mode 100644
index 1c5fdf4e9a..0000000000
--- a/workspace_tools/export/iar_mts_dragonfly_f411re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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diff --git a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl b/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl
deleted file mode 100644
index 8440f7dd5d..0000000000
--- a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_mts_mdot_f405rg.ewd.tmpl b/workspace_tools/export/iar_mts_mdot_f405rg.ewd.tmpl
deleted file mode 100644
index d606b523b8..0000000000
--- a/workspace_tools/export/iar_mts_mdot_f405rg.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCCatchNOCPERR</name>
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-        <option>
-          <name>CCCatchCHRERR</name>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
-          <name>CCCatchBUSERR</name>
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-        <option>
-          <name>CCCatchINTERR</name>
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-        <option>
-          <name>CCCatchHARDERR</name>
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-        <option>
-          <name>CCCatchDummy</name>
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-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
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-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
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-        </option>
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-        <option>
-          <name>jtago</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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diff --git a/workspace_tools/export/iar_mts_mdot_f405rg.ewp.tmpl b/workspace_tools/export/iar_mts_mdot_f405rg.ewp.tmpl
deleted file mode 100644
index ff5452582a..0000000000
--- a/workspace_tools/export/iar_mts_mdot_f405rg.ewp.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_mts_mdot_f411re.ewd.tmpl b/workspace_tools/export/iar_mts_mdot_f411re.ewd.tmpl
deleted file mode 100644
index 1c5fdf4e9a..0000000000
--- a/workspace_tools/export/iar_mts_mdot_f411re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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diff --git a/workspace_tools/export/iar_mts_mdot_f411re.ewp.tmpl b/workspace_tools/export/iar_mts_mdot_f411re.ewp.tmpl
deleted file mode 100644
index d56dc845e0..0000000000
--- a/workspace_tools/export/iar_mts_mdot_f411re.ewp.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_nrf51822.ewd.tmpl b/workspace_tools/export/iar_nrf51822.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_nrf51822.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>IjetMultiCPUNumber</name>
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-        <option>
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-        <option>
-          <name>ICpuName</name>
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-        <option>
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-        <option>
-          <name>IjetPreferETB</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>JLinkInitialSpeed</name>
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-        <option>
-          <name>CCDoJlinkMultiTarget</name>
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-        <option>
-          <name>CCScanChainNonARMDevices</name>
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-        <option>
-          <name>CCJLinkMultiTarget</name>
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-        <option>
-          <name>CCJLinkIRLength</name>
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-        <option>
-          <name>CCJLinkCommRadio</name>
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-        <option>
-          <name>CCJLinkTCPIP</name>
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-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCRDICatchUndef</name>
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-        <option>
-          <name>CCRDICatchSWI</name>
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-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
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-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
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-        <option>
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-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
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-        <option>
-          <name>CCJLinkInterfaceRadio</name>
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-        <option>
-          <name>OCJLinkAttachSlave</name>
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-        <option>
-          <name>CCJLinkResetList</name>
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-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
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-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
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-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
-          <name>CCCatchBUSERR</name>
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-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchHARDERR</name>
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-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCCpuClockEdit</name>
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-        <option>
-          <name>CCSwoClockAuto</name>
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-        <option>
-          <name>CCSwoClockEdit</name>
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-        </option>
-        <option>
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-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
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-        </option>
-        <option>
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-        </option>
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-        <option>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
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-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
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-        </option>
-      </data>
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-    <settings>
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-        <debug>1</debug>
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-          <state>0</state>
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-        <option>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>LogFile</name>
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-        <option>
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-        <option>
-          <name>CEmuCommPort</name>
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-        <option>
-          <name>jtago</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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diff --git a/workspace_tools/export/iar_nrf51822.ewp.tmpl b/workspace_tools/export/iar_nrf51822.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_nrf51822.ewp.tmpl
+++ /dev/null
@@ -1,956 +0,0 @@
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-          <name>IlinkOutputFile</name>
-          <state>cpp.out</state>
-        </option>
-        <option>
-          <name>IlinkDebugInfoEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkKeepSymbols</name>
-          <state>__soft_device_bin</state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile</name>
-          {% for bins in binary_files %}
-          <state>$PROJ_DIR$\{{bins}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>IlinkRawBinarySymbol</name>
-          <state>__soft_device_bin</state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state>.noinit_softdevice</state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state>SOFT_DEVICE_BIN=1</state>
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_nrf51_dk.ewd.tmpl b/workspace_tools/export/iar_nrf51_dk.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_nrf51_dk.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NordicSemi\nRF51822-QFAA.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NordicSemi\FlashNRF51822.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDeviceConfigMacroFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDebuggerExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiTargetEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPRestoreBreakpointsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>RDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchData</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchSTATERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state></state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>IjetMultiCPUNumber</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>IjetPreferETB</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
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-        <option>
-          <name>CCDoJlinkMultiTarget</name>
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-        <option>
-          <name>CCScanChainNonARMDevices</name>
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-        <option>
-          <name>CCJLinkMultiTarget</name>
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-        <option>
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-        <option>
-          <name>CCJLinkCommRadio</name>
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-        <option>
-          <name>CCJLinkTCPIP</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCRDICatchUndef</name>
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-        <option>
-          <name>CCRDICatchSWI</name>
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-        <option>
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-          <name>CCRDICatchPrefetch</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
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-        <option>
-          <name>CCJLinkInterfaceRadio</name>
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-        <option>
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-        <option>
-          <name>CCJLinkResetList</name>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
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-        <option>
-          <name>CCCatchCORERESET</name>
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-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
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-        <option>
-          <name>CCCatchBUSERR</name>
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-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchHARDERR</name>
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-        <option>
-          <name>CCCatchDummy</name>
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-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
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-          <state>0</state>
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-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
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-        <option>
-          <name>CCCpuClockEdit</name>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCSwoClockEdit</name>
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-        <option>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
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-        <option>
-          <name>OCJLinkDeviceName</name>
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-        <option>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
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-          <name>CCLmiFtdiInterfaceRadio</name>
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-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
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-        </option>
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-    <settings>
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-          <name>LogFile</name>
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-        <option>
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-        <option>
-          <name>jtago</name>
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-        <option>
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-          <name>CCMacraigorInterfaceCmdLine</name>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
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-      </plugin>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nrf51_dk.ewp.tmpl b/workspace_tools/export/iar_nrf51_dk.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_nrf51_dk.ewp.tmpl
+++ /dev/null
@@ -1,956 +0,0 @@
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-          <name>IlinkRawBinarySymbol</name>
-          <state>__soft_device_bin</state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state>.noinit_softdevice</state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state>SOFT_DEVICE_BIN=1</state>
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
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-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
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-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
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-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_nrf51_dongle.ewd.tmpl b/workspace_tools/export/iar_nrf51_dongle.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_nrf51_dongle.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\NordicSemi\nRF51822-QFAA.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>CMSISDAP_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\NordicSemi\FlashNRF51822.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
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-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
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-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
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-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
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-        <option>
-          <name>OCDeviceConfigMacroFile</name>
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-        <option>
-          <name>OCDebuggerExtraOption</name>
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-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
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-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>1</version>
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-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
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-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
-        </option>
-        <option>
-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
-        </option>
-        <option>
-          <name>CMSISDAPDoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CMSISDAPInterfaceRadio</name>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPInterfaceCmdLine</name>
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-          <name>CMSISDAPMultiTargetEnable</name>
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-          <name>CMSISDAPMultiTarget</name>
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-        </option>
-        <option>
-          <name>CMSISDAPJtagSpeedList</name>
-          <version>0</version>
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-        </option>
-        <option>
-          <name>CMSISDAPBreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPRestoreBreakpointsCheck</name>
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-        <option>
-          <name>CMSISDAPUpdateBreakpointsEdit</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>RDICatchReset</name>
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-        <option>
-          <name>RDICatchUndef</name>
-          <state>1</state>
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-        <option>
-          <name>RDICatchSWI</name>
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-        <option>
-          <name>RDICatchData</name>
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-        <option>
-          <name>RDICatchPrefetch</name>
-          <state>1</state>
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-        <option>
-          <name>RDICatchIRQ</name>
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-        </option>
-        <option>
-          <name>RDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>CatchCORERESET</name>
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-        <option>
-          <name>CatchMMERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchNOCPERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchCHKERR</name>
-          <state>1</state>
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-        <option>
-          <name>CatchSTATERR</name>
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-        <option>
-          <name>CatchBUSERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchINTERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchHARDERR</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state></state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-    <settings>
-      <name>IARROM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRomLogFileCheck</name>
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-        </option>
-        <option>
-          <name>CRomLogFileEditB</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-          <state></state>
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-        <option>
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-        <option>
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-        <option>
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-        <wantNonLocal>1</wantNonLocal>
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-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
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-        </option>
-        <option>
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-        <option>
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diff --git a/workspace_tools/export/iar_nrf51_dongle.ewp.tmpl b/workspace_tools/export/iar_nrf51_dongle.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_nrf51_dongle.ewp.tmpl
+++ /dev/null
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-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state>SOFT_DEVICE_BIN=1</state>
-        </option>
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-          <name>IlinkMapFile</name>
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-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
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-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
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-        <option>
-          <name>FillerStart</name>
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-          <name>CrcSize</name>
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-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
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-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
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-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
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-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
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-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
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-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f030r8.ewd.tmpl b/workspace_tools/export/iar_nucleo_f030r8.ewd.tmpl
deleted file mode 100644
index 0c003a9ab9..0000000000
--- a/workspace_tools/export/iar_nucleo_f030r8.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
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-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
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-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F030x8.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
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-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
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-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
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-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
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-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
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-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
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-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
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-        <option>
-          <name>OCDynDriverList</name>
-          <state>STLINK_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
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-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
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-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F03xx8.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
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-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
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-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
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-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
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-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
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-          <name>OCImagesOffset2</name>
-          <state></state>
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-          <name>OCImagesOffset3</name>
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-          <name>OCImagesUse1</name>
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-          <name>OCImagesUse2</name>
-          <state>0</state>
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-          <name>OCImagesUse3</name>
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-          <name>OCDeviceConfigMacroFile</name>
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-          <name>OCDebuggerExtraOption</name>
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-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
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-        <option>
-          <name>OCMulticoreNrOfCores</name>
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-        <option>
-          <name>OCMulticoreMaster</name>
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-        <option>
-          <name>OCMulticorePort</name>
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-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
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-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
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-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
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-          <name>OCSimDriverInfo</name>
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-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
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-          <name>OCSimPspOverrideConfig</name>
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-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
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-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-        <option>
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-          <version>0</version>
-          <state>3</state>
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-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
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-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
-          <name>AngelLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>CMSISDAP_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>CMSISDAPAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCIarProbeScriptFile</name>
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-        <option>
-          <name>CMSISDAPResetList</name>
-          <version>1</version>
-          <state>10</state>
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-        <option>
-          <name>CMSISDAPHWResetDuration</name>
-          <state>300</state>
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-          <name>CMSISDAPHWResetDelay</name>
-          <state>200</state>
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-          <name>CMSISDAPDoLogfile</name>
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-          <name>CMSISDAPLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-          <name>CMSISDAPInterfaceRadio</name>
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-          <name>CMSISDAPJtagSpeedList</name>
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-        <option>
-          <name>CatchHARDERR</name>
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-        <option>
-          <name>CatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPMultiCPUEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CMSISDAPMultiCPUNumber</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProbeCfgOverride</name>
-          <state>0</state>
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-        <option>
-          <name>OCProbeConfig</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CMSISDAPProbeConfigRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CMSISDAPSelectedCPUBehaviour</name>
-          <state>0</state>
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-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
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-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
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-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <version>1</version>
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-        <debug>0</debug>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
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-          <state>1000</state>
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-        <option>
-          <name>CCDoJlinkMultiTarget</name>
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-        <option>
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-        <option>
-          <name>CCJLinkMultiTarget</name>
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-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
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-        <option>
-          <name>CCRDICatchReset</name>
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-        <option>
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-        <option>
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-          <name>CCRDICatchData</name>
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-        <option>
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-        <option>
-          <name>CCRDICatchIRQ</name>
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-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>CCJLinkBreakpointRadio</name>
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-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-          <state>_call_main</state>
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-          <name>OCJLinkAttachSlave</name>
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-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchCORERESET</name>
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-          <state>0</state>
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-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
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-        <option>
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-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchINTERR</name>
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-          <name>CCCatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
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-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
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-      </data>
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-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
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-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
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-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
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-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f030r8.ewp.tmpl b/workspace_tools/export/iar_nucleo_f030r8.ewp.tmpl
deleted file mode 100644
index 1520c06d68..0000000000
--- a/workspace_tools/export/iar_nucleo_f030r8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.30.1.7765</state>
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-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
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-          <state>###Unitialized###</state>
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-    <settings>
-      <name>BILINK</name>
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-      <data/>
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-  {{source_files}}
-</project>
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-
diff --git a/workspace_tools/export/iar_nucleo_f031k6.ewd.tmpl b/workspace_tools/export/iar_nucleo_f031k6.ewd.tmpl
deleted file mode 100644
index 0c003a9ab9..0000000000
--- a/workspace_tools/export/iar_nucleo_f031k6.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-<project>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f031k6.ewp.tmpl b/workspace_tools/export/iar_nucleo_f031k6.ewp.tmpl
deleted file mode 100644
index 97b1ac6840..0000000000
--- a/workspace_tools/export/iar_nucleo_f031k6.ewp.tmpl
+++ /dev/null
@@ -1,1901 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>4</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.40.1.8463</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F031x6	ST STM32F031x6</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>21</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>21</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>31</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
-        </option>
-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
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-      <name>BILINK</name>
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-  {{source_files}}
-</project>
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-
diff --git a/workspace_tools/export/iar_nucleo_f042k6.ewd.tmpl b/workspace_tools/export/iar_nucleo_f042k6.ewd.tmpl
deleted file mode 100644
index 3c6396c651..0000000000
--- a/workspace_tools/export/iar_nucleo_f042k6.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-        <option>
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-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f042k6.ewp.tmpl b/workspace_tools/export/iar_nucleo_f042k6.ewp.tmpl
deleted file mode 100644
index df66e5d7ff..0000000000
--- a/workspace_tools/export/iar_nucleo_f042k6.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CoreVariant</name>
-          <version>22</version>
-          <state>34</state>
-        </option>
-        <option>
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-          <name>IlinkLogUnusedFragments</name>
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-          <name>IlinkOptInline</name>
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-        <option>
-          <name>IlinkOptExceptionsForce</name>
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-          <name>IlinkCmsis</name>
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-        <option>
-          <name>IlinkOptMergeDuplSections</name>
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-        <option>
-          <name>IlinkOptUseVfe</name>
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-        <option>
-          <name>IlinkOptForceVfe</name>
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-          <name>IlinkStackAnalysisEnable</name>
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-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
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-        <option>
-          <name>CrcAlgorithm</name>
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-        <option>
-          <name>CrcUnitSize</name>
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-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
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-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
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-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
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-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
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-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f070rb.ewd.tmpl b/workspace_tools/export/iar_nucleo_f070rb.ewd.tmpl
deleted file mode 100644
index cc1c31895a..0000000000
--- a/workspace_tools/export/iar_nucleo_f070rb.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-          <name>MemOverride</name>
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-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F072RB.ddf</state>
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-          <name>RunToEnable</name>
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-          <name>MacFile2</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>ICpuName</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCJetEmuParams</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetPreferETB</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IjetTraceSettingsList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IjetTraceSizeList</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>15</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>JLinkSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJLinkHWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>JLinkInitialSpeed</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCDoJlinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl b/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl
deleted file mode 100644
index 8c511747cb..0000000000
--- a/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
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-          <name>IlinkOptUseVfe</name>
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-          <name>IlinkStackControlFile</name>
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-          <state></state>
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-          <name>IlinkThreadsSlave</name>
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-    <settings>
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-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
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-        <option>
-          <name>IarchiveOverride</name>
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-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
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-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f072rb.ewd.tmpl b/workspace_tools/export/iar_nucleo_f072rb.ewd.tmpl
deleted file mode 100644
index cc1c31895a..0000000000
--- a/workspace_tools/export/iar_nucleo_f072rb.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-          <name>MemOverride</name>
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-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F072RB.ddf</state>
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-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f072rb.ewp.tmpl b/workspace_tools/export/iar_nucleo_f072rb.ewp.tmpl
deleted file mode 100644
index 923e2923ee..0000000000
--- a/workspace_tools/export/iar_nucleo_f072rb.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>34</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
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-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.30.1.7765</state>
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-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F072RB	ST STM32F072RB</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-        <option>
-          <name>GFPUCoreSlave</name>
-          <version>21</version>
-          <state>34</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>21</version>
-          <state>34</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>31</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
-          <state>0</state>
-        </option>
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diff --git a/workspace_tools/export/iar_nucleo_f091rc.ewd.tmpl b/workspace_tools/export/iar_nucleo_f091rc.ewd.tmpl
deleted file mode 100644
index 99fd82569a..0000000000
--- a/workspace_tools/export/iar_nucleo_f091rc.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
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-        <option>
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-          <name>CCJLinkInterfaceRadio</name>
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-    <settings>
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-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
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-    <settings>
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-      <archiveVersion>2</archiveVersion>
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-        <version>2</version>
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-        <debug>0</debug>
-        <option>
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-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
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-          <name>TIPackageOverride</name>
-          <state>0</state>
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-        <option>
-          <name>TIPackage</name>
-          <state></state>
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-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f091rc.ewp.tmpl b/workspace_tools/export/iar_nucleo_f091rc.ewp.tmpl
deleted file mode 100644
index b7e758c3a6..0000000000
--- a/workspace_tools/export/iar_nucleo_f091rc.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
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-      <name>ARM</name>
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-        <debug>1</debug>
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-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
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-        <option>
-          <name>Variant</name>
-          <version>21</version>
-          <state>34</state>
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-          <name>GEndianMode</name>
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-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
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-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
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-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-          <name>GOutputBinary</name>
-          <state>0</state>
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-          <name>FPU</name>
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-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
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-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <state>0</state>
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-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
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-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F091RC	ST STM32F091RC</state>
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-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
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-          <name>OGUseCmsis</name>
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-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-          <name>GRuntimeLibThreads</name>
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-          <name>CCDefines</name>
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diff --git a/workspace_tools/export/iar_nucleo_f103rb.ewd.tmpl b/workspace_tools/export/iar_nucleo_f103rb.ewd.tmpl
deleted file mode 100644
index 4f6c25937e..0000000000
--- a/workspace_tools/export/iar_nucleo_f103rb.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f103rb.ewp.tmpl b/workspace_tools/export/iar_nucleo_f103rb.ewp.tmpl
deleted file mode 100644
index e77beade94..0000000000
--- a/workspace_tools/export/iar_nucleo_f103rb.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
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-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>20</version>
-          <state>40</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>5</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>7.10.1.6733</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.10.1.6733</state>
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-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F103xB	ST STM32F103xB</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-          <name>GFPUCoreSlave</name>
-          <version>20</version>
-          <state>40</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>20</version>
-          <state>40</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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diff --git a/workspace_tools/export/iar_nucleo_f302r8.ewd.tmpl b/workspace_tools/export/iar_nucleo_f302r8.ewd.tmpl
deleted file mode 100644
index 2fb12f63c5..0000000000
--- a/workspace_tools/export/iar_nucleo_f302r8.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-          <name>CCRDICatchFIQ</name>
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-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        <option>
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-        <option>
-          <name>CCJLinkInterfaceRadio</name>
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-        </option>
-        <option>
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-        <option>
-          <name>CCJLinkResetList</name>
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-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
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-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchNOCPERR</name>
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-        <option>
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-        <option>
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-          <state>0</state>
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-        <option>
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-        <option>
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-          <state></state>
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-        <option>
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-        <option>
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-        <option>
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-          <name>CCLmiFtdiInterfaceCmdLine</name>
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-        </option>
-      </data>
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-    <settings>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
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-        <option>
-          <name>LogFile</name>
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-        <option>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
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-        <option>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
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-        <option>
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-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>OCPEMicroAttachSlave</name>
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-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
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-        <option>
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-        <option>
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-          <state>$PROJ_DIR$\cspycomm.log</state>
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-          <name>CCPEMicroSerialPort</name>
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-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
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-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
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-          <state>0</state>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
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-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
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-        <option>
-          <name>CRDILogFileCheck</name>
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-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
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-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
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-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
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-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
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-        <option>
-          <name>CThirdPartyLogFileCheck</name>
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-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-          <name>OCDriverInfo</name>
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-          <name>OCXDS100AttachSlave</name>
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-          <name>TIPackage</name>
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-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
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-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
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-
-
diff --git a/workspace_tools/export/iar_nucleo_f302r8.ewp.tmpl b/workspace_tools/export/iar_nucleo_f302r8.ewp.tmpl
deleted file mode 100644
index 9907e5eaac..0000000000
--- a/workspace_tools/export/iar_nucleo_f302r8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
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-<project>
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-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-          <name>ListPath</name>
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-          <state>40</state>
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-          <state>1</state>
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-          <name>Input description</name>
-          <state>Full formatting.</state>
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-          <state>1</state>
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-          <name>Output description</name>
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-          <name>FPU</name>
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-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F302x8	ST STM32F302x8</state>
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diff --git a/workspace_tools/export/iar_nucleo_f303k8.ewd.tmpl b/workspace_tools/export/iar_nucleo_f303k8.ewd.tmpl
deleted file mode 100644
index 3c6396c651..0000000000
--- a/workspace_tools/export/iar_nucleo_f303k8.ewd.tmpl
+++ /dev/null
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-        <option>
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-        <option>
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-          <name>CCLmiftdiDoLogfile</name>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
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-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
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-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
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-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
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-        <debug>1</debug>
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-          <name>jtag</name>
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-          <state>0</state>
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-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f303k8.ewp.tmpl b/workspace_tools/export/iar_nucleo_f303k8.ewp.tmpl
deleted file mode 100644
index 79d4e4a708..0000000000
--- a/workspace_tools/export/iar_nucleo_f303k8.ewp.tmpl
+++ /dev/null
@@ -1,1871 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
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-          <name>OGLastSavedByProductVersion</name>
-          <state>7.40.3.8937</state>
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-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F303x8	ST STM32F303x8</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>22</version>
-          <state>39</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-      </data>
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-    <settings>
-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>31</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
-          <state>0</state>
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-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-          <name>CCPreprocFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocComments</name>
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-          <name>CCPreprocLine</name>
-          <state>0</state>
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-          <state>0</state>
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-        <option>
-          <name>CCListCMnemonics</name>
-          <state>0</state>
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-        <option>
-          <name>CCListCMessages</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCListAssSource</name>
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-          <name>CCDiagSuppress</name>
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-          <name>CCDiagRemark</name>
-          <state></state>
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-          <state>00000000</state>
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-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
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-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
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-  {{source_files}}
-</project>
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-
diff --git a/workspace_tools/export/iar_nucleo_f303re.ewd.tmpl b/workspace_tools/export/iar_nucleo_f303re.ewd.tmpl
deleted file mode 100644
index 73c991419b..0000000000
--- a/workspace_tools/export/iar_nucleo_f303re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-<project>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
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-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
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-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
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-        <option>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
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-        <option>
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-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <wantNonLocal>1</wantNonLocal>
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-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
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-        <option>
-          <name>CCLmiftdiDoLogfile</name>
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-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
-          <name>DoLogfile</name>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
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-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>UnusedAddr</name>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
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-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>OCPEMicroAttachSlave</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCPEMicroJtagSpeed</name>
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-        <option>
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-          <name>DoLogfile</name>
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-        <option>
-          <name>LogFile</name>
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-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
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-        <option>
-          <name>CCPEMicroSerialPort</name>
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-        <option>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
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-        </option>
-      </data>
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-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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-          <state>###Uninitialized###</state>
-        </option>
-        <option>
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-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
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-          <state>0</state>
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-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
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-          <state>0</state>
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-          <state>0</state>
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-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
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-        </option>
-      </data>
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-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        <option>
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-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
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-        <option>
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-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
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-          <state>0</state>
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-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
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-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
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-          <state>0</state>
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-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
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-          <state></state>
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-          <state>_call_main</state>
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-          <name>CCMacraigorInterfaceCmdLine</name>
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-      </data>
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-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
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-        <option>
-          <name>OCPEMicroAttachSlave</name>
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-          <state>0</state>
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-          <name>CCPEMicroResetDelay</name>
-          <state></state>
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-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
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-        <option>
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-        <option>
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-          <name>CCPEMicroUSBDevice</name>
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-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
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-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
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-        <option>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
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-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
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-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
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-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
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-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
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-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCXds100InterfaceList</name>
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-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-    </debuggerPlugins>
-  </configuration>
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-
-
diff --git a/workspace_tools/export/iar_nucleo_f303re.ewp.tmpl b/workspace_tools/export/iar_nucleo_f303re.ewp.tmpl
deleted file mode 100644
index 6c83366262..0000000000
--- a/workspace_tools/export/iar_nucleo_f303re.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
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-<project>
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-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-          <name>ListPath</name>
-          <state>Debug\List</state>
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-          <state>40</state>
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-          <name>Input description</name>
-          <state>Full formatting.</state>
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-          <name>Output description</name>
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-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F303xE	ST STM32F303xE</state>
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diff --git a/workspace_tools/export/iar_nucleo_f334r8.ewd.tmpl b/workspace_tools/export/iar_nucleo_f334r8.ewd.tmpl
deleted file mode 100644
index 1b9216e2ee..0000000000
--- a/workspace_tools/export/iar_nucleo_f334r8.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-        <option>
-          <name>OCJLinkScriptFile</name>
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-        <option>
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-          <state></state>
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-        <option>
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-    <settings>
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-        <option>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
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-        <option>
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-        </option>
-      </data>
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-    <settings>
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-        <option>
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-        <option>
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-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
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-          <name>LogFile</name>
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-    <settings>
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-        <option>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
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-
diff --git a/workspace_tools/export/iar_nucleo_f334r8.ewp.tmpl b/workspace_tools/export/iar_nucleo_f334r8.ewp.tmpl
deleted file mode 100644
index 7f267e6463..0000000000
--- a/workspace_tools/export/iar_nucleo_f334r8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_f401re.ewd.tmpl b/workspace_tools/export/iar_nucleo_f401re.ewd.tmpl
deleted file mode 100644
index 75df20f13c..0000000000
--- a/workspace_tools/export/iar_nucleo_f401re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_f401re.ewp.tmpl b/workspace_tools/export/iar_nucleo_f401re.ewp.tmpl
deleted file mode 100644
index e9d54cbb5e..0000000000
--- a/workspace_tools/export/iar_nucleo_f401re.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_f410rb.ewd.tmpl b/workspace_tools/export/iar_nucleo_f410rb.ewd.tmpl
deleted file mode 100644
index 19714b839e..0000000000
--- a/workspace_tools/export/iar_nucleo_f410rb.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
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-        <option>
-          <name>LogFile</name>
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-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
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-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
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-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100CatchData</name>
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-        <option>
-          <name>CCXds100CatchFIQ</name>
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-        <option>
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-
diff --git a/workspace_tools/export/iar_nucleo_f410rb.ewp.tmpl b/workspace_tools/export/iar_nucleo_f410rb.ewp.tmpl
deleted file mode 100644
index da1151de1e..0000000000
--- a/workspace_tools/export/iar_nucleo_f410rb.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
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-<project>
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diff --git a/workspace_tools/export/iar_nucleo_f411re.ewd.tmpl b/workspace_tools/export/iar_nucleo_f411re.ewd.tmpl
deleted file mode 100644
index ca699244fa..0000000000
--- a/workspace_tools/export/iar_nucleo_f411re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-    <settings>
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-        <option>
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diff --git a/workspace_tools/export/iar_nucleo_f411re.ewp.tmpl b/workspace_tools/export/iar_nucleo_f411re.ewp.tmpl
deleted file mode 100644
index 05ecbefba2..0000000000
--- a/workspace_tools/export/iar_nucleo_f411re.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_f446re.ewd.tmpl b/workspace_tools/export/iar_nucleo_f446re.ewd.tmpl
deleted file mode 100644
index 0fbeb00b43..0000000000
--- a/workspace_tools/export/iar_nucleo_f446re.ewd.tmpl
+++ /dev/null
@@ -1,2977 +0,0 @@
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-        <option>
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-          <state>_call_main</state>
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-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
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-      </data>
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-    <settings>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
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-          <state>0</state>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
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-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
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-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
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-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
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-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
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-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_nucleo_f446re.ewp.tmpl b/workspace_tools/export/iar_nucleo_f446re.ewp.tmpl
deleted file mode 100644
index ddecc73b8f..0000000000
--- a/workspace_tools/export/iar_nucleo_f446re.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
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-    <toolchain>
-      <name>ARM</name>
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-      <name>General</name>
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-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
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-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
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-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
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-          <name>Input description</name>
-          <state>Full formatting.</state>
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-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
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-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
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-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
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-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <name>OGProductVersion</name>
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-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
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-          <name>OGChipSelectEditMenu</name>
-          <state>STM32F446RE	ST STM32F446RE</state>
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-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
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-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-          <name>GBECoreSlave</name>
-          <version>22</version>
-          <state>39</state>
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-          <name>OGUseCmsis</name>
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-          <name>OGUseCmsisDspLib</name>
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-          <name>CoreVariant</name>
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-        <option>
-          <name>GFPUDeviceSlave</name>
-          <state>STM32F446RE	ST STM32F446RE</state>
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-          <name>FPU2</name>
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-          <state>4</state>
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-          <name>NrRegs</name>
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-          <name>NEON</name>
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-          <version>22</version>
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-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
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-          {% endfor %}
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diff --git a/workspace_tools/export/iar_nucleo_l053r8.ewd.tmpl b/workspace_tools/export/iar_nucleo_l053r8.ewd.tmpl
deleted file mode 100644
index da36da6931..0000000000
--- a/workspace_tools/export/iar_nucleo_l053r8.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-          <state>0</state>
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-        <option>
-          <name>CCJLinkIRLength</name>
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-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCRDICatchReset</name>
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-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
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-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
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-        <option>
-          <name>CCRDICatchIRQ</name>
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-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>CCJLinkBreakpointRadio</name>
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-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
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-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
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-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
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-          <name>CCCatchCHRERR</name>
-          <state>0</state>
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-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
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-        <option>
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-        <option>
-          <name>CCCatchINTERR</name>
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-        <option>
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-          <state>0</state>
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-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkScriptFile</name>
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-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
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-        <option>
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-          <state>0</state>
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-        <option>
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-          <state></state>
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-        <option>
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-          <state>72.0</state>
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-        <option>
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-        <option>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
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-      <name>LMIFTDI_ID</name>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
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-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
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-        <debug>1</debug>
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-          <state>0</state>
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-        <option>
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-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-        <option>
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-        <option>
-          <name>LogFile</name>
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-        <option>
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-        <option>
-          <name>EmuMultiTarget</name>
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-        <option>
-          <name>EmuHWReset</name>
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-        <option>
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-          <state>4</state>
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-        <option>
-          <name>CEmuCommPort</name>
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-        <option>
-          <name>jtago</name>
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-        <option>
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-        <option>
-          <name>UnusedAddr</name>
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-        <option>
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-        <option>
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-        <option>
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-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
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-        <option>
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-          <name>CCMacraigorInterfaceCmdLine</name>
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-        </option>
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-    <settings>
-      <name>PEMICRO_ID</name>
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-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-        <option>
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-        <option>
-          <name>LogFile</name>
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-        <option>
-          <name>CCPEMicroUSBDevice</name>
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-    <settings>
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-        <debug>1</debug>
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-          <name>CRDILogFileEdit</name>
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-          <name>CCRDICatchReset</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-        <debug>1</debug>
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-          <state>0</state>
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-        <option>
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-          <state>1</state>
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-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
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-          <state>0x00800000</state>
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-          <state></state>
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-          <state>#UNINITIALIZED#</state>
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-          <state>0</state>
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-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
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-          <state>###Uninitialized###</state>
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-        <option>
-          <name>CRDILogFileCheck</name>
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-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchData</name>
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-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
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-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>2</version>
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-        <debug>0</debug>
-        <option>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
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-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
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-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
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-        <option>
-          <name>CCCpuClockEdit</name>
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-          <state>2000</state>
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-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
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-          <name>CThirdPartyLogFileEditB</name>
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-          <state>0</state>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-
-
diff --git a/workspace_tools/export/iar_nucleo_l053r8.ewp.tmpl b/workspace_tools/export/iar_nucleo_l053r8.ewp.tmpl
deleted file mode 100644
index c9c4362ada..0000000000
--- a/workspace_tools/export/iar_nucleo_l053r8.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
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-<project>
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-          <state>Debug\Obj</state>
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-          <name>ListPath</name>
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-          <name>Output description</name>
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-          <name>OGChipSelectEditMenu</name>
-          <state>STM32L053x8	ST STM32L053x8</state>
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diff --git a/workspace_tools/export/iar_nucleo_l073rz.ewd.tmpl b/workspace_tools/export/iar_nucleo_l073rz.ewd.tmpl
deleted file mode 100644
index 5249066059..0000000000
--- a/workspace_tools/export/iar_nucleo_l073rz.ewd.tmpl
+++ /dev/null
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diff --git a/workspace_tools/export/iar_nucleo_l073rz.ewp.tmpl b/workspace_tools/export/iar_nucleo_l073rz.ewp.tmpl
deleted file mode 100644
index 712f1c975b..0000000000
--- a/workspace_tools/export/iar_nucleo_l073rz.ewp.tmpl
+++ /dev/null
@@ -1,1903 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_l152re.ewd.tmpl b/workspace_tools/export/iar_nucleo_l152re.ewd.tmpl
deleted file mode 100644
index 025a9b5107..0000000000
--- a/workspace_tools/export/iar_nucleo_l152re.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_l152re.ewp.tmpl b/workspace_tools/export/iar_nucleo_l152re.ewp.tmpl
deleted file mode 100644
index 53025e0c17..0000000000
--- a/workspace_tools/export/iar_nucleo_l152re.ewp.tmpl
+++ /dev/null
@@ -1,1899 +0,0 @@
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diff --git a/workspace_tools/export/iar_nucleo_l476rg.ewd.tmpl b/workspace_tools/export/iar_nucleo_l476rg.ewd.tmpl
deleted file mode 100644
index b553dd59aa..0000000000
--- a/workspace_tools/export/iar_nucleo_l476rg.ewd.tmpl
+++ /dev/null
@@ -1,2975 +0,0 @@
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-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
diff --git a/workspace_tools/export/iar_nucleo_l476rg.ewp.tmpl b/workspace_tools/export/iar_nucleo_l476rg.ewp.tmpl
deleted file mode 100644
index 5aa362353b..0000000000
--- a/workspace_tools/export/iar_nucleo_l476rg.ewp.tmpl
+++ /dev/null
@@ -1,1927 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
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-          <name>OGLastSavedByProductVersion</name>
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-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
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-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>STM32L476RG	ST STM32L476RG</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>1</state>
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-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>22</version>
-          <state>39</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>1</state>
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-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
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-        <option>
-          <name>CoreVariant</name>
-          <version>22</version>
-          <state>39</state>
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-        <option>
-          <name>GFPUDeviceSlave</name>
-          <state>STM32L476RG	ST STM32L476RG</state>
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-        <option>
-          <name>FPU2</name>
-          <version>0</version>
-          <state>4</state>
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-          <name>NrRegs</name>
-          <version>0</version>
-          <state>1</state>
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-        <option>
-          <name>NEON</name>
-          <state>0</state>
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-          <name>GFPUCoreSlave2</name>
-          <version>22</version>
-          <state>39</state>
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-      <name>ICCARM</name>
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-        <version>31</version>
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-        <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
-          <state>0</state>
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-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-          <name>CCPreprocComments</name>
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-        {% for path in include_paths %}
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diff --git a/workspace_tools/export/iar_seeed_tiny_ble.ewd.tmpl b/workspace_tools/export/iar_seeed_tiny_ble.ewd.tmpl
deleted file mode 100644
index bf2ee4bd14..0000000000
--- a/workspace_tools/export/iar_seeed_tiny_ble.ewd.tmpl
+++ /dev/null
@@ -1,1370 +0,0 @@
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-        <option>
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-          <state>aaa.bbb.ccc.ddd</state>
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-          <state></state>
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-          <state>#UNINITIALIZED#</state>
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-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
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-          <state>0</state>
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-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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-          <state>###Uninitialized###</state>
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-          <name>CRDILogFileCheck</name>
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-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
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-          <name>CCRDICatchSWI</name>
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-          <name>CCRDICatchData</name>
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-          <name>CCRDICatchPrefetch</name>
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-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
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-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <version>2</version>
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-        <debug>1</debug>
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-          <name>CCSTLinkInterfaceRadio</name>
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-          <name>CCSTLinkResetList</name>
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-          <name>CCCpuClockEdit</name>
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-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-
diff --git a/workspace_tools/export/iar_seeed_tiny_ble.ewp.tmpl b/workspace_tools/export/iar_seeed_tiny_ble.ewp.tmpl
deleted file mode 100644
index 14a35a8a06..0000000000
--- a/workspace_tools/export/iar_seeed_tiny_ble.ewp.tmpl
+++ /dev/null
@@ -1,956 +0,0 @@
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-<project>
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-          <state>Debug\Obj</state>
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-  {{source_files}}
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-
diff --git a/workspace_tools/export/iar_stm32f407.ewp.tmpl b/workspace_tools/export/iar_stm32f407.ewp.tmpl
deleted file mode 100644
index b463eb74f8..0000000000
--- a/workspace_tools/export/iar_stm32f407.ewp.tmpl
+++ /dev/null
@@ -1,954 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-          <name>ListPath</name>
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-          <name>Variant</name>
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-          <state>40</state>
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-          <name>Input description</name>
-          <state>Full formatting.</state>
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-  {{source_files}} 
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-
diff --git a/workspace_tools/export/iar_ublox_c027.ewd.tmpl b/workspace_tools/export/iar_ublox_c027.ewd.tmpl
deleted file mode 100644
index e7f44e85b2..0000000000
--- a/workspace_tools/export/iar_ublox_c027.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
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-        <option>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
-        </option>
-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_ublox_c027.ewp.tmpl b/workspace_tools/export/iar_ublox_c027.ewp.tmpl
deleted file mode 100644
index 92e99379a1..0000000000
--- a/workspace_tools/export/iar_ublox_c027.ewp.tmpl
+++ /dev/null
@@ -1,1829 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>21</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
-        </option>
-        <option>
-          <name>Variant</name>
-          <version>19</version>
-          <state>37</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
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-        <option>
-          <name>FPU</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
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-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
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-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
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-          <name>OGLastSavedByProductVersion</name>
-          <state>6.30.6.53380</state>
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-          <name>GeneralEnableMisra</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>LPC1768	NXP LPC1768</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
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-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
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-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
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-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
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-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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-          <name>GFPUCoreSlave</name>
-          <version>19</version>
-          <state>37</state>
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-        <option>
-          <name>GBECoreSlave</name>
-          <version>19</version>
-          <state>37</state>
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-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
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-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
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-      <name>ICCARM</name>
-      <archiveVersion>2</archiveVersion>
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-        <version>28</version>
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-        <debug>1</debug>
-        <option>
-          <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
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-        <option>
-          <name>CCPreprocFile</name>
-          <state>0</state>
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-        <option>
-          <name>CCPreprocComments</name>
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-        <option>
-          <name>CCListCMessages</name>
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-          <name>CCListAssFile</name>
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-          <state>0</state>
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-        <option>
-          <name>CCDiagSuppress</name>
-          <state>Pa050,Pa084,Pa093,Pa082</state>
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-          <name>CCDiagRemark</name>
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-          <state>1</state>
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-          <state>1111111</state>
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From 028465a9b8e42300bf0eb1b362f8f474f40fae9b Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 12 Feb 2016 16:37:25 +0100
Subject: [PATCH 16/78] [B96B_F446VE] change serial type

Use only the index, not the UARTName any more.
In case of app with 2 serial (using DMA) + 1 serial (stdio), we have found a bug. The dma handler is overwritten by the last initialized serial object.
Therefore read and write functions did not work anymore.
We have reworked this file to save 1 handler per UART IP, and align it with MBED OS file.
Tests have been passed. Same status as before (OK except MBED_37, manual test for SERIAL_ASYNC also OK).
---
 .../TARGET_B96B_F446VE/objects.h              |   3 +-
 .../TARGET_STM/TARGET_STM32F4/serial_api.c    | 840 +++++++++++++-----
 2 files changed, 594 insertions(+), 249 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
index 137da19148..5ffe5b3c6a 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h
@@ -66,8 +66,7 @@ struct dac_s {
 };
 
 struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
+    int index;
     uint32_t baudrate;
     uint32_t databits;
     uint32_t stopbits;
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c
index e40896d7aa..1604288278 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c
@@ -27,7 +27,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
+#ifdef YOTTA_CFG_MBED_OS
+#include "target_config.h"
+#include "uvisor-lib/uvisor-lib.h"
+#include "mbed-drivers/mbed_assert.h"
+#else
 #include "mbed_assert.h"
+#endif
 #include "serial_api.h"
 
 #if DEVICE_SERIAL
@@ -36,25 +42,53 @@
 #include "pinmap.h"
 #include <string.h>
 #include "PeripheralPins.h"
+#ifdef YOTTA_CFG_MBED_OS
+#include "mbed-drivers/mbed_error.h"
+#else
 #include "mbed_error.h"
+#endif
+
+#define DEBUG_STDIO 0
+
+#ifndef DEBUG_STDIO
+#   define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+#   include <stdio.h>
+#   define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+#   define DEBUG_PRINTF(...) {}
+#endif
 
 #define UART_NUM (8)
 #define UART_STATE_RX_ACTIVE 0x20
 #define UART_STATE_TX_ACTIVE 0x10
 
-static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0};
-
 #if DEVICE_SERIAL_ASYNCH_DMA
-static const uint32_t DMA_UartRx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5};
-static const uint32_t DMA_UartRx_Stream[UART_NUM]  = {(uint32_t)DMA2_Stream5, (uint32_t) DMA1_Stream5, (uint32_t) DMA1_Stream1, (uint32_t) DMA1_Stream2, (uint32_t) DMA1_Stream0, (uint32_t) DMA2_Stream5, (uint32_t) DMA1_Stream3, (uint32_t) DMA1_Stream6};
-static const uint32_t DMA_UartTx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5};
-static const uint32_t DMA_UartTx_Stream[UART_NUM]  = {(uint32_t)DMA2_Stream7, (uint32_t) DMA1_Stream6, (uint32_t) DMA1_Stream3, (uint32_t) DMA1_Stream4, (uint32_t) DMA1_Stream7, (uint32_t) DMA2_Stream6, (uint32_t) DMA1_Stream1, (uint32_t) DMA1_Stream0};
-
+static const uint32_t DMA_UartRx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, \
+                                                      DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5};
+DMA_Stream_TypeDef *DMA_UartRx_Stream[UART_NUM] = {
+  DMA2_Stream5, DMA1_Stream5, DMA1_Stream1, \
+  DMA1_Stream2, DMA1_Stream0, DMA2_Stream1, \
+  DMA1_Stream3, DMA1_Stream6
+};
+static const uint32_t DMA_UartTx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, \
+                                                      DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5};
+DMA_Stream_TypeDef *DMA_UartTx_Stream[UART_NUM] = {
+    DMA2_Stream7, DMA1_Stream6, DMA1_Stream3, \
+    DMA1_Stream4, DMA1_Stream7, DMA2_Stream6,\
+    DMA1_Stream1, DMA1_Stream0
+};
+DMA_HandleTypeDef DmaHandle;
 #endif
+
+uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0};
 static uart_irq_handler irq_handler;
 
-DMA_HandleTypeDef DmaHandle;
-UART_HandleTypeDef UartHandle;
+static DMA_HandleTypeDef DmaTxHandle[UART_NUM];
+static DMA_HandleTypeDef DmaRxHandle[UART_NUM];
+static UART_HandleTypeDef UartHandle[UART_NUM];
 
 int stdio_uart_inited = 0;
 serial_t stdio_uart;
@@ -65,81 +99,91 @@ serial_t stdio_uart;
 #define SERIAL_OBJ(X) (obj->X)
 #endif
 
-static void init_uart(serial_t *obj)
+static void init_uart(serial_t *obj, UARTName instance)
 {
-#if DEVICE_SERIAL_ASYNCH_DMA
-    static DMA_HandleTypeDef hdma_tx;
-    static DMA_HandleTypeDef hdma_rx;
-#endif
 
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    handle->Instance = (USART_TypeDef *)instance;
 
-    UartHandle.Init.BaudRate     = SERIAL_OBJ(baudrate);
-    UartHandle.Init.WordLength   = SERIAL_OBJ(databits);
-    UartHandle.Init.StopBits     = SERIAL_OBJ(stopbits);
-    UartHandle.Init.Parity       = SERIAL_OBJ(parity);
+    handle->Init.BaudRate     = SERIAL_OBJ(baudrate);
+    handle->Init.WordLength   = SERIAL_OBJ(databits);
+    handle->Init.StopBits     = SERIAL_OBJ(stopbits);
+    handle->Init.Parity       = SERIAL_OBJ(parity);
 #if DEVICE_SERIAL_FC
-    UartHandle.Init.HwFlowCtl    = SERIAL_OBJ(hw_flow_ctl);
+    handle->Init.HwFlowCtl    = SERIAL_OBJ(hw_flow_ctl);
 #else
-    UartHandle.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
+    handle->Init.HwFlowCtl    = UART_HWCONTROL_NONE;
 #endif
-    UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+    handle->Init.OverSampling = UART_OVERSAMPLING_16;
+    handle->TxXferCount         = 0;
+    handle->RxXferCount         = 0;
 
     if (SERIAL_OBJ(pin_rx) == NC) {
-        UartHandle.Init.Mode = UART_MODE_TX;
+      handle->Init.Mode = UART_MODE_TX;
     } else if (SERIAL_OBJ(pin_tx) == NC) {
-        UartHandle.Init.Mode = UART_MODE_RX;
+      handle->Init.Mode = UART_MODE_RX;
     } else {
-        UartHandle.Init.Mode = UART_MODE_TX_RX;
+      handle->Init.Mode = UART_MODE_TX_RX;
     }
+    
+#ifdef YOTTA_CFG_MBED_OS
+    if (SERIAL_OBJ(pin_tx) == STDIO_UART_TX && SERIAL_OBJ(pin_rx) == STDIO_UART_RX) {
+        handle->Init.BaudRate = YOTTA_CFG_MBED_OS_STDIO_DEFAULT_BAUD;
+    }
+#endif
+    
 #if DEVICE_SERIAL_ASYNCH_DMA
     if (SERIAL_OBJ(pin_tx) != NC) {
         // set DMA in the UartHandle
+        DMA_HandleTypeDef *hdma_tx = &DmaTxHandle[SERIAL_OBJ(index)];
         /* Configure the DMA handler for Transmission process */
-        hdma_tx.Instance                 = (DMA_Stream_TypeDef *)DMA_UartTx_Stream[SERIAL_OBJ(index)];
-        hdma_tx.Init.Channel             = DMA_UartTx_Channel[SERIAL_OBJ(index)];
-        hdma_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
-        hdma_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
-        hdma_tx.Init.MemInc              = DMA_MINC_ENABLE;
-        hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
-        hdma_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
-        hdma_tx.Init.Mode                = DMA_NORMAL;
-        hdma_tx.Init.Priority            = DMA_PRIORITY_LOW;
-        hdma_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
-        hdma_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
-        hdma_tx.Init.MemBurst            = DMA_MBURST_INC4;
-        hdma_tx.Init.PeriphBurst         = DMA_PBURST_INC4;
+        hdma_tx->Instance                 = (DMA_Stream_TypeDef *)DMA_UartTx_Stream[SERIAL_OBJ(index)];
+        hdma_tx->Init.Channel             = DMA_UartTx_Channel[SERIAL_OBJ(index)];
+        hdma_tx->Init.Direction           = DMA_MEMORY_TO_PERIPH;
+        hdma_tx->Init.PeriphInc           = DMA_PINC_DISABLE;
+        hdma_tx->Init.MemInc              = DMA_MINC_ENABLE;
+        hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+        hdma_tx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+        hdma_tx->Init.Mode                = DMA_NORMAL;
+        hdma_tx->Init.Priority            = DMA_PRIORITY_LOW;
+        hdma_tx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
+        hdma_tx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+        hdma_tx->Init.MemBurst            = DMA_MBURST_INC4;
+        hdma_tx->Init.PeriphBurst         = DMA_PBURST_INC4;
 
-        HAL_DMA_Init(&hdma_tx);
+        HAL_DMA_Init(hdma_tx);
 
         /* Associate the initialized DMA handle to the UART handle */
-        __HAL_LINKDMA(&UartHandle, hdmatx, hdma_tx);
+        handle->hdmatx = hdma_tx;
+        hdma_tx->Parent = handle;
     }
     
     if (SERIAL_OBJ(pin_rx) != NC) {
         /* Configure the DMA handler for reception process */
-        hdma_rx.Instance                 = (DMA_Stream_TypeDef *)DMA_UartRx_Stream[SERIAL_OBJ(index)];
-        hdma_rx.Init.Channel             = DMA_UartRx_Channel[SERIAL_OBJ(index)];
-        hdma_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
-        hdma_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
-        hdma_rx.Init.MemInc              = DMA_MINC_ENABLE;
-        hdma_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
-        hdma_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
-        hdma_rx.Init.Mode                = DMA_NORMAL;
-        hdma_rx.Init.Priority            = DMA_PRIORITY_HIGH;
-        hdma_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
-        hdma_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
-        hdma_rx.Init.MemBurst            = DMA_MBURST_INC4;
-        hdma_rx.Init.PeriphBurst         = DMA_PBURST_INC4;
+        DMA_HandleTypeDef *hdma_rx = &DmaRxHandle[SERIAL_OBJ(index)];
+        hdma_rx->Instance                 = (DMA_Stream_TypeDef *)DMA_UartRx_Stream[SERIAL_OBJ(index)];
+        hdma_rx->Init.Channel             = DMA_UartRx_Channel[SERIAL_OBJ(index)];
+        hdma_rx->Init.Direction           = DMA_PERIPH_TO_MEMORY;
+        hdma_rx->Init.PeriphInc           = DMA_PINC_DISABLE;
+        hdma_rx->Init.MemInc              = DMA_MINC_ENABLE;
+        hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+        hdma_rx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+        hdma_rx->Init.Mode                = DMA_NORMAL;
+        hdma_rx->Init.Priority            = DMA_PRIORITY_HIGH;
+        hdma_rx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
+        hdma_rx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+        hdma_rx->Init.MemBurst            = DMA_MBURST_INC4;
+        hdma_rx->Init.PeriphBurst         = DMA_PBURST_INC4;
 
-        HAL_DMA_Init(&hdma_rx);
+        HAL_DMA_Init(hdma_rx);
 
         /* Associate the initialized DMA handle to the UART handle */
-        __HAL_LINKDMA(&UartHandle, hdmarx, hdma_rx);
+        handle->hdmarx = hdma_rx;
+        hdma_rx->Parent = handle;
     }
 #endif
 
-    if (HAL_UART_Init(&UartHandle) != HAL_OK) {
+    if (HAL_UART_Init(handle) != HAL_OK) {
         error("Cannot initialize UART\n");
     }
 }
@@ -151,12 +195,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
     UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
 
     // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    SERIAL_OBJ(uart) = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    UARTName instance = (UARTName)pinmap_merge(uart_tx, uart_rx);
     
-    MBED_ASSERT(SERIAL_OBJ(uart) != (UARTName)NC);
+    MBED_ASSERT(instance != (UARTName)NC);
 
     // Enable USART clock
-    switch (SERIAL_OBJ(uart)) {
+    switch (instance) {
         case UART_1:
             __HAL_RCC_USART1_CLK_ENABLE();
             SERIAL_OBJ(index) = 0;
@@ -247,38 +291,45 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
     SERIAL_OBJ(pin_tx) = tx;
     SERIAL_OBJ(pin_rx) = rx;
 
-    init_uart(obj);
+    init_uart(obj, instance);
 
+#ifndef YOTTA_CFG_MBED_OS
     // For stdio management
-    if (SERIAL_OBJ(uart) == STDIO_UART) {
+    if ((int)(UartHandle[SERIAL_OBJ(index)].Instance) == STDIO_UART) {
         stdio_uart_inited = 1;
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
+#endif
+
+    DEBUG_PRINTF("UART%u: Init\n", obj->serial.module+1);
 }
 
 void serial_free(serial_t *obj)
 {
     // Reset UART and disable clock
-    switch (SERIAL_OBJ(uart)) {
-        case UART_1:
+    switch (SERIAL_OBJ(index)) {
+        case 0:
             __USART1_FORCE_RESET();
             __USART1_RELEASE_RESET();
             __USART1_CLK_DISABLE();
             break;
-        case UART_2:
+        case 1:
             __USART2_FORCE_RESET();
             __USART2_RELEASE_RESET();
             __USART2_CLK_DISABLE();
+#if DEVICE_SERIAL_ASYNCH_DMA
+            __HAL_RCC_DMA1_CLK_DISABLE();
+#endif
             break;
 #if defined(USART3_BASE)
-        case UART_3:
+        case 2:
             __USART3_FORCE_RESET();
             __USART3_RELEASE_RESET();
             __USART3_CLK_DISABLE();
             break;
 #endif
 #if defined(UART4_BASE)
-        case UART_4:
+        case 3:
             __UART4_FORCE_RESET();
             __UART4_RELEASE_RESET();
             __UART4_CLK_DISABLE();
@@ -288,100 +339,138 @@ void serial_free(serial_t *obj)
             break;
 #endif
 #if defined(UART5_BASE)
-        case UART_5:
+        case 4:
             __UART5_FORCE_RESET();
             __UART5_RELEASE_RESET();
             __UART5_CLK_DISABLE();
             break;
 #endif
 #if defined(USART6_BASE)
-        case UART_6:
+        case 5:
             __USART6_FORCE_RESET();
             __USART6_RELEASE_RESET();
             __USART6_CLK_DISABLE();
             break;
 #endif
 #if defined(UART7_BASE)
-        case UART_7:
+        case 6:
             __UART7_FORCE_RESET();
             __UART7_RELEASE_RESET();
             __UART7_CLK_DISABLE();
             break;
 #endif
 #if defined(UART8_BASE)
-        case UART_8:
+        case 7:
             __UART8_FORCE_RESET();
             __UART8_RELEASE_RESET();
             __UART8_CLK_DISABLE();
             break;
 #endif
     }
+    
     // Configure GPIOs
     pin_function(SERIAL_OBJ(pin_tx), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
     pin_function(SERIAL_OBJ(pin_rx), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
 
     serial_irq_ids[SERIAL_OBJ(index)] = 0;
+
+    DEBUG_PRINTF("UART%u: Free\n", obj->serial.module+1);
 }
 
 void serial_baud(serial_t *obj, int baudrate)
 {
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    
     SERIAL_OBJ(baudrate) = baudrate;
-    init_uart(obj);
+    handle->Init.BaudRate = baudrate;
+    
+    if (HAL_UART_Init(handle) != HAL_OK) {
+           error("Cannot initialize UART\n");
+    }
+    
+    DEBUG_PRINTF("UART%u: Baudrate: %u\n", obj->serial.module+1, baudrate);
 }
 
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
 {
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+  
     if (data_bits == 9) {
         SERIAL_OBJ(databits) = UART_WORDLENGTH_9B;
+        handle->Init.WordLength = UART_WORDLENGTH_9B;
     } else {
         SERIAL_OBJ(databits) = UART_WORDLENGTH_8B;
+        handle->Init.WordLength = UART_WORDLENGTH_8B;
     }
 
     switch (parity) {
         case ParityOdd:
-        case ParityForced0:
             SERIAL_OBJ(parity) = UART_PARITY_ODD;
+            handle->Init.Parity = UART_PARITY_ODD;
             break;
         case ParityEven:
-        case ParityForced1:
             SERIAL_OBJ(parity) = UART_PARITY_EVEN;
+            handle->Init.Parity = UART_PARITY_EVEN;
             break;
         default: // ParityNone
+        case ParityForced0: // unsupported!
+        case ParityForced1: // unsupported!
             SERIAL_OBJ(parity) = UART_PARITY_NONE;
+            handle->Init.Parity = UART_PARITY_NONE;
             break;
     }
 
     if (stop_bits == 2) {
         SERIAL_OBJ(stopbits) = UART_STOPBITS_2;
+        handle->Init.StopBits = UART_STOPBITS_2;
     } else {
         SERIAL_OBJ(stopbits) = UART_STOPBITS_1;
+        handle->Init.StopBits = UART_STOPBITS_1;
     }
 
-    init_uart(obj);
+    if (HAL_UART_Init(handle) != HAL_OK) {
+           error("Cannot initialize UART\n");
+    }
+
+    DEBUG_PRINTF("UART%u: Format: %u, %u, %u\n", obj->serial.module+1, data_bits, parity, stop_bits);
 }
 
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
 
-static void uart_irq(UARTName name, int id)
+static void uart_irq(int id)
 {
-    UartHandle.Instance = (USART_TypeDef *)name;
+  UART_HandleTypeDef *handle = &UartHandle[id];
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(handle, UART_FLAG_TC) != RESET) {
             irq_handler(serial_irq_ids[id], TxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC);
+            __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TC);
         }
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
+        if (__HAL_UART_GET_FLAG(handle, UART_FLAG_RXNE) != RESET) {
             irq_handler(serial_irq_ids[id], RxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+            __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_RXNE);
         }
     }
 }
+
 #if DEVICE_SERIAL_ASYNCH_DMA
-static void dma_irq(DMAName name, int id)
+static void dma_irq(DMAName name, int id, SerialIrq txrxirq)
 {
-  // TO DO
+
+  if (serial_irq_ids[id] != 0) {
+    if (txrxirq == RxIrq) {
+      if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) {
+            irq_handler(serial_irq_ids[id], RxIrq);
+            __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF2_6);
+        }
+    } else {
+      if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) {
+            irq_handler(serial_irq_ids[id], TxIrq);
+            __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF0_4);
+        }
+    }    
+  }
     DmaHandle.Instance = (DMA_Stream_TypeDef *)name;
     if (serial_irq_ids[id] != 0) {
         if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) {
@@ -398,66 +487,131 @@ static void dma_irq(DMAName name, int id)
 
 static void uart1_irq(void)
 {
-    uart_irq(UART_1, 0);
+    uart_irq(0);
 }
 
 static void uart2_irq(void)
 {
-    uart_irq(UART_2, 1);
+    uart_irq(1);
 }
 
 #if defined(USART3_BASE)
 static void uart3_irq(void)
 {
-    uart_irq(UART_3, 2);
+    uart_irq(2);
 }
 #endif
 
 #if defined(UART4_BASE)
 static void uart4_irq(void)
 {
-    uart_irq(UART_4, 3);
+    uart_irq(3);
 }
+#endif
+
 #if DEVICE_SERIAL_ASYNCH_DMA
 
+#if defined(UART5_BASE)
+static void dma1_stream0_irq(void)
+{
+    dma_irq(DMA_1, 4, RxIrq); // uart5_rx
+}
+#endif
+
+#if defined(USART3_BASE)
+static void dma1_stream1_irq(void)
+{
+    dma_irq(DMA_1, 2, RxIrq); // uart3_rx
+}
+#endif
+
+#if defined(UART4_BASE)
 static void dma1_stream2_irq(void)
 {
-    dma_irq(DMA_1, 3 /* TO DO : ??? WHAT IS THIS 3 ??? */);
+    dma_irq(DMA_1, 3, RxIrq); // uart4_rx
 }
+#endif
 
+#if defined(USART3_BASE)
+static void dma1_stream3_irq(void)
+{
+    dma_irq(DMA_1, 2, TxIrq); // uart3_tx
+}
+#endif
 
+#if defined(UART4_BASE)
 static void dma1_stream4_irq(void)
 {
-    dma_irq(DMA_1, 3 /* TO DO : ??? WHAT IS THIS 3 ??? */);
+    dma_irq(DMA_1, 3, TxIrq); // uart4_tx
 }
 #endif
+
+static void dma1_stream5_irq(void)
+{
+    dma_irq(DMA_1, 1, RxIrq); // uart2_rx
+}
+
+static void dma1_stream6_irq(void)
+{
+    dma_irq(DMA_1, 1, TxIrq); // uart2_tx
+}
+
+#if defined(UART5_BASE)
+static void dma1_stream7_irq(void)
+{
+    dma_irq(DMA_1, 4, TxIrq); // uart5_tx
+}
 #endif
 
+#if defined(USART6_BASE)
+static void dma2_stream1_irq(void)
+{
+    dma_irq(DMA_2, 5, RxIrq); // uart6_rx
+}
+#endif
+
+static void dma2_stream5_irq(void)
+{
+    dma_irq(DMA_2, 0, RxIrq); // uart1_rx
+}
+
+static void dma2_stream6_irq(void)
+{
+    dma_irq(DMA_2, 5, TxIrq); // uart6_tx
+}
+
+static void dma2_stream7_irq(void)
+{
+    dma_irq(DMA_2, 0, TxIrq); // uart1_tx
+}
+
+#endif // DEVICE_SERIAL_ASYNCH_DMA
+
 #if defined(UART5_BASE)
 static void uart5_irq(void)
 {
-    uart_irq(UART_5, 4);
+    uart_irq(4);
 }
 #endif
 
 #if defined(USART6_BASE)
 static void uart6_irq(void)
 {
-    uart_irq(UART_6, 5);
+    uart_irq(5);
 }
 #endif
 
 #if defined(UART7_BASE)
 static void uart7_irq(void)
 {
-    uart_irq(UART_7, 6);
+    uart_irq(6);
 }
 #endif
 
 #if defined(UART8_BASE)
 static void uart8_irq(void)
 {
-    uart_irq(UART_8, 7);
+    uart_irq(7);
 }
 #endif
 
@@ -476,26 +630,53 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
     uint32_t vector_dma = 0;
 #endif
 
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
 
-    switch (SERIAL_OBJ(uart)) {
-        case UART_1:
+    switch (SERIAL_OBJ(index)) {
+        case 0:
             irq_n = USART1_IRQn;
             vector = (uint32_t)&uart1_irq;
+#if DEVICE_SERIAL_ASYNCH_DMA
+            if (irq == RxIrq) {
+                irqn_dma = DMA2_Stream5_IRQn;
+                vector_dma = (uint32_t)&dma2_stream5_irq;
+            } else {
+                irqn_dma = DMA2_Stream7_IRQn;
+                vector_dma = (uint32_t)&dma2_stream7_irq;
+            }
+#endif
             break;
 
-        case UART_2:
+        case 1:
             irq_n = USART2_IRQn;
             vector = (uint32_t)&uart2_irq;
+#if DEVICE_SERIAL_ASYNCH_DMA
+            if (irq == RxIrq) {
+                irqn_dma = DMA1_Stream5_IRQn;
+                vector_dma = (uint32_t)&dma1_stream5_irq;
+            } else {
+                irqn_dma = DMA1_Stream6_IRQn;
+                vector_dma = (uint32_t)&dma1_stream6_irq;
+            }
+#endif
             break;
 #if defined(USART3_BASE)
-        case UART_3:
+        case 2:
             irq_n = USART3_IRQn;
             vector = (uint32_t)&uart3_irq;
+#if DEVICE_SERIAL_ASYNCH_DMA
+            if (irq == RxIrq) {
+                irqn_dma = DMA1_Stream1_IRQn;
+                vector_dma = (uint32_t)&dma1_stream1_irq;
+            } else {
+                irqn_dma = DMA1_Stream3_IRQn;
+                vector_dma = (uint32_t)&dma1_stream3_irq;
+            }
+#endif
             break;
 #endif
 #if defined(UART4_BASE)
-        case UART_4:
+        case 3:
             irq_n = UART4_IRQn;
             vector = (uint32_t)&uart4_irq;
 #if DEVICE_SERIAL_ASYNCH_DMA
@@ -510,25 +691,43 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
             break;
 #endif
 #if defined(UART5_BASE)
-        case UART_5:
+        case 4:
             irq_n = UART5_IRQn;
             vector = (uint32_t)&uart5_irq;
+#if DEVICE_SERIAL_ASYNCH_DMA
+            if (irq == RxIrq) {
+                irqn_dma = DMA1_Stream0_IRQn;
+                vector_dma = (uint32_t)&dma1_stream0_irq;
+            } else {
+                irqn_dma = DMA1_Stream4_IRQn;
+                vector_dma = (uint32_t)&dma1_stream7_irq;
+            }
+#endif
             break;
 #endif
 #if defined(USART6_BASE)
-        case UART_6:
+        case 5:
             irq_n = USART6_IRQn;
             vector = (uint32_t)&uart6_irq;
+#if DEVICE_SERIAL_ASYNCH_DMA
+            if (irq == RxIrq) {
+                irqn_dma = DMA2_Stream1_IRQn;
+                vector_dma = (uint32_t)&dma2_stream1_irq;
+            } else {
+                irqn_dma = DMA2_Stream6_IRQn;
+                vector_dma = (uint32_t)&dma2_stream6_irq;
+            }
+#endif
             break;
 #endif
 #if defined(UART7_BASE)
-        case UART_7:
+        case 6:
             irq_n = UART7_IRQn;
             vector = (uint32_t)&uart7_irq;
             break;
 #endif
 #if defined(UART8_BASE)
-        case UART_8:
+        case 7:
             irq_n = UART8_IRQn;
             vector = (uint32_t)&uart8_irq;
             break;
@@ -538,7 +737,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
     if (enable) {
 
         if (irq == RxIrq) {
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+            __HAL_UART_ENABLE_IT(handle, UART_IT_RXNE);
 #if DEVICE_SERIAL_ASYNCH_DMA
             NVIC_SetVector(irq_n, vector_dma);
             NVIC_EnableIRQ(irq_n);
@@ -549,7 +748,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
             NVIC_EnableIRQ(irq_n);
 #endif
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(handle, UART_IT_TC);
             NVIC_SetVector(irq_n, vector);
             NVIC_EnableIRQ(irq_n);
 #if DEVICE_SERIAL_ASYNCH_DMA
@@ -562,13 +761,13 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
         int all_disabled = 0;
 
         if (irq == RxIrq) {
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+            __HAL_UART_DISABLE_IT(handle, UART_IT_RXNE);
             // Check if TxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
+            if ((handle->Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TXE);
+            __HAL_UART_DISABLE_IT(handle, UART_IT_TXE);
             // Check if RxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+            if ((handle->Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
         }
 
         if (all_disabled) {
@@ -587,41 +786,41 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
 
 int serial_getc(serial_t *obj)
 {
-    USART_TypeDef *uart = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     while (!serial_readable(obj));
-    return (int)(uart->DR & 0x1FF);
+    return (int)(handle->Instance->DR & 0x1FF);
 }
 
 void serial_putc(serial_t *obj, int c)
 {
-    USART_TypeDef *uart = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     while (!serial_writable(obj));
-    uart->DR = (uint32_t)(c & 0x1FF);
+    handle->Instance->DR = (uint32_t)(c & 0x1FF);
 }
 
 int serial_readable(serial_t *obj)
 {
     int status;
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     // Check if data is received
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
+    status = ((__HAL_UART_GET_FLAG(handle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
     return status;
 }
 
 int serial_writable(serial_t *obj)
 {
     int status;
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     // Check if data is transmitted
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
+    status = ((__HAL_UART_GET_FLAG(handle, UART_FLAG_TXE) != RESET) ? 1 : 0);
     return status;
 }
 
 void serial_clear(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE);
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TXE);
+    __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_RXNE);
 }
 
 void serial_pinout_tx(PinName tx)
@@ -631,12 +830,13 @@ void serial_pinout_tx(PinName tx)
 
 void serial_break_set(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    HAL_LIN_SendBreak(&UartHandle);
+    UART_HandleTypeDef *uart = &UartHandle[SERIAL_OBJ(index)];
+    HAL_LIN_SendBreak(uart);
 }
 
 void serial_break_clear(serial_t *obj)
 {
+    (void)obj;
 }
 
 //########################################################################################
@@ -657,7 +857,6 @@ static void h_serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8
 {
     // We only support byte buffers for now
     MBED_ASSERT(width == 8);
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
   
     // Exit if a transmit is already on-going
     if (serial_tx_active(obj)) return;
@@ -729,46 +928,44 @@ static IRQn_Type h_serial_get_irq_index(serial_t *obj)
 {
     IRQn_Type irq_n = (IRQn_Type)0;
 
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
-
-    switch (SERIAL_OBJ(uart)) {
+    switch (SERIAL_OBJ(index)) {
 #if defined(USART1_BASE)
-        case UART_1:
+        case 0:
             irq_n = USART1_IRQn;
             break;
 #endif
 #if defined(USART2_BASE)
-        case UART_2:
+        case 1:
             irq_n = USART2_IRQn;
             break;
 #endif
 #if defined(USART3_BASE)
-        case UART_3:
+        case 2:
             irq_n = USART3_IRQn;
             break;
 #endif
 #if defined(UART4_BASE)
-        case UART_4:
+        case 3:
             irq_n = UART4_IRQn;
             break;
 #endif
-#if defined(UART5_BASE)
-        case UART_5:
+#if defined(USART5_BASE)
+        case 4:
             irq_n = UART5_IRQn;
             break;
 #endif
 #if defined(USART6_BASE)
-        case UART_6:
+        case 5:
             irq_n = USART6_IRQn;
             break;
 #endif
 #if defined(UART7_BASE)
-        case UART_7:
+        case 6:
             irq_n = UART7_IRQn;
             break;
 #endif
 #if defined(UART8_BASE)
-        case UART_8:
+        case 7:
             irq_n = UART8_IRQn;
             break;
 #endif
@@ -781,24 +978,177 @@ static IRQn_Type h_serial_get_irq_index(serial_t *obj)
 
 #if DEVICE_SERIAL_ASYNCH_DMA
 
-/** The asynchronous TX and RX handler.
- *
- * @param obj The serial object
- * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
- */
-static void h_serial_txdma_irq_handler_asynch()
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef MBED_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-    HAL_DMA_IRQHandler(UartHandle.hdmatx);
+    /* Process locked */
+    __HAL_LOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+     /* Check the parameters */
+    assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    /* Clear DBM bit */
+    hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+    /* Configure DMA Stream data length */
+    hdma->Instance->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
+        /* Configure DMA Stream destination address */
+        hdma->Instance->PAR = DstAddress;
+
+        /* Configure DMA Stream source address */
+        hdma->Instance->M0AR = SrcAddress;
+    } else {
+        /* Memory to Peripheral */
+        /* Configure DMA Stream source address */
+        hdma->Instance->PAR = SrcAddress;
+
+        /* Configure DMA Stream destination address */
+        hdma->Instance->M0AR = DstAddress;
+    }
+
+    /* Enable all interrupts EXCEPT HALF TRANSFER COMPLETE */
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+
+     /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+
+    return HAL_OK;
 }
-/** The asynchronous TX and RX handler.
- *
- * @param obj The serial object
- * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
- */
-void h_serial_rxdma_irq_handler_asynch(serial_t *obj)
+/**
+  * @brief DMA UART receive process half complete callback
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void h_UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-//    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    HAL_DMA_IRQHandler(UartHandle.hdmarx);
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+  * @brief  DMA UART receive process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void h_UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  /* DMA Normal mode*/
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  {
+    huart->RxXferCount = 0;
+
+    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+       in the UART CR3 register */
+    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+
+    /* Check if a transmit process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_READY;
+    }
+  }
+  HAL_UART_RxCpltCallback(huart);
+}
+/**
+  * @brief  DMA UART communication error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void h_UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  huart->RxXferCount = 0;
+  huart->TxXferCount = 0;
+  huart->State= HAL_UART_STATE_READY;
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+  HAL_UART_ErrorCallback(huart);
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode.
+  * @note   This function differs from HAL's function as it does not enable HalfTranferComplete
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef MBED_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+    uint32_t *tmp;
+    uint32_t tmp1 = 0;
+
+    tmp1 = huart->State;
+    if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) {
+        if((pData == NULL ) || (Size == 0)) {
+          return HAL_ERROR;
+        }
+
+        /* Process Locked */
+        __HAL_LOCK(huart);
+
+        huart->pRxBuffPtr = pData;
+        huart->RxXferSize = Size;
+
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+        /* Check if a transmit process is ongoing or not */
+        if(huart->State == HAL_UART_STATE_BUSY_TX) {
+            huart->State = HAL_UART_STATE_BUSY_TX_RX;
+        } else {
+            huart->State = HAL_UART_STATE_BUSY_RX;
+        }
+
+        /* Set the UART DMA transfer complete callback */
+        huart->hdmarx->XferCpltCallback = h_UART_DMAReceiveCplt;
+
+        /* Set the UART DMA Half transfer complete callback */
+        huart->hdmarx->XferHalfCpltCallback = h_UART_DMARxHalfCplt;
+
+        /* Set the DMA error callback */
+        huart->hdmarx->XferErrorCallback = h_UART_DMAError;
+
+        /* Enable the DMA Stream */
+        tmp = (uint32_t*)&pData;
+        MBED_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+
+        /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+        in the UART CR3 register */
+        huart->Instance->CR3 |= USART_CR3_DMAR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
+
+        return HAL_OK;
+    } else {
+        return HAL_BUSY;
+    }
 }
 
 /**
@@ -811,48 +1161,36 @@ static IRQn_Type h_serial_tx_get_irqdma_index(serial_t *obj)
 {
     IRQn_Type irq_n = (IRQn_Type)0;
 
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
-
-    switch (SERIAL_OBJ(uart)) {
+    switch (SERIAL_OBJ(index)) {
 #if defined(USART1_BASE)
-        case UART_1:
+        case 0:
             irq_n = DMA2_Stream7_IRQn;
             break;
 #endif
 #if defined(USART2_BASE)
-        case UART_2:
+        case 1:
             irq_n = DMA1_Stream6_IRQn;
             break;
 #endif
 #if defined(USART3_BASE)
-        case UART_3:
+        case 2:
             irq_n = DMA1_Stream3_IRQn;
             break;
 #endif
 #if defined(UART4_BASE)
-        case UART_4:
+        case 3:
             irq_n = DMA1_Stream4_IRQn;
             break;
 #endif
 #if defined(UART5_BASE)
-        case UART_5:
+        case 4:
             irq_n = DMA1_Stream7_IRQn;
             break;
 #endif
 #if defined(USART6_BASE)
-        case UART_6:
+        case 5:
             irq_n = DMA2_Stream6_IRQn;
             break;
-#endif
-#if defined(UART7_BASE)
-        case UART_7:
-            irq_n = DMA1_Stream1_IRQn;
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            irq_n = DMA1_Stream0_IRQn;
-            break;
 #endif
         default:
             irq_n = (IRQn_Type)0;
@@ -870,47 +1208,35 @@ static IRQn_Type h_serial_rx_get_irqdma_index(serial_t *obj)
 {
     IRQn_Type irq_n = (IRQn_Type)0;
 
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
-
-    switch (SERIAL_OBJ(uart)) {
+    switch (SERIAL_OBJ(index)) {
 #if defined(USART1_BASE)
-        case UART_1:
+        case 0:
             irq_n = DMA2_Stream5_IRQn;
             break;
 #endif
 #if defined(USART2_BASE)
-        case UART_2:
+        case 1:
             irq_n = DMA1_Stream5_IRQn;
             break;
 #endif
 #if defined(USART3_BASE)
-        case UART_3:
+        case 2:
             irq_n = DMA1_Stream1_IRQn;
             break;
 #endif
 #if defined(UART4_BASE)
-        case UART_4:
+        case 3:
             irq_n = DMA1_Stream2_IRQn;
             break;
 #endif
 #if defined(UART5_BASE)
-        case UART_5:
+        case 4:
             irq_n = DMA1_Stream0_IRQn;
             break;
 #endif
 #if defined(USART6_BASE)
-        case UART_6:
-            irq_n = DMA2_Stream2_IRQn;
-            break;
-#endif
-#if defined(UART7_BASE)
-        case UART_7:
-            irq_n = DMA1_Stream3_IRQn;
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            irq_n = DMA1_Stream6_IRQn;
+        case 5:
+            irq_n = DMA2_Stream1_IRQn;
             break;
 #endif
         default:
@@ -936,9 +1262,15 @@ static IRQn_Type h_serial_rx_get_irqdma_index(serial_t *obj)
  * @param hint      A suggestion for how to use DMA with this transfer
  * @return Returns number of data transfered, or 0 otherwise
  */
+#ifdef YOTTA_CFG_MBED_OS
+int serial_tx_asynch(serial_t *obj, void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+#else
 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+#endif
 {
-  
+    // DMA usage is currently ignored
+    (void) hint;
+    
     // Check buffer is ok
     MBED_ASSERT(tx != (void*)0);
     MBED_ASSERT(tx_width == 8); // support only 8b width
@@ -952,13 +1284,13 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
     h_serial_tx_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
     h_serial_tx_enable_event(obj, event, 1); // Set only the wanted events
   
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     // Enable interrupt
     IRQn_Type irqn = h_serial_get_irq_index(obj);
     NVIC_ClearPendingIRQ(irqn);
     NVIC_DisableIRQ(irqn);
     NVIC_SetPriority(irqn, 1);
     NVIC_SetVector(irqn, (uint32_t)handler);
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
     NVIC_EnableIRQ(irqn);
 
 #if DEVICE_SERIAL_ASYNCH_DMA
@@ -967,25 +1299,26 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
     NVIC_ClearPendingIRQ(irqn);
     NVIC_DisableIRQ(irqn);
     NVIC_SetPriority(irqn, 1);
-//    NVIC_SetVector(irqn, (uint32_t)&h_serial_txdma_irq_handler_asynch);
     NVIC_SetVector(irqn, (uint32_t)handler);
     NVIC_EnableIRQ(irqn);
 
     // the following function will enable program and enable the DMA transfer
-    if (HAL_UART_Transmit_DMA(&UartHandle, (uint8_t*)tx, tx_length) != HAL_OK)
+    if (HAL_UART_Transmit_DMA(handle, (uint8_t*)tx, tx_length) != HAL_OK)
     {
       /* Transfer error in transmission process */
       return 0;
     }
 #else
     // the following function will enable UART_IT_TXE and error interrupts
-    if (HAL_UART_Transmit_IT(&UartHandle, (uint8_t*)tx, tx_length) != HAL_OK)
+    if (HAL_UART_Transmit_IT(handle, (uint8_t*)tx, tx_length) != HAL_OK)
     {
       /* Transfer error in transmission process */
       return 0;
     }
 #endif
-  
+
+    DEBUG_PRINTF("UART%u: Tx: 0=(%u, %u) %x\n", obj->serial.module+1, tx_length, tx_width, HAL_UART_GetState(handle));
+
     return tx_length;
 }
 
@@ -1004,6 +1337,9 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
  */
 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
 {
+    // DMA usage is currently ignored
+    (void) hint;
+
     /* Sanity check arguments */
     MBED_ASSERT(obj);
     MBED_ASSERT(rx != (void*)0);
@@ -1024,9 +1360,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
     NVIC_SetVector(irqn, (uint32_t)handler);
     NVIC_EnableIRQ(irqn);
 
-    UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart);
+
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
     // flush current data + error flags
-    __HAL_UART_CLEAR_PEFLAG(&UartHandle);
+    __HAL_UART_CLEAR_PEFLAG(handle);
 #if DEVICE_SERIAL_ASYNCH_DMA
     // Enable DMA interrupt
     irqn = h_serial_rx_get_irqdma_index(obj);
@@ -1034,17 +1371,17 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
     NVIC_DisableIRQ(irqn);
     NVIC_SetPriority(irqn, 1);
     NVIC_SetVector(irqn, (uint32_t)handler);
-
     NVIC_EnableIRQ(irqn);
     // following HAL function will program and enable the DMA transfer
-    HAL_UART_Receive_DMA(&UartHandle, (uint8_t*)rx, rx_length);
+    MBED_UART_Receive_DMA(handle, (uint8_t*)rx, rx_length);
 #else
     // following HAL function will enable the RXNE interrupt + error interrupts    
-    HAL_UART_Receive_IT(&UartHandle, (uint8_t*)rx, rx_length);
+    HAL_UART_Receive_IT(handle, (uint8_t*)rx, rx_length);
 #endif
     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_ERR);
+    __HAL_UART_ENABLE_IT(handle, UART_IT_ERR);
 
+    DEBUG_PRINTF("UART%u: Rx: 0=(%u, %u, %u) %x\n", obj->serial.module+1, rx_length, rx_width, char_match, HAL_UART_GetState(handle));
     return;
 }
 
@@ -1056,8 +1393,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
 uint8_t serial_tx_active(serial_t *obj)
 {
     MBED_ASSERT(obj);
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    return ((HAL_UART_GetState(&UartHandle) & UART_STATE_TX_ACTIVE) ? 1 : 0);
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    return ((HAL_UART_GetState(handle) & UART_STATE_TX_ACTIVE) ? 1 : 0);
 }
 
 /** Attempts to determine if the serial peripheral is already in use for RX
@@ -1068,8 +1405,8 @@ uint8_t serial_tx_active(serial_t *obj)
 uint8_t serial_rx_active(serial_t *obj)
 {
     MBED_ASSERT(obj);
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    return ((HAL_UART_GetState(&UartHandle) & UART_STATE_RX_ACTIVE) ? 1 : 0);
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    return ((HAL_UART_GetState(handle) & UART_STATE_RX_ACTIVE) ? 1 : 0);
 
 }
 
@@ -1085,62 +1422,62 @@ int serial_irq_handler_asynch(serial_t *obj)
     uint8_t i = 0;
 
   // Irq handler is common to Tx and Rx
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
 #if DEVICE_SERIAL_ASYNCH_DMA
-    if ((UartHandle.Instance->CR3 & USART_CR3_DMAT) !=0) {
+    if ((handle->Instance->CR3 & USART_CR3_DMAT) !=0) {
         // call dma tx interrupt
-        HAL_DMA_IRQHandler(UartHandle.hdmatx);
+        HAL_DMA_IRQHandler(handle->hdmatx);
     }
-    if ((UartHandle.Instance->CR3 & USART_CR3_DMAR) !=0) {
+    if ((handle->Instance->CR3 & USART_CR3_DMAR) !=0) {
         // call dma rx interrupt
-        HAL_DMA_IRQHandler(UartHandle.hdmarx);
+        HAL_DMA_IRQHandler(handle->hdmarx);
     }
 #endif
-    HAL_UART_IRQHandler(&UartHandle);
+    HAL_UART_IRQHandler(handle);
   // TX PART:
-    if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
-        __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC);
+    if (__HAL_UART_GET_FLAG(handle, UART_FLAG_TC) != RESET) {
+        __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TC);
         // return event SERIAL_EVENT_TX_COMPLETE if requested
         if ((SERIAL_OBJ(events) & SERIAL_EVENT_TX_COMPLETE ) != 0){
             return_event |= SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
         }
     }
     // handle error events:
-    if (__HAL_UART_GET_FLAG(&UartHandle, HAL_UART_ERROR_PE)) {
-        __HAL_UART_CLEAR_FLAG(&UartHandle, HAL_UART_ERROR_PE);
+    if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_PE)) {
+        __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_PE);
         return_event |= SERIAL_EVENT_RX_PARITY_ERROR & obj->serial.events;
     }
-    if (__HAL_UART_GET_FLAG(&UartHandle, HAL_UART_ERROR_NE)||(UartHandle.ErrorCode & HAL_UART_ERROR_NE)!=0) {
-      __HAL_UART_CLEAR_FLAG(&UartHandle, HAL_UART_ERROR_NE);
+    if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_NE)||(handle->ErrorCode & HAL_UART_ERROR_NE)!=0) {
+      __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_NE);
       // not supported by mbed
     }
-    if (__HAL_UART_GET_FLAG(&UartHandle, HAL_UART_ERROR_FE)||(UartHandle.ErrorCode & HAL_UART_ERROR_FE)!=0) {
-      __HAL_UART_CLEAR_FLAG(&UartHandle, HAL_UART_ERROR_FE);
-        return_event |= SERIAL_EVENT_RX_FRAMING_ERROR & obj->serial.events;
+    if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_FE)||(handle->ErrorCode & HAL_UART_ERROR_FE)!=0) {
+      __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_FE);
+        return_event |= SERIAL_EVENT_RX_FRAMING_ERROR & SERIAL_OBJ(events);
     }
-    if (__HAL_UART_GET_FLAG(&UartHandle, HAL_UART_ERROR_ORE)||(UartHandle.ErrorCode & HAL_UART_ERROR_ORE)!=0) {
-      __HAL_UART_CLEAR_FLAG(&UartHandle, HAL_UART_ERROR_ORE);
-        return_event |= SERIAL_EVENT_RX_OVERRUN_ERROR & obj->serial.events;
+    if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_ORE)||(handle->ErrorCode & HAL_UART_ERROR_ORE)!=0) {
+      __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_ORE);
+        return_event |= SERIAL_EVENT_RX_OVERRUN_ERROR & SERIAL_OBJ(events);
     }
 
     //RX PART
     // increment rx_buff.pos
-    if (UartHandle.RxXferSize !=0) { 
-        obj->rx_buff.pos = UartHandle.RxXferSize - UartHandle.RxXferCount;
+    if (handle->RxXferSize !=0) {
+        obj->rx_buff.pos = handle->RxXferSize - handle->RxXferCount;
     }
-    if ((UartHandle.RxXferCount==0)&&(obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
-        return_event |= SERIAL_EVENT_RX_COMPLETE & obj->serial.events;
+    if ((handle->RxXferCount==0)&&(obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
+        return_event |= SERIAL_EVENT_RX_COMPLETE & SERIAL_OBJ(events);
     }
     // Chek if Char_match is present
     if (SERIAL_OBJ(events) & SERIAL_EVENT_RX_CHARACTER_MATCH) {
       if (buf != NULL){
-        while((buf[i] != obj->char_match)&&(i<UartHandle.RxXferSize)){//for (i=0;i<UartHandle.RxXferSize;i++){
+        while((buf[i] != obj->char_match)&&(i<handle->RxXferSize)){//for (i=0;i<UartHandle.RxXferSize;i++){
           i++;//if (buf[i] == obj->char_match{
           //}
         }
-        if (i<UartHandle.RxXferSize){
+        if (i<handle->RxXferSize){
             obj->rx_buff.pos = i;
-            return_event |= SERIAL_EVENT_RX_CHARACTER_MATCH & obj->serial.events;
+            return_event |= SERIAL_EVENT_RX_CHARACTER_MATCH & SERIAL_OBJ(events);
         }
       }
     }
@@ -1154,13 +1491,18 @@ int serial_irq_handler_asynch(serial_t *obj)
  */
 void serial_tx_abort_asynch(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC|UART_IT_TXE);
-    UartHandle.Instance = 0;
-
-    obj->tx_buff.buffer = 0;
-    obj->tx_buff.length = 0;
-  
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    __HAL_UART_DISABLE_IT(handle, UART_IT_TC|UART_IT_TXE);
+    // clear flags
+      __HAL_UART_CLEAR_PEFLAG(handle);
+      // reset states
+      handle->TxXferCount = 0;
+      // update handle state
+      if (handle->State == HAL_UART_STATE_BUSY_TX_RX) {
+          handle->State = HAL_UART_STATE_BUSY_RX;
+      } else {
+          handle->State = HAL_UART_STATE_READY;
+      }
 }
 
 /** Abort the ongoing RX transaction It disables the enabled interrupt for RX and
@@ -1170,13 +1512,18 @@ void serial_tx_abort_asynch(serial_t *obj)
  */
 void serial_rx_abort_asynch(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
-    __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
-    UartHandle.Instance = 0;
-  
-    obj->rx_buff.buffer = 0;
-    obj->rx_buff.length = 0;
-
+    UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)];
+    __HAL_UART_DISABLE_IT(handle, UART_IT_RXNE);
+    // clear flags
+    __HAL_UART_CLEAR_PEFLAG(handle);
+    // reset states
+    handle->RxXferCount = 0;
+    // update handle state
+    if (handle->State == HAL_UART_STATE_BUSY_TX_RX) {
+        handle->State = HAL_UART_STATE_BUSY_TX;
+    } else {
+        handle->State = HAL_UART_STATE_READY;
+    }
 }
 
 #endif
@@ -1196,10 +1543,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
     UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
 
     // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    SERIAL_OBJ(uart) = (UARTName)pinmap_merge(uart_cts, uart_rts);
+    UARTName instance = (UARTName)pinmap_merge(uart_cts, uart_rts);
 
-    MBED_ASSERT(SERIAL_OBJ(uart) != (UARTName)NC);
-    UartHandle.Instance = (USART_TypeDef *)(SERIAL_OBJ(uart));
+    MBED_ASSERT(instance != (UARTName)NC);
 
     if(type == FlowControlNone) {
         // Disable hardware flow control
@@ -1233,7 +1579,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
         // Enable the pin for RTS function
         pinmap_pinout(rxflow, PinMap_UART_RTS);
     }
-    init_uart(obj);
+    init_uart(obj, instance);
 }
 #endif
 #endif

From ab3cda47b9915c6f0854ebd50e1e694500cb53c3 Mon Sep 17 00:00:00 2001
From: dbestm <dbe.stm13@gmail.com>
Date: Mon, 22 Feb 2016 14:28:20 +0100
Subject: [PATCH 17/78] fix formatting

---
 .../mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c   | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
index cde22774e1..1176bdf9ae 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c
@@ -147,8 +147,11 @@ int rtc_isenabled(void)
 #if DEVICE_RTC_LSI
   return rtc_inited;
 #else
-  if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return 1;
-  else return 0;
+  if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) {
+    return 1;
+  } else {
+    return 0;
+  }
 #endif
 }
 

From 3df28ea0b82044ece799543762230c8593a487dc Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 15:24:42 +0100
Subject: [PATCH 18/78] [B96B_F446VE] remove unused IRQ_RX1 interrupt

---
 libraries/mbed/hal/can_api.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/libraries/mbed/hal/can_api.h b/libraries/mbed/hal/can_api.h
index bdf259a35d..120b2873a8 100644
--- a/libraries/mbed/hal/can_api.h
+++ b/libraries/mbed/hal/can_api.h
@@ -37,8 +37,7 @@ typedef enum {
     IRQ_PASSIVE,
     IRQ_ARB,
     IRQ_BUS,
-    IRQ_READY,
-    IRQ_RX1
+    IRQ_READY
 } CanIrqType;
 
 

From 4a4cb7fb07a512fb1ab937ee177e14e5725c1d65 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 15:27:51 +0100
Subject: [PATCH 19/78] [B96B_F446VE] Add more details about the timing_pts
 table

---
 .../mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
index e931c290bf..d5cb7603d5 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
@@ -105,8 +105,10 @@ void can_free(can_t *obj)
     }
 }
 
-// This table has the sampling points as close to 75% as possible. The first
-// value is TSEG1, the second TSEG2.
+// The following table is used to program bit_timing. It is an adjustment of the sample
+// point by synchronizing on the start-bit edge and resynchronizing on the following edges.
+// This table has the sampling points as close to 75% as possible (most commonly used).
+// The first value is TSEG1, the second TSEG2.
 static const int timing_pts[23][2] = {
     {0x0, 0x0},      // 2,  50%
     {0x1, 0x0},      // 3,  67%

From 8e8af8fb62b397d83dc19ce58adb6fa35959f23b Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 15:28:47 +0100
Subject: [PATCH 20/78] [B96B_F446VE] Remove unused IRQ_RX1 interrupt (init /
 irq_set / ...)

---
 .../hal/TARGET_STM/TARGET_STM32F4/can_api.c   | 28 -------------------
 1 file changed, 28 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
index d5cb7603d5..86e2864c76 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/can_api.c
@@ -396,14 +396,6 @@ static void can_irq(CANName name, int id)
          irq_handler(can_irq_ids[id], IRQ_RX);
     }
   
-    tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO1);
-    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP1);
-  
-    if((tmp1 != 0) && tmp2) {
-         irq_handler(can_irq_ids[id], IRQ_RX1);
-    }
-      
-  
     tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
     tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
     tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR); 
@@ -430,11 +422,6 @@ void CAN1_RX0_IRQHandler(void)
     can_irq(CAN_1, 0);
 }
 
-void CAN1_RX1_IRQHandler(void) 
-{
-    can_irq(CAN_1, 0);
-}
-
 void CAN1_TX_IRQHandler(void) 
 {
     can_irq(CAN_1, 0);
@@ -450,11 +437,6 @@ void CAN2_RX0_IRQHandler(void)
     can_irq(CAN_2, 1);
 }
 
-void CAN2_RX1_IRQHandler(void)
-{
-    can_irq(CAN_2, 1);
-}
-
 void CAN2_TX_IRQHandler(void)
 {
     can_irq(CAN_2, 1);
@@ -480,11 +462,6 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 irq_n = CAN1_RX0_IRQn;
                 vector = (uint32_t)&CAN1_RX0_IRQHandler;
                 break;
-            case IRQ_RX1:      
-                ier = CAN_IT_FMP1;
-                irq_n = CAN1_RX1_IRQn;
-                vector = (uint32_t)&CAN1_RX1_IRQHandler;
-                break;                
             case IRQ_TX:      
                 ier = CAN_IT_TME;
                 irq_n = CAN1_TX_IRQn;
@@ -514,11 +491,6 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                   irq_n = CAN2_RX0_IRQn;
                   vector = (uint32_t)&CAN2_RX0_IRQHandler;
                   break;
-              case IRQ_RX1:
-                  ier = CAN_IT_FMP1;
-                  irq_n = CAN2_RX1_IRQn;
-                  vector = (uint32_t)&CAN2_RX1_IRQHandler;
-                  break;
               case IRQ_TX:      
                   ier = CAN_IT_TME;
                   irq_n = CAN2_TX_IRQn;

From 20c34f47ad46007d9a0b7567bf6b61286ff816ae Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 15:29:05 +0100
Subject: [PATCH 21/78] [B96B_F446VE] remove spaces (typo)

---
 .../hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h
index b42a45998f..2cede5bd9b 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h
@@ -120,7 +120,7 @@ typedef enum {
     PC_15 = 0x2F,
 
     PD_0  = 0x30,
-    PD_1  = 0x31,    
+    PD_1  = 0x31,
     PD_2  = 0x32,
     PD_3  = 0x33,
     PD_4  = 0x34,

From fc84dd9234ecd29b26f74835674da272c7ba5a9a Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 17:20:27 +0100
Subject: [PATCH 22/78] [STM32F7 family] fix issue with RTC init

the logical test for RTC_ISR_INITS was wronlgy reported from other
STMfamilies.
MBED_16 test works with this modification.
---
 .../hal/TARGET_STM/TARGET_STM32F7/rtc_api.c   | 85 +++++++++----------
 1 file changed, 42 insertions(+), 43 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
index d25acb860f..276c13a176 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
@@ -40,59 +40,58 @@ void rtc_init(void)
     RCC_OscInitTypeDef RCC_OscInitStruct;
     uint32_t rtc_freq = 0;
 
-        RtcHandle.Instance = RTC;
+    RtcHandle.Instance = RTC;
 
-        // Enable Power clock
-        __PWR_CLK_ENABLE();
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
 
-        // Enable access to Backup domain
-        HAL_PWR_EnableBkUpAccess();
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
 
-        // Reset Backup domain
-        __HAL_RCC_BACKUPRESET_FORCE();
-        __HAL_RCC_BACKUPRESET_RELEASE();
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
 
-        // Enable LSE Oscillator
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    // Enable LSE Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        // Connect LSE to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+        rtc_freq = LSE_VALUE;
+    } else {
+        // Enable LSI clock
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
         RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-            // Connect LSE to RTC
-            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-            rtc_freq = LSE_VALUE;
-        } else {
-            // Enable LSI clock
-            RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-            RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-            RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-            RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-            if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-                error("RTC error: LSI clock initialization failed.");
-            }
-            // Connect LSI to RTC
-            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-            // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
-            rtc_freq = LSI_VALUE;
+        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+            error("RTC error: LSI clock initialization failed.");
         }
+        // Connect LSI to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+        // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+        rtc_freq = LSI_VALUE;
+    }
 
-    if((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) {     // RTC initialization and status register (RTC_ISR), cold start (with no backup domain power) RTC reset value
+    // Check if RTC is already initialized
+    if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return;
 
-        // Enable RTC
-        __HAL_RCC_RTC_ENABLE();
+    // Enable RTC
+    __HAL_RCC_RTC_ENABLE();
 
-        RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-        RtcHandle.Init.AsynchPrediv   = 127;
-        RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-        RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-        RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-        RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-        if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-            error("RTC error: RTC initialization failed.");
-        }
+    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    RtcHandle.Init.AsynchPrediv   = 127;
+    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
+    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
 
+    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+        error("RTC error: RTC initialization failed.");
     }
 }
 

From faf99119fc97238a37af31c92e59b4fa64464e05 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Sat, 20 Feb 2016 21:56:27 +0000
Subject: [PATCH 23/78] Export - IAR progen addition

The IAR exporter is replaced by progen.
---
 workspace_tools/export/iar.py | 107 +++++-----------------------------
 1 file changed, 16 insertions(+), 91 deletions(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 50d64f5a6e..52334ec25b 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -1,6 +1,6 @@
 """
 mbed SDK
-Copyright (c) 2011-2013 ARM Limited
+Copyright (c) 2011-2015 ARM Limited
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
@@ -17,106 +17,31 @@ limitations under the License.
 from workspace_tools.export.exporters import Exporter
 import re
 import os
+
 class IAREmbeddedWorkbench(Exporter):
     """
     Exporter class for IAR Systems.
     """
     NAME = 'IAR'
     TOOLCHAIN = 'IAR'
-
-    TARGETS = [
-        'LPC1768',
-        'LPC1347',
-        'LPC11U24',
-        'LPC11U35_401',
-        'LPC11U35_501',
-        #Removed LPCCAPPUCCINO linker file and startup file missing
-        #'LPCCAPPUCCINO',
-        'LPC1114',
-        'LPC1549',
-        'LPC812',
-        'LPC4088',
-        'LPC4088_DM',
-        'LPC824',
-        'UBLOX_C027',
-        'ARCH_PRO',
-        'K20D50M',
-        'KL05Z',
-        'KL25Z',
-        'KL46Z',
-        'K22F',
-        'K64F',
-        'NUCLEO_F030R8',
-        'NUCLEO_F031K6',
-        'NUCLEO_F042K6',
-        'NUCLEO_F070RB',
-        'NUCLEO_F072RB',
-        'NUCLEO_F091RC',
-        'NUCLEO_F103RB',
-        'NUCLEO_F302R8',
-        'NUCLEO_F303K8',
-        'NUCLEO_F303RE',
-        'NUCLEO_F334R8',
-        'NUCLEO_F401RE',
-        'NUCLEO_F410RB',
-        'NUCLEO_F411RE',
-        'NUCLEO_F446RE',
-        'NUCLEO_L053R8',
-        'NUCLEO_L073RZ',
-        'NUCLEO_L152RE',
-        'NUCLEO_L476RG',
-        'DISCO_F429ZI',
-        'DISCO_L053C8',
-        'DISCO_F334C8',
-        'DISCO_F469NI',
-        'DISCO_F746NG',
-        'DISCO_L476VG',
-        'B96B_F446VE',
-        #'STM32F407', Fails to build same for GCC
-        'MAXWSNENV',
-        'MAX32600MBED',
-        'MTS_MDOT_F405RG',
-        'MTS_MDOT_F411RE',
-        'MTS_DRAGONFLY_F411RE',
-        'NRF51822',
-        'NRF51_DK',
-        'NRF51_DONGLE',
-        'DELTA_DFCM_NNN40',
-        'SEEED_TINY_BLE',
-        'HRM1017',
-        'ARCH_BLE',
-        'MOTE_L152RC',
-        'EFM32PG_STK3401',
-        'RZ_A1H',
-    ]
+    PROGEN_ACTIVE = True
 
     def generate(self):
-        """
-        Generates the project files
-        """
-        sources = []
-        sources += self.resources.c_sources
-        sources += self.resources.cpp_sources
-        sources += self.resources.s_sources
-
-        iar_files = IarFolder("", "", [])
-        for source in sources:
-            iar_files.insert_file(source)
-
-        ctx = {
-            'name': self.program_name,
-            'include_paths': self.resources.inc_dirs,
-            'linker_script': self.resources.linker_script,
-            'object_files': self.resources.objects,
-            'libraries': self.resources.libraries,
-            'symbols': self.get_symbols(),
-            'source_files': iar_files.__str__(),
-            'binary_files': self.resources.bin_files,
+        """ Generates the project files """
+        project_data = self.progen_get_project_data()
+        tool_specific = {
+            'iar': {
+                'misc': {
+                    'cxx_flags': ['--no_rtti', '--no_exceptions'],
+                    'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
+                }
+            }
         }
-        self.gen_file('iar_%s.ewp.tmpl' % self.target.lower(), ctx, '%s.ewp' % self.program_name)
-        self.gen_file('iar.eww.tmpl', ctx, '%s.eww' % self.program_name)
-        self.gen_file('iar_%s.ewd.tmpl' % self.target.lower(), ctx, '%s.ewd' % self.program_name)
+        project_data['tool_specific'] = {}
+        project_data['tool_specific'].update(tool_specific)
+        self.progen_gen_file('iar_arm', project_data)
 
+# Currently not used, we should reuse folder_name to create virtual folders
 class IarFolder():
     """
     This is a recursive folder object.

From b5a3fe53162b6d63453692d2c3e5b57ce494aa6a Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Mon, 22 Feb 2016 20:43:35 +0000
Subject: [PATCH 24/78] IAR - add TARGETS for backward compatibility

---
 workspace_tools/export/iar.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 52334ec25b..7aadf2b910 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -15,8 +15,11 @@ See the License for the specific language governing permissions and
 limitations under the License.
 """
 from workspace_tools.export.exporters import Exporter
+from workspace_tools.targets import TARGET_MAP, TARGET_NAMES
 import re
 import os
+from project_generator_definitions.definitions import ProGenDef
+
 
 class IAREmbeddedWorkbench(Exporter):
     """
@@ -26,6 +29,17 @@ class IAREmbeddedWorkbench(Exporter):
     TOOLCHAIN = 'IAR'
     PROGEN_ACTIVE = True
 
+    # backward compatibility with our scripts
+    TARGETS = []
+    for target in TARGET_NAMES:
+        try:
+            if (ProGenDef('iar').is_supported(TARGET_MAP[target]) or
+                ProGenDef('iar').is_supported(TARGET_MAP[target].progen_target)):
+                TARGETS.append(target)
+        except AttributeError:
+            # not supported yet
+            continue
+
     def generate(self):
         """ Generates the project files """
         project_data = self.progen_get_project_data()
@@ -34,6 +48,7 @@ class IAREmbeddedWorkbench(Exporter):
                 'misc': {
                     'cxx_flags': ['--no_rtti', '--no_exceptions'],
                     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
+                    'ld_flags': ['--skip_dynamic_initialization'],
                 }
             }
         }

From 3f2c7bf5f85fc11391d02da0eb1b49e3fc97b5d7 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Mon, 22 Feb 2016 21:04:53 +0000
Subject: [PATCH 25/78] Exporters iar - add comments to IAR progen
 implementation

---
 workspace_tools/export/iar.py | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 7aadf2b910..9128acbbc7 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -14,19 +14,23 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 """
-from workspace_tools.export.exporters import Exporter
-from workspace_tools.targets import TARGET_MAP, TARGET_NAMES
 import re
 import os
 from project_generator_definitions.definitions import ProGenDef
 
+from workspace_tools.export.exporters import Exporter
+from workspace_tools.targets import TARGET_MAP, TARGET_NAMES
 
+# If you wish to add a new target, add it to project_generator_definitions, and then
+# define progen_target name in the target class (`` self.progen_target = 'my_target_name' ``)
 class IAREmbeddedWorkbench(Exporter):
     """
-    Exporter class for IAR Systems.
+    Exporter class for IAR Systems. This class uses project generator.
     """
+    # These 2 are currently for exporters backward compatiblity
     NAME = 'IAR'
     TOOLCHAIN = 'IAR'
+    # PROGEN_ACTIVE contains information for exporter scripts that this is using progen
     PROGEN_ACTIVE = True
 
     # backward compatibility with our scripts
@@ -37,12 +41,14 @@ class IAREmbeddedWorkbench(Exporter):
                 ProGenDef('iar').is_supported(TARGET_MAP[target].progen_target)):
                 TARGETS.append(target)
         except AttributeError:
-            # not supported yet
+            # target is not supported yet
             continue
 
     def generate(self):
         """ Generates the project files """
         project_data = self.progen_get_project_data()
+        # Expand tool specific settings by IAR specific settings which are required
+        # by the mbed projects
         tool_specific = {
             'iar': {
                 'misc': {

From 9bc9668287f52942b05026cfa6f616321ca2c98d Mon Sep 17 00:00:00 2001
From: Kevin Gillespie <kevin.gillespie@maximintegrated.com>
Date: Mon, 22 Feb 2016 15:45:54 -0600
Subject: [PATCH 26/78] Fixing the return for i2c_byte_write.

---
 .../hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c        | 11 +++++++++++
 .../hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c        | 11 +++++++++++
 2 files changed, 22 insertions(+)

diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c
index cb986662db..a6aafe26e7 100644
--- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c
@@ -227,6 +227,17 @@ int i2c_byte_write(i2c_t *obj, int data)
 
     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 
+    // Wait for the FIFO to be empty
+    while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY)) {}
+
+    if(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
+        return 1;
+    }
+
+    if(obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
+        return 2;
+    }
+    
     return 0;
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c
index cb986662db..192075c494 100644
--- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c
@@ -227,6 +227,17 @@ int i2c_byte_write(i2c_t *obj, int data)
 
     obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
 
+    // Wait for the FIFO to be empty
+    while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY)) {}
+
+    if(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
+        return 1;
+    }
+
+    if(obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
+        return 2;
+    }
+
     return 0;
 }
 

From efbecd6cdd1c3d300397f30cdc1723c966880ecc Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Mon, 22 Feb 2016 22:16:41 +0000
Subject: [PATCH 27/78] Exporters - progen data - add inc_dirs

---
 workspace_tools/export/exporters.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/workspace_tools/export/exporters.py b/workspace_tools/export/exporters.py
index 741bafed41..e64382aa6e 100644
--- a/workspace_tools/export/exporters.py
+++ b/workspace_tools/export/exporters.py
@@ -62,7 +62,7 @@ class Exporter(object):
                         self.resources.objects + self.resources.libraries,
                 },
                 'includes':  { 
-                    'Include Files': self.resources.headers,
+                    'Include Files': self.resources.headers + self.resources.inc_dirs,
                 },
                 'target': [TARGET_MAP[self.target].progen_target],
                 'macros': self.get_symbols(),

From 36fe6a0b740f45370a2c6f6185c54e020b99f523 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Mon, 22 Feb 2016 22:55:58 +0000
Subject: [PATCH 28/78] Exporters IAR - add template mbed file

---
 workspace_tools/export/iar.py                |    3 +-
 workspace_tools/export/iar_template.ewp.tmpl | 1351 ++++++++++++++++++
 2 files changed, 1353 insertions(+), 1 deletion(-)
 create mode 100644 workspace_tools/export/iar_template.ewp.tmpl

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 9128acbbc7..e84f194e68 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -55,7 +55,8 @@ class IAREmbeddedWorkbench(Exporter):
                     'cxx_flags': ['--no_rtti', '--no_exceptions'],
                     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
                     'ld_flags': ['--skip_dynamic_initialization'],
-                }
+                },
+                'template': ['workspace_tools/export/iar_template.ewp.tmpl'],
             }
         }
         project_data['tool_specific'] = {}
diff --git a/workspace_tools/export/iar_template.ewp.tmpl b/workspace_tools/export/iar_template.ewp.tmpl
new file mode 100644
index 0000000000..5ee0917e64
--- /dev/null
+++ b/workspace_tools/export/iar_template.ewp.tmpl
@@ -0,0 +1,1351 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>MBED_12</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ExePath</name>
+          <state>$PROJ_DIR$\build\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>$PROJ_DIR$\build\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>$PROJ_DIR$\build\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>No specifier a, A.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.50.3.10745</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>LPC1768	NXP LPC1768</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>22</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>22</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>LPC1768	NXP LPC1768</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>22</version>
+          <state>38</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>__CORTEX_M3</state>
+          <state>ARM_MATH_CM3</state>
+          <state>TARGET_LIKE_CORTEX_M3</state>
+          <state>TARGET_CORTEX_M</state>
+          <state>TARGET_LIKE_MBED</state>
+          <state>TARGET_LPC176X</state>
+          <state>TARGET_NXP</state>
+          <state>TARGET_LPC1768</state>
+          <state>MBED_BUILD_TIMESTAMP=1456180263.22</state>
+          <state>TARGET_M3</state>
+          <state>TOOLCHAIN_IAR</state>
+          <state>TARGET_MBED_LPC1768</state>
+          <state>__MBED__=1</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+          <state>--no_rtti</state>
+          <state>--no_exceptions</state>
+          <state>--diag_suppress=Pa050,Pa084,Pa093,Pa082</state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
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+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm4_simd.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm7.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmFunc.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmInstr.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmSimd.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_sc000.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_sc300.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\CThunk.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\device.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\DigitalIn.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\DigitalInOut.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\DigitalOut.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\DirHandle.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\dma_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\env</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Ethernet.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\ethernet_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FileBase.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FileHandle.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FileLike.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FilePath.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FileSystemLike.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\FunctionPointer.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\gpio_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\gpio_irq_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\gpio_object.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\I2C.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\i2c_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\I2CSlave.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\InterruptIn.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\InterruptManager.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\LocalFileSystem.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\LowPowerTicker.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\LowPowerTimeout.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\LowPowerTimer.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\lp_ticker_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\LPC17xx.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\mbed.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\mbed_assert.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\mbed_debug.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\mbed_error.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\mbed_interface.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\objects.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\PeripheralNames.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\pinmap.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\PinNames.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\platform.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\port_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\PortIn.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\PortInOut.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\PortNames.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\PortOut.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\PwmOut.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\pwmout_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\RawSerial.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\reserved_pins.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\rtc_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\rtc_time.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\semihost_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Serial.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\serial_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\SerialBase.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\sleep_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\SPI.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\spi_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\SPISlave.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Stream.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\system_LPC17xx.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\env\test_env.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Ticker.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\ticker_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Timeout.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Timer.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TimerEvent.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\toolchain.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\Transaction.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\us_ticker_api.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\wait_api.h</name>
+    </file>
+  </group>
+  <group>
+    <name>Source Files</name>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\board.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\cmain.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\cmsis_nvic.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\main.cpp</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\mbed.a</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\retarget.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\startup_LPC17xx.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\system_LPC17xx.o</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\env\test_env.cpp</name>
+    </file>
+  </group>
+</project>
+
+

From 31f74b8e45679693c17c98f1ca34147eff074f9d Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Tue, 23 Feb 2016 17:28:33 +0000
Subject: [PATCH 29/78] Exporters IAR - fix template path

---
 workspace_tools/export/iar.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index e84f194e68..9f79fd759b 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -56,9 +56,10 @@ class IAREmbeddedWorkbench(Exporter):
                     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
                     'ld_flags': ['--skip_dynamic_initialization'],
                 },
-                'template': ['workspace_tools/export/iar_template.ewp.tmpl'],
+                'template': [os.path.join(os.path.dirname(__file__),  'iar_template.ewp.tmpl')],
             }
         }
+        # print tool_specific['iar']['template']
         project_data['tool_specific'] = {}
         project_data['tool_specific'].update(tool_specific)
         self.progen_gen_file('iar_arm', project_data)

From 2727c942e08b403f067a61a54a2e04bbc5b78b57 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Tue, 23 Feb 2016 17:51:32 +0000
Subject: [PATCH 30/78] Exporters IAR - use template from older mbed templates

---
 workspace_tools/export/iar.py                |  12 +-
 workspace_tools/export/iar_template.ewp.tmpl | 588 ++++---------------
 2 files changed, 122 insertions(+), 478 deletions(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 9f79fd759b..a098e2851b 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -51,15 +51,15 @@ class IAREmbeddedWorkbench(Exporter):
         # by the mbed projects
         tool_specific = {
             'iar': {
-                'misc': {
-                    'cxx_flags': ['--no_rtti', '--no_exceptions'],
-                    'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
-                    'ld_flags': ['--skip_dynamic_initialization'],
-                },
+                # We currently don't use misc, template sets those for us
+                # 'misc': {
+                #     'cxx_flags': ['--no_rtti', '--no_exceptions'],
+                #     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
+                #     'ld_flags': ['--skip_dynamic_initialization'],
+                # },
                 'template': [os.path.join(os.path.dirname(__file__),  'iar_template.ewp.tmpl')],
             }
         }
-        # print tool_specific['iar']['template']
         project_data['tool_specific'] = {}
         project_data['tool_specific'].update(tool_specific)
         self.progen_gen_file('iar_arm', project_data)
diff --git a/workspace_tools/export/iar_template.ewp.tmpl b/workspace_tools/export/iar_template.ewp.tmpl
index 5ee0917e64..332c5814b2 100644
--- a/workspace_tools/export/iar_template.ewp.tmpl
+++ b/workspace_tools/export/iar_template.ewp.tmpl
@@ -3,7 +3,7 @@
 <project>
   <fileVersion>2</fileVersion>
   <configuration>
-    <name>MBED_12</name>
+    <name>Debug</name>
     <toolchain>
       <name>ARM</name>
     </toolchain>
@@ -12,24 +12,25 @@
       <name>General</name>
       <archiveVersion>3</archiveVersion>
       <data>
-        <version>24</version>
+        <version>22</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
         <option>
           <name>ExePath</name>
-          <state>$PROJ_DIR$\build\Exe</state>
+          <state>Debug\Exe</state>
         </option>
         <option>
           <name>ObjPath</name>
-          <state>$PROJ_DIR$\build\Obj</state>
+          <state>Debug\Obj</state>
         </option>
         <option>
           <name>ListPath</name>
-          <state>$PROJ_DIR$\build\List</state>
+          <state>Debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>35</state>
         </option>
         <option>
           <name>GEndianMode</name>
@@ -47,16 +48,21 @@
         <option>
           <name>Output variant</name>
           <version>2</version>
-          <state>3</state>
+          <state>1</state>
         </option>
         <option>
           <name>Output description</name>
-          <state>No specifier a, A.</state>
+          <state>Full formatting.</state>
         </option>
         <option>
           <name>GOutputBinary</name>
           <state>0</state>
         </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
         <option>
           <name>OGCoreOrChip</name>
           <state>1</state>
@@ -77,11 +83,11 @@
         </option>
         <option>
           <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
+          <state>7.10.1.6733</state>
         </option>
         <option>
           <name>OGLastSavedByProductVersion</name>
-          <state>7.50.3.10745</state>
+          <state>7.10.1.6733</state>
         </option>
         <option>
           <name>GeneralEnableMisra</name>
@@ -93,7 +99,7 @@
         </option>
         <option>
           <name>OGChipSelectEditMenu</name>
-          <state>LPC1768	NXP LPC1768</state>
+          <state>MKL25Z128xxx4	Freescale MKL25Z128xxx4</state>
         </option>
         <option>
           <name>GenLowLevelInterface</name>
@@ -129,10 +135,15 @@
           <name>RTConfigPath2</name>
           <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
         </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>35</state>
+        </option>
         <option>
           <name>GBECoreSlave</name>
-          <version>22</version>
-          <state>38</state>
+          <version>20</version>
+          <state>35</state>
         </option>
         <option>
           <name>OGUseCmsis</name>
@@ -143,61 +154,47 @@
           <state>0</state>
         </option>
         <option>
-          <name>CoreVariant</name>
-          <version>22</version>
-          <state>38</state>
-        </option>
-        <option>
-          <name>GFPUDeviceSlave</name>
-          <state>LPC1768	NXP LPC1768</state>
-        </option>
-        <option>
-          <name>FPU2</name>
-          <version>0</version>
+          <name>GRuntimeLibThreads</name>
           <state>0</state>
         </option>
-        <option>
-          <name>NrRegs</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>NEON</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave2</name>
-          <version>22</version>
-          <state>38</state>
-        </option>
       </data>
     </settings>
     <settings>
       <name>ICCARM</name>
       <archiveVersion>2</archiveVersion>
       <data>
-        <version>31</version>
+        <version>30</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
-        <option>
-          <name>CCOptimizationNoSizeConstraints</name>
-          <state>0</state>
-        </option>
         <option>
           <name>CCDefines</name>
-          <state>__CORTEX_M3</state>
-          <state>ARM_MATH_CM3</state>
-          <state>TARGET_LIKE_CORTEX_M3</state>
-          <state>TARGET_CORTEX_M</state>
-          <state>TARGET_LIKE_MBED</state>
-          <state>TARGET_LPC176X</state>
-          <state>TARGET_NXP</state>
-          <state>TARGET_LPC1768</state>
-          <state>MBED_BUILD_TIMESTAMP=1456180263.22</state>
-          <state>TARGET_M3</state>
-          <state>TOOLCHAIN_IAR</state>
-          <state>TARGET_MBED_LPC1768</state>
-          <state>__MBED__=1</state>
+          
+            <state>TARGET_FF_ARDUINO</state>
+          
+            <state>TARGET_KLXX</state>
+          
+            <state>TARGET_KL25Z</state>
+          
+            <state>TARGET_CORTEX_M</state>
+          
+            <state>TARGET_LIKE_MBED</state>
+          
+            <state>TARGET_M0P</state>
+          
+            <state>TARGET_Freescale</state>
+          
+            <state>__MBED__=1</state>
+          
+            <state>__CORTEX_M0PLUS</state>
+          
+            <state>TOOLCHAIN_IAR</state>
+          
+            <state>MBED_BUILD_TIMESTAMP=1456248884.8</state>
+          
+            <state>TARGET_LIKE_CORTEX_M0</state>
+          
+            <state>ARM_MATH_CM0PLUS</state>
+          
         </option>
         <option>
           <name>CCPreprocFile</name>
@@ -213,7 +210,7 @@
         </option>
         <option>
           <name>CCListCFile</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>CCListCMnemonics</name>
@@ -225,7 +222,7 @@
         </option>
         <option>
           <name>CCListAssFile</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>CCListAssSource</name>
@@ -237,7 +234,7 @@
         </option>
         <option>
           <name>CCDiagSuppress</name>
-          <state></state>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
         </option>
         <option>
           <name>CCDiagRemark</name>
@@ -258,7 +255,7 @@
         <option>
           <name>CCAllowList</name>
           <version>1</version>
-          <state>00000000</state>
+          <state>11111110</state>
         </option>
         <option>
           <name>CCDebugInfo</name>
@@ -274,14 +271,11 @@
         </option>
         <option>
           <name>IExtraOptionsCheck</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>IExtraOptions</name>
           <state></state>
-          <state>--no_rtti</state>
-          <state>--no_exceptions</state>
-          <state>--diag_suppress=Pa050,Pa084,Pa093,Pa082</state>
         </option>
         <option>
           <name>CCLangConformance</name>
@@ -309,7 +303,7 @@
         </option>
         <option>
           <name>IFpuProcessor</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>OutputFile</name>
@@ -317,7 +311,7 @@
         </option>
         <option>
           <name>CCLibConfigHeader</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>PreInclude</name>
@@ -329,13 +323,23 @@
         </option>
         <option>
           <name>CCIncludePath2</name>
-          <state>$PROJ_DIR$\env</state>
-          <state>$PROJ_DIR$\mbed</state>
-          <state>$PROJ_DIR$\mbed\TARGET_LPC1768</state>
-          <state>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X</state>
-          <state>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768</state>
+        
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP</state>
+        
+          <state>$PROJ_DIR$\env</state>
+        
+          <state>$PROJ_DIR$\mbed</state>
+        
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z</state>
+        
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z\TARGET_Freescale</state>
+        
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z\TARGET_Freescale\TARGET_KLXX</state>
+        
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z\TARGET_Freescale\TARGET_KLXX\TARGET_KL25Z</state>
+        
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z\TOOLCHAIN_IAR</state>
+        
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -355,7 +359,7 @@
         </option>
         <option>
           <name>CCOptLevel</name>
-          <state>1</state>
+          <state>3</state>
         </option>
         <option>
           <name>CCOptStrategy</name>
@@ -364,7 +368,7 @@
         </option>
         <option>
           <name>CCOptLevelSlave</name>
-          <state>1</state>
+          <state>3</state>
         </option>
         <option>
           <name>CompilerMisraRules98</name>
@@ -428,6 +432,10 @@
           <name>IccFloatSemantics</name>
           <state>0</state>
         </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
         <option>
           <name>CCNoLiteralPool</name>
           <state>0</state>
@@ -437,10 +445,6 @@
           <version>0</version>
           <state>0</state>
         </option>
-        <option>
-          <name>CCGuardCalls</name>
-          <state>1</state>
-        </option>
       </data>
     </settings>
     <settings>
@@ -456,7 +460,7 @@
         </option>
         <option>
           <name>AEndian</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>ACaseSensitivity</name>
@@ -477,15 +481,15 @@
         </option>
         <option>
           <name>AWarnOne</name>
-          <state>0</state>
+          <state></state>
         </option>
         <option>
           <name>AWarnRange1</name>
-          <state>0</state>
+          <state></state>
         </option>
         <option>
           <name>AWarnRange2</name>
-          <state>0</state>
+          <state></state>
         </option>
         <option>
           <name>ADebug</name>
@@ -501,7 +505,7 @@
         </option>
         <option>
           <name>AList</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>AListHeader</name>
@@ -545,11 +549,11 @@
         </option>
         <option>
           <name>TabSpacing</name>
-          <state>4</state>
+          <state>8</state>
         </option>
         <option>
           <name>AXRef</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>AXRefDefines</name>
@@ -565,11 +569,11 @@
         </option>
         <option>
           <name>AProcessor</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>AFpuProcessor</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>AOutputFile</name>
@@ -589,7 +593,7 @@
         </option>
         <option>
           <name>AIgnoreStdInclude</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>AUserIncludes</name>
@@ -601,7 +605,7 @@
         </option>
         <option>
           <name>AExtraOptionsV2</name>
-          <state>0</state>
+          <state></state>
         </option>
         <option>
           <name>AsmNoLiteralPool</name>
@@ -618,8 +622,8 @@
         <debug>1</debug>
         <option>
           <name>OOCOutputFormat</name>
-          <version>3</version>
-          <state>3</state>
+          <version>2</version>
+          <state>2</state>
         </option>
         <option>
           <name>OCOutputOverride</name>
@@ -631,7 +635,7 @@
         </option>
         <option>
           <name>OOCCommandLineProducer</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>OOCObjCopyEnable</name>
@@ -645,7 +649,6 @@
       <data>
         <extensions></extensions>
         <cmdline></cmdline>
-        <hasPrio>0</hasPrio>
       </data>
     </settings>
     <settings>
@@ -665,13 +668,9 @@
       <name>ILINK</name>
       <archiveVersion>0</archiveVersion>
       <data>
-        <version>17</version>
+        <version>16</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
-        <option>
-          <name>IlinkOutputFile</name>
-          <state>mbed.out</state>
-        </option>
         <option>
           <name>IlinkLibIOConfig</name>
           <state>1</state>
@@ -684,6 +683,10 @@
           <name>IlinkInputFileSlave</name>
           <state>0</state>
         </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
         <option>
           <name>IlinkDebugInfoEnable</name>
           <state>1</state>
@@ -746,7 +749,7 @@
         </option>
         <option>
           <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\LPC17xx.icf</state>
+          <state>$PROJ_DIR$\mbed\TARGET_KL25Z\TOOLCHAIN_IAR\MKL25Z4.icf</state>
         </option>
         <option>
           <name>IlinkIcfFileSlave</name>
@@ -782,7 +785,6 @@
         </option>
         <option>
           <name>IlinkExtraOptions</name>
-          <state></state>
           <state>--skip_dynamic_initialization</state>
         </option>
         <option>
@@ -795,7 +797,7 @@
         </option>
         <option>
           <name>IlinkAdditionalLibs</name>
-          <state></state>
+          <state></state>        
         </option>
         <option>
           <name>IlinkOverrideProgramEntryLabel</name>
@@ -950,10 +952,6 @@
           <name>IlinkThreadsSlave</name>
           <state>1</state>
         </option>
-        <option>
-          <name>IlinkLogCallGraph</name>
-          <state>0</state>
-        </option>
       </data>
     </settings>
     <settings>
@@ -983,369 +981,15 @@
       <data/>
     </settings>
   </configuration>
-  <group>
-    <name>Include Files</name>
-    <file>
-      <name>$PROJ_DIR$\mbed\AnalogIn.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\analogin_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\AnalogOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\analogout_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\arm_common_tables.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\arm_const_structs.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\arm_math.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\buffer.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\BusIn.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\BusInOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\BusOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\CallChain.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\CAN.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\can_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\can_helper.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\CircularBuffer.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\cmsis.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\cmsis_nvic.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_ca9.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_ca_mmu.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_caFunc.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_caInstr.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm0.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm0plus.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm3.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm4.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm4_simd.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cm7.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmFunc.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmInstr.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_cmSimd.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_sc000.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\core_sc300.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\CThunk.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\device.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\DigitalIn.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\DigitalInOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\DigitalOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\DirHandle.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\dma_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\env</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Ethernet.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\ethernet_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FileBase.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FileHandle.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FileLike.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FilePath.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FileSystemLike.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\FunctionPointer.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\gpio_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\gpio_irq_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\gpio_object.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\I2C.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\i2c_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\I2CSlave.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\InterruptIn.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\InterruptManager.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\LocalFileSystem.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\LowPowerTicker.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\LowPowerTimeout.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\LowPowerTimer.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\lp_ticker_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\LPC17xx.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\mbed.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\mbed_assert.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\mbed_debug.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\mbed_error.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\mbed_interface.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\objects.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\PeripheralNames.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\pinmap.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\PinNames.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\platform.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\port_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\PortIn.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\PortInOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\PortNames.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\PortOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\PwmOut.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\pwmout_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\RawSerial.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768\reserved_pins.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\rtc_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\rtc_time.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\semihost_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Serial.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\serial_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\SerialBase.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\sleep_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\SPI.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\spi_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\SPISlave.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Stream.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\system_LPC17xx.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP\TARGET_LPC176X\TARGET_MBED_LPC1768</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TARGET_NXP</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\env\test_env.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Ticker.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\ticker_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Timeout.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Timer.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TimerEvent.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\toolchain.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\Transaction.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\us_ticker_api.h</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\wait_api.h</name>
-    </file>
-  </group>
-  <group>
-    <name>Source Files</name>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\board.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\cmain.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\cmsis_nvic.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\main.cpp</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\mbed.a</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\retarget.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\startup_LPC17xx.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\mbed\TARGET_LPC1768\TOOLCHAIN_IAR\system_LPC17xx.o</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\env\test_env.cpp</name>
-    </file>
-  </group>
+  <file>
+<name>$PROJ_DIR$/main.cpp</name>
+</file>
+<group>
+<name>env</name>
+<file>
+<name>$PROJ_DIR$/env\test_env.cpp</name>
+</file>
+</group>
+
 </project>
 
-

From 7bdd08918fe1dcfadfcd85fbbb546841990f6390 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Tue, 23 Feb 2016 18:04:19 +0000
Subject: [PATCH 31/78] Setup - req progen v0.8.8 - for IAR

---
 setup.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/setup.py b/setup.py
index 42fbcec45f..3a2e5325d1 100644
--- a/setup.py
+++ b/setup.py
@@ -40,7 +40,7 @@ setup(name='mbed-tools',
       url='https://github.com/mbedmicro/mbed',
       packages=find_packages(),
       license=LICENSE,
-      install_requires=["PrettyTable>=0.7.2", "PySerial>=2.7", "IntelHex>=1.3", "colorama>=0.3.3", "Jinja2>=2.7.3", "project-generator>=0.8.4,<0.9.0"])
+      install_requires=["PrettyTable>=0.7.2", "PySerial>=2.7", "IntelHex>=1.3", "colorama>=0.3.3", "Jinja2>=2.7.3", "project-generator>=0.8.8,<0.9.0"])
 
 # Restore previous private_settings if needed
 if backup:

From ba6ba1f687ce1c444be3fd5e488a5e0713ca0006 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Wed, 24 Feb 2016 17:58:53 +0000
Subject: [PATCH 32/78] Progen data refactor

The new format progen = dict() should allow to add more data used by progen.
The target can add tool flags to be overwritten by the default mbed template, or
even inject own template. This might be required for some targets. Therefore we
shall allow thiss.
---
 workspace_tools/export/__init__.py  |   2 +-
 workspace_tools/export/exporters.py |   2 +-
 workspace_tools/targets.py          | 304 ++++++++++++++++++++--------
 3 files changed, 225 insertions(+), 83 deletions(-)

diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py
index 9daf998988..81b36ee04a 100755
--- a/workspace_tools/export/__init__.py
+++ b/workspace_tools/export/__init__.py
@@ -88,7 +88,7 @@ def export(project_path, project_name, ide, target, destination='/tmp/',
             except AttributeError:
                 pass
             if use_progen:
-                if not ProGenDef(ide).is_supported(TARGET_MAP[target].progen_target):
+                if not ProGenDef(ide).is_supported(TARGET_MAP[target].progen['target']):
                     supported = False
             else:
                 if target not in Exporter.TARGETS:
diff --git a/workspace_tools/export/exporters.py b/workspace_tools/export/exporters.py
index e64382aa6e..3697fae0d6 100644
--- a/workspace_tools/export/exporters.py
+++ b/workspace_tools/export/exporters.py
@@ -64,7 +64,7 @@ class Exporter(object):
                 'includes':  { 
                     'Include Files': self.resources.headers + self.resources.inc_dirs,
                 },
-                'target': [TARGET_MAP[self.target].progen_target],
+                'target': [TARGET_MAP[self.target].progen['target']],
                 'macros': self.get_symbols(),
                 'export_dir': [self.inputDir],
                 'linker_file': [self.resources.linker_script],
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index e27c8446e2..a2932865c3 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -123,7 +123,10 @@ class LPC11C24(LPCTarget):
         self.core = "Cortex-M0"
         self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11CXX']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
-        self.progen_target = 'lpc11c24_301'
+
+        self.progen = {
+            "target":"lpc11c24_301",
+        }
 
 class LPC1114(LPCTarget):
     def __init__(self):
@@ -132,7 +135,9 @@ class LPC1114(LPCTarget):
         self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11XX']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"]
         self.default_toolchain = "uARM"
-        self.progen_target = 'lpc1114_102'
+        self.progen = {
+            "target":"lpc1114_102",
+        }
 
 class LPC11U24(LPCTarget):
     def __init__(self):
@@ -142,7 +147,9 @@ class LPC11U24(LPCTarget):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "uARM"
         self.detect_code = ["1040"]
-        self.progen_target = 'lpc11u24_201'
+        self.progen = {
+            "target":"lpc11u24_201",
+        }
 
 class OC_MBUINO(LPC11U24):
     def __init__(self):
@@ -152,7 +159,9 @@ class OC_MBUINO(LPC11U24):
         self.macros = ['TARGET_LPC11U24']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "uARM"
-        self.progen_target = 'lpc11u24_201'
+        self.progen = {
+            "target":"lpc11u24_201",
+        }
 
 class LPC11U24_301(LPCTarget):
     def __init__(self):
@@ -184,7 +193,9 @@ class LPC11U35_401(LPCTarget):
         self.extra_labels = ['NXP', 'LPC11UXX']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"]
         self.default_toolchain = "uARM"
-        self.progen_target = 'lpc11u35_401'
+        self.progen = {
+            "target":"lpc11u35_401",
+        }
 
 class LPC11U35_501(LPCTarget):
     def __init__(self):
@@ -193,8 +204,9 @@ class LPC11U35_501(LPCTarget):
         self.extra_labels = ['NXP', 'LPC11UXX', 'MCU_LPC11U35_501']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR" , "IAR"]
         self.default_toolchain = "uARM"
-        self.progen_target ='lpc11u35_501'
-
+        self.progen = {
+            "target":"lpc11u35_501",
+        }
 class LPC11U35_501_IBDAP(LPCTarget):
     def __init__(self):
         LPCTarget.__init__(self)
@@ -249,15 +261,18 @@ class LPC11U68(LPCTarget):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["1168"]
-        self.progen_target ='lpc11u68'
-
+        self.progen = {
+            "target":"lpc11u68",
+        }
 class LPC1347(LPCTarget):
     def __init__(self):
         LPCTarget.__init__(self)
         self.core = "Cortex-M3"
         self.extra_labels = ['NXP', 'LPC13XX']
         self.supported_toolchains = ["ARM", "GCC_ARM","IAR"]
-        self.progen_target = 'lpc1347'
+        self.progen = {
+            "target":"lpc1347",
+        }
 
 class LPC1549(LPCTarget):
     def __init__(self):
@@ -268,8 +283,9 @@ class LPC1549(LPCTarget):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["1549"]
-        self.progen_target ='lpc1549'
-
+        self.progen = {
+            "target":"lpc1549",
+        }
 class LPC1768(LPCTarget):
     def __init__(self):
         LPCTarget.__init__(self)
@@ -277,7 +293,9 @@ class LPC1768(LPCTarget):
         self.extra_labels = ['NXP', 'LPC176X', 'MBED_LPC1768']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"]
         self.detect_code = ["1010"]
-        self.progen_target = 'mbed-lpc1768'
+        self.progen = {
+            "target":"mbed-lpc1768",
+        }
 
 class ARCH_PRO(LPCTarget):
     def __init__(self):
@@ -287,7 +305,9 @@ class ARCH_PRO(LPCTarget):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"]
         self.macros = ['TARGET_LPC1768']
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='arch-pro'
+        self.progen = {
+            "target":"arch-pro",
+        }
 
 class UBLOX_C027(LPCTarget):
     def __init__(self):
@@ -297,7 +317,9 @@ class UBLOX_C027(LPCTarget):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"]
         self.macros = ['TARGET_LPC1768']
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='ublox-c027'
+        self.progen = {
+            "target":"ublox-c027",
+        }
 
 class XBED_LPC1768(LPCTarget):
     def __init__(self):
@@ -341,7 +363,9 @@ class LPC812(LPCTarget):
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
         self.detect_code = ["1050"]
-        self.progen_target = 'lpc812m101'
+        self.progen = {
+            "target":"lpc812m101",
+        }
 
 class LPC824(LPCTarget):
     def __init__(self):
@@ -352,7 +376,9 @@ class LPC824(LPCTarget):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
-        self.progen_target = 'lpc824m201'
+        self.progen = {
+            "target":"lpc824m201",
+        }
 
 class SSCI824(LPCTarget):
     def __init__(self):
@@ -370,7 +396,9 @@ class LPC4088(LPCTarget):
         self.extra_labels = ['NXP', 'LPC408X']
         self.supported_toolchains = ["ARM", "GCC_CR", "GCC_ARM", "IAR"]
         self.is_disk_virtual = True
-        self.progen_target = 'lpc4088'
+        self.progen = {
+            "target":"lpc4088",
+        }
 
     def init_hooks(self, hook, toolchain_name):
         if toolchain_name in ['ARM_STD', 'ARM_MICRO']:
@@ -415,7 +443,9 @@ class LPC4330_M4(LPCTarget):
         self.core = "Cortex-M4F"
         self.extra_labels = ['NXP', 'LPC43XX', 'LPC4330']
         self.supported_toolchains = ["ARM", "GCC_CR", "IAR", "GCC_ARM"]
-        self.progen_target = 'lpc4330'
+        self.progen = {
+            "target":"lpc4330",
+        }
 
 class LPC4330_M0(LPCTarget):
     def __init__(self):
@@ -430,7 +460,9 @@ class LPC4337(LPCTarget):
         self.core = "Cortex-M4F"
         self.extra_labels = ['NXP', 'LPC43XX', 'LPC4337']
         self.supported_toolchains = ["ARM"]
-        self.progen_target = 'lpc4337'
+        self.progen = {
+            "target":"lpc4337",
+        }
 class LPC1800(LPCTarget):
     def __init__(self):
         LPCTarget.__init__(self)
@@ -446,8 +478,9 @@ class LPC11U37H_401(LPCTarget):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"]
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='lpc11u37_401'
-
+        self.progen = {
+            "target":"lpc11u37_401",
+        }
 ### Freescale ###
 
 class KL05Z(Target):
@@ -459,7 +492,9 @@ class KL05Z(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
-        self.progen_target ='frdm-kl05z'
+        self.progen = {
+            "target":"frdm-kl05z",
+        }
 
 class KL25Z(Target):
     def __init__(self):
@@ -470,7 +505,9 @@ class KL25Z(Target):
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
         self.detect_code = ["0200"]
-        self.progen_target ='frdm-kl25z'
+        self.progen = {
+            "target":"frdm-kl25z",
+        }
 
 class KL26Z(Target):
     def __init__(self):
@@ -489,7 +526,9 @@ class KL43Z(Target):
         self.supported_toolchains = ["GCC_ARM", "ARM"]
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
-        self.progen_target ='frdm-kl43z'
+        self.progen = {
+            "target":"frdm-kl43z",
+        }
 
 class KL46Z(Target):
     def __init__(self):
@@ -500,7 +539,9 @@ class KL46Z(Target):
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
         self.detect_code = ["0220"]
-        self.progen_target ='frdm-kl46z'
+        self.progen = {
+            "target":"frdm-kl46z",
+        }
 
 class K20D50M(Target):
     def __init__(self):
@@ -510,7 +551,9 @@ class K20D50M(Target):
         self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"]
         self.is_disk_virtual = True
         self.detect_code = ["0230"]
-        self.progen_target = 'frdm-k20d50m'
+        self.progen = {
+            "target":"frdm-k20d50m",
+        }
 
 class TEENSY3_1(Target):
     OUTPUT_EXT = 'hex'
@@ -522,7 +565,9 @@ class TEENSY3_1(Target):
         self.supported_toolchains = ["GCC_ARM", "ARM"]
         self.is_disk_virtual = True
         self.detect_code = ["0230"]
-        self.progen_target ='teensy-31'
+        self.progen = {
+            "target":"teensy-31",
+        }
 
     def init_hooks(self, hook, toolchain_name):
         if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']:
@@ -547,7 +592,9 @@ class K22F(Target):
         self.supported_form_factors = ["ARDUINO"]
         self.is_disk_virtual = True
         self.detect_code = ["0201"]
-        self.progen_target = 'frdm-k22f'
+        self.progen = {
+            "target":"frdm-k22f",
+        }
 
 class K64F(Target):
     def __init__(self):
@@ -560,7 +607,9 @@ class K64F(Target):
         self.is_disk_virtual = True
         self.default_toolchain = "ARM"
         self.detect_code = ["0240"]
-        self.progen_target = 'frdm-k64f'
+        self.progen = {
+            "target":"frdm-k64f",
+        }
 
 class MTS_GAMBIT(Target):
     def __init__(self):
@@ -571,7 +620,9 @@ class MTS_GAMBIT(Target):
         self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"]
         self.is_disk_virtual = True
         self.default_toolchain = "ARM"
-        self.progen_target ='mts-gambit'
+        self.progen = {
+            "target":"mts-gambit",
+        }
 
 ### STMicro ###
 
@@ -584,7 +635,9 @@ class NUCLEO_F030R8(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0725"]
-        self.progen_target ='nucleo-f030r8'
+        self.progen = {
+            "target":"nucleo-f030r8",
+        }
 
 class NUCLEO_F031K6(Target):
     def __init__(self):
@@ -595,7 +648,9 @@ class NUCLEO_F031K6(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["0791"]
-        self.progen_target ='nucleo-f031k6'
+        self.progen = {
+            "target":"nucleo-f031k6",
+        }
 
 class NUCLEO_F042K6(Target):
     def __init__(self):
@@ -606,7 +661,9 @@ class NUCLEO_F042K6(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["0785"]
-        self.progen_target ='nucleo-f042k6'
+        self.progen = {
+            "target":"nucleo-f042k6",
+        }
 
 class NUCLEO_F070RB(Target):
     def __init__(self):
@@ -617,7 +674,9 @@ class NUCLEO_F070RB(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0755"]
-        self.progen_target ='nucleo-f070rb'
+        self.progen = {
+            "target":"nucleo-f070rb",
+        }
 
 class NUCLEO_F072RB(Target):
     def __init__(self):
@@ -628,7 +687,9 @@ class NUCLEO_F072RB(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0730"]
-        self.progen_target ='nucleo-f072rb'
+        self.progen = {
+            "target":"nucleo-f072rb",
+        }
 
 class NUCLEO_F091RC(Target):
     def __init__(self):
@@ -639,7 +700,9 @@ class NUCLEO_F091RC(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0750"]
-        self.progen_target ='nucleo-f091rc'
+        self.progen = {
+            "target":"nucleo-f091rc",
+        }
 
 class NUCLEO_F103RB(Target):
     def __init__(self):
@@ -650,7 +713,9 @@ class NUCLEO_F103RB(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0700"]
-        self.progen_target ='nucleo-f103rb'
+        self.progen = {
+            "target":"nucleo-f103rb",
+        }
 
 class NUCLEO_F302R8(Target):
     def __init__(self):
@@ -661,7 +726,9 @@ class NUCLEO_F302R8(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0705"]
-        self.progen_target ='nucleo-f302r8'
+        self.progen = {
+            "target":"nucleo-f302r8",
+        }
 
 class NUCLEO_F303K8(Target):
     def __init__(self):
@@ -672,7 +739,9 @@ class NUCLEO_F303K8(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["0775"]
-        self.progen_target ='nucleo-f303k8'
+        self.progen = {
+            "target":"nucleo-f303k8",
+        }
 
 class NUCLEO_F303RE(Target):
     def __init__(self):
@@ -683,7 +752,9 @@ class NUCLEO_F303RE(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0745"]
-        self.progen_target ='nucleo-f303re'
+        self.progen = {
+            "target":"nucleo-f303re",
+        }
 
 class NUCLEO_F334R8(Target):
     def __init__(self):
@@ -694,7 +765,9 @@ class NUCLEO_F334R8(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0735"]
-        self.progen_target ='nucleo-f334r8'
+        self.progen = {
+            "target":"nucleo-f334r8",
+        }
 
 class NUCLEO_F401RE(Target):
     def __init__(self):
@@ -705,7 +778,9 @@ class NUCLEO_F401RE(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0720"]
-        self.progen_target ='nucleo-f401re'
+        self.progen = {
+            "target":"nucleo-f401re",
+        }
 
 class NUCLEO_F410RB(Target):
     def __init__(self):
@@ -716,7 +791,9 @@ class NUCLEO_F410RB(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0740"]
-        self.progen_target ='nucleo-f410rb'
+        self.progen = {
+            "target":"",
+        }
 
 class NUCLEO_F411RE(Target):
     def __init__(self):
@@ -727,7 +804,9 @@ class NUCLEO_F411RE(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0740"]
-        self.progen_target ='nucleo-f411re'
+        self.progen = {
+            "target":"nucleo-f411re",
+        }
 
 class ELMO_F411RE(Target):
     def __init__(self):
@@ -748,7 +827,9 @@ class NUCLEO_F446RE(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0777"]
-        self.progen_target ='nucleo-f446re'
+        self.progen = {
+            "target":"nucleo-f446re",
+        }
 
 class B96B_F446VE(Target):
     def __init__(self):
@@ -769,7 +850,9 @@ class NUCLEO_L053R8(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0715"]
-        self.progen_target ='nucleo-l053r8'
+        self.progen = {
+            "target":"nucleo-l053r8",
+        }
 
 class NUCLEO_L073RZ(Target):
     def __init__(self):
@@ -780,7 +863,9 @@ class NUCLEO_L073RZ(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0760"]
-        self.progen_target ='nucleo-l073rz'
+        self.progen = {
+            "target":"nucleo-l073rz",
+        }
 
 class NUCLEO_L152RE(Target):
     def __init__(self):
@@ -791,7 +876,9 @@ class NUCLEO_L152RE(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0710"]
-        self.progen_target ='nucleo-l152re'
+        self.progen = {
+            "target":"nucleo-l152re",
+        }
 
 class NUCLEO_L476RG(Target):
     def __init__(self):
@@ -802,7 +889,9 @@ class NUCLEO_L476RG(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0765"]
-        self.progen_target ='nucleo-l476rg'
+        self.progen = {
+            "target":"nucleo-l476rg",
+        }
 
 class STM32F3XX(Target):
     def __init__(self):
@@ -827,8 +916,9 @@ class ARCH_MAX(Target):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
         self.supported_form_factors = ["ARDUINO"]
         self.macros = ['LSI_VALUE=32000']
-        self.progen_target ='lpc1768'
-
+        self.progen = {
+            "target":"lpc1768",
+        }
     def program_cycle_s(self):
         return 2
 
@@ -864,7 +954,9 @@ class DISCO_F334C8(Target):
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.default_toolchain = "uARM"
         self.detect_code = ["0810"]
-        self.progen_target ='disco-f334c8'
+        self.progen = {
+            "target":"disco-f334c8",
+        }
 
 class DISCO_F407VG(Target):
     def __init__(self):
@@ -872,7 +964,9 @@ class DISCO_F407VG(Target):
         self.core = "Cortex-M4F"
         self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
-        self.progen_target ='disco-f407vg'
+        self.progen = {
+            "target":"disco-f407vg",
+        }
         self.default_toolchain = "ARM"
 
 class DISCO_F429ZI(Target):
@@ -882,7 +976,9 @@ class DISCO_F429ZI(Target):
         self.extra_labels = ['STM', 'STM32F4', 'STM32F429', 'STM32F429ZI']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "uARM"
-        self.progen_target ='disco-f429zi'
+        self.progen = {
+            "target":"",
+        }
 
 class DISCO_F469NI(Target):
     def __init__(self):
@@ -893,7 +989,9 @@ class DISCO_F469NI(Target):
         self.default_toolchain = "uARM"
         self.supported_form_factors = ["ARDUINO"]
         self.detect_code = ["0788"]
-        self.progen_target ='disco-f469ni'
+        self.progen = {
+            "target":"disco-f469ni",
+        }
 
 class DISCO_L053C8(Target):
     def __init__(self):
@@ -902,7 +1000,9 @@ class DISCO_L053C8(Target):
         self.extra_labels = ['STM', 'STM32L0', 'STM32L053C8']
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.default_toolchain = "uARM"
-        self.progen_target ='disco-l053c8'
+        self.progen = {
+            "target":"disco-l053c8",
+        }
 
 class DISCO_F746NG(Target):
     def __init__(self):
@@ -911,7 +1011,9 @@ class DISCO_F746NG(Target):
         self.extra_labels = ['STM', 'STM32F7', 'STM32F746', 'STM32F746NG']
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.detect_code = ["0815"]
-        self.progen_target ='disco-f746ng'
+        self.progen = {
+            "target":"disco-f746ng",
+        }
 
 class DISCO_L476VG(Target):
     def __init__(self):
@@ -921,7 +1023,9 @@ class DISCO_L476VG(Target):
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.default_toolchain = "uARM"
         self.detect_code = ["0820"]
-        self.progen_target ='disco-l476vg'
+        self.progen = {
+            "target":"disco-l476vg",
+        }
 
 class MTS_MDOT_F405RG(Target):
     def __init__(self):
@@ -932,7 +1036,9 @@ class MTS_MDOT_F405RG(Target):
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.is_disk_virtual = True
         self.default_toolchain = "ARM"
-        self.progen_target ='mts-mdot-f405rg'
+        self.progen = {
+            "target":"mts-mdot-f405rg",
+        }
 
 class MTS_MDOT_F411RE(Target):
     def __init__(self):
@@ -942,7 +1048,9 @@ class MTS_MDOT_F411RE(Target):
         self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0', 'VECT_TAB_OFFSET=0x00010000']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "ARM"
-        self.progen_target = 'mts-mdot-f411re'
+        self.progen = {
+            "target":"mts-mdot-f411re",
+        }
 
     def init_hooks(self, hook, toolchain_name):
         if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']:
@@ -984,7 +1092,9 @@ class MTS_DRAGONFLY_F411RE(Target):
         self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08010000']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "ARM"
-        self.progen_target = 'mts-dragonfly-f411re'
+        self.progen = {
+            "target":"mts-dragonfly-f411re",
+        }
 
     def init_hooks(self, hook, toolchain_name):
         if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']:
@@ -1026,8 +1136,9 @@ class MOTE_L152RC(Target):
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.default_toolchain = "uARM"
         self.detect_code = ["4100"]
-        self.progen_target ='stm32l151rc'
-
+        self.progen = {
+            "target":"stm32l151rc",
+        }
 class DISCO_F401VC(Target):
     def __init__(self):
         Target.__init__(self)
@@ -1053,7 +1164,9 @@ class NZ32_SC151(Target):
         self.extra_labels = ['STM', 'STM32L1', 'STM32L151RC']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
         self.default_toolchain = "uARM"
-        self.progen_target ='stm32l151rc'
+        self.progen = {
+            "target":"stm32l151rc",
+        }
     # After flashing device, how long to delay until we assume program is running
     def program_cycle_s(self):
         return 1.5
@@ -1281,8 +1394,9 @@ class NRF51822(MCU_NRF51_16K):
         MCU_NRF51_16K.__init__(self)
         self.extra_labels += ['NRF51822', 'NRF51822_MKIT']
         self.macros += ['TARGET_NRF51822_MKIT']
-        self.progen_target ='mkit'
-
+        self.progen = {
+            "target":"mkit",
+        }
 class NRF51822_BOOT(MCU_NRF51_16K_BOOT):
     def __init__(self):
         MCU_NRF51_16K_BOOT.__init__(self)
@@ -1299,7 +1413,9 @@ class ARCH_BLE(MCU_NRF51_16K):
     def __init__(self):
         MCU_NRF51_16K.__init__(self)
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='arch-ble'
+        self.progen = {
+            "target":"arch-ble",
+        }
 
 class ARCH_BLE_BOOT(MCU_NRF51_16K_BOOT):
     def __init__(self):
@@ -1339,7 +1455,9 @@ class ARCH_LINK_OTA(MCU_NRF51_16K_OTA):
 class SEEED_TINY_BLE(MCU_NRF51_16K):
     def __init__(self):
         MCU_NRF51_16K.__init__(self)
-        self.progen_target ='seed-tinyble'
+        self.progen = {
+            "target":"seed-tinyble",
+        }
 
 class SEEED_TINY_BLE_BOOT(MCU_NRF51_16K_BOOT):
     def __init__(self):
@@ -1357,8 +1475,9 @@ class HRM1017(MCU_NRF51_16K):
     def __init__(self):
         MCU_NRF51_16K.__init__(self)
         self.macros += ['TARGET_NRF_LFCLK_RC']
-        self.progen_target ='hrm1017'
-
+        self.progen = {
+            "target":"hrm1017",
+        }
 class HRM1017_BOOT(MCU_NRF51_16K_BOOT):
     def __init__(self):
         MCU_NRF51_16K_BOOT.__init__(self)
@@ -1375,7 +1494,9 @@ class RBLAB_NRF51822(MCU_NRF51_16K):
     def __init__(self):
         MCU_NRF51_16K.__init__(self)
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='rblab-nrf51822'
+        self.progen = {
+            "target":"rblab-nrf51822",
+        }
 
 class RBLAB_NRF51822_BOOT(MCU_NRF51_16K_BOOT):
     def __init__(self):
@@ -1432,7 +1553,9 @@ class DELTA_DFCM_NNN40(MCU_NRF51_32K):
         MCU_NRF51_32K.__init__(self)
         self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.macros += ['TARGET_NRF_LFCLK_RC']
-        self.progen_target ='dfcm-nnn40'
+        self.progen = {
+            "target":"dfcm-nnn40",
+        }
     def program_cycle_s(self):
         return 10
 
@@ -1459,7 +1582,9 @@ class NRF51_DK(MCU_NRF51_32K):
         MCU_NRF51_32K.__init__(self)
         self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.supported_form_factors = ["ARDUINO"]
-        self.progen_target ='nrf51-dk'
+        self.progen = {
+            "target":"nrf51-dk",
+        }
 
 class NRF51_DK_BOOT(MCU_NRF51_32K_BOOT):
     def __init__(self):
@@ -1480,7 +1605,9 @@ class NRF51_DK_OTA(MCU_NRF51_32K_OTA):
 class NRF51_DONGLE(MCU_NRF51_32K):
     def __init__(self):
         MCU_NRF51_32K.__init__(self)
-        self.progen_target ='nrf51-dongle'
+        self.progen = {
+            "target":"nrf51-dongle",
+        }
 
 class NRF51_DONGLE_BOOT(MCU_NRF51_32K_BOOT):
     def __init__(self):
@@ -1633,6 +1760,9 @@ class RZ_A1H(Target):
         self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"]
         self.supported_form_factors = ["ARDUINO"]
         self.default_toolchain = "ARM"
+        self.progen = {
+            "target": "gr-peach",
+        }
 
     def program_cycle_s(self):
         return 2
@@ -1648,7 +1778,9 @@ class MAXWSNENV(Target):
         self.macros = ['__SYSTEM_HFX=24000000']
         self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='maxwsnenv'
+        self.progen = {
+            "target": "maxwsnenv", 
+        }
 
 class MAX32600MBED(Target):
     def __init__(self):
@@ -1658,7 +1790,9 @@ class MAX32600MBED(Target):
         self.macros = ['__SYSTEM_HFX=24000000']
         self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='max32600mbed'
+        self.progen = {
+            "target": "max32600mbed", 
+        }
 
 ### Silicon Labs ###
 
@@ -1757,7 +1891,9 @@ class SAMR21G18A(Target):
         self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
         self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='samr21g18a'
+        self.progen = {
+            "target":"samr21g18a",
+        }
 
 class SAMD21J18A(Target):
     def __init__(self):
@@ -1767,7 +1903,9 @@ class SAMD21J18A(Target):
         self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
         self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='samd21j18a'
+        self.progen = {
+            "target":"samd21j18a",
+        }
 
 class SAMD21G18A(Target):
     def __init__(self):
@@ -1777,7 +1915,9 @@ class SAMD21G18A(Target):
         self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
         self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='samd21g18a'
+        self.progen = {
+            "target":"samd21g18a",
+        }
 
 class SAML21J18A(Target):
     def __init__(self):
@@ -1787,7 +1927,9 @@ class SAML21J18A(Target):
         self.macros = ['__SAML21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
         self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
         self.default_toolchain = "ARM"
-        self.progen_target ='samr21j18a'
+        self.progen = {
+            "target":"samr21j18a",
+        }
 
 # Get a single instance for each target
 TARGETS = [

From 364143773562e94de74c25242405a97fa8383031 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Wed, 24 Feb 2016 18:16:18 +0000
Subject: [PATCH 33/78] Exporter IAR - fix issupported argument - string

---
 workspace_tools/export/iar.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index a098e2851b..07ec5fb7a4 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -37,8 +37,8 @@ class IAREmbeddedWorkbench(Exporter):
     TARGETS = []
     for target in TARGET_NAMES:
         try:
-            if (ProGenDef('iar').is_supported(TARGET_MAP[target]) or
-                ProGenDef('iar').is_supported(TARGET_MAP[target].progen_target)):
+            if (ProGenDef('iar').is_supported(str(TARGET_MAP[target])) or
+                ProGenDef('iar').is_supported(TARGET_MAP[target].progen['target'])):
                 TARGETS.append(target)
         except AttributeError:
             # target is not supported yet

From 6525b8ee3e31bc819da2f52a4771b95455108733 Mon Sep 17 00:00:00 2001
From: neilt6 <neilt66@icloud.com>
Date: Wed, 24 Feb 2016 14:07:09 -0700
Subject: [PATCH 34/78] [LPC1549] Improve AnalogIn Performance

Modified the LPC1549 AnalogIn implementation to use the ADCs in
synchronous mode, which is consistent with the LPC11U68 implementation.
This improves performance, and allows the IRC oscillator to be powered
down if necessary.
---
 .../targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c  | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c
index da3bcef999..509f913706 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c
@@ -77,10 +77,6 @@ void analogin_init(analogin_t *obj, PinName pin) {
         LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
     }
 
-    // select IRC as asynchronous clock, divided by 1
-    LPC_SYSCON->ADCASYNCCLKSEL  = 0;
-    LPC_SYSCON->ADCASYNCCLKDIV  = 1;
-
     __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
 
     // determine the system clock divider for a 500kHz ADC clock during calibration
@@ -90,8 +86,8 @@ void analogin_init(analogin_t *obj, PinName pin) {
     adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
     while ((adc_reg->CTRL & (1UL << 30)) != 0);
 
-    // switch to asynchronous mode
-    adc_reg->CTRL = (1UL << 8);
+    // Sampling clock: SystemClock divided by 1
+    adc_reg->CTRL = 0;
 }
 
 static inline uint32_t adc_read(analogin_t *obj) {

From d8f60f387d905829dcc9483b832a4d461467af52 Mon Sep 17 00:00:00 2001
From: Toyomasa Watarai <toyomasa.watarai@gmail.com>
Date: Thu, 25 Feb 2016 15:49:35 +0900
Subject: [PATCH 35/78] Add LPC11U35 uvision exporter support

* Add LPC11U35_401 uvision exporter
* Add LPC11U35_501 uvision exporter
---
 workspace_tools/export/uvision4.py            |   4 +
 .../export/uvision4_lpc11u35_401.uvopt.tmpl   | 215 +++++++++
 .../export/uvision4_lpc11u35_401.uvproj.tmpl  | 429 ++++++++++++++++++
 .../export/uvision4_lpc11u35_501.uvopt.tmpl   | 218 +++++++++
 .../export/uvision4_lpc11u35_501.uvproj.tmpl  | 424 +++++++++++++++++
 workspace_tools/export_test.py                |   2 +
 6 files changed, 1292 insertions(+)
 create mode 100644 workspace_tools/export/uvision4_lpc11u35_401.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_lpc11u35_401.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_lpc11u35_501.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_lpc11u35_501.uvproj.tmpl

diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index 031a5cbc65..466e02bbf3 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -24,6 +24,8 @@ class Uvision4(Exporter):
     TARGETS = [
         'LPC1768',
         'LPC11U24',
+        'LPC11U35_401',
+        'LPC11U35_501',
         'KL05Z',
         'KL25Z',
         'KL43Z',
@@ -102,6 +104,8 @@ class Uvision4(Exporter):
 
     USING_MICROLIB = [
         'LPC11U24',
+        'LPC11U35_401',
+        'LPC11U35_501',
         'LPC1114',
         'LPC11C24',
         'LPC812',
diff --git a/workspace_tools/export/uvision4_lpc11u35_401.uvopt.tmpl b/workspace_tools/export/uvision4_lpc11u35_401.uvopt.tmpl
new file mode 100644
index 0000000000..6dfb7e6143
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc11u35_401.uvopt.tmpl
@@ -0,0 +1,215 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>mbed NXP LPC11U35_401</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC11Uxx\LPC11U3x_DS.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC11Uxx\UM10462.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>0</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>14</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"MBED CMSIS-DAP" -UA000000001 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>2</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_lpc11u35_401.uvproj.tmpl b/workspace_tools/export/uvision4_lpc11u35_401.uvproj.tmpl
new file mode 100644
index 0000000000..e09027c936
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc11u35_401.uvproj.tmpl
@@ -0,0 +1,429 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>mbed NXP LPC11U35_401</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC11U35/401</Device>
+          <Vendor>NXP</Vendor>
+          <Cpu>IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0xFFFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000)</FlashDriverDll>
+          <DeviceId>6505</DeviceId>
+          <RegisterFile>LPC11Uxx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC11Uxx\LPC11Uxx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC11Uxx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC11Uxx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>1</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ELFDWT.EXE "!L"</UserProg1Name>
+            <UserProg2Name>fromelf --bin -o {{name}}_LPC11U35_401.bin build\{{name}}.axf</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>0</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>13</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4104</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>BIN\CMSIS_AGDI.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20004000</StartAddress>
+                <Size>0x800</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_lpc11u35_501.uvopt.tmpl b/workspace_tools/export/uvision4_lpc11u35_501.uvopt.tmpl
new file mode 100644
index 0000000000..9b96939968
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc11u35_501.uvopt.tmpl
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>mbed NXP LPC11U35_501</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC11Uxx\LPC11U3x_DS.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC11Uxx\LPC11U3x_UM.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>0</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"MBED CMSIS-DAP" -UA000000001 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>2</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_lpc11u35_501.uvproj.tmpl b/workspace_tools/export/uvision4_lpc11u35_501.uvproj.tmpl
new file mode 100644
index 0000000000..01b8e541ab
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc11u35_501.uvproj.tmpl
@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>mbed NXP LPC11U35_501</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC11U35/501</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0xFFFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_64 -FS00 -FL010000)</FlashDriverDll>
+          <DeviceId>6506</DeviceId>
+          <RegisterFile>LPC11Uxx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC11Uxx\LPC11Uxx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC11Uxx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC11Uxx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>1</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ELFDWT.EXE "!L"</UserProg1Name>
+            <UserProg2Name>fromelf --bin -o {{name}}_LPC11U35_501.bin build\{{name}}.axf</UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>0</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>13</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4104</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\CMSIS_AGDI.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20004000</StartAddress>
+                <Size>0x800</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py
index fed903ae85..32b1cd6b4e 100644
--- a/workspace_tools/export_test.py
+++ b/workspace_tools/export_test.py
@@ -114,6 +114,8 @@ if __name__ == '__main__':
 
             ('uvision', 'LPC1768'),
             ('uvision', 'LPC11U24'),
+            ('uvision', 'LPC11U35_401'),
+            ('uvision', 'LPC11U35_501'),
             ('uvision', 'KL25Z'),
             ('uvision', 'LPC1347'),
             ('uvision', 'LPC1114'),

From 6076b3a49b2109feebc4020ddcf5fe6790940823 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Thu, 25 Feb 2016 14:01:36 +0000
Subject: [PATCH 36/78] Exporters -removal of iar_rz_a1h template

---
 workspace_tools/export/iar_rz_a1h.ewd.tmpl | 2733 --------------------
 workspace_tools/export/iar_rz_a1h.ewp.tmpl | 1840 -------------
 2 files changed, 4573 deletions(-)
 delete mode 100644 workspace_tools/export/iar_rz_a1h.ewd.tmpl
 delete mode 100644 workspace_tools/export/iar_rz_a1h.ewp.tmpl

diff --git a/workspace_tools/export/iar_rz_a1h.ewd.tmpl b/workspace_tools/export/iar_rz_a1h.ewd.tmpl
deleted file mode 100644
index baa751f071..0000000000
--- a/workspace_tools/export/iar_rz_a1h.ewd.tmpl
+++ /dev/null
@@ -1,2733 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>6</version>
-          <state>5</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkScriptFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkUsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCTcpIpAlt</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTcpIpSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
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-        <option>
-          <name>OCJLinkTraceSource</name>
-          <state>0</state>
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-        <option>
-          <name>OCJLinkTraceSourceDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkDeviceName</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCMacraigorInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroInterfaceList</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
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-        <option>
-          <name>CCJPEMicroShowSettings</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCPEMicroUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCPEMicroSerialPort</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
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-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
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-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
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-          <state>###Uninitialized###</state>
-        </option>
-        <option>
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-        </option>
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-          <name>CThirdPartyLogFileEditB</name>
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-        <option>
-          <name>OCDriverInfo</name>
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-    <settings>
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-        <debug>1</debug>
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-          <state>1</state>
-        </option>
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-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
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-        <option>
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-          <version>2</version>
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-        <option>
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-          <state></state>
-        </option>
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-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
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-    <debuggerPlugins>
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-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
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-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
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-        <option>
-          <name>CCMacraigorHWResetDelay</name>
-          <state></state>
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-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
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-        <option>
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-      </data>
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-      <name>PEMICRO_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCPEMicroAttachSlave</name>
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-        <option>
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-          <state>0</state>
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-          <name>CCPEMicroResetDelay</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCPEMicroJtagSpeed</name>
-          <state>#UNINITIALIZED#</state>
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-        <option>
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-        <option>
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-          <name>CCPEMicroUSBDevice</name>
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-          <name>CCPEMicroSerialPort</name>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCPEMicroTCPIP</name>
-          <state>10.0.0.1</state>
-        </option>
-        <option>
-          <name>CCPEMicroCommCmdLineProducer</name>
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-        <option>
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-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
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-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
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-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
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-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
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-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceList</name>
-          <version>2</version>
-          <state>0</state>
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-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
-
diff --git a/workspace_tools/export/iar_rz_a1h.ewp.tmpl b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
deleted file mode 100644
index 6a9dbe0950..0000000000
--- a/workspace_tools/export/iar_rz_a1h.ewp.tmpl
+++ /dev/null
@@ -1,1840 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-          <name>ExePath</name>
-          <state>Debug\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-        <option>
-          <name>ListPath</name>
-          <state>Debug\List</state>
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-        <option>
-          <name>Variant</name>
-          <version>19</version>
-          <state>37</state>
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-          <name>GEndianMode</name>
-          <state>0</state>
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-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
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-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
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-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>1</state>
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-        <option>
-          <name>Output description</name>
-          <state>Full formatting.</state>
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-          <name>GOutputBinary</name>
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-          <name>FPU</name>
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-          <name>OGCoreOrChip</name>
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-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
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-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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-          <state>0</state>
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-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>R7S721001	Renesas R7S721001</state>
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-          <name>GenLowLevelInterface</name>
-          <state>0</state>
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-          <name>GEndianModeBE</name>
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-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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-          <state>0</state>
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-        <option>
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-        {% for path in include_paths %}
-          <state>$PROJ_DIR$\{{path}}</state>
-        {% endfor %}
-          <state></state>
-        </option>
-        <option>
-          <name>CCStdIncCheck</name>
-          <state>0</state>
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-        <option>
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-          <state>3</state>
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-        <option>
-          <name>ALimitErrorsCheck</name>
-          <state>0</state>
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-        <option>
-          <name>ALimitErrorsEdit</name>
-          <state>100</state>
-        </option>
-        <option>
-          <name>AIgnoreStdInclude</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>AUserIncludes</name>
-          <state></state>
-        </option>
-        <option>
-          <name>AExtraOptionsCheckV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AExtraOptionsV2</name>
-          <state></state>
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-      </data>
-    </settings>
-    <settings>
-      <name>OBJCOPY</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OOCOutputFormat</name>
-          <version>2</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCOutputOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OOCOutputFile</name>
-          <state>5.srec</state>
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-        <option>
-          <name>OOCCommandLineProducer</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OOCObjCopyEnable</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>CUSTOM</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <extensions></extensions>
-        <cmdline></cmdline>
-      </data>
-    </settings>
-    <settings>
-      <name>BICOMP</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-    <settings>
-      <name>BUILDACTION</name>
-      <archiveVersion>1</archiveVersion>
-      <data>
-        <prebuild></prebuild>
-        <postbuild></postbuild>
-      </data>
-    </settings>
-    <settings>
-      <name>ILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>14</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>IlinkOutputFile</name>
-          <state>cpp.out</state>
-        </option>
-        <option>
-          <name>IlinkLibIOConfig</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>XLinkMisraHandler</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkInputFileSlave</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkDebugInfoEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkKeepSymbols</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySymbol</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--skip_dynamic_initialization</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
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-        </option>
-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlgo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state></state>
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-      </data>
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-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-  </configuration>
-  {{source_files}}
-</project>
-
-

From 5f2541c8aa9eecb14b29c6e24b18858bcc56e789 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Thu, 25 Feb 2016 14:02:08 +0000
Subject: [PATCH 37/78] Target + Exporters - progen data expansion by template
 for tools

Each target can specify own template. This is however not recommended for general use.
Each target should be supported by progendef, and well definied. However, as tools are
quickly changing, some targets add extra information which might not be supported, this
template expansion allows a target to temporary override default mbed tool template.

In this commit, we add RZ_A1H iar template. I experienced with never tools some breakage in
the templates, this might come handy, but repeat, please consider using the default template, and
contribute to progen or progendef which should contain fixes or support for newer targets/tools.
---
 workspace_tools/export/iar.py | 27 ++++++++++++++++-----------
 workspace_tools/targets.py    |  4 ++++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 07ec5fb7a4..3ba8e64b0c 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -47,19 +47,24 @@ class IAREmbeddedWorkbench(Exporter):
     def generate(self):
         """ Generates the project files """
         project_data = self.progen_get_project_data()
+        tool_specific = {}
         # Expand tool specific settings by IAR specific settings which are required
-        # by the mbed projects
-        tool_specific = {
-            'iar': {
-                # We currently don't use misc, template sets those for us
-                # 'misc': {
-                #     'cxx_flags': ['--no_rtti', '--no_exceptions'],
-                #     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
-                #     'ld_flags': ['--skip_dynamic_initialization'],
-                # },
-                'template': [os.path.join(os.path.dirname(__file__),  'iar_template.ewp.tmpl')],
+        try:
+            if TARGET_MAP[self.target].progen['iar']['template']:
+                tool_specific['iar'] = TARGET_MAP[self.target].progen['iar']
+        except KeyError:
+            # use default template
+            # by the mbed projects
+            tool_specific['iar'] = {
+                    # We currently don't use misc, template sets those for us
+                    # 'misc': {
+                    #     'cxx_flags': ['--no_rtti', '--no_exceptions'],
+                    #     'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'],
+                    #     'ld_flags': ['--skip_dynamic_initialization'],
+                    # },
+                    'template': [os.path.join(os.path.dirname(__file__),  'iar_template.ewp.tmpl')],
             }
-        }
+
         project_data['tool_specific'] = {}
         project_data['tool_specific'].update(tool_specific)
         self.progen_gen_file('iar_arm', project_data)
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index a2932865c3..cbdc9d4480 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -1762,6 +1762,10 @@ class RZ_A1H(Target):
         self.default_toolchain = "ARM"
         self.progen = {
             "target": "gr-peach",
+            "iar": {
+                # rewrite generic template, this device needs futher support for FPU in progendef
+                "template": [os.path.join(os.path.dirname(__file__), 'export', 'iar_rz_a1h.ewp.tmpl')],
+            }
         }
 
     def program_cycle_s(self):

From a64119fcbb465cb494bf2fd663de7b198f74303c Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Thu, 25 Feb 2016 16:05:08 +0000
Subject: [PATCH 38/78] Exporters IAR - rza1h template fix

---
 workspace_tools/export/iar_rz_a1h.ewp.tmpl | 972 +++++++++++++++++++++
 1 file changed, 972 insertions(+)
 create mode 100644 workspace_tools/export/iar_rz_a1h.ewp.tmpl

diff --git a/workspace_tools/export/iar_rz_a1h.ewp.tmpl b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
new file mode 100644
index 0000000000..8a74ba898c
--- /dev/null
+++ b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
@@ -0,0 +1,972 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
+        </option>
+        <option>
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+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlgo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <file>
+<name>$PROJ_DIR$/main.cpp</name>
+</file>
+<group>
+<name>env</name>
+<file>
+<name>$PROJ_DIR$/env\test_env.cpp</name>
+</file>
+</group>
+
+</project>
+

From 6eabf37d204314da9420e0baac396c614b15e4cd Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Thu, 25 Feb 2016 19:45:38 +0000
Subject: [PATCH 39/78] Exporter - rza iar template clean-up

This is not required for progen functionality, but better to have the template
clean from files and defines.
---
 workspace_tools/export/iar_rz_a1h.ewp.tmpl | 51 +---------------------
 1 file changed, 2 insertions(+), 49 deletions(-)

diff --git a/workspace_tools/export/iar_rz_a1h.ewp.tmpl b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
index 8a74ba898c..4d5338da84 100644
--- a/workspace_tools/export/iar_rz_a1h.ewp.tmpl
+++ b/workspace_tools/export/iar_rz_a1h.ewp.tmpl
@@ -165,42 +165,7 @@
         <option>
           <name>CCDefines</name>
           
-            <state>TARGET_RZ_A1H</state>
-          
-            <state>TARGET_MBRZA1H</state>
-          
-            <state>TARGET_FF_ARDUINO</state>
-          
-            <state>ARM_MATH_CA9</state>
-          
-            <state>__FPU_PRESENT</state>
-          
-            <state>TARGET_CORTEX_A</state>
-          
-            <state>TOOLCHAIN_IAR</state>
-          
-            <state>__MBED__=1</state>
-          
-            <state>TARGET_RENESAS</state>
-          
-            <state>TARGET_LIKE_MBED</state>
-          
-            <state>__MBED_CMSIS_RTOS_CA9</state>
-          
-            <state>MBED_USERNAME=Kojto</state>
-          
-            <state>TARGET_LIKE_CORTEX_A9</state>
-          
-            <state>__CMSIS_RTOS</state>
-          
-            <state>TARGET_A9</state>
-          
-            <state>MBED_BUILD_TIMESTAMP=1456409454.2</state>
-          
-            <state>__CORTEX_A9</state>
-          
-            <state>__EVAL</state>
-          
+            <state></state>
         </option>
         <option>
           <name>CCPreprocFile</name>
@@ -330,19 +295,7 @@
         <option>
           <name>CCIncludePath2</name>
         
-          <state>$PROJ_DIR$\.</state>
-        
-          <state>$PROJ_DIR$\env</state>
-        
-          <state>$PROJ_DIR$\mbed</state>
-        
-          <state>$PROJ_DIR$\mbed\TARGET_RZ_A1H</state>
-        
-          <state>$PROJ_DIR$\mbed\TARGET_RZ_A1H\TARGET_RENESAS</state>
-        
-          <state>$PROJ_DIR$\mbed\TARGET_RZ_A1H\TARGET_RENESAS\TARGET_RZ_A1H</state>
-        
-          <state>$PROJ_DIR$\mbed\TARGET_RZ_A1H\TOOLCHAIN_IAR</state>
+          <state></state>
         
         </option>
         <option>

From 3148d1009e9755c8b3a894d254c12604e604a455 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Thu, 25 Feb 2016 16:29:26 -0600
Subject: [PATCH 40/78] Adding the ability for tests to report they aren't
 supported on a target

---
 workspace_tools/build_api.py           | 11 +++++++---
 workspace_tools/test_api.py            | 28 +++++++++++++++++++-------
 workspace_tools/test_exporters.py      |  6 +++---
 workspace_tools/toolchains/__init__.py | 10 +++++++--
 workspace_tools/toolchains/gcc.py      |  3 +++
 workspace_tools/utils.py               |  2 ++
 6 files changed, 45 insertions(+), 15 deletions(-)

diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py
index 13335c2aec..3dca0adbae 100644
--- a/workspace_tools/build_api.py
+++ b/workspace_tools/build_api.py
@@ -25,7 +25,7 @@ from shutil import rmtree
 from os.path import join, exists, basename
 from time import time
 
-from workspace_tools.utils import mkdir, run_cmd, run_cmd_ext
+from workspace_tools.utils import mkdir, run_cmd, run_cmd_ext, NotSupportedException
 from workspace_tools.paths import MBED_TARGETS_PATH, MBED_LIBRARIES, MBED_API, MBED_HAL, MBED_COMMON
 from workspace_tools.targets import TARGET_NAMES, TARGET_MAP
 from workspace_tools.libraries import Library
@@ -139,13 +139,13 @@ def build_project(src_path, build_path, target, toolchain_name,
                 resources.inc_dirs.extend(inc_dirs)
             else:
                 resources.inc_dirs.append(inc_dirs)
-
         # Compile Sources
         for path in src_paths:
             src = toolchain.scan_resources(path)
             objects = toolchain.compile_sources(src, build_path, resources.inc_dirs)
             resources.objects.extend(objects)
 
+
         # Link Program
         res, needed_update = toolchain.link_program(resources, build_path, name)
 
@@ -162,7 +162,12 @@ def build_project(src_path, build_path, target, toolchain_name,
     except Exception, e:
         if report != None:
             end = time()
-            cur_result["result"] = "FAIL"
+
+            if isinstance(e, NotSupportedException):
+                cur_result["result"] = "NOT_SUPPORTED"
+            else:
+                cur_result["result"] = "FAIL"
+
             cur_result["elapsed_time"] = end - start
 
             toolchain_output = toolchain.get_output()
diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py
index 95bf1f8838..d80c0c3f07 100644
--- a/workspace_tools/test_api.py
+++ b/workspace_tools/test_api.py
@@ -44,6 +44,7 @@ from workspace_tools.tests import TEST_MAP
 from workspace_tools.paths import BUILD_DIR
 from workspace_tools.paths import HOST_TESTS
 from workspace_tools.utils import ToolException
+from workspace_tools.utils import NotSupportedException
 from workspace_tools.utils import construct_enum
 from workspace_tools.targets import TARGET_MAP
 from workspace_tools.test_db import BaseDBAccess
@@ -130,6 +131,7 @@ class SingleTestRunner(object):
     TEST_RESULT_NO_IMAGE = "NO_IMAGE"
     TEST_RESULT_MBED_ASSERT = "MBED_ASSERT"
     TEST_RESULT_BUILD_FAILED = "BUILD_FAILED"
+    TEST_RESULT_NOT_SUPPORTED = "NOT_SUPPORTED"
 
     GLOBAL_LOOPS_COUNT = 1  # How many times each test should be repeated
     TEST_LOOPS_LIST = []    # We redefine no.of loops per test_id
@@ -149,7 +151,8 @@ class SingleTestRunner(object):
                            "no_image" : TEST_RESULT_NO_IMAGE,
                            "end" : TEST_RESULT_UNDEF,
                            "mbed_assert" : TEST_RESULT_MBED_ASSERT,
-                           "build_failed" : TEST_RESULT_BUILD_FAILED
+                           "build_failed" : TEST_RESULT_BUILD_FAILED,
+                           "not_supproted" : TEST_RESULT_NOT_SUPPORTED
     }
 
     def __init__(self,
@@ -476,13 +479,23 @@ class SingleTestRunner(object):
                                      project_id=test_id,
                                      project_description=test.get_description())
 
-                except ToolException:
+                except Exception, e:
                     project_name_str = project_name if project_name is not None else test_id
-                    print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str))
+
+
+                    test_result = self.TEST_RESULT_FAIL
+
+                    if isinstance(e, ToolException):
+                        print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str))
+                        test_result = self.TEST_RESULT_BUILD_FAILED
+                    elif isinstance(e, NotSupportedException):
+                        print self.logger.log_line(self.logger.LogType.INFO, 'The project %s is not supported'% (project_name_str))
+                        test_result = self.TEST_RESULT_NOT_SUPPORTED
+
 
                     # Append test results to global test summary
                     self.test_summary.append(
-                        (self.TEST_RESULT_BUILD_FAILED, target, toolchain, test_id, 'Toolchain build failed', 0, 0, '-')
+                        (test_result, target, toolchain, test_id, test.get_description(), 0, 0, '-')
                     )
 
                     # Add detailed test result to test summary structure
@@ -490,13 +503,13 @@ class SingleTestRunner(object):
                         self.test_summary_ext[target][toolchain][test_id] = []
 
                     self.test_summary_ext[target][toolchain][test_id].append({ 0: {
-                        'result' : self.TEST_RESULT_BUILD_FAILED,
+                        'result' : test_result,
                         'output' : '',
                         'target_name' : target,
                         'target_name_unique': target,
                         'toolchain_name' : toolchain,
                         'id' : test_id,
-                        'description' : 'Toolchain build failed',
+                        'description' : test.get_description(),
                         'elapsed_time' : 0,
                         'duration' : 0,
                         'copy_method' : None
@@ -736,7 +749,8 @@ class SingleTestRunner(object):
                        self.TEST_RESULT_NO_IMAGE : 0,
                        self.TEST_RESULT_TIMEOUT : 0,
                        self.TEST_RESULT_MBED_ASSERT : 0,
-                       self.TEST_RESULT_BUILD_FAILED : 0
+                       self.TEST_RESULT_BUILD_FAILED : 0,
+                       self.TEST_RESULT_NOT_SUPPORTED : 0
         }
 
         for test in test_summary:
diff --git a/workspace_tools/test_exporters.py b/workspace_tools/test_exporters.py
index 014703d87d..623acd6f4d 100644
--- a/workspace_tools/test_exporters.py
+++ b/workspace_tools/test_exporters.py
@@ -238,7 +238,7 @@ class ReportExporter():
                     tc.add_failure_info(description, _stdout)
                 elif result == 'ERROR':
                     tc.add_error_info(description, _stdout)
-                elif result == 'SKIP':
+                elif result == 'SKIP' or result == 'NOT_SUPPORTED':
                     tc.add_skipped_info(description, _stdout)
 
                 test_cases.append(tc)
@@ -282,7 +282,7 @@ class ReportExporter():
                             message = test_result['result']
                             if test_result['result'] == 'FAIL':
                                 tc.add_failure_info(message, _stdout)
-                            elif test_result['result'] == 'SKIP':
+                            elif test_result['result'] == 'SKIP' or test_result["result"] == 'NOT_SUPPORTED':
                                 tc.add_skipped_info(message, _stdout)
                             elif test_result['result'] != 'OK':
                                 tc.add_error_info(message, _stdout)
@@ -319,7 +319,7 @@ class ReportExporter():
 
                         if test_run["result"] == "FAIL":
                             failures.append(test_run)
-                        elif test_run["result"] == "SKIP":
+                        elif test_run["result"] == "SKIP" or test_run["result"] == "NOT_SUPPORTED":
                             skips.append(test_run)
                         elif test_run["result"] == "OK":
                             successes.append(test_run)
diff --git a/workspace_tools/toolchains/__init__.py b/workspace_tools/toolchains/__init__.py
index 5b4d3942aa..d122fb72d1 100644
--- a/workspace_tools/toolchains/__init__.py
+++ b/workspace_tools/toolchains/__init__.py
@@ -26,7 +26,7 @@ from os.path import join, splitext, exists, relpath, dirname, basename, split
 from inspect import getmro
 
 from multiprocessing import Pool, cpu_count
-from workspace_tools.utils import run_cmd, mkdir, rel_path, ToolException, split_path
+from workspace_tools.utils import run_cmd, mkdir, rel_path, ToolException, NotSupportedException, split_path
 from workspace_tools.settings import BUILD_OPTIONS, MBED_ORG_USER
 import workspace_tools.hooks as hooks
 
@@ -604,6 +604,9 @@ class mbedToolchain:
 
         return None
 
+    def is_not_supported_error(self, output):
+        return "#error directive: [NOT_SUPPORTED]" in output
+
     def compile_output(self, output=[]):
         _rc = output[0]
         _stderr = output[1]
@@ -621,7 +624,10 @@ class mbedToolchain:
             for line in _stderr.splitlines():
                 self.tool_error(line)
 
-            raise ToolException(_stderr)
+            if self.is_not_supported_error(_stderr):
+                raise NotSupportedException(_stderr)
+            else:
+                raise ToolException(_stderr)
 
     def compile(self, cc, source, object, includes):
         _, ext = splitext(source)
diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py
index ec43c7fa5e..0f493cf7d3 100644
--- a/workspace_tools/toolchains/gcc.py
+++ b/workspace_tools/toolchains/gcc.py
@@ -118,6 +118,9 @@ class GCC(mbedToolchain):
                     dependencies = dependencies + [f.replace('\a', ' ') for f in file.split(" ")]
         return dependencies
 
+    def is_not_supported_error(self, output):
+        return "error: #error [NOT_SUPPORTED]" in output
+
     def parse_output(self, output):
         # The warning/error notification is multiline
         WHERE, WHAT = 0, 1
diff --git a/workspace_tools/utils.py b/workspace_tools/utils.py
index 14cc0a1eda..21f0e1496b 100644
--- a/workspace_tools/utils.py
+++ b/workspace_tools/utils.py
@@ -123,6 +123,8 @@ def rel_path(path, base, dot=False):
 class ToolException(Exception):
     pass
 
+class NotSupportedException(Exception):
+    pass
 
 def split_path(path):
     base, file = split(path)

From bee5cad5ef2917511dffe416d3426bc9131830d2 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Thu, 25 Feb 2016 18:29:38 -0600
Subject: [PATCH 41/78] Remove IAR from all NRF51822-based targets

---
 workspace_tools/targets.py | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index cbdc9d4480..568c001d66 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -1214,7 +1214,7 @@ class MCU_NRF51(Target):
         self.core = "Cortex-M0"
         self.extra_labels = ["NORDIC", "MCU_NRF51", "MCU_NRF51822"]
         self.macros = ['NRF51', 'TARGET_NRF51822']
-        self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"]
+        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.is_disk_virtual = True
         self.detect_code = ["1070"]
 
@@ -1222,12 +1222,12 @@ class MCU_NRF51(Target):
         return 6
 
     def init_hooks(self, hook, toolchain_name):
-        if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM', 'IAR']:
+        if toolchain_name in ['ARM_STD', 'GCC_ARM']:
             hook.hook_add_binary("post", self.binary_hook)
 
     @staticmethod
     def binary_hook(t_self, resources, elf, binf):
-    
+
         # Scan to find the actual paths of soft device
         sdf = None
         for softdeviceAndOffsetEntry in t_self.target.EXPECTED_SOFTDEVICES_WITH_OFFSETS:
@@ -1242,7 +1242,7 @@ class MCU_NRF51(Target):
         if sdf is None:
             t_self.debug("Hex file not found. Aborting.")
             return
-            
+
         # Look for bootloader file that matches this soft device or bootloader override image
         blf = None
         if t_self.target.MERGE_BOOTLOADER is True:
@@ -1274,7 +1274,7 @@ class MCU_NRF51(Target):
         with open(binf.replace(".bin", ".hex"), "w") as f:
             binh.tofile(f, format='hex')
 
-            
+
 # 16KB Nordic targets are tight on SRAM using S130 (default) so we
 # introduce two possible options:
 # 1) Use S130 (default) - for this derive from MCU_NRF51_16K
@@ -1551,7 +1551,6 @@ class WALLBOT_BLE_OTA(MCU_NRF51_16K_OTA):
 class DELTA_DFCM_NNN40(MCU_NRF51_32K):
     def __init__(self):
         MCU_NRF51_32K.__init__(self)
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.macros += ['TARGET_NRF_LFCLK_RC']
         self.progen = {
             "target":"dfcm-nnn40",
@@ -1562,7 +1561,6 @@ class DELTA_DFCM_NNN40(MCU_NRF51_32K):
 class DELTA_DFCM_NNN40_BOOT(MCU_NRF51_32K_BOOT):
     def __init__(self):
         MCU_NRF51_32K_BOOT.__init__(self)
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.extra_labels += ['DELTA_DFCM_NNN40']
         self.macros += ['TARGET_DELTA_DFCM_NNN40', 'TARGET_NRF_LFCLK_RC']
     def program_cycle_s(self):
@@ -1571,7 +1569,6 @@ class DELTA_DFCM_NNN40_BOOT(MCU_NRF51_32K_BOOT):
 class DELTA_DFCM_NNN40_OTA(MCU_NRF51_32K_OTA):
     def __init__(self):
         MCU_NRF51_32K_OTA.__init__(self)
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.extra_labels += ['DELTA_DFCM_NNN40']
         self.macros += ['TARGET_DELTA_DFCM_NNN40', 'TARGET_NRF_LFCLK_RC']
     def program_cycle_s(self):
@@ -1580,7 +1577,6 @@ class DELTA_DFCM_NNN40_OTA(MCU_NRF51_32K_OTA):
 class NRF51_DK(MCU_NRF51_32K):
     def __init__(self):
         MCU_NRF51_32K.__init__(self)
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.supported_form_factors = ["ARDUINO"]
         self.progen = {
             "target":"nrf51-dk",
@@ -1591,7 +1587,6 @@ class NRF51_DK_BOOT(MCU_NRF51_32K_BOOT):
         MCU_NRF51_32K_BOOT.__init__(self)
         self.extra_labels += ['NRF51_DK']
         self.macros += ['TARGET_NRF51_DK']
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.supported_form_factors = ["ARDUINO"]
 
 class NRF51_DK_OTA(MCU_NRF51_32K_OTA):
@@ -1599,7 +1594,6 @@ class NRF51_DK_OTA(MCU_NRF51_32K_OTA):
         MCU_NRF51_32K_OTA.__init__(self)
         self.extra_labels += ['NRF51_DK']
         self.macros += ['TARGET_NRF51_DK']
-        self.supported_toolchains = ["ARM", "GCC_ARM"]
         self.supported_form_factors = ["ARDUINO"]
 
 class NRF51_DONGLE(MCU_NRF51_32K):
@@ -1676,7 +1670,7 @@ class TY51822R3_OTA(MCU_NRF51_32K_OTA):
         self.macros += ['TARGET_TY51822R3', 'TARGET_NRF_32MHZ_XTAL']
         self.supported_toolchains = ["ARM", "GCC_ARM"]
 
-        
+
 ### ARM ###
 
 class ARM_MPS2_Target(Target):
@@ -1736,7 +1730,7 @@ class ARM_MPS2_M7(ARM_MPS2_Target):
         self.macros = ['CMSDK_CM7']
         self.supported_toolchains = ["ARM"]
         self.default_toolchain = "ARM"
-        
+
 class ARM_MPS2_BEID(ARM_MPS2_Target):
     def __init__(self):
         ARM_MPS2_Target.__init__(self)
@@ -1783,7 +1777,7 @@ class MAXWSNENV(Target):
         self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"]
         self.default_toolchain = "ARM"
         self.progen = {
-            "target": "maxwsnenv", 
+            "target": "maxwsnenv",
         }
 
 class MAX32600MBED(Target):
@@ -1795,7 +1789,7 @@ class MAX32600MBED(Target):
         self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"]
         self.default_toolchain = "ARM"
         self.progen = {
-            "target": "max32600mbed", 
+            "target": "max32600mbed",
         }
 
 ### Silicon Labs ###
@@ -1886,7 +1880,7 @@ class WIZWIKI_W7500ECO(Target):
         self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500ECO']
         self.supported_toolchains = ["uARM", "ARM"]
         self.default_toolchain = "ARM"
-		
+
 class SAMR21G18A(Target):
     def __init__(self):
         Target.__init__(self)

From 1535bf2874b670c58e227b95f67a88272013dfde Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 15 Jan 2016 17:34:57 +0100
Subject: [PATCH 42/78] [NUCLEO_F746ZG] support rtos for this new target

---
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h  | 2 +-
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
index e6e754b883..3fe584ae10 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
@@ -310,7 +310,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
 #elif defined(TARGET_STM32F303K8)
 #define INITIAL_SP            (0x20003000UL)
 
-#elif defined(TARGET_STM32F746NG)
+#elif (defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG))
 #define INITIAL_SP            (0x20050000UL)
 
 #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
index d73002c179..70ac3c2f16 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
@@ -52,7 +52,7 @@
 #  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
    || defined(TARGET_STM32F410RB) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z)  || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
    || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) \
-   || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32L152RC)
+   || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC)
 #    define OS_TASKCNT         14
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL26Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
@@ -70,7 +70,7 @@
 #  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347)  || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
    || defined(TARGET_STM32F410RB) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
    || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) \
-   || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32L152RC)
+   || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC)
 #      define OS_SCHEDULERSTKSIZE    256
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)  || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL26Z)        || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
@@ -178,7 +178,7 @@
 #elif defined(TARGET_STM32F401VC)
 #    define OS_CLOCK       84000000
 
-#  elif defined(TARGET_STM32F746NG)
+#  elif defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG)
 #     define OS_CLOCK      216000000
 
 #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)

From c6e57e50a0e6498527acff56d73ac2dff2ed8bba Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 15 Jan 2016 17:49:24 +0100
Subject: [PATCH 43/78] [NUCLEO_F746ZG] Add new target to hal files

---
 .../TARGET_NUCLEO_F746ZG/PeripheralNames.h    |  99 ++++++
 .../TARGET_NUCLEO_F746ZG/PeripheralPins.c     | 327 ++++++++++++++++++
 .../TARGET_NUCLEO_F746ZG/PinNames.h           | 260 ++++++++++++++
 .../TARGET_NUCLEO_F746ZG/PortNames.h          |  54 +++
 .../TARGET_NUCLEO_F746ZG/device.h             |  70 ++++
 .../TARGET_NUCLEO_F746ZG/objects.h            | 119 +++++++
 6 files changed, 929 insertions(+)
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
new file mode 100644
index 0000000000..48a340330f
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    UART_6 = (int)USART6_BASE,
+    UART_7 = (int)UART7_BASE,
+    UART_8 = (int)UART8_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_9
+#define STDIO_UART_RX  PB_7
+#define STDIO_UART     UART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE,
+    SPI_4 = (int)SPI4_BASE,
+    SPI_5 = (int)SPI5_BASE,
+    SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE,
+    I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE,
+    PWM_12 = (int)TIM12_BASE,
+    PWM_13 = (int)TIM13_BASE,
+    PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
new file mode 100644
index 0000000000..695b9028e1
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
@@ -0,0 +1,327 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =============================================================================
+// Notes:
+// * Commented lines are alternative possibilities which are not used per default.
+//   If you change them, you will have also to modify the corresponding xxx_api.c file
+//   for pwmout, analogin, analogout, ...
+// * Only the pins that are placed on the Arduino connector are described.
+// =============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0  - ARDUINO A0
+ // {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1  (used by ethernet)
+ // {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2  (used by ethernet)
+    {PA_3,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+    {PA_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+    {PA_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5  - ARDUINO D13
+    {PA_6,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6  - ARDUINO D12
+    {PA_7,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (JP6) - ARDUINO D11
+ // {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (used by LED1)
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,10, 0)}, // ADC1_IN10 - ARDUINO A1
+ // {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,11, 0)}, // ADC1_IN11 (used by ethernet)
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC1_IN12
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,13, 0)}, // ADC1_IN13 - ARDUINO A2
+ // {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,14, 0)}, // ADC1_IN14 (used by ethernet)
+ // {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,15, 0)}, // ADC1_IN15 (used by ethernet)
+
+    {PF_3,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9  - ARDUINO A3
+    {PF_4,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,14, 0)}, // ADC3_IN14
+    {PF_5,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,15, 0)}, // ADC3_IN15 - ARDUINO A4
+    {PF_6,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+    {PF_7,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+    {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+    {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+    {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    // {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // (used by LED2)
+       {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+       {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+       {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+       {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+       {PF_0,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+       {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+       {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PF_1,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  1, 0)}, // TIM2_CH1
+ // {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5,  1, 0)}, // TIM5_CH1 (used by us_ticker)
+ // {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  2, 0)}, // TIM2_CH2 (used by ethernet)
+ // {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5,  2, 0)}, // TIM5_CH2 (used by ethernet & us_ticker)
+ // {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  3, 0)}, // TIM2_CH3 (used by ethernet)
+ // {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5,  3, 0)}, // TIM5_CH3 (used by ethernet & us_ticker)
+ // {PA_2,  PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9,  1, 0)}, // TIM9_CH1 (used by ethernet)
+    {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  4, 0)}, // TIM2_CH4
+ // {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5,  4, 0)}, // TIM5_CH4 (used by us_ticker)
+ // {PA_3,  PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9,  2, 0)}, // TIM9_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  1, 0)}, // TIM2_CH1
+ // {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 1)}, // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1
+ // {PA_6,  PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+    {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 1)}, // TIM1_CH1N (remove JP6 to use it)
+ // {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2  (remove JP6 to use it)
+ // {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 1)}, // TIM8_CH1N (remove JP6 to use it)
+ // {PA_7,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (remove JP6 to use it)
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 0)}, // TIM1_CH1
+ // {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 0)}, // TIM1_CH2 (used by USB)
+ // {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 0)}, // TIM1_CH3 (used by USB)
+ // {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  4, 0)}, // TIM1_CH4 (used by USB)
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  1, 0)}, // TIM2_CH1
+
+ // {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 1)}, // TIM1_CH2N (used by LED1)
+ // {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  3, 0)}, // TIM3_CH3
+ // {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  2, 1)}, // TIM8_CH2N
+    {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 1)}, // TIM1_CH3N
+ // {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  4, 0)}, // TIM3_CH4
+ // {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  3, 1)}, // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  2, 0)}, // TIM2_CH2
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  1, 0)}, // TIM4_CH1
+ // {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  2, 0)}, // TIM4_CH2 (used by LED2)
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  3, 0)}, // TIM4_CH3
+//  {PB_8,  PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  4, 0)}, // TIM4_CH4
+//  {PB_9,  PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  3, 0)}, // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2,  4, 0)}, // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 1)}, // TIM1_CH1N (remove JP7 to use it)
+ // {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 1)}, // TIM1_CH2N (used by LED3)
+ // {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  2, 1)}, // TIM8_CH2N (used by LED3)
+ // {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 (used by LED3)
+ // {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 1)}, // TIM1_CH3N
+ // {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  3, 1)}, // TIM8_CH3N
+    {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+
+ // {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 0)}, // TIM8_CH1
+ // {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  2, 0)}, // TIM8_CH2
+ // {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  3, 0)}, // TIM3_CH3
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  3, 0)}, // TIM8_CH3
+ // {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  4, 0)}, // TIM3_CH4
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  4, 0)}, // TIM8_CH4
+
+    {PD_12, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  1, 0)}, // TIM4_CH1
+    {PD_13, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  2, 0)}, // TIM4_CH2
+    {PD_14, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  3, 0)}, // TIM4_CH3
+    {PD_15, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  4, 0)}, // TIM4_CH4
+
+    {PE_5,  PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9,  1, 0)}, // TIM9_CH1
+    {PE_6,  PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9,  2, 0)}, // TIM9_CH2
+    {PE_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 1)}, // TIM1_CH1N
+    {PE_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 0)}, // TIM1_CH1
+    {PE_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 1)}, // TIM1_CH2N
+    {PE_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 0)}, // TIM1_CH2
+    {PE_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 1)}, // TIM1_CH3N
+    {PE_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 0)}, // TIM1_CH3
+
+    {PF_6,  PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+    {PF_7,  PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+    {PF_8,  PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+    {PF_9,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ // {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},  // (used by ethernet)
+ // {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ // {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)},
+    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PD_8,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_TX
+
+    {PE_1,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)},
+    {PE_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+
+    {PF_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    // {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},  // (used by ethernet)
+       {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)}, // ARDUINO A0
+    // {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
+    // {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by LED2)
+       {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+       {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+       {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    // {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+       {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)},
+       {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+       {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_RX
+
+       {PE_0,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)},
+       {PE_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+
+       {PF_6,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+
+       {PG_9,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D0
+       {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ // {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},  // (used by ethernet)
+ // {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
+    {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART4)},
+ // {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (used by LED3)
+    {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART5)},
+    {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)}, // ARDUINO D9
+    {PE_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)}, // ARDUINO D6
+    {PF_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PG_8,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+ // {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
+ // {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART4)}, // (used by LED1)
+    {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (remove JP7 to use it)
+    {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART5)},
+    {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)}, // ARDUINO D10
+    {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+    {PF_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (remove JP6 to use it)
+    {PB_2,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ // {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ // {PC_1,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by Ethernet)
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PD_6,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+    {PE_6,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PF_9,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+    {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+    {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // ARDUINO D1
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ // {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ // {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by LED3)
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PE_5,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // ARDUINO D3
+    {PF_8,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+    {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D13
+ // {PA_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by USB)
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ // {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (remove JP7 to use it)
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PD_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PE_2,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PF_7,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by Ethernet)
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ // {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_4,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D14
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PE_4,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // ARDUINO D5
+    {PF_6,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+    {NC,    NC,    0}
+};
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h
new file mode 100644
index 0000000000..4f5e0120ee
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h
@@ -0,0 +1,260 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
+                                                ((PUPD  & 0x07) << 4) |\
+                                                ((AFNUM & 0x0F) << 7)))
+
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
+                                                                       ((PUPD     & 0x07) <<  4) |\
+                                                                       ((AFNUM    & 0x0F) <<  7) |\
+                                                                       ((CHANNEL  & 0x0F) << 11) |\
+                                                                       ((INVERTED & 0x01) << 15)))
+
+#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
+#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
+#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
+#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+
+#define STM_MODE_INPUT              (0)
+#define STM_MODE_OUTPUT_PP          (1)
+#define STM_MODE_OUTPUT_OD          (2)
+#define STM_MODE_AF_PP              (3)
+#define STM_MODE_AF_OD              (4)
+#define STM_MODE_ANALOG             (5)
+#define STM_MODE_IT_RISING          (6)
+#define STM_MODE_IT_FALLING         (7)
+#define STM_MODE_IT_RISING_FALLING  (8)
+#define STM_MODE_EVT_RISING         (9)
+#define STM_MODE_EVT_FALLING        (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET       (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PF_0  = 0x50,
+    PF_1  = 0x51,
+    PF_2  = 0x52,
+    PF_3  = 0x53,
+    PF_4  = 0x54,
+    PF_5  = 0x55,
+    PF_6  = 0x56,
+    PF_7  = 0x57,
+    PF_8  = 0x58,
+    PF_9  = 0x59,
+    PF_10 = 0x5A,
+    PF_11 = 0x5B,
+    PF_12 = 0x5C,
+    PF_13 = 0x5D,
+    PF_14 = 0x5E,
+    PF_15 = 0x5F,
+
+    PG_0  = 0x60,
+    PG_1  = 0x61,
+    PG_2  = 0x62,
+    PG_3  = 0x63,
+    PG_4  = 0x64,
+    PG_5  = 0x65,
+    PG_6  = 0x66,
+    PG_7  = 0x67,
+    PG_8  = 0x68,
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    PG_15 = 0x6F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // Arduino connector namings
+    A0          = PA_3,
+    A1          = PC_0,
+    A2          = PC_3,
+    A3          = PF_3,
+    A4          = PF_5,
+    A5          = PF_10,
+    D0          = PG_9,
+    D1          = PG_14,
+    D2          = PF_15,
+    D3          = PE_13,
+    D4          = PF_14,
+    D5          = PE_11,
+    D6          = PE_9,
+    D7          = PF_13,
+    D8          = PF_12,
+    D9          = PD_15,
+    D10         = PD_14,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PB_0,  // LD1 = GREEN
+    LED2        = PB_7,  // Blue
+    LED3        = PB_14, // Red
+    LED4        = PB_0,
+    USER_BUTTON = PC_13,
+    SERIAL_TX   = PD_8, // Virtual Com Port
+    SERIAL_RX   = PD_9, // Virtual Com Port
+    USBTX       = PD_8, // Virtual Com Port
+    USBRX       = PD_9, // Virtual Com Port
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone  = 0,
+    PullUp    = 1,
+    PullDown  = 2,
+    OpenDrain = 3,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
new file mode 100644
index 0000000000..f7d2f9076d
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5,
+    PortG = 6,
+    PortH = 7,
+//    PortI = 8,
+//    PortJ = 9,
+//    PortK = 10
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
new file mode 100644
index 0000000000..73525825f7
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SLEEP            1
+
+//=======================================
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       24
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        0
+
+#include "objects.h"
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
new file mode 100644
index 0000000000..b5beed24ba
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+    uint8_t channel;
+};
+
+struct dac_s {
+    DACName dac;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+#if DEVICE_SERIAL_FC
+    uint32_t hw_flow_ctl;
+    PinName pin_rts;
+    PinName pin_cts;
+#endif
+};
+
+struct spi_s {
+    SPIName spi;
+    uint32_t bits;
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t nss;
+    uint32_t br_presc;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+};
+
+struct i2c_s {
+    I2CName  i2c;
+    uint32_t slave;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    PinName pin;
+    uint32_t period;
+    uint32_t pulse;
+    uint8_t channel;
+    uint8_t inverted;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

From a7ed768eef865bb00ad68c931c2cb3c350a1a8d8 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 18 Jan 2016 11:12:30 +0100
Subject: [PATCH 44/78] [NUCLEO_F746ZG] new target

---
 workspace_tools/targets.py | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index cbdc9d4480..1dcca62622 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -841,6 +841,15 @@ class B96B_F446VE(Target):
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0840"]
 
+class NUCLEO_F746ZG(Target):
+    def __init__(self):
+        Target.__init__(self)
+        self.core = "Cortex-M7F"
+        self.extra_labels = ['STM', 'STM32F7', 'STM32F746', 'STM32F746ZG']
+        self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
+        self.detect_code = ["0816"]
+        self.progen_target ='nucleo-f746zg'
+
 class NUCLEO_L053R8(Target):
     def __init__(self):
         Target.__init__(self)
@@ -2002,6 +2011,7 @@ TARGETS = [
     NUCLEO_F401RE(),
     NUCLEO_F410RB(),
     NUCLEO_F411RE(),
+    NUCLEO_F746ZG(),
     ELMO_F411RE(),
     NUCLEO_F446RE(),
     NUCLEO_L053R8(),

From 252056c17d6aaaa41496e0f0dec25f33f45747ef Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 18 Jan 2016 11:15:12 +0100
Subject: [PATCH 45/78] [NUCLEO_F746ZG] HAL Files

---
 .../TARGET_NUCLEO_F746ZG/PeripheralNames.h    |  6 +--
 .../TARGET_NUCLEO_F746ZG/PeripheralPins.c     | 38 +++++++++----------
 .../TARGET_NUCLEO_F746ZG/PortNames.h          |  6 +--
 .../TARGET_NUCLEO_F746ZG/device.h             |  1 +
 4 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
index 48a340330f..819b12e8fc 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
@@ -57,9 +57,9 @@ typedef enum {
     UART_8 = (int)UART8_BASE
 } UARTName;
 
-#define STDIO_UART_TX  PA_9
-#define STDIO_UART_RX  PB_7
-#define STDIO_UART     UART_1
+#define STDIO_UART_TX  PD_8
+#define STDIO_UART_RX  PD_9
+#define STDIO_UART     UART_3
 
 typedef enum {
     SPI_1 = (int)SPI1_BASE,
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
index 695b9028e1..04a8d7ebae 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
@@ -195,12 +195,12 @@ const PinMap PinMap_UART_TX[] = {
     {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
  // {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)},
-    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PD_8,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_TX
 
-    {PE_1,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)},
-    {PE_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+    {PE_1,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+    {PE_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
 
     {PF_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
     {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1
@@ -209,19 +209,19 @@ const PinMap PinMap_UART_TX[] = {
 
 const PinMap PinMap_UART_RX[] = {
     // {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},  // (used by ethernet)
-       {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)}, // ARDUINO A0
+       {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO A0
     // {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
     // {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by LED2)
        {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
        {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
        {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     // {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-       {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)},
-       {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+       {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+       {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
        {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_RX
 
-       {PE_0,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)},
-       {PE_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+       {PE_0,  UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+       {PE_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
 
        {PF_6,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
 
@@ -232,13 +232,13 @@ const PinMap PinMap_UART_RX[] = {
 const PinMap PinMap_UART_RTS[] = {
  // {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},  // (used by ethernet)
  // {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
-    {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART4)},
+    {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
  // {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (used by LED3)
-    {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART5)},
-    {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+    {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)}, // ARDUINO D9
-    {PE_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)}, // ARDUINO D6
+    {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // ARDUINO D9
+    {PE_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // ARDUINO D6
     {PF_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
     {PG_8,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
@@ -246,15 +246,15 @@ const PinMap PinMap_UART_RTS[] = {
 };
 
 const PinMap PinMap_UART_CTS[] = {
-    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
  // {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb)
  // {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART4)}, // (used by LED1)
     {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (remove JP7 to use it)
-    {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART5)},
-    {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)},
+    {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+    {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART8)}, // ARDUINO D10
-    {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART7)},
+    {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // ARDUINO D10
+    {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
     {PF_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
     {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
index f7d2f9076d..e875a51cdc 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
@@ -43,9 +43,9 @@ typedef enum {
     PortF = 5,
     PortG = 6,
     PortH = 7,
-//    PortI = 8,
-//    PortJ = 9,
-//    PortK = 10
+    PortI = 8, // kept for compilation
+    PortJ = 9, // kept for compilation
+    PortK = 10 // kept for compilation
 } PortName;
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
index 73525825f7..a16c172165 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h
@@ -40,6 +40,7 @@
 #define DEVICE_ANALOGOUT        1
 
 #define DEVICE_SERIAL           1
+#define DEVICE_SERIAL_FC        0
 
 #define DEVICE_I2C              1
 #define DEVICE_I2CSLAVE         1

From 809afe780286392a7118ed2c1453e1c167d09fd9 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 18 Jan 2016 11:15:51 +0100
Subject: [PATCH 46/78] [NUCLEO_F746ZG] cmsis files

---
 .../TARGET_NUCLEO_F746ZG/cmsis.h              |   38 +
 .../TARGET_NUCLEO_F746ZG/cmsis_nvic.c         |   55 +
 .../TARGET_NUCLEO_F746ZG/cmsis_nvic.h         |   54 +
 .../TARGET_NUCLEO_F746ZG/hal_tick.c           |  140 +
 .../TARGET_NUCLEO_F746ZG/hal_tick.h           |   62 +
 .../TARGET_NUCLEO_F746ZG/stm32f746xx.h        | 9445 +++++++++++++++++
 .../TARGET_NUCLEO_F746ZG/stm32f7xx.h          |  197 +
 .../TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h |  421 +
 .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.c   |  709 ++
 .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.h   |  123 +
 10 files changed, 11244 insertions(+)
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.c
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.c
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis.h
new file mode 100644
index 0000000000..ee3ba9007b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f7xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.c
new file mode 100644
index 0000000000..69a0fa5832
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.h
new file mode 100644
index 0000000000..0a26d73682
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7
+// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+#define NVIC_NUM_VECTORS      114
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.c
new file mode 100644
index 0000000000..e21ca156ae
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.c
@@ -0,0 +1,140 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+// 0=NO, 1=PG6 toggles at each tick
+#define DEBUG_TICK 0
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void HAL_IncTick(void);
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+        us_ticker_irq_handler();
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+            // Increment HAL variable
+            HAL_IncTick();
+            // Prepare next interrupt
+            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+            PreviousVal = val;
+#if DEBUG_TICK > 0
+            HAL_GPIO_TogglePin(GPIOG, GPIO_PIN_6);
+#endif
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    uint32_t PclkFreq;
+
+    // Get clock configuration
+    // Note: PclkFreq contains here the Latency (not used after)
+    HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+    // Get TIM5 clock value
+    PclkFreq = HAL_RCC_GetPCLK1Freq();
+
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period = 0xFFFFFFFF;
+
+    // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+    if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1)
+      TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick
+    else
+      TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick  
+
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    TimMasterHandle.Init.RepetitionCounter = 0;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if DEBUG_TICK > 0
+    __GPIOG_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.h
new file mode 100644
index 0000000000..6501819b5d
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/hal_tick.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f7xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
new file mode 100644
index 0000000000..a510fb023c
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
@@ -0,0 +1,9445 @@
+/**
+  ******************************************************************************
+  * @file    stm32f746xx.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    25-June-2015
+  * @brief   CMSIS STM32F746xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f746xx
+  * @{
+  */
+    
+#ifndef __STM32F746xx_H
+#define __STM32F746xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97      /*!< SPDIF-RX global Interrupt                                         */  
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/**
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
+ */
+#define __CM7_REV                 0x0000   /*!< Cortex-M7 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals      */
+  
+  
+#include "system_stm32f7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
+  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
+  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+ 
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef; 
+
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;  
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+  
+typedef struct
+{  
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                              Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
+  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
+  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;   /*!< Reserved  */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */  
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */ 
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
+} QUADSPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
+
+} TIM_TypeDef;
+
+/** 
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;       /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */                                               
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
+} USB_OTG_DeviceTypeDef;
+
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define RAMITCM_BASE           ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM   */
+#define FLASHITCM_BASE         ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory  accessible over ITCM               */                       
+#define FLASHAXI_BASE          ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */                       
+#define RAMDTCM_BASE           ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
+#define SRAM1_BASE             ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
+#define PERIPH_BASE            ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals                                                   */
+#define BKPSRAM_BASE           ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB)                                                     */
+#define QSPI_BASE              ((uint32_t)0x90000000) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+#define FMC_R_BASE             ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers                                                 */
+#define QSPI_R_BASE            ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control  registers                                               */
+#define FLASH_END              ((uint32_t)0x080FFFFF) /*!< FLASH end address */
+
+/* Legacy define */
+#define FLASH_BASE     FLASHAXI_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
+#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE) 
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!<Analog watchdog flag                                 */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!<End of conversion                                    */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!<Injected channel end of conversion                   */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!<Injected channel Start flag                          */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!<Regular channel Start flag                           */
+#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!<Overrun flag                                         */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                             */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                    */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels               */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                  */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels               */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels              */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels          */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels           */
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                           */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF                                       */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion                                        */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode                                    */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC)                           */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection                                  */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                                               */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag               */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion                  */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag        */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag         */
+#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag                  */
+#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag               */
+#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion                  */
+#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag        */
+#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag         */
+#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag                  */
+#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag               */
+#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion                  */
+#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag        */
+#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag         */
+#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag                  */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001)        /*!<Initialization Request            */
+#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002)        /*!<Sleep Mode Request                */
+#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004)        /*!<Transmit FIFO Priority            */
+#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008)        /*!<Receive FIFO Locked Mode          */
+#define  CAN_MCR_NART                        ((uint32_t)0x00000010)        /*!<No Automatic Retransmission       */
+#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020)        /*!<Automatic Wakeup Mode             */
+#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040)        /*!<Automatic Bus-Off Management      */
+#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080)        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint32_t)0x00008000)        /*!<bxCAN software master reset       */
+                                                                           
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint32_t)0x00000001)        /*!<Initialization Acknowledge  */
+#define  CAN_MSR_SLAK                        ((uint32_t)0x00000002)        /*!<Sleep Acknowledge           */
+#define  CAN_MSR_ERRI                        ((uint32_t)0x00000004)        /*!<Error Interrupt             */
+#define  CAN_MSR_WKUI                        ((uint32_t)0x00000008)        /*!<Wakeup Interrupt            */
+#define  CAN_MSR_SLAKI                       ((uint32_t)0x00000010)        /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint32_t)0x00000100)        /*!<Transmit Mode               */
+#define  CAN_MSR_RXM                         ((uint32_t)0x00000200)        /*!<Receive Mode                */
+#define  CAN_MSR_SAMP                        ((uint32_t)0x00000400)        /*!<Last Sample Point           */
+#define  CAN_MSR_RX                          ((uint32_t)0x00000800)        /*!<CAN Rx Signal               */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0      */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0     */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0   */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0  */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0      */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1      */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1     */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1   */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1  */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1     */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2      */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2    */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2  */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2     */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code                    */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint32_t)0x00000003)        /*!<FIFO 0 Message Pending        */
+#define  CAN_RF0R_FULL0                      ((uint32_t)0x00000008)        /*!<FIFO 0 Full                   */
+#define  CAN_RF0R_FOVR0                      ((uint32_t)0x00000010)        /*!<FIFO 0 Overrun                */
+#define  CAN_RF0R_RFOM0                      ((uint32_t)0x00000020)        /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint32_t)0x00000003)        /*!<FIFO 1 Message Pending        */
+#define  CAN_RF1R_FULL1                      ((uint32_t)0x00000008)        /*!<FIFO 1 Full                   */
+#define  CAN_RF1R_FOVR1                      ((uint32_t)0x00000010)        /*!<FIFO 1 Overrun                */
+#define  CAN_RF1R_RFOM1                      ((uint32_t)0x00000020)        /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable          */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable          */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable                */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable        */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable                  */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable                 */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable                  */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler           */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1                */
+#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2                */
+#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width  */
+#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug)        */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode                   */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request                */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension                       */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier                        */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code     */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp   */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request                */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension                       */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier                        */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code     */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp   */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request                */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension                       */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier                        */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code      */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time  */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp    */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request                */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension                       */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier                        */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request                */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension                       */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier                        */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code   */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00)        /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint32_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint32_t)0x0001)            /*!<Filter Init Mode bit 0  */
+#define  CAN_FM1R_FBM1                       ((uint32_t)0x0002)            /*!<Filter Init Mode bit 1  */
+#define  CAN_FM1R_FBM2                       ((uint32_t)0x0004)            /*!<Filter Init Mode bit 2  */
+#define  CAN_FM1R_FBM3                       ((uint32_t)0x0008)            /*!<Filter Init Mode bit 3  */
+#define  CAN_FM1R_FBM4                       ((uint32_t)0x0010)            /*!<Filter Init Mode bit 4  */
+#define  CAN_FM1R_FBM5                       ((uint32_t)0x0020)            /*!<Filter Init Mode bit 5  */
+#define  CAN_FM1R_FBM6                       ((uint32_t)0x0040)            /*!<Filter Init Mode bit 6  */
+#define  CAN_FM1R_FBM7                       ((uint32_t)0x0080)            /*!<Filter Init Mode bit 7  */
+#define  CAN_FM1R_FBM8                       ((uint32_t)0x0100)            /*!<Filter Init Mode bit 8  */
+#define  CAN_FM1R_FBM9                       ((uint32_t)0x0200)            /*!<Filter Init Mode bit 9  */
+#define  CAN_FM1R_FBM10                      ((uint32_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint32_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint32_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint32_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint32_t)0x00003FFF)        /*!<Filter Scale Configuration        */
+#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001)        /*!<Filter Scale Configuration bit 0  */
+#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002)        /*!<Filter Scale Configuration bit 1  */
+#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004)        /*!<Filter Scale Configuration bit 2  */
+#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008)        /*!<Filter Scale Configuration bit 3  */
+#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010)        /*!<Filter Scale Configuration bit 4  */
+#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020)        /*!<Filter Scale Configuration bit 5  */
+#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040)        /*!<Filter Scale Configuration bit 6  */
+#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080)        /*!<Filter Scale Configuration bit 7  */
+#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100)        /*!<Filter Scale Configuration bit 8  */
+#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200)        /*!<Filter Scale Configuration bit 9  */
+#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400)        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800)        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000)        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000)        /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint32_t)0x00003FFF)        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint32_t)0x00000001)        /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint32_t)0x00000002)        /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint32_t)0x00000004)        /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint32_t)0x00000008)        /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint32_t)0x00000010)        /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint32_t)0x00000020)        /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint32_t)0x00000040)        /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint32_t)0x00000080)        /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint32_t)0x00000100)        /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint32_t)0x00000200)        /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint32_t)0x00000400)        /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint32_t)0x00000800)        /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint32_t)0x00001000)        /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint32_t)0x00002000)        /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint32_t)0x00003FFF)        /*!<Filter Active    */
+#define  CAN_FA1R_FACT0                      ((uint32_t)0x00000001)        /*!<Filter 0 Active  */
+#define  CAN_FA1R_FACT1                      ((uint32_t)0x00000002)        /*!<Filter 1 Active  */
+#define  CAN_FA1R_FACT2                      ((uint32_t)0x00000004)        /*!<Filter 2 Active  */
+#define  CAN_FA1R_FACT3                      ((uint32_t)0x00000008)        /*!<Filter 3 Active  */
+#define  CAN_FA1R_FACT4                      ((uint32_t)0x00000010)        /*!<Filter 4 Active  */
+#define  CAN_FA1R_FACT5                      ((uint32_t)0x00000020)        /*!<Filter 5 Active  */
+#define  CAN_FA1R_FACT6                      ((uint32_t)0x00000040)        /*!<Filter 6 Active  */
+#define  CAN_FA1R_FACT7                      ((uint32_t)0x00000080)        /*!<Filter 7 Active  */
+#define  CAN_FA1R_FACT8                      ((uint32_t)0x00000100)        /*!<Filter 8 Active  */
+#define  CAN_FA1R_FACT9                      ((uint32_t)0x00000200)        /*!<Filter 9 Active  */
+#define  CAN_FA1R_FACT10                     ((uint32_t)0x00000400)        /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint32_t)0x00000800)        /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint32_t)0x00001000)        /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint32_t)0x00002000)        /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LBPEGEN                    ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIE                       ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)     /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint32_t)0x000000FF)     /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001)     /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLYSIZE                     ((uint32_t)0x00000018)     /*!< Polynomial size bits               */
+#define  CRC_CR_POLYSIZE_0                   ((uint32_t)0x00000008)     /*!< Polynomial size bit 0              */
+#define  CRC_CR_POLYSIZE_1                   ((uint32_t)0x00000010)     /*!< Polynomial size bit 1              */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060)     /*!< REV_IN Reverse Input Data bits     */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020)     /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040)     /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080)     /*!< REV_OUT Reverse Output Data bits   */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF)     /*!< Initial CRC value bits         */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF)     /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable                         */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable          */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable                 */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable                     */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable                         */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable          */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable                 */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
+#define DCMI_CR_CM                           ((uint32_t)0x00000002)
+#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
+#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
+#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
+#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
+#define DCMI_CR_BSM                          ((uint32_t)0x00030000)
+#define DCMI_CR_BSM_0                        ((uint32_t)0x00010000)
+#define DCMI_CR_BSM_1                        ((uint32_t)0x00020000)
+#define DCMI_CR_OEBS                         ((uint32_t)0x00040000)
+#define DCMI_CR_LSM                          ((uint32_t)0x00080000)
+#define DCMI_CR_OELS                         ((uint32_t)0x00100000)
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
+#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
+
+/********************  Bits definition for DCMI_RISR register  ****************/
+#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_MISR register  ****************/
+#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
+#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
+#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
+#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
+#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
+#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
+#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
+#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
+#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
+#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
+#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
+#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
+#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
+#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
+#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
+#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
+#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
+#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
+#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
+#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer                          */
+#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer                          */
+#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode                              */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFSR register  ****************/
+
+#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode      */
+#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start           */
+#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size       */
+#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode      */
+#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value     */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value  */
+#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value   */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode      */
+#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start           */
+#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size       */
+#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode      */
+#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value     */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value  */
+#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value   */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value          */
+#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value         */
+#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value           */
+#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value   */
+#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value    */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value          */
+#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value         */
+#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value           */
+#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value          */
+#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value         */
+#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value           */
+#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable    */
+#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
+
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
+#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
+#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
+#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
+#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
+#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
+#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
+#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
+#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
+#define FLASH_ACR_ARTEN                      ((uint32_t)0x00000200)
+#define FLASH_ACR_ARTRST                     ((uint32_t)0x00000800)
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
+#define FLASH_SR_OPERR                       ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
+#define FLASH_SR_ERSERR                      ((uint32_t)0x00000080)
+#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          ((uint32_t)0x00000001)
+#define FLASH_CR_SER                         ((uint32_t)0x00000002)
+#define FLASH_CR_MER                         ((uint32_t)0x00000004)
+#define FLASH_CR_SNB                         ((uint32_t)0x00000078)
+#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
+#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
+#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
+#define FLASH_CR_ERRIE                       ((uint32_t)0x02000000)
+#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
+#define FLASH_OPTCR_WWDG_SW                 ((uint32_t)0x00000010)
+#define FLASH_OPTCR_IWDG_SW                 ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP                    ((uint32_t)0x00FF0000)
+#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
+#define FLASH_OPTCR_IWDG_STDBY              ((uint32_t)0x40000000)
+#define FLASH_OPTCR_IWDG_STOP               ((uint32_t)0x80000000)
+
+/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_BOOT_ADD0              ((uint32_t)0x0000FFFF)
+#define FLASH_OPTCR1_BOOT_ADD1              ((uint32_t)0xFFFF0000)
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                     ((uint32_t)0x00070000)        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     ((uint32_t)0x00200000)        /*!<Write FIFO Disable         */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                     ((uint32_t)0x00070000)        /*!<CRAM page size             */
+#define  FMC_BCR2_CPSIZE_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                     ((uint32_t)0x00070000)        /*!<CRAM page size             */
+#define  FMC_BCR3_CPSIZE_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                     ((uint32_t)0x00070000)        /*!<CRAM page size             */
+#define  FMC_BCR4_CPSIZE_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define  FMC_PCR_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+
+#define  FMC_PCR_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_PCR_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FMC_PCR_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FMC_PCR_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define  FMC_SR_IRS                        ((uint32_t)0x01)              /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        ((uint32_t)0x02)              /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        ((uint32_t)0x04)              /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       ((uint32_t)0x08)              /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       ((uint32_t)0x10)              /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       ((uint32_t)0x20)              /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      ((uint32_t)0x40)              /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define  FMC_PMEM_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PMEM_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PMEM_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PMEM_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define  FMC_PATT_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PATT_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PATT_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PATT_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_ECCR register  ******************/
+#define  FMC_ECCR_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+
+#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+
+#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+
+#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+
+#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+
+#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+
+#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
+                                            
+#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
+
+#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
+
+#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
+
+#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
+
+#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
+
+#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
+
+#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
+
+#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable                   */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable                 */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable                 */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable      */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable      */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable     */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable  */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable             */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF             */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset                      */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable    */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable       */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control                  */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable            */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable             */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable                 */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable           */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable                  */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode)                             */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode)                        */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode)                    */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation                                        */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode)                           */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode)                            */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes                                         */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode                                      */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode)                        */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1   */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks     */
+#define  I2C_OAR2_OA2NOMASK                  ((uint32_t)0x00000000)        /*!< No mask */
+#define  I2C_OAR2_OA2MASK01                  ((uint32_t)0x00000100)        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define  I2C_OAR2_OA2MASK02                  ((uint32_t)0x00000200)        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define  I2C_OAR2_OA2MASK03                  ((uint32_t)0x00000300)        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define  I2C_OAR2_OA2MASK04                  ((uint32_t)0x00000400)        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define  I2C_OAR2_OA2MASK05                  ((uint32_t)0x00000500)        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define  I2C_OAR2_OA2MASK06                  ((uint32_t)0x00000600)        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define  I2C_OAR2_OA2MASK07                  ((uint32_t)0x00000700)        /*!< OA2[7:1] is masked, No comparison is done */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable    */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode)  */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time                */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time               */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A                 */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection  */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable          */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B                 */
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty    */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status       */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)    */
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag              */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag             */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload        */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error                       */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost                */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun                */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception          */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag  */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert                     */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy                        */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag      */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag                 */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag       */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag            */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag     */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag     */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag            */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag              */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag                */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register        */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data  */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint32_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       ((uint32_t)0x0FFF)             /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width                    */
+#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value  */
+#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR1 register  ********************/
+#define  PWR_CR1_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR1_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
+#define  PWR_CR1_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
+#define  PWR_CR1_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+
+#define  PWR_CR1_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR1_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
+#define  PWR_CR1_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
+#define  PWR_CR1_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR1_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
+#define  PWR_CR1_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
+#define  PWR_CR1_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
+#define  PWR_CR1_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
+#define  PWR_CR1_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
+#define  PWR_CR1_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
+#define  PWR_CR1_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
+#define  PWR_CR1_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+
+#define  PWR_CR1_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR1_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
+
+#define  PWR_CR1_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-power regulator in deepsleep under-drive mode          */
+#define  PWR_CR1_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in deepsleep under-drive mode               */
+
+#define  PWR_CR1_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
+
+#define  PWR_CR1_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR1_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
+#define  PWR_CR1_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
+
+#define  PWR_CR1_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
+#define  PWR_CR1_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
+#define  PWR_CR1_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR1_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
+#define  PWR_CR1_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
+
+/*******************  Bit definition for PWR_CSR1 register  ********************/
+#define  PWR_CSR1_WUIF                        ((uint32_t)0x00000001)     /*!< Wake up internal Flag                            */
+#define  PWR_CSR1_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
+#define  PWR_CSR1_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
+#define  PWR_CSR1_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
+#define  PWR_CSR1_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
+#define  PWR_CSR1_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+
+#define  PWR_CSR1_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
+#define  PWR_CSR1_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR1_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define  PWR_CR2_CWUPF1                         ((uint32_t)0x00000001)     /*!< Clear Wakeup Pin Flag for PA0      */
+#define  PWR_CR2_CWUPF2                         ((uint32_t)0x00000002)     /*!< Clear Wakeup Pin Flag for PA2      */
+#define  PWR_CR2_CWUPF3                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Pin Flag for PC1      */
+#define  PWR_CR2_CWUPF4                         ((uint32_t)0x00000008)     /*!< Clear Wakeup Pin Flag for PC13     */
+#define  PWR_CR2_CWUPF5                         ((uint32_t)0x00000010)     /*!< Clear Wakeup Pin Flag for PI8      */
+#define  PWR_CR2_CWUPF6                         ((uint32_t)0x00000020)     /*!< Clear Wakeup Pin Flag for PI11     */
+
+#define  PWR_CR2_WUPP1                          ((uint32_t)0x00000100)     /*!< Wakeup Pin Polarity bit for PA0    */
+#define  PWR_CR2_WUPP2                          ((uint32_t)0x00000200)     /*!< Wakeup Pin Polarity bit for PA2    */
+#define  PWR_CR2_WUPP3                          ((uint32_t)0x00000400)     /*!< Wakeup Pin Polarity bit for PC1    */
+#define  PWR_CR2_WUPP4                          ((uint32_t)0x00000800)     /*!< Wakeup Pin Polarity bit for PC13   */
+#define  PWR_CR2_WUPP5                          ((uint32_t)0x00001000)     /*!< Wakeup Pin Polarity bit for PI8    */
+#define  PWR_CR2_WUPP6                          ((uint32_t)0x00002000)     /*!< Wakeup Pin Polarity bit for PI11   */
+
+/*******************  Bit definition for PWR_CSR2 register  ********************/
+#define  PWR_CSR2_WUPF1                         ((uint32_t)0x00000001)     /*!< Wakeup Pin Flag for PA0            */
+#define  PWR_CSR2_WUPF2                         ((uint32_t)0x00000002)     /*!< Wakeup Pin Flag for PA2            */
+#define  PWR_CSR2_WUPF3                         ((uint32_t)0x00000004)     /*!< Wakeup Pin Flag for PC1            */
+#define  PWR_CSR2_WUPF4                         ((uint32_t)0x00000008)     /*!< Wakeup Pin Flag for PC13           */
+#define  PWR_CSR2_WUPF5                         ((uint32_t)0x00000010)     /*!< Wakeup Pin Flag for PI8            */
+#define  PWR_CSR2_WUPF6                         ((uint32_t)0x00000020)     /*!< Wakeup Pin Flag for PI11           */
+
+#define  PWR_CSR2_EWUP1                         ((uint32_t)0x00000100)     /*!< Enable Wakeup Pin PA0              */
+#define  PWR_CSR2_EWUP2                         ((uint32_t)0x00000200)     /*!< Enable Wakeup Pin PA2              */
+#define  PWR_CSR2_EWUP3                         ((uint32_t)0x00000400)     /*!< Enable Wakeup Pin PC1              */
+#define  PWR_CSR2_EWUP4                         ((uint32_t)0x00000800)     /*!< Enable Wakeup Pin PC13             */
+#define  PWR_CSR2_EWUP5                         ((uint32_t)0x00001000)     /*!< Enable Wakeup Pin PI8              */
+#define  PWR_CSR2_EWUP6                         ((uint32_t)0x00002000)     /*!< Enable Wakeup Pin PI11             */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001)            /*!< Enable                            */
+#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002)            /*!< Abort request                     */
+#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004)            /*!< DMA Enable                        */
+#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008)            /*!< Timeout Counter Enable            */
+#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000010)            /*!< Sample Shift                      */
+#define  QUADSPI_CR_DFM                          ((uint32_t)0x00000040)            /*!< Dual Flash Mode                   */
+#define  QUADSPI_CR_FSEL                         ((uint32_t)0x00000080)            /*!< Flash Select                      */
+#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00000F00)            /*!< FTHRES[3:0] FIFO Level            */
+#define  QUADSPI_CR_FTHRES_0                     ((uint32_t)0x00000100)            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     ((uint32_t)0x00000200)            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     ((uint32_t)0x00000400)            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     ((uint32_t)0x00000800)            /*!< Bit 3 */
+#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000)            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000)            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000)            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000)            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000)            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000)            /*!< Bit 1                              */
+#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000)            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000)            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  ((uint32_t)0x01000000)            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  ((uint32_t)0x02000000)            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  ((uint32_t)0x04000000)            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  ((uint32_t)0x08000000)            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  ((uint32_t)0x10000000)            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  ((uint32_t)0x20000000)            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  ((uint32_t)0x40000000)            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  ((uint32_t)0x80000000)            /*!< Bit 7 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001)            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700)            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100)            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200)            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400)            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000)            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     ((uint32_t)0x00100000)            /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001)             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002)             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004)             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008)             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010)             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020)             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00001F00)             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     ((uint32_t)0x00000100)             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     ((uint32_t)0x00000200)             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     ((uint32_t)0x00000400)             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     ((uint32_t)0x00000800)             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     ((uint32_t)0x00001000)             /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001)             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002)             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008)             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010)             /*!< Clear Timeout Flag           */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFF)               /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FF)            /*!< INSTRUCTION[7:0]: Instruction    */
+#define  QUADSPI_CCR_INSTRUCTION_0                ((uint32_t)0x00000001)            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                ((uint32_t)0x00000002)            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                ((uint32_t)0x00000004)            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                ((uint32_t)0x00000008)            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                ((uint32_t)0x00000010)            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                ((uint32_t)0x00000020)            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                ((uint32_t)0x00000040)            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                ((uint32_t)0x00000080)            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300)            /*!< IMODE[1:0]: Instruction Mode      */
+#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100)            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200)            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00)            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400)            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800)            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000)            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000)            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000)            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       ((uint32_t)0x00040000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       ((uint32_t)0x00080000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       ((uint32_t)0x00100000)            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       ((uint32_t)0x00200000)            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       ((uint32_t)0x00400000)            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000)            /*!< DMODE[1:0]: Data Mode              */
+#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000)            /*!< FMODE[1:0]: Functional Mode        */
+#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000)            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000)            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000)            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         ((uint32_t)0x40000000)            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000)            /*!< DDRM: Double Data Rate Mode           */ 
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFF)            /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFF)            /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFF)            /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFF)            /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFF)            /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFF)            /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFF)            /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008) /*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010) /*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020) /*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040) /*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100) /*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200) /*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400) /*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800) /*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000) /*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000) /*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000) /*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
+#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
+#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
+#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
+#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
+#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
+#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
+#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
+#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+
+#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
+#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
+#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
+#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
+#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
+#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
+#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
+#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
+#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
+#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+
+#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
+#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
+#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+
+#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+
+#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
+#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
+#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
+#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
+#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
+#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
+#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
+#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
+#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
+#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
+#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
+#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+
+#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
+#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
+#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
+#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+
+#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
+#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
+#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
+#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+
+#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
+#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
+#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
+#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
+#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
+#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
+#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
+#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
+#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
+#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
+#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
+#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
+#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
+#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
+#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
+#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
+#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
+#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
+#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
+#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
+#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
+#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
+#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
+#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+
+#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
+#define  RCC_AHB3RSTR_QSPIRST               ((uint32_t)0x00000002)
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
+#define  RCC_APB1RSTR_LPTIM1RST              ((uint32_t)0x00000200)
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
+#define  RCC_APB1RSTR_SPDIFRXRST             ((uint32_t)0x00010000)
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
+#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
+#define  RCC_APB1RSTR_I2C4RST                ((uint32_t)0x01000000)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
+#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x08000000)
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
+#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
+#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
+#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
+#define  RCC_APB2RSTR_SDMMC1RST              ((uint32_t)0x00000800)
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
+#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
+#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
+#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
+#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
+#define  RCC_APB2RSTR_SAI2RST                ((uint32_t)0x00800000)
+#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
+#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
+#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
+#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
+#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
+#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
+#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
+#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
+#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
+#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
+#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
+#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
+#define  RCC_AHB1ENR_DTCMRAMEN               ((uint32_t)0x00100000)
+#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
+#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
+#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
+#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
+#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
+#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
+#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
+#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
+#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+
+#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB3ENR_QSPIEN                 ((uint32_t)0x00000002)
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
+#define  RCC_APB1ENR_LPTIM1EN                ((uint32_t)0x00000200)
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
+#define  RCC_APB1ENR_SPDIFRXEN               ((uint32_t)0x00010000)
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
+#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
+#define  RCC_APB1ENR_I2C4EN                  ((uint32_t)0x01000000)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
+#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x08000000)
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
+#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
+#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
+#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
+#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
+#define  RCC_APB2ENR_SDMMC1EN                ((uint32_t)0x00000800)
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
+#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
+#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
+#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
+#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
+#define  RCC_APB2ENR_SAI2EN                  ((uint32_t)0x00800000)
+#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
+#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
+#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
+#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
+#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
+#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
+#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
+#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
+#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
+#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
+
+#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
+#define  RCC_AHB1LPENR_AXILPEN               ((uint32_t)0x00002000)
+#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
+#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
+#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
+#define  RCC_AHB1LPENR_DTCMLPEN              ((uint32_t)0x00100000)
+#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
+#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
+#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
+#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
+#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
+#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB3LPENR_QSPILPEN             ((uint32_t)0x00000002)
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
+#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
+#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
+#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
+#define  RCC_APB1LPENR_LPTIM1LPEN            ((uint32_t)0x00000200)
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
+#define  RCC_APB1LPENR_SPDIFRXLPEN           ((uint32_t)0x00010000)
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
+#define  RCC_APB1LPENR_I2C4LPEN              ((uint32_t)0x01000000)
+#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
+#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
+#define  RCC_APB1LPENR_CECLPEN               ((uint32_t)0x08000000)
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
+#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
+#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
+#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200)
+#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
+#define  RCC_APB2LPENR_SDMMC1LPEN            ((uint32_t)0x00000800)
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
+#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
+#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
+#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB2LPENR_SAI2LPEN              ((uint32_t)0x00800000)
+#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
+#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
+#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
+#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
+#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
+
+#define  RCC_PLLI2SCFGR_PLLI2SP              ((uint32_t)0x00030000)
+#define  RCC_PLLI2SCFGR_PLLI2SP_0            ((uint32_t)0x00010000)
+#define  RCC_PLLI2SCFGR_PLLI2SP_1            ((uint32_t)0x00020000)
+
+#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000)
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000)
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000)
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000)
+
+#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040)
+#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080)
+#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100)
+#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200)
+#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400)
+#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800)
+#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000)
+#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000)
+#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000)
+
+#define  RCC_PLLSAICFGR_PLLSAIP              ((uint32_t)0x00030000)
+#define  RCC_PLLSAICFGR_PLLSAIP_0            ((uint32_t)0x00010000)
+#define  RCC_PLLSAICFGR_PLLSAIP_1            ((uint32_t)0x00020000)
+
+#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000)
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000)
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000)
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000)
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000)
+
+#define  RCC_PLLSAICFGR_PLLSAIR              ((uint32_t)0x70000000)
+#define  RCC_PLLSAICFGR_PLLSAIR_0            ((uint32_t)0x10000000)
+#define  RCC_PLLSAICFGR_PLLSAIR_1            ((uint32_t)0x20000000)
+#define  RCC_PLLSAICFGR_PLLSAIR_2            ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
+#define  RCC_DCKCFGR1_PLLI2SDIVQ              ((uint32_t)0x0000001F)
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_0            ((uint32_t)0x00000001)
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_1            ((uint32_t)0x00000002)
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_2            ((uint32_t)0x00000004)
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_3            ((uint32_t)0x00000008)
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_4            ((uint32_t)0x00000010)
+
+#define  RCC_DCKCFGR1_PLLSAIDIVQ              ((uint32_t)0x00001F00)
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_0            ((uint32_t)0x00000100)
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_1            ((uint32_t)0x00000200)
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_2            ((uint32_t)0x00000400)
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_3            ((uint32_t)0x00000800)
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_4            ((uint32_t)0x00001000)
+
+#define  RCC_DCKCFGR1_PLLSAIDIVR              ((uint32_t)0x00030000)
+#define  RCC_DCKCFGR1_PLLSAIDIVR_0            ((uint32_t)0x00010000)
+#define  RCC_DCKCFGR1_PLLSAIDIVR_1            ((uint32_t)0x00020000)
+
+#define  RCC_DCKCFGR1_SAI1SEL                 ((uint32_t)0x00300000)
+#define  RCC_DCKCFGR1_SAI1SEL_0               ((uint32_t)0x00100000)
+#define  RCC_DCKCFGR1_SAI1SEL_1               ((uint32_t)0x00200000)
+
+#define  RCC_DCKCFGR1_SAI2SEL                 ((uint32_t)0x00C00000)
+#define  RCC_DCKCFGR1_SAI2SEL_0               ((uint32_t)0x00400000)
+#define  RCC_DCKCFGR1_SAI2SEL_1               ((uint32_t)0x00800000)
+
+#define  RCC_DCKCFGR1_TIMPRE                  ((uint32_t)0x01000000)
+
+/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
+#define  RCC_DCKCFGR2_USART1SEL              ((uint32_t)0x00000003)
+#define  RCC_DCKCFGR2_USART1SEL_0            ((uint32_t)0x00000001)
+#define  RCC_DCKCFGR2_USART1SEL_1            ((uint32_t)0x00000002)
+#define  RCC_DCKCFGR2_USART2SEL              ((uint32_t)0x0000000C)
+#define  RCC_DCKCFGR2_USART2SEL_0            ((uint32_t)0x00000004)
+#define  RCC_DCKCFGR2_USART2SEL_1            ((uint32_t)0x00000008)
+#define  RCC_DCKCFGR2_USART3SEL              ((uint32_t)0x00000030)
+#define  RCC_DCKCFGR2_USART3SEL_0            ((uint32_t)0x00000010)
+#define  RCC_DCKCFGR2_USART3SEL_1            ((uint32_t)0x00000020)
+#define  RCC_DCKCFGR2_UART4SEL               ((uint32_t)0x000000C0)
+#define  RCC_DCKCFGR2_UART4SEL_0             ((uint32_t)0x00000040)
+#define  RCC_DCKCFGR2_UART4SEL_1             ((uint32_t)0x00000080)
+#define  RCC_DCKCFGR2_UART5SEL               ((uint32_t)0x00000300)
+#define  RCC_DCKCFGR2_UART5SEL_0             ((uint32_t)0x00000100)
+#define  RCC_DCKCFGR2_UART5SEL_1             ((uint32_t)0x00000200)
+#define  RCC_DCKCFGR2_USART6SEL              ((uint32_t)0x00000C00)
+#define  RCC_DCKCFGR2_USART6SEL_0            ((uint32_t)0x00000400)
+#define  RCC_DCKCFGR2_USART6SEL_1            ((uint32_t)0x00000800)
+#define  RCC_DCKCFGR2_UART7SEL               ((uint32_t)0x00003000)
+#define  RCC_DCKCFGR2_UART7SEL_0             ((uint32_t)0x00001000)
+#define  RCC_DCKCFGR2_UART7SEL_1             ((uint32_t)0x00002000)
+#define  RCC_DCKCFGR2_UART8SEL               ((uint32_t)0x0000C000)
+#define  RCC_DCKCFGR2_UART8SEL_0             ((uint32_t)0x00004000)
+#define  RCC_DCKCFGR2_UART8SEL_1             ((uint32_t)0x00008000)
+#define  RCC_DCKCFGR2_I2C1SEL                ((uint32_t)0x00030000)
+#define  RCC_DCKCFGR2_I2C1SEL_0              ((uint32_t)0x00010000)
+#define  RCC_DCKCFGR2_I2C1SEL_1              ((uint32_t)0x00020000)
+#define  RCC_DCKCFGR2_I2C2SEL                ((uint32_t)0x000C0000)
+#define  RCC_DCKCFGR2_I2C2SEL_0              ((uint32_t)0x00040000)
+#define  RCC_DCKCFGR2_I2C2SEL_1              ((uint32_t)0x00080000)
+#define  RCC_DCKCFGR2_I2C3SEL                ((uint32_t)0x00300000)
+#define  RCC_DCKCFGR2_I2C3SEL_0              ((uint32_t)0x00100000)
+#define  RCC_DCKCFGR2_I2C3SEL_1              ((uint32_t)0x00200000)
+#define  RCC_DCKCFGR2_I2C4SEL                ((uint32_t)0x00C00000)
+#define  RCC_DCKCFGR2_I2C4SEL_0              ((uint32_t)0x00400000)
+#define  RCC_DCKCFGR2_I2C4SEL_1              ((uint32_t)0x00800000)
+#define  RCC_DCKCFGR2_LPTIM1SEL              ((uint32_t)0x03000000)
+#define  RCC_DCKCFGR2_LPTIM1SEL_0            ((uint32_t)0x01000000)
+#define  RCC_DCKCFGR2_LPTIM1SEL_1            ((uint32_t)0x02000000)
+#define  RCC_DCKCFGR2_CECSEL                 ((uint32_t)0x04000000)
+#define  RCC_DCKCFGR2_CK48MSEL               ((uint32_t)0x08000000)
+#define  RCC_DCKCFGR2_SDMMC1SEL              ((uint32_t)0x10000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
+#define RNG_CR_IE                            ((uint32_t)0x00000008)
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
+#define RNG_SR_CECS                          ((uint32_t)0x00000002)
+#define RNG_SR_SECS                          ((uint32_t)0x00000004)
+#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
+#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE                          ((uint32_t)0x01000000) 
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF                         ((uint32_t)0x00020000)
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAMPCR register  ****************/
+#define RTC_TAMPCR_TAMP3MF                    ((uint32_t)0x01000000)
+#define RTC_TAMPCR_TAMP3NOERASE               ((uint32_t)0x00800000)
+#define RTC_TAMPCR_TAMP3IE                    ((uint32_t)0x00400000)
+#define RTC_TAMPCR_TAMP2MF                    ((uint32_t)0x00200000)
+#define RTC_TAMPCR_TAMP2NOERASE               ((uint32_t)0x00100000)
+#define RTC_TAMPCR_TAMP2IE                    ((uint32_t)0x00080000)
+#define RTC_TAMPCR_TAMP1MF                    ((uint32_t)0x00040000)
+#define RTC_TAMPCR_TAMP1NOERASE               ((uint32_t)0x00020000)
+#define RTC_TAMPCR_TAMP1IE                    ((uint32_t)0x00010000)
+#define RTC_TAMPCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAMPCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAMPCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAMPCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAMPCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAMPCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAMPCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAMPCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAMPCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAMPCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAMPCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAMPCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAMPCR_TAMP3_TRG                  ((uint32_t)0x00000040)
+#define RTC_TAMPCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAMPCR_TAMP2_TRG                   ((uint32_t)0x00000010)
+#define RTC_TAMPCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAMPCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAMPCR_TAMP1_TRG                   ((uint32_t)0x00000002)
+#define RTC_TAMPCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_OR register  ****************/
+#define RTC_OR_TSINSEL                      ((uint32_t)0x00000006)
+#define RTC_OR_TSINSEL_0                    ((uint32_t)0x00000002)
+#define RTC_OR_TSINSEL_1                    ((uint32_t)0x00000004)
+#define RTC_OR_ALARMTYPE                    ((uint32_t)0x00000008)
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       ((uint32_t)0x00000020)
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
+
+#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
+
+#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
+
+#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000)        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000)        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000)        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000)        /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007)        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+
+#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
+
+#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
+
+#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
+
+#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
+
+#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
+                                     
+#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
+
+#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000)         /*!<Bit 2 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  *******************/
+#define  SPDIFRX_CR_SPDIFEN                  ((uint32_t)0x00000003)        /*!<Peripheral Block Enable                      */
+#define  SPDIFRX_CR_RXDMAEN                  ((uint32_t)0x00000004)        /*!<Receiver DMA Enable for data flow            */
+#define  SPDIFRX_CR_RXSTEO                   ((uint32_t)0x00000008)        /*!<Stereo Mode                                  */
+#define  SPDIFRX_CR_DRFMT                    ((uint32_t)0x00000030)        /*!<RX Data format                               */
+#define  SPDIFRX_CR_PMSK                     ((uint32_t)0x00000040)        /*!<Mask Parity error bit                        */
+#define  SPDIFRX_CR_VMSK                     ((uint32_t)0x00000080)        /*!<Mask of Validity bit                         */
+#define  SPDIFRX_CR_CUMSK                    ((uint32_t)0x00000100)        /*!<Mask of channel status and user bits         */
+#define  SPDIFRX_CR_PTMSK                    ((uint32_t)0x00000200)        /*!<Mask of Preamble Type bits                   */
+#define  SPDIFRX_CR_CBDMAEN                  ((uint32_t)0x00000400)        /*!<Control Buffer DMA ENable for control flow   */
+#define  SPDIFRX_CR_CHSEL                    ((uint32_t)0x00000800)        /*!<Channel Selection                            */
+#define  SPDIFRX_CR_NBTR                     ((uint32_t)0x00003000)        /*!<Maximum allowed re-tries during synchronization phase */
+#define  SPDIFRX_CR_WFA                      ((uint32_t)0x00004000)        /*!<Wait For Activity     */
+#define  SPDIFRX_CR_INSEL                    ((uint32_t)0x00070000)        /*!<SPDIF input selection */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define  SPDIFRX_IMR_RXNEIE                   ((uint32_t)0x00000001)        /*!<RXNE interrupt enable                              */
+#define  SPDIFRX_IMR_CSRNEIE                  ((uint32_t)0x00000002)        /*!<Control Buffer Ready Interrupt Enable              */
+#define  SPDIFRX_IMR_PERRIE                   ((uint32_t)0x00000004)        /*!<Parity error interrupt enable                      */
+#define  SPDIFRX_IMR_OVRIE                    ((uint32_t)0x00000008)        /*!<Overrun error Interrupt Enable                     */
+#define  SPDIFRX_IMR_SBLKIE                   ((uint32_t)0x00000010)        /*!<Synchronization Block Detected Interrupt Enable    */
+#define  SPDIFRX_IMR_SYNCDIE                  ((uint32_t)0x00000020)        /*!<Synchronization Done                               */
+#define  SPDIFRX_IMR_IFEIE                    ((uint32_t)0x00000040)        /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define  SPDIFRX_SR_RXNE                   ((uint32_t)0x00000001)       /*!<Read data register not empty                          */
+#define  SPDIFRX_SR_CSRNE                  ((uint32_t)0x00000002)       /*!<The Control Buffer register is not empty              */
+#define  SPDIFRX_SR_PERR                   ((uint32_t)0x00000004)       /*!<Parity error                                          */
+#define  SPDIFRX_SR_OVR                    ((uint32_t)0x00000008)       /*!<Overrun error                                         */
+#define  SPDIFRX_SR_SBD                    ((uint32_t)0x00000010)       /*!<Synchronization Block Detected                        */
+#define  SPDIFRX_SR_SYNCD                  ((uint32_t)0x00000020)       /*!<Synchronization Done                                  */
+#define  SPDIFRX_SR_FERR                   ((uint32_t)0x00000040)       /*!<Framing error                                         */
+#define  SPDIFRX_SR_SERR                   ((uint32_t)0x00000080)       /*!<Synchronization error                                 */
+#define  SPDIFRX_SR_TERR                   ((uint32_t)0x00000100)       /*!<Time-out error                                        */
+#define  SPDIFRX_SR_WIDTH5                 ((uint32_t)0x7FFF0000)       /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define  SPDIFRX_IFCR_PERRCF               ((uint32_t)0x00000004)       /*!<Clears the Parity error flag                         */
+#define  SPDIFRX_IFCR_OVRCF                ((uint32_t)0x00000008)       /*!<Clears the Overrun error flag                        */
+#define  SPDIFRX_IFCR_SBDCF                ((uint32_t)0x00000010)       /*!<Clears the Synchronization Block Detected flag       */
+#define  SPDIFRX_IFCR_SYNCDCF              ((uint32_t)0x00000020)       /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define  SPDIFRX_DR0_DR                    ((uint32_t)0x00FFFFFF)        /*!<Data value            */
+#define  SPDIFRX_DR0_PE                    ((uint32_t)0x01000000)        /*!<Parity Error bit      */
+#define  SPDIFRX_DR0_V                     ((uint32_t)0x02000000)        /*!<Validity bit          */
+#define  SPDIFRX_DR0_U                     ((uint32_t)0x04000000)        /*!<User bit              */
+#define  SPDIFRX_DR0_C                     ((uint32_t)0x08000000)        /*!<Channel Status bit    */
+#define  SPDIFRX_DR0_PT                    ((uint32_t)0x30000000)        /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define  SPDIFRX_DR1_DR                    ((uint32_t)0xFFFFFF00)        /*!<Data value            */
+#define  SPDIFRX_DR1_PT                    ((uint32_t)0x00000030)        /*!<Preamble Type         */
+#define  SPDIFRX_DR1_C                     ((uint32_t)0x00000008)        /*!<Channel Status bit    */
+#define  SPDIFRX_DR1_U                     ((uint32_t)0x00000004)        /*!<User bit              */
+#define  SPDIFRX_DR1_V                     ((uint32_t)0x00000002)        /*!<Validity bit          */
+#define  SPDIFRX_DR1_PE                    ((uint32_t)0x00000001)        /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define  SPDIFRX_DR1_DRNL1                 ((uint32_t)0xFFFF0000)        /*!<Data value Channel B      */
+#define  SPDIFRX_DR1_DRNL2                 ((uint32_t)0x0000FFFF)        /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define  SPDIFRX_CSR_USR                     ((uint32_t)0x0000FFFF)        /*!<User data information           */
+#define  SPDIFRX_CSR_CS                      ((uint32_t)0x00FF0000)        /*!<Channel A status information    */
+#define  SPDIFRX_CSR_SOB                     ((uint32_t)0x01000000)        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define  SPDIFRX_DIR_THI                 ((uint32_t)0x000013FF)        /*!<Threshold LOW      */
+#define  SPDIFRX_DIR_TLO                 ((uint32_t)0x1FFF0000)        /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define  SDMMC_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDMMC_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!<Bit 0 */
+#define  SDMMC_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!<Bit 1 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define  SDMMC_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!<Clock divide factor             */
+#define  SDMMC_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!<Clock enable bit                */
+#define  SDMMC_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!<Power saving configuration bit  */
+#define  SDMMC_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!<Clock divider bypass enable bit */
+         
+#define  SDMMC_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDMMC_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!<Bit 0 */
+#define  SDMMC_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!<Bit 1 */
+         
+#define  SDMMC_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!<SDMMC_CK dephasing selection bit */
+#define  SDMMC_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define  SDMMC_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define  SDMMC_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!<Command Index                               */
+         
+#define  SDMMC_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDMMC_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!< Bit 0 */
+#define  SDMMC_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!< Bit 1 */
+         
+#define  SDMMC_CMD_WAITINT                    ((uint32_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDMMC_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDMMC_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDMMC_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define  SDMMC_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define  SDMMC_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define  SDMMC_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define  SDMMC_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define  SDMMC_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define  SDMMC_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define  SDMMC_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define  SDMMC_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define  SDMMC_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!<Data transfer enabled bit         */
+#define  SDMMC_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!<Data transfer direction selection */
+#define  SDMMC_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!<Data transfer mode selection      */
+#define  SDMMC_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!<DMA enabled bit                   */
+
+#define  SDMMC_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDMMC_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  SDMMC_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!<Read wait start         */
+#define  SDMMC_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!<Read wait stop          */
+#define  SDMMC_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!<Read wait mode          */
+#define  SDMMC_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define  SDMMC_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define  SDMMC_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
+#define  SDMMC_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
+#define  SDMMC_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
+#define  SDMMC_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
+#define  SDMMC_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
+#define  SDMMC_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
+#define  SDMMC_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
+#define  SDMMC_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
+#define  SDMMC_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDMMC_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
+#define  SDMMC_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
+#define  SDMMC_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
+#define  SDMMC_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
+#define  SDMMC_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDMMC_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDMMC_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
+#define  SDMMC_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
+#define  SDMMC_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
+#define  SDMMC_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
+#define  SDMMC_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
+#define  SDMMC_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
+#define  SDMMC_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDMMC interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define  SDMMC_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
+#define  SDMMC_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
+#define  SDMMC_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
+#define  SDMMC_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
+#define  SDMMC_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
+#define  SDMMC_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
+#define  SDMMC_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
+#define  SDMMC_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
+#define  SDMMC_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
+#define  SDMMC_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
+#define  SDMMC_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDMMCIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define  SDMMC_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDMMC_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDMMC_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
+#define  SDMMC_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
+#define  SDMMC_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDMMC_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDMMC_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
+#define  SDMMC_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
+#define  SDMMC_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
+#define  SDMMC_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
+#define  SDMMC_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
+#define  SDMMC_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDMMC_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
+#define  SDMMC_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDMMC_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDMMC_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDMMC_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDMMC_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDMMC Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define  SDMMC_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define  SDMMC_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)        /*!< Clock Phase                        */
+#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)        /*!< Clock Polarity                     */
+#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)        /*!< Master Selection                   */
+#define  SPI_CR1_BR                          ((uint32_t)0x00000038)        /*!< BR[2:0] bits (Baud Rate Control)   */
+#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)        /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)        /*!< SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)        /*!< Frame Format                        */
+#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)        /*!< Internal slave select               */
+#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)        /*!< Software slave management           */
+#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)        /*!< Receive only                        */
+#define  SPI_CR1_CRCL                        ((uint32_t)0x00000800)        /*!< CRC Length                          */
+#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)        /*!< Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)        /*!< Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)        /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)        /*!< Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)        /*!< Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)        /*!< Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)        /*!< SS Output Enable                     */
+#define  SPI_CR2_NSSP                        ((uint32_t)0x00000008)        /*!< NSS pulse management Enable          */
+#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)        /*!< Frame Format Enable                  */
+#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)        /*!< Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)        /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)        /*!< Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_DS                          ((uint32_t)0x00000F00)        /*!< DS[3:0] Data Size                    */
+#define  SPI_CR2_DS_0                        ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint32_t)0x00001000)        /*!< FIFO reception Threshold           */
+#define  SPI_CR2_LDMARX                      ((uint32_t)0x00002000)        /*!< Last DMA transfer for reception    */
+#define  SPI_CR2_LDMATX                      ((uint32_t)0x00004000)        /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)        /*!< Receive buffer Not Empty  */
+#define  SPI_SR_TXE                          ((uint32_t)0x00000002)        /*!< Transmit buffer Empty     */
+#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)        /*!< Channel side              */
+#define  SPI_SR_UDR                          ((uint32_t)0x00000008)        /*!< Underrun flag             */
+#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)        /*!< CRC Error flag            */
+#define  SPI_SR_MODF                         ((uint32_t)0x00000020)        /*!< Mode fault                */
+#define  SPI_SR_OVR                          ((uint32_t)0x00000040)        /*!< Overrun flag              */
+#define  SPI_SR_BSY                          ((uint32_t)0x00000080)        /*!< Busy flag                 */
+#define  SPI_SR_FRE                          ((uint32_t)0x00000100)        /*!< TI frame format error     */
+#define  SPI_SR_FRLVL                        ((uint32_t)0x00000600)        /*!< FIFO Reception Level      */
+#define  SPI_SR_FRLVL_0                      ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint32_t)0x00001800)        /*!< FIFO Transmission Level   */
+#define  SPI_SR_FTLVL_0                      ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint32_t)0x00001000)        /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint32_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)        /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)        /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)        /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)        /*!<steady state clock polarity                       */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)        /*!<PCM frame synchronization                         */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)        /*!<I2S Enable                                        */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)        /*!<I2S mode selection                                */
+#define  SPI_I2SCFGR_ASTRTEN                 ((uint32_t)0x00001000)        /*!<Asynchronous start enable                        */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x00FF)            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       ((uint32_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x0200)            /*!<Master Clock Output Enable   */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_BOOT          ((uint32_t)0x00000001) /*!< Boot information after Reset */
+
+#define SYSCFG_MEMRMP_SWP_FMC          ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
+#define SYSCFG_MEMRMP_SWP_FMC_0        ((uint32_t)0x00000400) 
+#define SYSCFG_MEMRMP_SWP_FMC_1        ((uint32_t)0x00000800) 
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
+
+#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009) /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000A) /*!<PK[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090) /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0) /*!<PK[1] pin */
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900) /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00) /*!<PK[2] pin */
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000) /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000) /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009) /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000A) /*!<PK[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090) /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0) /*!<PK[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900) /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00) /*!<PK[6] pin */
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000) /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000) /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009) /*!<PJ[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090) /*!<PJ[9] pin */
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900) /*!<PJ[10] pin */
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000) /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008) /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009) /*!<PJ[12] pin */
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008) /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009) /*!<PJ[13] pin */
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800) /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900) /*!<PJ[14] pin */
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000) /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000) /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
+#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CR1_UIFREMAP                    ((uint32_t)0x0800)            /*!<UIF status bit */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_OIS5                        ((uint32_t)0x00010000)            /*!<Output Idle state 4 (OC4 output) */
+#define  TIM_CR2_OIS6                        ((uint32_t)0x00040000)            /*!<Output Idle state 4 (OC4 output) */
+
+#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_MMS2                        ((uint32_t)0x00F00000)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS2_0                      ((uint32_t)0x00100000)            /*!<Bit 0 */
+#define  TIM_CR2_MMS2_1                      ((uint32_t)0x00200000)            /*!<Bit 1 */
+#define  TIM_CR2_MMS2_2                      ((uint32_t)0x00400000)            /*!<Bit 2 */
+#define  TIM_CR2_MMS2_3                      ((uint32_t)0x00800000)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint32_t)0x00010007)            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS_3                      ((uint32_t)0x00010000)            /*!<Bit 3 */
+#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+
+
+#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
+#define  TIM_SR_B2IF                         ((uint32_t)0x0100)            /*!<Break2 interrupt Flag               */
+#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        ((uint32_t)0x00000020)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          ((uint32_t)0x00000080)               /*!<Break Generation                          */
+#define  TIM_EGR_B2G                         ((uint32_t)0x00000100)              /*!<Break2 Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00010070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      ((uint32_t)0x01007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M_3                    ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)        /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)        /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00010070)        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M_3                    ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+
+
+#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)        /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)        /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)        /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint32_t)0x01007000)        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M_3                    ((uint32_t)0x01000000)        /*!<Bit 3 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC5E                       ((uint32_t)0x00010000)            /*!<Capture/Compare 5 output enable */
+#define  TIM_CCER_CC5P                       ((uint32_t)0x00020000)            /*!<Capture/Compare 5 output Polarity */
+#define  TIM_CCER_CC6E                       ((uint32_t)0x00100000)            /*!<Capture/Compare 6 output enable */
+#define  TIM_CCER_CC6P                       ((uint32_t)0x00200000)            /*!<Capture/Compare 6 output Polarity */
+
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable                */
+#define  TIM_BDTR_BKF                        ((uint32_t)0x000F0000)            /*!<Break Filter for Break1 */
+#define  TIM_BDTR_BK2F                       ((uint32_t)0x00F00000)            /*!<Break Filter for Break2 */
+#define  TIM_BDTR_BK2E                       ((uint32_t)0x01000000)            /*!<Break enable for Break2 */
+#define  TIM_BDTR_BK2P                       ((uint32_t)0x02000000)            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400)            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800)            /*!<Bit 1 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define  TIM_CCMR3_OC5FE                     ((uint32_t)0x00000004)            /*!<Output Compare 5 Fast enable */
+#define  TIM_CCMR3_OC5PE                     ((uint32_t)0x00000008)            /*!<Output Compare 5 Preload enable */
+
+#define  TIM_CCMR3_OC5M                      ((uint32_t)0x00010070)            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define  TIM_CCMR3_OC5M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR3_OC5M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR3_OC5M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR3_OC5M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC5CE                     ((uint32_t)0x00000080)            /*!<Output Compare 5 Clear Enable */
+
+#define  TIM_CCMR3_OC6FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR3_OC6PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR3_OC6M                      ((uint32_t)0x01007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR3_OC6M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR3_OC6M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR3_OC6M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR3_OC6M_3                    ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC6CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define  TIM_CCR5_CCR5                       ((uint32_t)0xFFFFFFFF)        /*!<Capture/Compare 5 Value */
+#define  TIM_CCR5_GC5C1                      ((uint32_t)0x20000000)        /*!<Group Channel 5 and Channel 1 */
+#define  TIM_CCR5_GC5C2                      ((uint32_t)0x40000000)        /*!<Group Channel 5 and Channel 2 */
+#define  TIM_CCR5_GC5C3                      ((uint32_t)0x80000000)        /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 6 Value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define  LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match                       */
+#define  LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match                    */
+#define  LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event         */
+#define  LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK          */
+#define  LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK       */
+#define  LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */
+#define  LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define  LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag                       */
+#define  LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag                    */
+#define  LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag         */
+#define  LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag          */
+#define  LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag       */
+#define  LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */
+#define  LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define  LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable                       */
+#define  LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable                    */
+#define  LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable         */
+#define  LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable          */
+#define  LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable       */
+#define  LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */
+#define  LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define  LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */
+
+#define  LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */
+#define  LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define  LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define  LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */
+#define  LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */
+#define  LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */
+#define  LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define  LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define  LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable           */
+#define  LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape          */
+#define  LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */
+#define  LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode         */
+#define  LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable     */     
+#define  LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable     */          
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define  LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable                 */
+#define  LPTIM_CR_SNGSTRT                       ((uint32_t)0x00080002)             /*!< Timer start in single mode     */
+#define  LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define  LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register     */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define  LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define  LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register     */
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable                                    */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable                                 */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable                              */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable                           */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable                           */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable          */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable                            */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable                             */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection                                */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable                           */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method                          */
+#define  USART_CR1_M                         ((uint32_t)0x10001000)            /*!< Word length                                     */
+#define  USART_CR1_M_0                       ((uint32_t)0x00001000)            /*!< Word length - Bit 0                             */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable                                */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable                */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode            */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable     */
+#define  USART_CR1_M_1                       ((uint32_t)0x10000000)            /*!< Word length - Bit 1               */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection       */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length             */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable   */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse                   */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase                            */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity                         */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable                           */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits)             */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable                        */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins                        */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion          */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion          */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion                  */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First             */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable                  */
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable  */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable                         */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable                               */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power                                 */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection                          */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable                          */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable                          */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver                            */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter                         */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable                                     */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable                                     */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable                           */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable                   */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable                                */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error                 */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode                             */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection               */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint32_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint32_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint32_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     ((uint32_t)0x0001)                /*!< Auto-Baud Rate Request      */
+#define  USART_RQR_SBKRQ                     ((uint32_t)0x0002)                /*!< Send Break Request          */
+#define  USART_RQR_MMRQ                      ((uint32_t)0x0004)                /*!< Mute Mode Request           */
+#define  USART_RQR_RXFRQ                     ((uint32_t)0x0008)                /*!< Receive Data flush Request  */
+#define  USART_RQR_TXFRQ                     ((uint32_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error                        */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error                       */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag                 */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error                       */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected                  */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty        */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete               */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty        */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag            */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag                  */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag                            */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out                   */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag                   */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error                */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag                 */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag                           */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag                */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag                     */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag         */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag    */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag     */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag             */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag            */
+#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag           */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag            */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag       */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag    */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag      */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag            */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag        */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag             */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag          */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag   */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint32_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint32_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040) /*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080) /*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
+#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
+#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001)         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002)         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                ((uint32_t)0x00000004)         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               ((uint32_t)0x00000008)         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 ((uint32_t)0x00000010)         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                ((uint32_t)0x00000020)         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 ((uint32_t)0x00000040)         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                ((uint32_t)0x00000080)         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100)         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200)         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400)         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800)         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    ((uint32_t)0x00001000)         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000)         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000)         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000)         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 ((uint32_t)0x00080000)         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  ((uint32_t)0x00100000)         /*!< OTG version  */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003)            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004)            /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003)            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004)            /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0)            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080)            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100)            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200)            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400)            /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800)            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000)            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000)            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001)            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002)            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010)            /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004)            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100)            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200)            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000)            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000)            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000)            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  ((uint32_t)0x00100000)            /*!< Change in ID pin input value           */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001)            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002)            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004)            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008)            /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070)            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080)            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100)            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200)            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400)            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800)            /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFF)            /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFF)            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000)            /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001)            /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006)            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008)            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00)            /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001E)            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008)            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010)            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020)            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080)            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100)            /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007)            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100)            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00)            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000)            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000)            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000)            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000)            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000)            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000)            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000)            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000)            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000)            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000)            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000)            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000)            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000)            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000)            /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001)            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002)            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004)            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010)            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020)            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0)            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040)            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080)            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100)            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200)            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400)            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000)            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000)            /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFF)            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000)            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000)            /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000)            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000)            /*!<Bit 7 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFF)            /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask                             */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001)            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008)            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010)            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040)            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080)            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400)            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800)            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000)            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000)            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  ((uint32_t)0x00800000)            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000)            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000)            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  ((uint32_t)0x08000000)            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000)            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008)            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010)            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040)            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080)            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400)            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800)            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000)            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000)            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000)            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  ((uint32_t)0x00800000)            /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000)            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000)            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 ((uint32_t)0x08000000)            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000)            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFF)            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000)            /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFF)            /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000F)            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000)            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFF)            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000)            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+
+#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
+#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+
+#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
+#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFF)            /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFF)            /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFF)            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000)            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFF)            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000)            /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFF)            /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFF)            /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000)            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000)            /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000)            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000)            /*!<Bit 6 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001)            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002)            /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FC)            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000)            /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000)            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000)            /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFF)         /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002)           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000)           /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN                 ((uint32_t)0x00010000)              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  ((uint32_t)0x00200000)              /*!< USB VBUS Detection Enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN                 ((uint32_t)0x00000001)             /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF                  ((uint32_t)0x00800000)             /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM          ((uint32_t)0x00000002)            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          ((uint32_t)0x00020000)            /*!< OUT Endpoint 1 interrupt mask bit */
+ 
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID               ((uint32_t)0xFFFFFFFF)            /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define  USB_OTG_GLPMCFG_LPMEN               ((uint32_t)0x00000001)            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              ((uint32_t)0x00000002)            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                ((uint32_t)0x0000003C)            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             ((uint32_t)0x00000040)            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              ((uint32_t)0x00000080)            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            ((uint32_t)0x00000F00)            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              ((uint32_t)0x00001000)            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              ((uint32_t)0x00006000)            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              ((uint32_t)0x00008000)            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             ((uint32_t)0x00010000)            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            ((uint32_t)0x001E0000)            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             ((uint32_t)0x00E00000)            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              ((uint32_t)0x01000000)            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          ((uint32_t)0x0E000000)            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              ((uint32_t)0x10000000)            /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM           ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          ((uint32_t)0x00000100)            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             ((uint32_t)0x00000200)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            ((uint32_t)0x00002000)            /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001)            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002)            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004)            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008)            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010)            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020)            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040)            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080)            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100)            /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00)            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000)            /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000)            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000)            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000)            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000)            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000)            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000)            /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFF)            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000)            /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000)            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000)            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000)            /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000)            /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000)            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000)            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000)            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000)            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000)            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000)            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000)            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000)            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000)            /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800)            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000)            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000)            /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000)            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000)            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000)            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000)            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000)            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000)            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000)            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000)            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000)            /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007F)            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040)            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80)            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000)            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000)            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000)            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000)            /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002)            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008)            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010)            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040)            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080)            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100)            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200)            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400)            /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008)            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080)            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100)            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200)            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800)            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000)            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000)            /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002)            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008)            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010)            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040)            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080)            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100)            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200)            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400)            /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000)            /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000)            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000)            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000)            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000)            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFF)            /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFF)            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000)            /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FF)            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000)            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000)            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000)            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000)            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000)            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000)            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000)            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000)            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000)            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000)            /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000)            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000)            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000)            /*!<Bit 1 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001)            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010)            /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
+                                       ((__INSTANCE__) == ADC2) || \
+                                       ((__INSTANCE__) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
+                                       ((__INSTANCE__) == CAN2))
+ 
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
+                                              ((__INSTANCE__) == DMA1_Stream1) || \
+                                              ((__INSTANCE__) == DMA1_Stream2) || \
+                                              ((__INSTANCE__) == DMA1_Stream3) || \
+                                              ((__INSTANCE__) == DMA1_Stream4) || \
+                                              ((__INSTANCE__) == DMA1_Stream5) || \
+                                              ((__INSTANCE__) == DMA1_Stream6) || \
+                                              ((__INSTANCE__) == DMA1_Stream7) || \
+                                              ((__INSTANCE__) == DMA2_Stream0) || \
+                                              ((__INSTANCE__) == DMA2_Stream1) || \
+                                              ((__INSTANCE__) == DMA2_Stream2) || \
+                                              ((__INSTANCE__) == DMA2_Stream3) || \
+                                              ((__INSTANCE__) == DMA2_Stream4) || \
+                                              ((__INSTANCE__) == DMA2_Stream5) || \
+                                              ((__INSTANCE__) == DMA2_Stream6) || \
+                                              ((__INSTANCE__) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+										
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** QSPI Instances *********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+                                        
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
+                                       ((__INSTANCE__) == I2C2) || \
+                                       ((__INSTANCE__) == I2C3) || \
+                                       ((__INSTANCE__) == I2C4))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
+                                    ((__INSTANCE__) == SPI2) || \
+                                    ((__INSTANCE__) == SPI3))
+
+/******************************* LPTIM Instances ********************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
+                                     ((__PERIPH__) == SAI1_Block_B) || \
+                                     ((__PERIPH__) == SAI2_Block_A) || \
+                                     ((__PERIPH__) == SAI2_Block_B))
+
+
+/******************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
+
+
+/****************************** SPDIFRX Instances *********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
+                                     
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
+                                       ((__INSTANCE__) == SPI2) || \
+                                       ((__INSTANCE__) == SPI3) || \
+                                       ((__INSTANCE__) == SPI4) || \
+                                       ((__INSTANCE__) == SPI5) || \
+                                       ((__INSTANCE__) == SPI6))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
+                                   ((__INSTANCE__) == TIM2)   || \
+                                   ((__INSTANCE__) == TIM3)   || \
+                                   ((__INSTANCE__) == TIM4)   || \
+                                   ((__INSTANCE__) == TIM5)   || \
+                                   ((__INSTANCE__) == TIM6)   || \
+                                   ((__INSTANCE__) == TIM7)   || \
+                                   ((__INSTANCE__) == TIM8)   || \
+                                   ((__INSTANCE__) == TIM9)   || \
+                                   ((__INSTANCE__) == TIM10)  || \
+                                   ((__INSTANCE__) == TIM11)  || \
+                                   ((__INSTANCE__) == TIM12)  || \
+                                   ((__INSTANCE__) == TIM13)  || \
+                                   ((__INSTANCE__) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM10) || \
+                                         ((__INSTANCE__) == TIM11) || \
+                                         ((__INSTANCE__) == TIM12) || \
+                                         ((__INSTANCE__) == TIM13) || \
+                                         ((__INSTANCE__) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM8))
+                                       
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
+                                       (((__INSTANCE__) == TIM1)    || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
+                                  (((__INSTANCE__) == TIM1)    || \
+                                   ((__INSTANCE__) == TIM2)    || \
+                                   ((__INSTANCE__) == TIM3)    || \
+                                   ((__INSTANCE__) == TIM4)    || \
+                                   ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
+                                                 (((__INSTANCE__) == TIM1)    || \
+                                                  ((__INSTANCE__) == TIM2)    || \
+                                                  ((__INSTANCE__) == TIM3)    || \
+                                                  ((__INSTANCE__) == TIM4)    || \
+                                                  ((__INSTANCE__) == TIM5)    || \
+                                                  ((__INSTANCE__) == TIM8))
+ 
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
+                                                   (((__INSTANCE__) == TIM1)    || \
+                                                    ((__INSTANCE__) == TIM2)    || \
+                                                    ((__INSTANCE__) == TIM3)    || \
+                                                    ((__INSTANCE__) == TIM4)    || \
+                                                    ((__INSTANCE__) == TIM5)    || \
+                                                    ((__INSTANCE__) == TIM8))
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+
+                                       
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                            ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+   
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM6) || \
+                                       ((__INSTANCE__) == TIM7) || \
+                                       ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8)) 
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                             ((__INSTANCE__) == TIM2) || \
+                                             ((__INSTANCE__) == TIM3) || \
+                                             ((__INSTANCE__) == TIM4) || \
+                                             ((__INSTANCE__) == TIM5) || \
+                                             ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM6) || \
+                                          ((__INSTANCE__) == TIM7) || \
+                                          ((__INSTANCE__) == TIM8) || \
+                                          ((__INSTANCE__) == TIM13) || \
+                                          ((__INSTANCE__) == TIM14))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8) || \
+                                         ((__INSTANCE__) == TIM9) || \
+                                         ((__INSTANCE__) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
+                                              ((__INSTANCE__) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                        ((__INSTANCE__) == TIM2) || \
+                                        ((__INSTANCE__) == TIM3) || \
+                                        ((__INSTANCE__) == TIM4) || \
+                                        ((__INSTANCE__) == TIM5) || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
+    ((((__INSTANCE__) == TIM1) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM2) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM3) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM4) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM5) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM8) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM9) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM10) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM11) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM12) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM13) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM14) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
+   ((((__INSTANCE__) == TIM1) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((__INSTANCE__) == TIM8) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM7)    || \
+     ((__INSTANCE__) == TIM8))  
+      
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                     ((__INSTANCE__) == USART2) || \
+                                     ((__INSTANCE__) == USART3) || \
+                                     ((__INSTANCE__) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                         ((__INSTANCE__) == USART2) || \
+                                         ((__INSTANCE__) == USART3) || \
+                                         ((__INSTANCE__) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))     
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F7xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F7 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define HASH_RNG_IRQn              RNG_IRQn
+
+/* Aliases for __IRQHandler */
+#define HASH_RNG_IRQHandler        RNG_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F746xx_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
new file mode 100644
index 0000000000..5ec8dd9f13
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    25-June-2015
+  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F7xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx
+  * @{
+  */
+    
+#ifndef __STM32F7xx_H
+#define __STM32F7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F7)
+#define STM32F7
+#endif /* STM32F7 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx)
+  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+                                   STM32F756NG Devices */
+#define STM32F746xx           /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
+                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
+  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.0.1
+  */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7xx_CMSIS_DEVICE_VERSION        ((__STM32F7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
+                                                |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
+                                                |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
+                                                |(__STM32F7xx_CMSIS_DEVICE_VERSION))
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32F756xx)
+  #include "stm32f756xx.h"
+#elif defined(STM32F746xx)
+  #include "stm32f746xx.h"
+#elif defined(STM32F745xx)
+  #include "stm32f745xx.h"
+#else
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+/**
+  * @}
+  */
+
+#ifdef USE_HAL_DRIVER
+  #include "stm32f7xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F7xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
new file mode 100644
index 0000000000..8c67585b9b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
@@ -0,0 +1,421 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    25-June-2015
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f7xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CONF_H
+#define __STM32F7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED  
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED  
+#define HAL_CRC_MODULE_ENABLED  
+#define HAL_CRYP_MODULE_ENABLED  
+#define HAL_DAC_MODULE_ENABLED  
+#define HAL_DCMI_MODULE_ENABLED 
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED 
+#define HAL_ETH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED  
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED   
+#define HAL_IWDG_MODULE_ENABLED 
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED   
+#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RNG_MODULE_ENABLED   
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED   
+#define HAL_SD_MODULE_ENABLED  
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED   
+#define HAL_TIM_MODULE_ENABLED   
+#define HAL_UART_MODULE_ENABLED 
+#define HAL_USART_MODULE_ENABLED 
+#define HAL_IRDA_MODULE_ENABLED 
+#define HAL_SMARTCARD_MODULE_ENABLED 
+#define HAL_WWDG_MODULE_ENABLED  
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)200)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  ART_ACCLERATOR_ENABLE        1 /* To enable instruction cache and prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f7xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32f7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f7xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
new file mode 100644
index 0000000000..9c3676eb68
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
@@ -0,0 +1,709 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    25-June-2015
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
+  *                           | (external 25MHz xtal) | (internal 16MHz clock)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)               | 216                   | 216
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)              | 216                   | 216
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)             |  54                   |  54
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)             | 108                   | 108
+  *-----------------------------------------------------------------------------
+  * USB capable               | YES                   |  NO
+  * with 48 MHz precise clock |                       |
+  *-----------------------------------------------------------------------------  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f7xx.h"
+#include "hal_tick.h"
+
+HAL_StatusTypeDef HAL_Init(void);
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+     on EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */ 
+/* #define DATA_IN_ExtSDRAM */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " 
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */ 
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = HSI_VALUE;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  // Enable CPU L1-Cache
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f7xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0;
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x50150005;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554005;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC000000C;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80020A0A;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80020A0A;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40010505;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+  
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  
+    /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55000555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00100555;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
+
+#endif /* DATA_IN_ExtSRAM */
+
+  (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  // Output clock on MCO2 pin(PC9) for debugging purpose
+  // Can be visualized on uSD card CN3 connector pin 8
+  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  // Enable power clock  
+  __PWR_CLK_ENABLE();
+  
+  // Enable HSE oscillator and activate PLL with HSE as source
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+  }
+  // Warning: this configuration is for a 25 MHz xtal clock only
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
+  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+  
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  // Activate the OverDrive to reach the 216 MHz Frequency
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+  
+  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+  
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  // Enable CPU L1-Cache
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
+  // Enable power clock  
+  __PWR_CLK_ENABLE();
+ 
+  // Enable HSI oscillator and activate PLL with HSI as source
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
+  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
+  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+  
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  // Activate the OverDrive to reach the 216 MHz Frequency
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+  
+  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
new file mode 100644
index 0000000000..529cb4a24d
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    25-June-2015
+  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F7XX_H
+#define __SYSTEM_STM32F7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F7xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+    */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F7XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 0068bb55d247391991e1f4d9c429b3e649710017 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 18 Jan 2016 11:16:06 +0100
Subject: [PATCH 47/78] [NUCLEO_F746ZG] cmsis toolchain files

---
 .../TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S | 463 +++++++++++
 .../TOOLCHAIN_ARM_MICRO/stm32f746zg.sct       |  45 ++
 .../TOOLCHAIN_ARM_MICRO/sys.cpp               |  56 ++
 .../TOOLCHAIN_ARM_STD/startup_stm32f746zg.S   | 436 +++++++++++
 .../TOOLCHAIN_ARM_STD/stm32f746zg.sct         |  45 ++
 .../TOOLCHAIN_ARM_STD/sys.cpp                 |  56 ++
 .../TOOLCHAIN_GCC_ARM/STM32F746ZG.ld          | 153 ++++
 .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S   | 596 ++++++++++++++
 .../TOOLCHAIN_IAR/startup_stm32f746xx.S       | 732 ++++++++++++++++++
 .../TOOLCHAIN_IAR/stm32f746zg.icf             |  35 +
 10 files changed, 2617 insertions(+)
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/sys.cpp
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/stm32f746zg.sct
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/sys.cpp
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
new file mode 100644
index 0000000000..71ee787e89
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
@@ -0,0 +1,463 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name          : startup_stm32f746xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 28-April-2015
+;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20050000 ; Top of RAM
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDMMC1_IRQHandler                  ; SDMMC1                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
new file mode 100644
index 0000000000..b87630da88
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2016, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F746ZG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1C8) (0x50000-0x1C8)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 0000000000..bb665909b9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
new file mode 100644
index 0000000000..92857c9fda
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
@@ -0,0 +1,436 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name          : startup_stm32f746xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 28-April-2015
+;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+__initial_sp    EQU     0x20050000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDMMC1_IRQHandler                  ; SDMMC1                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/stm32f746zg.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/stm32f746zg.sct
new file mode 100644
index 0000000000..b87630da88
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/stm32f746zg.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2016, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F746ZG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1C8) (0x50000-0x1C8)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..bb665909b9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
new file mode 100644
index 0000000000..198ac5c584
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+  RAM (rwx)  : ORIGIN = 0x200001C8, LENGTH = 320K - 0x1C8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
new file mode 100644
index 0000000000..1fcde5f2bd
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
@@ -0,0 +1,596 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f746xx.s
+  * @author    MCD Application Team
+  * Version    V1.0.0
+  * Date       28-April-2015
+  * @brief     STM32F746xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M7 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M7. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+   
+   
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FMC_IRQHandler                    /* FMC                          */                   
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     RNG_IRQHandler                    /* Rng                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */      
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5	 		              */
+  .word     SPI6_IRQHandler                   /* SPI6   			          */
+  .word     SAI1_IRQHandler                   /* SAI1						  */
+  .word     LTDC_IRQHandler                   /* LTDC					      */
+  .word     LTDC_ER_IRQHandler                /* LTDC error					  */
+  .word     DMA2D_IRQHandler                  /* DMA2D    				      */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     QUADSPI_IRQHandler                /* QUADSPI                      */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */  
+  
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FMC_IRQHandler            
+   .thumb_set FMC_IRQHandler,Default_Handler
+                     
+   .weak      SDMMC1_IRQHandler            
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+   
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler   
+
+   .weak      ETH_IRQHandler   
+   .thumb_set ETH_IRQHandler,Default_Handler
+   
+   .weak      ETH_WKUP_IRQHandler   
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler   
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler            
+   .thumb_set RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler                  
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler                  
+   .thumb_set UART8_IRQHandler,Default_Handler   
+
+   .weak      SPI4_IRQHandler            
+   .thumb_set SPI4_IRQHandler,Default_Handler
+   
+   .weak      SPI5_IRQHandler            
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler            
+   .thumb_set SPI6_IRQHandler,Default_Handler   
+
+   .weak      SAI1_IRQHandler            
+   .thumb_set SAI1_IRQHandler,Default_Handler
+   
+   .weak      LTDC_IRQHandler            
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler            
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler            
+   .thumb_set DMA2D_IRQHandler,Default_Handler   
+
+   .weak      SAI2_IRQHandler            
+   .thumb_set SAI2_IRQHandler,Default_Handler
+   
+   .weak      QUADSPI_IRQHandler            
+   .thumb_set QUADSPI_IRQHandler,Default_Handler
+ 
+   .weak      LPTIM1_IRQHandler            
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler            
+   .thumb_set CEC_IRQHandler,Default_Handler
+   
+   .weak      I2C4_EV_IRQHandler            
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler 
+ 
+   .weak      I2C4_ER_IRQHandler            
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+   .weak      SPDIF_RX_IRQHandler            
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/		
+ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
new file mode 100644
index 0000000000..70dad9c77c
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
@@ -0,0 +1,732 @@
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32f746xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 28-April-2015
+;* Description        : STM32F746xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+        DCD     FLASH_IRQHandler                  ; FLASH                                           
+        DCD     RCC_IRQHandler                    ; RCC                                             
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+        DCD     TIM2_IRQHandler                   ; TIM2                                            
+        DCD     TIM3_IRQHandler                   ; TIM3                                            
+        DCD     TIM4_IRQHandler                   ; TIM4                                            
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+        DCD     SPI1_IRQHandler                   ; SPI1                                            
+        DCD     SPI2_IRQHandler                   ; SPI2                                            
+        DCD     USART1_IRQHandler                 ; USART1                                          
+        DCD     USART2_IRQHandler                 ; USART2                                          
+        DCD     USART3_IRQHandler                 ; USART3                                          
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+        DCD     FMC_IRQHandler                    ; FMC                                            
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1                                            
+        DCD     TIM5_IRQHandler                   ; TIM5                                            
+        DCD     SPI3_IRQHandler                   ; SPI3                                            
+        DCD     UART4_IRQHandler                  ; UART4                                           
+        DCD     UART5_IRQHandler                  ; UART5                                           
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+        DCD     TIM7_IRQHandler                   ; TIM7                   
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+        DCD     ETH_IRQHandler                    ; Ethernet                                        
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+        DCD     USART6_IRQHandler                 ; USART6                                           
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+        DCD     DCMI_IRQHandler                   ; DCMI                                            
+        DCD     0                                 ; Reserved                                    
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     QUADSPI_IRQHandler                ; QUADSPI
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                             
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_BRK_TIM9_IRQHandler  
+        B TIM1_BRK_TIM9_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_UP_TIM10_IRQHandler  
+        B TIM1_UP_TIM10_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_TRG_COM_TIM11_IRQHandler  
+        B TIM1_TRG_COM_TIM11_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_FS_WKUP_IRQHandler  
+        B OTG_FS_WKUP_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler  
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN2_TX_IRQHandler  
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_RX0_IRQHandler  
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_RX1_IRQHandler  
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_SCE_IRQHandler  
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler  
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler  
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RNG_IRQHandler  
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)      
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+UART8_IRQHandler             
+        B UART8_IRQHandler
+        
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI4_IRQHandler
+        B SPI4_IRQHandler                 
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI5_IRQHandler   
+        B SPI5_IRQHandler                  
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI6_IRQHandler 
+        B SPI6_IRQHandler                    
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI1_IRQHandler  
+        B SAI1_IRQHandler                  
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_IRQHandler 
+        B LTDC_IRQHandler                     
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_ER_IRQHandler 
+        B LTDC_ER_IRQHandler                 
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler                  
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI2_IRQHandler 
+        B SAI2_IRQHandler          
+
+       PUBWEAK QUADSPI_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+QUADSPI_IRQHandler 
+        B QUADSPI_IRQHandler       
+        
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM1_IRQHandler 
+        B LPTIM1_IRQHandler   
+        
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CEC_IRQHandler 
+        B CEC_IRQHandler 
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_EV_IRQHandler 
+        B I2C4_EV_IRQHandler   
+        
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_ER_IRQHandler 
+        B I2C4_ER_IRQHandler 
+ 
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPDIF_RX_IRQHandler 
+        B SPDIF_RX_IRQHandler 
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf
new file mode 100644
index 0000000000..2982e0ddc7
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf
@@ -0,0 +1,35 @@
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x080FFFFF;
+
+/* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200001C7; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x200001C8;
+define symbol __region_RAM_end__      = 0x2004FFFF;
+
+define symbol __region_ITCMRAM_start__ = 0x00000000;
+define symbol __region_ITCMRAM_end__   = 0x00003FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__   = 0x8000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

From ddea20a775c72c7a49c0d100bd960f25c42743f1 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 21 Jan 2016 09:36:51 +0100
Subject: [PATCH 48/78] [NUCLEO_F746ZG] add exporters files

---
 .../export/gcc_arm_nucleo_f746zg.tmpl         |    1 +
 workspace_tools/export/gccarm.py              |    1 +
 .../export/iar_nucleo_f746zg.ewd.tmpl         | 2976 +++++++++++++++++
 .../export/iar_nucleo_f746zg.ewp.tmpl         | 1927 +++++++++++
 workspace_tools/export/uvision4.py            |    2 +
 .../export/uvision4_nucleo_f746zg.uvopt.tmpl  |  185 +
 .../export/uvision4_nucleo_f746zg.uvproj.tmpl |  446 +++
 7 files changed, 5538 insertions(+)
 create mode 100644 workspace_tools/export/gcc_arm_nucleo_f746zg.tmpl
 create mode 100644 workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl
 create mode 100644 workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
 create mode 100644 workspace_tools/export/uvision4_nucleo_f746zg.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_nucleo_f746zg.uvproj.tmpl

diff --git a/workspace_tools/export/gcc_arm_nucleo_f746zg.tmpl b/workspace_tools/export/gcc_arm_nucleo_f746zg.tmpl
new file mode 100644
index 0000000000..6e616cc884
--- /dev/null
+++ b/workspace_tools/export/gcc_arm_nucleo_f746zg.tmpl
@@ -0,0 +1 @@
+{% extends "gcc_arm_common.tmpl" %}
diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py
index 0d030ccac6..40e6bbdac8 100755
--- a/workspace_tools/export/gccarm.py
+++ b/workspace_tools/export/gccarm.py
@@ -82,6 +82,7 @@ class GccArm(Exporter):
         'NUCLEO_F303K8',
         'NUCLEO_F303RE',
         'NUCLEO_F334R8',
+        'NUCLEO_F746ZG',
         'DISCO_L053C8',
         'NUCLEO_L053R8',
         'NUCLEO_L073RZ',
diff --git a/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl b/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl
new file mode 100644
index 0000000000..882f379267
--- /dev/null
+++ b/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl
@@ -0,0 +1,2976 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F746ZG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.30.4.8186</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F756xG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>6</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>FlashBoardPathSlave</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>4</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCXds100BreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100DoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCXds100CatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockEdit</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCXds100HWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ResetList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100JtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ProbeList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.30.4.8186</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>ARMSIM_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>6</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>FlashBoardPathSlave</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>4</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCXds100BreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100DoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCXds100CatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockEdit</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCXds100HWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ResetList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100JtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ProbeList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
diff --git a/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl b/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
new file mode 100644
index 0000000000..9727b84c50
--- /dev/null
+++ b/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
@@ -0,0 +1,1927 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Debug\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F746ZG	ST STM32F746ZG</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>22</version>
+          <state>41</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>22</version>
+          <state>41</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>STM32F746ZG	ST STM32F746ZG</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>6</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>22</version>
+          <state>41</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          {% for s in symbols %}
+            <state>{{s}}</state>
+          {% endfor %}
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        {% for path in include_paths %}
+          <state>$PROJ_DIR$\{{path}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>{{name}}.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\{{linker_script}}</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state>--skip_dynamic_initialization</state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+        {% for library in libraries %}
+          <state>$PROJ_DIR$\{{library}}</state>
+        {% endfor %}
+        {% for object in object_files %}
+          <state>$PROJ_DIR$\{{object}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Release\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Release\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Release\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>Default	None</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>22</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>22</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>Default	None</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>22</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>NDEBUG</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>11111110</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCNoLiteralPool</name>
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+          <name>CCOptStrategySlave</name>
+          <version>0</version>
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+          <name>CCGuardCalls</name>
+          <state>1</state>
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+      </data>
+    </settings>
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+      <archiveVersion>2</archiveVersion>
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+          <name>ACaseSensitivity</name>
+          <state>1</state>
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+          <name>AWarnOne</name>
+          <state></state>
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+          <name>AWarnRange1</name>
+          <state></state>
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+          <name>AWarnRange2</name>
+          <state></state>
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+          <state>0</state>
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+          <name>AListHeader</name>
+          <state>1</state>
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+          <state>1</state>
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+          <name>Includes</name>
+          <state>0</state>
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+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
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+          <name>MacExps</name>
+          <state>1</state>
+        </option>
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+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>5.srec</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\generic.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  {{source_files}}
+</project>
+
+
diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index 466e02bbf3..d402812bb3 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -59,6 +59,7 @@ class Uvision4(Exporter):
         'NUCLEO_F410RB',
         'NUCLEO_F411RE',
         'NUCLEO_F446RE',
+        'NUCLEO_F746ZG',
         'NUCLEO_L053R8',
         'NUCLEO_L073RZ',
         'NUCLEO_L152RE',
@@ -126,6 +127,7 @@ class Uvision4(Exporter):
         'NUCLEO_F410RB',
         'NUCLEO_F411RE',
         'NUCLEO_F446RE',
+        'NUCLEO_F746ZG',
         'NUCLEO_L053R8',
         'NUCLEO_L073RZ',
         'NUCLEO_L152RE',
diff --git a/workspace_tools/export/uvision4_nucleo_f746zg.uvopt.tmpl b/workspace_tools/export/uvision4_nucleo_f746zg.uvopt.tmpl
new file mode 100644
index 0000000000..4df60993ac
--- /dev/null
+++ b/workspace_tools/export/uvision4_nucleo_f746zg.uvopt.tmpl
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM32F746ZG</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>1</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>11</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7x_TCM -FS1200000 -FL1100000 -FP0($$Device:STM32F756IG$Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F756IG$Flash\STM32F7x_TCM.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U066EFF535651727067055449 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZG$CMSIS\Flash\STM32F7x_1024.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_nucleo_f746zg.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f746zg.uvproj.tmpl
new file mode 100644
index 0000000000..82dc736b7d
--- /dev/null
+++ b/workspace_tools/export/uvision4_nucleo_f746zg.uvproj.tmpl
@@ -0,0 +1,446 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>STM32F746ZG</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F746ZG</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32F7xx_DFP.1.0.0</PackID>
+          <PackURL>http://www.keil.com/pack</PackURL>
+          <Cpu>IROM(0x08000000-0x080FFFFF) IRAM(0x20000000-0x2004FFFF) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId></DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F756IG$CMSIS\SVD\STM32F7x.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin -o build\{{name}}_STM32F746ZG.bin build\{{name}}.axf</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>11</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4107</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x50000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x50000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+                --any_placement=first_fit
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

From d47d87c869768fb30078b53057a8fa5ff01e5c2b Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 21 Jan 2016 09:37:21 +0100
Subject: [PATCH 49/78] [NUCLEO_F746ZG] 8MHz, not 25

---
 .../TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h               | 2 +-
 .../TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c  | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
index 8c67585b9b..313fa4355e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
@@ -102,7 +102,7 @@
   *        (when HSE is used as system clock source, directly or through the PLL).  
   */
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
index 9c3676eb68..4ff3b6b2a4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
@@ -133,7 +133,7 @@ HAL_StatusTypeDef HAL_Init(void);
   */
 
 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */ 
+#define USE_PLL_HSE_EXTC (1) /* Use external clock --> NOT USED ON THIS BOARD */ 
 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 
 /**
@@ -607,10 +607,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
   {
     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
   }
-  // Warning: this configuration is for a 25 MHz xtal clock only
+  // Warning: this configuration is for a 8 MHz xtal clock only
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
+  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
   RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
   RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
   RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB

From 1ecd69bd876912effd915317e1bda0331c211ceb Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Tue, 9 Feb 2016 17:58:46 +0100
Subject: [PATCH 50/78] [STMF7 family] add more SPI and I2C for the new
 NUCLEO_F746ZG platform

---
 .../hal/TARGET_STM/TARGET_STM32F7/i2c_api.c   |  5 +-
 .../hal/TARGET_STM/TARGET_STM32F7/spi_api.c   | 92 ++++++++++++++-----
 2 files changed, 71 insertions(+), 26 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/i2c_api.c
index b24c5d53f8..be16a137c0 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/i2c_api.c
@@ -46,11 +46,10 @@
 I2C_HandleTypeDef I2cHandle;
 
 int i2c1_inited = 0;
-/* Ready for next F7 devices
 int i2c2_inited = 0;
 int i2c3_inited = 0;
 int i2c4_inited = 0;
-*/
+
 
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 {
@@ -73,7 +72,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
         pin_mode(scl, OpenDrain);
     }
 
-    /* Ready for next F7 devices
     #if defined(I2C2_BASE)
         if ((obj->i2c == I2C_2) && !i2c2_inited) {
             i2c2_inited = 1;
@@ -112,7 +110,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
             pin_mode(scl, OpenDrain);
         }
     #endif
-    */
 
     // Reset to clear pending flags if any
     i2c_reset(obj);
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/spi_api.c
index 7b0ab7b422..10f163a271 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/spi_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/spi_api.c
@@ -80,14 +80,30 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     MBED_ASSERT(obj->spi != (SPIName)NC);
 
     // Enable SPI clock
+    if (obj->spi == SPI_1) {
+        __HAL_RCC_SPI1_CLK_ENABLE();
+    }
+
     if (obj->spi == SPI_2) {
         __HAL_RCC_SPI2_CLK_ENABLE();
     }
 
+    if (obj->spi == SPI_3) {
+        __HAL_RCC_SPI3_CLK_ENABLE();
+    }
+
+    if (obj->spi == SPI_4) {
+        __HAL_RCC_SPI4_CLK_ENABLE();
+    }
+
     if (obj->spi == SPI_5) {
         __HAL_RCC_SPI5_CLK_ENABLE();
     }
 
+    if (obj->spi == SPI_6) {
+        __HAL_RCC_SPI6_CLK_ENABLE();
+    }
+
     // Configure the SPI pins
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
     pinmap_pinout(miso, PinMap_SPI_MISO);
@@ -116,18 +132,42 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
 void spi_free(spi_t *obj)
 {
     // Reset SPI and disable clock
+    if (obj->spi == SPI_1) {
+        __HAL_RCC_SPI1_FORCE_RESET();
+        __HAL_RCC_SPI1_RELEASE_RESET();
+        __HAL_RCC_SPI1_CLK_DISABLE();
+    }
+
     if (obj->spi == SPI_2) {
         __HAL_RCC_SPI2_FORCE_RESET();
         __HAL_RCC_SPI2_RELEASE_RESET();
         __HAL_RCC_SPI2_CLK_DISABLE();
     }
 
+    if (obj->spi == SPI_3) {
+        __HAL_RCC_SPI3_FORCE_RESET();
+        __HAL_RCC_SPI3_RELEASE_RESET();
+        __HAL_RCC_SPI3_CLK_DISABLE();
+    }
+    
+    if (obj->spi == SPI_4) {
+        __HAL_RCC_SPI4_FORCE_RESET();
+        __HAL_RCC_SPI4_RELEASE_RESET();
+        __HAL_RCC_SPI4_CLK_DISABLE();
+    }
+
     if (obj->spi == SPI_5) {
         __HAL_RCC_SPI5_FORCE_RESET();
         __HAL_RCC_SPI5_RELEASE_RESET();
         __HAL_RCC_SPI5_CLK_DISABLE();
     }
 
+    if (obj->spi == SPI_6) {
+        __HAL_RCC_SPI6_FORCE_RESET();
+        __HAL_RCC_SPI6_RELEASE_RESET();
+        __HAL_RCC_SPI6_CLK_DISABLE();
+    }
+
     // Configure GPIOs
     pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
     pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
@@ -175,9 +215,33 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
 void spi_frequency(spi_t *obj, int hz)
 {
     // The frequencies are obtained with:
-    // - SPI2 clock =  54 MHz (APB1 clock)
-    // - SPI5 clock = 108 MHz (APB2 clock)
-    if (obj->spi == SPI_2) {
+    // - SPI2/SPI3 clock =  54 MHz (APB1 clock)
+    // - SPI1/SPI4/SPI5/SPI6 clocks = 108 MHz (APB2 clock)
+    switch(obj->spi) {
+      case SPI_1:
+      case SPI_4:
+      case SPI_5:
+      case SPI_6:
+                if (hz < 800000) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 422 kHz
+        } else if ((hz >= 800000) && (hz < 1000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 844 kHz
+        } else if ((hz >= 1000000) && (hz < 3000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.69 MHz
+        } else if ((hz >= 3000000) && (hz < 6000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 3.38 MHz
+        } else if ((hz >= 6000000) && (hz < 12000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 6.75 MHz
+        } else if ((hz >= 12000000) && (hz < 24000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 13.5 MHz
+        } else if ((hz >= 24000000) && (hz < 54000000)) {
+            obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 27 MHz
+        } else { // >= 54000000
+            obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 54 MHz
+        }
+        break;
+      case SPI_2:
+      case SPI_3:
         if (hz < 400000) {
             obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 211 kHz
         } else if ((hz >= 400000) && (hz < 800000)) {
@@ -195,27 +259,11 @@ void spi_frequency(spi_t *obj, int hz)
         } else { // >= 24000000
             obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 27 MHz
         }
-    } else if (obj->spi == SPI_5) {
-        if (hz < 800000) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 422 kHz
-        } else if ((hz >= 800000) && (hz < 1000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 844 kHz
-        } else if ((hz >= 1000000) && (hz < 3000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.69 MHz
-        } else if ((hz >= 3000000) && (hz < 6000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 3.38 MHz
-        } else if ((hz >= 6000000) && (hz < 12000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 6.75 MHz
-        } else if ((hz >= 12000000) && (hz < 24000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 13.5 MHz
-        } else if ((hz >= 24000000) && (hz < 54000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 27 MHz
-        } else { // >= 54000000
-            obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 54 MHz
-        }
-    } else {
+        break;
+      default:
         return;
     }
+    
     init_spi(obj);
 }
 

From 3b3f89294ee732576436060268ad0f030cd31fec Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Tue, 9 Feb 2016 17:59:38 +0100
Subject: [PATCH 51/78] [NUCLEO_F746ZG] fix pins and system files after manual
 and automatic test phase

---
 .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.c   | 248 +-----------------
 .../TARGET_NUCLEO_F746ZG/PeripheralPins.c     |  15 +-
 2 files changed, 11 insertions(+), 252 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
index 4ff3b6b2a4..9a9ffb49e3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
@@ -84,7 +84,7 @@
 HAL_StatusTypeDef HAL_Init(void);
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
@@ -108,15 +108,6 @@ HAL_StatusTypeDef HAL_Init(void);
   */
 
 /************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " 
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
-
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
@@ -133,7 +124,7 @@ HAL_StatusTypeDef HAL_Init(void);
   */
 
 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock --> NOT USED ON THIS BOARD */ 
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */ 
 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 
 /**
@@ -162,10 +153,6 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
   * @{
   */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 #endif
@@ -212,10 +199,6 @@ void SystemInit(void)
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
 
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@@ -324,231 +307,6 @@ void SystemCoreClockUpdate(void)
   SystemCoreClock >>= tmp;
 }
 
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif /* DATA_IN_ExtSDRAM */
-
-#if defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
 /**
   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
   *               AHB/APBx prescalers and Flash settings
@@ -581,7 +339,7 @@ void SetSysClock(void)
   }
   
   // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on uSD card CN3 connector pin 8
+  // Can be visualized on CN8 connector pin 4
   //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
index 04a8d7ebae..f128dd2320 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
@@ -44,7 +44,7 @@ const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0  - ARDUINO A0
  // {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1  (used by ethernet)
  // {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2  (used by ethernet)
-    {PA_3,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+    {PA_3,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN2
     {PA_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
     {PA_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5  - ARDUINO D13
     {PA_6,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6  - ARDUINO D12
@@ -119,10 +119,10 @@ const PinMap PinMap_PWM[] = {
  // {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 1)}, // TIM8_CH1N
     {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1
  // {PA_6,  PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
-    {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 1)}, // TIM1_CH1N (remove JP6 to use it)
- // {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2  (remove JP6 to use it)
- // {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 1)}, // TIM8_CH1N (remove JP6 to use it)
- // {PA_7,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (remove JP6 to use it)
+ // {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 1)}, // TIM1_CH1N (used by ethernet)
+ // {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2  (used by ethernet)
+ // {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 1)}, // TIM8_CH1N (used by ethernet)
+ // {PA_7,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet)
     {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  1, 0)}, // TIM1_CH1
  // {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 0)}, // TIM1_CH2 (used by USB)
  // {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 0)}, // TIM1_CH3 (used by USB)
@@ -176,6 +176,7 @@ const PinMap PinMap_PWM[] = {
     {PE_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 0)}, // TIM1_CH2
     {PE_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 1)}, // TIM1_CH3N
     {PE_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 0)}, // TIM1_CH3
+    {PE_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  4, 0)}, // TIM1_CH4
 
     {PF_6,  PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
     {PF_7,  PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
@@ -214,8 +215,8 @@ const PinMap PinMap_UART_RX[] = {
     // {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by LED2)
        {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
        {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
-       {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    // {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    // {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+       {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
        {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
        {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
        {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_RX

From d53f444a6fab6942ac578b9112b8d21ba721db9d Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 16:40:12 +0100
Subject: [PATCH 52/78] [STM32F7 family] revert RTC change in this PR that is
 due to new platform. It will be done through a separate PR.

---
 .../hal/TARGET_STM/TARGET_STM32F7/rtc_api.c   | 85 ++++++++++---------
 1 file changed, 43 insertions(+), 42 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
index 276c13a176..d25acb860f 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
@@ -40,58 +40,59 @@ void rtc_init(void)
     RCC_OscInitTypeDef RCC_OscInitStruct;
     uint32_t rtc_freq = 0;
 
-    RtcHandle.Instance = RTC;
+        RtcHandle.Instance = RTC;
 
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
+        // Enable Power clock
+        __PWR_CLK_ENABLE();
 
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
+        // Enable access to Backup domain
+        HAL_PWR_EnableBkUpAccess();
 
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
+        // Reset Backup domain
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
 
-    // Enable LSE Oscillator
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        // Connect LSE to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-        rtc_freq = LSE_VALUE;
-    } else {
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+        // Enable LSE Oscillator
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
         RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("RTC error: LSI clock initialization failed.");
+        RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+            // Connect LSE to RTC
+            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+            rtc_freq = LSE_VALUE;
+        } else {
+            // Enable LSI clock
+            RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+            RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+            RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+            RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+            if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+                error("RTC error: LSI clock initialization failed.");
+            }
+            // Connect LSI to RTC
+            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+            // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+            rtc_freq = LSI_VALUE;
         }
-        // Connect LSI to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-        // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
-        rtc_freq = LSI_VALUE;
-    }
 
-    // Check if RTC is already initialized
-    if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return;
+    if((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) {     // RTC initialization and status register (RTC_ISR), cold start (with no backup domain power) RTC reset value
 
-    // Enable RTC
-    __HAL_RCC_RTC_ENABLE();
+        // Enable RTC
+        __HAL_RCC_RTC_ENABLE();
 
-    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-    RtcHandle.Init.AsynchPrediv   = 127;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+        RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+        RtcHandle.Init.AsynchPrediv   = 127;
+        RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
+        RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+        RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+        RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+        if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+            error("RTC error: RTC initialization failed.");
+        }
 
-    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
     }
 }
 

From f3816bdd2590cf818e7788ef30a905d8653fd32b Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Fri, 26 Feb 2016 11:25:41 +0000
Subject: [PATCH 53/78] Exporter IAR - nucleo f746 template fix

Remove ewd file, fix .ewp file - remove jinja2, to have valid ewp file
---
 .../export/iar_nucleo_f746zg.ewd.tmpl         | 2976 -----------------
 .../export/iar_nucleo_f746zg.ewp.tmpl         |   20 +-
 2 files changed, 5 insertions(+), 2991 deletions(-)
 delete mode 100644 workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl

diff --git a/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl b/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl
deleted file mode 100644
index 882f379267..0000000000
--- a/workspace_tools/export/iar_nucleo_f746zg.ewd.tmpl
+++ /dev/null
@@ -1,2976 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>Debug</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>26</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F746ZG.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>7.30.4.8186</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>STLINK_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>7.40.3.8937</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F756xG.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDeviceConfigMacroFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDebuggerExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCAllMTBOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreNrOfCores</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCMulticoreMaster</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCMulticorePort</name>
-          <state>53461</state>
-        </option>
-        <option>
-          <name>OCMulticoreWorkspace</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveProject</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCMulticoreSlaveConfiguration</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
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-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>RDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CRDIDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CRDILogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRDILogFileEdit</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCRDIHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>STLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSTLinkResetList</name>
-          <version>1</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCSwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCSwoClockEdit</name>
-          <state>2000</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>CThirdPartyDriverDll</name>
-          <state>###Uninitialized###</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CThirdPartyLogFileEditB</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>XDS100_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>4</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCXDS100AttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TIPackageOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>TIPackage</name>
-          <state></state>
-        </option>
-        <option>
-          <name>BoardFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCXds100BreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100DoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UpdateBreakpoints</name>
-          <state>_call_main</state>
-        </option>
-        <option>
-          <name>CCXds100CatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CatchDummy</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100CpuClockEdit</name>
-          <state>72.0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockAuto</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100SwoClockEdit</name>
-          <state>1000</state>
-        </option>
-        <option>
-          <name>CCXds100HWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ResetList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNo</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CCXds100UsbSerialNoSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100JtagSpeedList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100InterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCXds100ProbeList</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
-        <loadFlag>1</loadFlag>
-      </plugin>
-      <plugin>
-        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
-      </plugin>
-    </debuggerPlugins>
-  </configuration>
-</project>
-
diff --git a/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl b/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
index 9727b84c50..228fbf8b18 100644
--- a/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
+++ b/workspace_tools/export/iar_nucleo_f746zg.ewp.tmpl
@@ -185,9 +185,7 @@
         </option>
         <option>
           <name>CCDefines</name>
-          {% for s in symbols %}
-            <state>{{s}}</state>
-          {% endfor %}
+            <state></state>
         </option>
         <option>
           <name>CCPreprocFile</name>
@@ -316,9 +314,7 @@
         </option>
         <option>
           <name>CCIncludePath2</name>
-        {% for path in include_paths %}
-          <state>$PROJ_DIR$\{{path}}</state>
-        {% endfor %}
+          <state></state>
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -610,7 +606,7 @@
         </option>
         <option>
           <name>OOCOutputFile</name>
-          <state>{{name}}.bin</state>
+          <state>name.bin</state>
         </option>
         <option>
           <name>OOCCommandLineProducer</name>
@@ -729,7 +725,7 @@
         </option>
         <option>
           <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\{{linker_script}}</state>
+          <state></state>
         </option>
         <option>
           <name>IlinkIcfFileSlave</name>
@@ -777,12 +773,7 @@
         </option>
         <option>
           <name>IlinkAdditionalLibs</name>
-        {% for library in libraries %}
-          <state>$PROJ_DIR$\{{library}}</state>
-        {% endfor %}
-        {% for object in object_files %}
-          <state>$PROJ_DIR$\{{object}}</state>
-        {% endfor %}
+          <state></state>
         </option>
         <option>
           <name>IlinkOverrideProgramEntryLabel</name>
@@ -1921,7 +1912,6 @@
       <data/>
     </settings>
   </configuration>
-  {{source_files}}
 </project>
 
 

From 121804a99d058122097dc72cb02236fa317a1cb4 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Fri, 26 Feb 2016 11:28:34 +0000
Subject: [PATCH 54/78] Target - nucleo f746 - progen data aligned to master
 branch

---
 workspace_tools/targets.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index 1dcca62622..b1e6387b2a 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -848,7 +848,12 @@ class NUCLEO_F746ZG(Target):
         self.extra_labels = ['STM', 'STM32F7', 'STM32F746', 'STM32F746ZG']
         self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
         self.detect_code = ["0816"]
-        self.progen_target ='nucleo-f746zg'
+        self.progen = {
+            "target":"nucleo-f746zg",
+            "iar": {
+                "template": [os.path.join(os.path.dirname(__file__), 'export', 'iar_nucleo_f746cg.ewp.tmpl')],
+            }
+        }
 
 class NUCLEO_L053R8(Target):
     def __init__(self):

From 65355e26103531c456c93a349a5466a9d8811f14 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Fri, 26 Feb 2016 13:00:47 +0000
Subject: [PATCH 55/78] Target - remove cortex-m7 IAR support for 2 targets

They will be reenabled once we update IAR version for the release/test
---
 workspace_tools/targets.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index b1e6387b2a..54ce5def01 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -846,7 +846,7 @@ class NUCLEO_F746ZG(Target):
         Target.__init__(self)
         self.core = "Cortex-M7F"
         self.extra_labels = ['STM', 'STM32F7', 'STM32F746', 'STM32F746ZG']
-        self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
+        self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
         self.detect_code = ["0816"]
         self.progen = {
             "target":"nucleo-f746zg",
@@ -1023,7 +1023,7 @@ class DISCO_F746NG(Target):
         Target.__init__(self)
         self.core = "Cortex-M7F"
         self.extra_labels = ['STM', 'STM32F7', 'STM32F746', 'STM32F746NG']
-        self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
+        self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
         self.detect_code = ["0815"]
         self.progen = {
             "target":"disco-f746ng",

From 775c5c9eb242e2bd7d14351496ab7188ea6a8432 Mon Sep 17 00:00:00 2001
From: dc37 <rehdblob@gmail.com>
Date: Fri, 26 Feb 2016 19:42:23 -0600
Subject: [PATCH 56/78] Fix clock configuration for LPC1549.

Datasheet (Table 82) says MSEL bits should be 5, and the PSEL bits should
be 1, for the correct FCCO frequency of 288MHz. The current configuration
has FCCO = 144MHz, which is technically out of spec.
Tested on a custom LPC1549 board with crystal oscillator running at 12MHz.
---
 .../cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c        | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
index 86dbd933ed..e5704f1acf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
@@ -73,14 +73,14 @@
 //       <o.0..5> MSEL: Feedback Divider Selection
 //              <i> M = MSEL + 1
 //            <0-31>
-//       <o.5..7> PSEL: Post Divider Selection
+//       <o.6..7> PSEL: Post Divider Selection
 //              <i> Post divider ratio P. Division ratio is 2 * P
 //            <0=> P = 1
 //            <1=> P = 2
 //            <2=> P = 4
 //            <3=> P = 8
 //     </h>
-#define SYSPLLCTRL_Val        0x00000005              // Reset value: 0x000
+#define SYSPLLCTRL_Val        0x00000045              // Reset value: 0x000
 //
 //     <o.0..7>   System AHB Clock Divider (SYSAHBCLKDIV.DIV)
 //            <i> Divides main clock to provide system clock to core, memories, and peripherals.
@@ -156,7 +156,7 @@
 //            <2=> P = 4
 //            <3=> P = 8
 //     </h>
-#define SCTPLLCTRL_Val        0x00000005              // Reset value: 0x000
+#define SCTPLLCTRL_Val        0x00000045              // Reset value: 0x000
 //
 //     <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
 //                   <0=> IRC Oscillator

From 1a3a19bb0819fb1ebbb4dddd6ab9c3d4006d456b Mon Sep 17 00:00:00 2001
From: mtkrtk <mtkrtk@gmail.com>
Date: Mon, 29 Feb 2016 17:06:32 +0900
Subject: [PATCH 57/78] Fix analogin peripheral names

---
 .../targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c
index 80ebd767ea..90dc113be4 100644
--- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c
+++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c
@@ -29,9 +29,9 @@ static const PinMap PinMap_ADC[] = {
     {P1_9,  AN1, 1},
     {P1_10, AN2, 1},
     {P1_11, AN3, 1},
-    {P1_12, AN3, 1},
+    {P1_12, AN4, 1},
     {P1_13, AN5, 1},
-    {P1_14, AN5, 1},
+    {P1_14, AN6, 1},
     {P1_15, AN7, 1},
     {NC,    NC,  0}
 };

From bec257786a3ae7a2d3f373dea395ede94cf311de Mon Sep 17 00:00:00 2001
From: Peter Conheeney <Peter.Conheeney@arm.com>
Date: Mon, 29 Feb 2016 12:02:47 +0000
Subject: [PATCH 58/78] commit of latest changes to arduino support, plus fixes
 for IOTSS BEID

---
 .../CMSDK_BEID.h                              | 170 +++---
 .../SMM_MPS2.h                                | 150 +++--
 .../TOOLCHAIN_ARM_STD/MPS2.sct                |  47 ++
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 358 +++++++++++
 .../TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h  |  42 ++
 .../TARGET_IOTSS_BEID/cmsis_nvic.c            |  58 ++
 .../TARGET_IOTSS_BEID/cmsis_nvic.h            |  54 ++
 .../TARGET_IOTSS_BEID/peripherallink.h        |  45 ++
 .../TARGET_IOTSS_BEID/system_CMSDK_BEID.c     |  95 +++
 .../TARGET_IOTSS_BEID/system_CMSDK_BEID.h     |  76 +++
 .../TOOLCHAIN_ARM_STD/MPS2.sct                |  15 -
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 291 ---------
 .../TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h   |  14 -
 .../TARGET_MPS2_BEID/cmsis_nvic.c             |  30 -
 .../TARGET_MPS2_BEID/cmsis_nvic.h             |  26 -
 .../TARGET_MPS2_BEID/peripherallink.h         |  34 --
 .../TARGET_MPS2_BEID/system_CMSDK_BEID.c      |  95 ---
 .../TARGET_MPS2_BEID/system_CMSDK_BEID.h      |  75 ---
 .../TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h | 135 ++---
 .../TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h  | 119 ++--
 .../TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct |  50 +-
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 157 +++--
 .../TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h     |  46 +-
 .../TARGET_MPS2_M0/cmsis_nvic.c               |  52 +-
 .../TARGET_MPS2_M0/cmsis_nvic.h               |  48 +-
 .../TARGET_MPS2_M0/peripherallink.h           |  46 +-
 .../TARGET_MPS2_M0/system_CMSDK_CM0.c         |  50 +-
 .../TARGET_MPS2_M0/system_CMSDK_CM0.h         |  50 +-
 .../TARGET_MPS2_M0P/CMSDK_CM0plus.h           | 137 ++---
 .../TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h | 119 ++--
 .../TOOLCHAIN_ARM_STD/MPS2.sct                |  50 +-
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 163 +++--
 .../TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h    |  46 +-
 .../TARGET_MPS2_M0P/cmsis_nvic.c              |  52 +-
 .../TARGET_MPS2_M0P/cmsis_nvic.h              |  48 +-
 .../TARGET_MPS2_M0P/peripherallink.h          |  46 +-
 .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.c    |  51 +-
 .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.h    |  50 +-
 .../TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h | 121 ++--
 .../TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h  | 119 ++--
 .../TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct |  50 +-
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 157 +++--
 .../TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h     |  46 +-
 .../TARGET_MPS2_M3/cmsis_nvic.c               |  46 +-
 .../TARGET_MPS2_M3/cmsis_nvic.h               |  48 +-
 .../TARGET_MPS2_M3/peripherallink.h           |  46 +-
 .../TARGET_MPS2_M3/system_CMSDK_CM3.c         |  50 +-
 .../TARGET_MPS2_M3/system_CMSDK_CM3.h         |  50 +-
 .../TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h | 281 ++++-----
 .../TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h  | 119 ++--
 .../TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct |  50 +-
 .../TOOLCHAIN_ARM_STD/startup_MPS2.s          | 129 ++--
 .../TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h     |  46 +-
 .../TARGET_MPS2_M4/cmsis_nvic.c               |  46 +-
 .../TARGET_MPS2_M4/cmsis_nvic.h               |  48 +-
 .../TARGET_MPS2_M4/peripherallink.h           |  46 +-
 .../TARGET_MPS2_M4/system_CMSDK_CM4.c         |  51 +-
 .../TARGET_MPS2_M4/system_CMSDK_CM4.h         |  51 +-
 .../TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h |  67 +-
 .../TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h  |  37 +-
 .../TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct |   6 +-
 .../TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s     |  85 ++-
 .../TOOLCHAIN_GCC_ARM/gcc_arm.ld              | 195 ------
 .../TOOLCHAIN_GCC_ARM/startup_ARMCM7.s        | 314 ----------
 .../TARGET_MPS2_M7/cmsis_nvic.h               |   2 +-
 .../TARGET_MPS2_M7/system_CMSDK_CM7.c         |   9 +-
 .../TARGET_MPS2_M7/system_CMSDK_CM7.h         |   6 +-
 .../TARGET_IOTSS/PeripheralNames.h            |  91 +++
 .../TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h    | 241 ++++++++
 .../TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h   |  31 +
 .../TARGET_IOTSS/SDK/ETH_MPS2.c               | 450 ++++++++++++++
 .../TARGET_IOTSS/SDK/ETH_MPS2.h               |  65 ++
 .../TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c    |  90 +++
 .../TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h    |  34 ++
 .../TARGET_IOTSS/SDK/mps2_ethernet_api.c      | 166 +++++
 .../TARGET_IOTSS/SDK/mps2_ethernet_api.h      |  57 ++
 .../TARGET_IOTSS/analogin_api.c               | 110 ++++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h  |  64 ++
 .../TARGET_IOTSS/ethernet_api.c               | 164 +++++
 .../TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c    | 140 +++++
 .../TARGET_IOTSS/gpio_irq_api.c               | 241 ++++++++
 .../TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h |  55 ++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c | 542 +++++++++++++++++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h |  82 +++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c  |  28 +
 .../TARGET_ARM_SSG/TARGET_IOTSS/port_api.c    |  68 +++
 .../TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c  | 367 +++++++++++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c | 286 +++++++++
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h | 174 ++++++
 .../TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c   |  84 +++
 .../TARGET_MPS2/PeripheralNames.h             |  30 +-
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h | 309 ++++++----
 .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c |  21 +-
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c |  12 +-
 .../TARGET_MPS2/SDK/mps2_ethernet_api.c       |  53 +-
 .../TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c | 110 ++++
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/device.h   |   4 +-
 .../TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c |  10 +-
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c | 180 +++---
 .../TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c | 318 +++++-----
 .../TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h  |  18 +-
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c  | 573 +++++++++++-------
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h  |  12 +-
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c   |   4 +-
 .../TARGET_ARM_SSG/TARGET_MPS2/serial_api.c   | 233 +++++--
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c  | 115 +++-
 .../TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c    |  26 +-
 workspace_tools/export/uvision4.py            |   6 +
 .../export/uvision4_arm_iotss_beid.uvopt.tmpl | 190 ++++++
 .../uvision4_arm_iotss_beid.uvproj.tmpl       | 428 +++++++++++++
 .../export/uvision4_arm_mps2_m0.uvopt.tmpl    | 190 ++++++
 .../export/uvision4_arm_mps2_m0.uvproj.tmpl   | 428 +++++++++++++
 .../export/uvision4_arm_mps2_m0p.uvopt.tmpl   | 190 ++++++
 .../export/uvision4_arm_mps2_m0p.uvproj.tmpl  | 428 +++++++++++++
 .../export/uvision4_arm_mps2_m3.uvopt.tmpl    | 190 ++++++
 .../export/uvision4_arm_mps2_m3.uvproj.tmpl   | 428 +++++++++++++
 .../export/uvision4_arm_mps2_m4.uvopt.tmpl    | 190 ++++++
 .../export/uvision4_arm_mps2_m4.uvproj.tmpl   | 428 +++++++++++++
 .../export/uvision4_arm_mps2_m7.uvopt.tmpl    | 190 ++++++
 .../export/uvision4_arm_mps2_m7.uvproj.tmpl   | 428 +++++++++++++
 .../host_tests_plugins/module_copy_mps2.py    |   6 +-
 workspace_tools/targets.py                    |  20 +-
 122 files changed, 11281 insertions(+), 3628 deletions(-)
 rename libraries/mbed/targets/cmsis/TARGET_ARM_SSG/{TARGET_MPS2_BEID => TARGET_IOTSS_BEID}/CMSDK_BEID.h (88%)
 rename libraries/mbed/targets/cmsis/TARGET_ARM_SSG/{TARGET_MPS2_BEID => TARGET_IOTSS_BEID}/SMM_MPS2.h (90%)
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c
 create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld
 delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c
 create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c
 create mode 100644 workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0p.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m3.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m4.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m4.uvproj.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl
 create mode 100644 workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl

diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h
similarity index 88%
rename from libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h
rename to libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h
index 6c1b55ec69..e4cff93f8f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h
@@ -1,39 +1,39 @@
-/**************************************************************************//**
- * @file     CMSDK_BEID.h
- * @brief    CMSIS Core Peripheral Access Layer Header File for
- *           CMSDK_BEID Device
- * @version  V3.02
- * @date     15. November 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file     CMSDK_BEID.h
+* @brief    CMSIS Core Peripheral Access Layer Header File for
+*           CMSDK_BEID Device
+*
+*******************************************************************************/
 
 
 #ifndef CMSDK_BEID_H
@@ -59,40 +59,61 @@ typedef enum IRQn
   PendSV_IRQn                   =  -2,        /* 14 Pend SV Interrupt               */
   SysTick_IRQn                  =  -1,        /* 15 System Tick Interrupt           */
 
-/* ----------------------  CMSDK_BEID Specific Interrupt Numbers  ------------------ */
-  UARTRX0_IRQn                  = 0,       /* UART 0 RX Interrupt                   */
-  UARTTX0_IRQn                  = 1,       /* UART 0 TX Interrupt                   */
-  UARTRX1_IRQn                  = 2,       /* UART 1 RX Interrupt                   */
-  UARTTX1_IRQn                  = 3,       /* UART 1 TX Interrupt                   */
-  UARTRX2_IRQn                  = 4,       /* UART 2 RX Interrupt                   */
-  UARTTX2_IRQn                  = 5,       /* UART 2 TX Interrupt                   */
-  UARTRX3_IRQn                  = 6,       /* Was PORT0_ALL_IRQn Port 1 combined Interrupt             */
-  UARTTX3_IRQn                  = 7,       /* Was PORT1_ALL_IRQn Port 1 combined Interrupt             */
+/* ----------------------  CMSDK_CM3 Specific Interrupt Numbers  ------------------ */
+  UART0_IRQn                    = 0,       /* UART 0 RX and TX Combined Interrupt   */
+  Spare_IRQn                    = 1,       /* Undefined                             */
+  UART1_IRQn                    = 2,       /* UART 1 RX and TX Combined Interrupt   */
+  I2C0_IRQn                     = 3,       /* I2C 0 Interrupt                       */
+  I2C1_IRQn                     = 4,       /* I2C 1 Interrupt                       */
+  RTC_IRQn                      = 5,       /* RTC Interrupt                         */
+  PORT0_ALL_IRQn                = 6,       /* GPIO Port 0 combined Interrupt        */
+  PORT1_ALL_IRQn                = 7,       /* GPIO Port 1 combined Interrupt        */
   TIMER0_IRQn                   = 8,       /* TIMER 0 Interrupt                     */
   TIMER1_IRQn                   = 9,       /* TIMER 1 Interrupt                     */
   DUALTIMER_IRQn                = 10,      /* Dual Timer Interrupt                  */
-  SPI_IRQn                      = 11,      /* SPI Interrupt                         */
+  SPI0_IRQn                     = 11,      /* SPI 0 Interrupt                       */
   UARTOVF_IRQn                  = 12,      /* UART 0,1,2 Overflow Interrupt         */
-  ETHERNET_IRQn                 = 13,      /* Ethernet Interrupt                    */
-  I2S_IRQn                      = 14,      /* I2S Interrupt                         */
+  SPI1_IRQn                     = 13,      /* SPI 1 Interrupt                       */
+  RESERVED0_IRQn                = 14,      /* Reserved                              */
   TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /* All P0 I/O pins used as irq source    */
-  PORT0_1_IRQn                  = 17,      /* There are 16 pins in total            */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+  PORT01_0_IRQn                 = 16,      /* GPIO Port 0 pin 0 Handler             */
+  PORT01_1_IRQn                 = 17,      /* GPIO Port 0 pin 1 Handler             */
+  PORT01_2_IRQn                 = 18,      /* GPIO Port 0 pin 2 Handler             */
+  PORT01_3_IRQn                 = 19,      /* GPIO Port 0 pin 3 Handler             */
+  PORT01_4_IRQn                 = 20,      /* GPIO Port 0 pin 4 Handler             */
+  PORT01_5_IRQn                 = 21,      /* GPIO Port 0 pin 5 Handler             */
+  PORT01_6_IRQn                 = 22,      /* GPIO Port 0 pin 6 Handler             */
+  PORT01_7_IRQn                 = 23,      /* GPIO Port 0 pin 7 Handler             */
+  PORT01_8_IRQn                 = 24,      /* GPIO Port 0 pin 8 Handler             */
+  PORT01_9_IRQn                 = 25,      /* GPIO Port 0 pin 9 Handler             */
+  PORT01_10_IRQn                = 26,      /* GPIO Port 0 pin 10 Handler            */
+  PORT01_11_IRQn                = 27,      /* GPIO Port 0 pin 11 Handler            */
+  PORT01_12_IRQn                = 28,      /* GPIO Port 0 pin 12 Handler            */
+  PORT01_13_IRQn                = 29,      /* GPIO Port 0 pin 13 Handler            */
+  PORT01_14_IRQn                = 30,      /* GPIO Port 0 pin 14 Handler            */
+  PORT01_15_IRQn                = 31,      /* GPIO Port 0 pin 15 Handler            */
+  SYSERROR_IRQn                 = 32,      /* System Error Interrupt                */
+  EFLASH_IRQn                   = 33,      /* Embedded Flash Interrupt              */
+  RESERVED1_IRQn                = 34,      /* Reserved                              */
+  RESERVED2_IRQn                = 35,      /* Reserved                              */
+  RESERVED3_IRQn                = 36,      /* Reserved                              */
+  RESERVED4_IRQn                = 37,      /* Reserved                              */
+  RESERVED5_IRQn                = 38,      /* Reserved                              */
+  RESERVED6_IRQn                = 39,      /* Reserved                              */
+  RESERVED7_IRQn                = 40,      /* Reserved                              */
+  RESERVED8_IRQn                = 41,      /* Reserved                              */
+  PORT2_ALL_IRQn                = 42,      /* GPIO Port 2 combined Interrupt        */
+  PORT3_ALL_IRQn                = 43,      /* GPIO Port 3 combined Interrupt        */
+  TRNG_IRQn                     = 44,      /* Random number generator Interrupt     */
+  UART2_IRQn                    = 45,      /* UART 2 RX and TX Combined Interrupt   */
+  UART3_IRQn                    = 46,      /* UART 3 RX and TX Combined Interrupt   */
+  ETHERNET_IRQn                 = 47,      /* Ethernet interrupt     t.b.a.         */
+  I2S_IRQn                      = 48,      /* I2S Interrupt                         */
+  MPS2_SPI0_IRQn                = 49,      /* SPI Interrupt (spi header)            */
+  MPS2_SPI1_IRQn                = 50,      /* SPI Interrupt (clcd)                  */
+  MPS2_SPI2_IRQn                = 51,      /* SPI Interrupt (spi 1 ADC replacement) */
+  MPS2_SPI3_IRQn                = 52,      /* SPI Interrupt (spi 0 shield 0 replacement) */
+  MPS2_SPI4_IRQn                = 53       /* SPI Interrupt  (shield 1)             */
 } IRQn_Type;
 
 
@@ -101,7 +122,7 @@ typedef enum IRQn
 /* ================================================================================ */
 
 /* --------  Configuration of the Cortex-M3 Processor and Core Peripherals  ------- */
-#define __CM3_REV                 0x0201      /* Core revision r2p1                              */
+#define __BEID_REV                 0x0201      /* Core revision r2p1                              */
 #define __MPU_PRESENT             1           /* MPU present or not                              */
 #define __NVIC_PRIO_BITS          3           /* Number of Bits used for Priority Levels         */
 #define __Vendor_SysTickConfig    0           /* Set to 1 if different SysTick Config is used    */
@@ -725,18 +746,19 @@ typedef struct
 #define CMSDK_DUALTIMER_BASE    (CMSDK_APB_BASE + 0x2000UL)
 #define CMSDK_DUALTIMER_1_BASE  (CMSDK_DUALTIMER_BASE)
 #define CMSDK_DUALTIMER_2_BASE  (CMSDK_DUALTIMER_BASE + 0x20UL)
-#define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x5000UL)
-#define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x4000UL)
-#define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
-#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
+#define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE        (0x4002C000UL)
+#define CMSDK_UART3_BASE        (0x4002D000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
-#define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals                                                                  */
 #define CMSDK_GPIO0_BASE        (CMSDK_AHB_BASE + 0x0000UL)
 #define CMSDK_GPIO1_BASE        (CMSDK_AHB_BASE + 0x1000UL)
 #define CMSDK_GPIO2_BASE        (CMSDK_AHB_BASE + 0x2000UL)
 #define CMSDK_GPIO3_BASE        (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_GPIO4_BASE        (0x40030000UL)
+#define CMSDK_GPIO5_BASE        (0x40031000UL)
 #define CMSDK_SYSCTRL_BASE      (CMSDK_AHB_BASE + 0xF000UL)
 
 
@@ -745,7 +767,7 @@ typedef struct
 /* ================================================================================ */
 
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE   )
-#define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
+#define CMSDK_UART1            ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE   )
 #define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
 #define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
@@ -754,11 +776,13 @@ typedef struct
 #define CMSDK_DUALTIMER1        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_1_BASE )
 #define CMSDK_DUALTIMER2        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_2_BASE )
 #define CMSDK_WATCHDOG          ((CMSDK_WATCHDOG_TypeDef  *) CMSDK_WATCHDOG_BASE   )
-#define CMSDK_DMA               ((CMSDK_PL230_TypeDef  *) CMSDK_PL230_BASE   )
+//#define CMSDK_DMA               ((CMSDK_PL230_TypeDef  *) CMSDK_PL230_BASE   )
 #define CMSDK_GPIO0             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO0_BASE   )
 #define CMSDK_GPIO1             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO1_BASE   )
 #define CMSDK_GPIO2             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO2_BASE )
 #define CMSDK_GPIO3             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO3_BASE )
+#define CMSDK_GPIO4             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO4_BASE )
+#define CMSDK_GPIO5             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO5_BASE )
 #define CMSDK_SYSCON            ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
 
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h
similarity index 90%
rename from libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h
rename to libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h
index a0c3199080..7e4d7c4c71 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h
@@ -1,18 +1,37 @@
-/*
- * Copyright:
- * ----------------------------------------------------------------
- * This confidential and proprietary software may be used only as
- * authorised by a licensing agreement from ARM Limited
- *   (C) COPYRIGHT 2014 ARM Limited
- *       ALL RIGHTS RESERVED
- * The entire notice above must be reproduced on all authorised
- * copies and copies may only be made to the extent permitted
- * by a licensing agreement from ARM Limited.
- * ----------------------------------------------------------------
- * File:     smm_mps2.h
- * Release:  Version 1.0
- * ----------------------------------------------------------------
- */
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File:     smm_mps2.h
+* Release:  Version 1.1
+*******************************************************************************/
 
 #ifndef __SMM_MPS2_H
 #define __SMM_MPS2_H
@@ -27,7 +46,7 @@
 /*                          FPGA System Register declaration                  */
 /******************************************************************************/
 
-typedef struct                   
+typedef struct
 {
   __IO uint32_t LED;             // Offset: 0x000 (R/W)  LED connections
                                  //                         [31:2] : Reserved
@@ -41,14 +60,13 @@ typedef struct
   __IO uint32_t CLK100HZ;        // Offset: 0x014 (R/W)  100Hz up counter
   __IO uint32_t COUNTER;         // Offset: 0x018 (R/W)  Cycle Up Counter
                                  //                         Increments when 32-bit prescale counter reach zero
-       uint32_t RESERVED3[1];
-  __IO uint32_t PRESCALE;        // Offset: 0x020 (R/W)  Prescaler
+  __IO uint32_t PRESCALE;        // Offset: 0x1C (R/W)  Prescaler
                                  //                         Bit[31:0] : reload value for prescale counter
-  __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
+  __IO uint32_t PSCNTR;          // Offset: 0x020 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
-       uint32_t RESERVED4[9];
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+       uint32_t RESERVED4[10];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
                                  //                         [31:10] : Reserved
                                  //                            [9] : SHIELD_1_SPI_nCS
@@ -88,7 +106,7 @@ typedef struct
 /*                        SCC Register declaration                            */
 /******************************************************************************/
 
-typedef struct                   // 
+typedef struct                   //
 {
   __IO uint32_t CFG_REG0;        // Offset: 0x000 (R/W)  Remaps block RAM to ZBT
                                  //                         [31:1] : Reserved
@@ -298,10 +316,10 @@ typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
 typedef struct
 {
   union {
-  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W) 
-  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ ) 
+  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W)
+  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ )
   };
-  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)  
+  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)
 } MPS2_I2C_TypeDef;
 
 #define SDA                1 << 1
@@ -336,7 +354,7 @@ typedef struct
                               //     <4=> Undefined!
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.14..12> RX Buffer Water Level
                               //     <0=> Undefined!
                               //     <1=> / IRQ triggers when less than 1 space available
@@ -345,7 +363,7 @@ typedef struct
                               //     <4=> / IRQ triggers when less than 4 space available
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.16> FIFO reset
                               //     <0=> Normal operation
                               //     <1=> FIFO reset
@@ -353,12 +371,12 @@ typedef struct
                               //     <0=> Normal operation
                               //     <1=> Assert audio Codec reset
   /*!< Offset: 0x004 STATUS Register     (R/ ) */
-  __I    uint32_t  STATUS;  // <h> STATUS </h> 
+  __I    uint32_t  STATUS;  // <h> STATUS </h>
                               //   <o.0> TX Buffer alert
                               //     <0=> TX buffer don't need service yet
                               //     <1=> TX buffer need service
                               //   <o.1> RX Buffer alert
-                              //     <0=> RX buffer don't need service yet 
+                              //     <0=> RX buffer don't need service yet
                               //     <1=> RX buffer need service
                               //   <o.2> TX Buffer Empty
                               //     <0=> TX buffer have data
@@ -373,33 +391,33 @@ typedef struct
                               //     <0=> RX buffer not full
                               //     <1=> RX buffer full
   union {
-   /*!< Offset: 0x008 Error Status Register (R/ ) */  
-    __I    uint32_t  ERROR;  // <h> ERROR </h> 
+   /*!< Offset: 0x008 Error Status Register (R/ ) */
+    __I    uint32_t  ERROR;  // <h> ERROR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> TX overrun/underrun
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> RX overrun/underrun
-   /*!< Offset: 0x008 Error Clear Register  ( /W) */    
-    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h> 
+   /*!< Offset: 0x008 Error Clear Register  ( /W) */
+    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> Clear TX error
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> Clear RX error
     };
-   /*!< Offset: 0x00C Divide ratio Register (R/W) */  
-  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+   /*!< Offset: 0x00C Divide ratio Register (R/W) */
+  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h>
+                              //   <o.9..0> TX error (default 0x80)
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
-  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h>
+                              //   <o.15..0> Right channel
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
-  __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __I    uint32_t  RXBUF;  // <h> Receive buffer </h>
+                              //   <o.15..0> Right channel
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -554,14 +572,10 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
-#ifdef CORTEX_M7
-#define SMSC9220_BASE           (0xA0000000ul)       /* Ethernet SMSC9220 Base Address   */
-#else
 #define SMSC9220_BASE           (0x40200000ul)       /* Ethernet SMSC9220 Base Address   */
-#endif
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -577,40 +591,20 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
-#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )	
-#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )	
-#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )	
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )
 
-//******************************************************************************/
+/******************************************************************************/
+/*                     General Function Definitions                           */
+/******************************************************************************/
+
+
+/******************************************************************************/
 /*                     General MACRO Definitions                              */
 /******************************************************************************/
 
-//#define DEBUG
-//#ifdef DEBUG
-//    #define debug(...)      printf(__VA_ARGS__)
-//#else
-//    #define debug(...)
-//#endif  // ifdef DEBUG
 
-// Bit control macros
-//#define HW_REG(base,offset) *((volatile unsigned int *)((base) + (offset)))
-
-#define CREATE_MASK(msb, lsb)               (((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
-#define MASK_BITS(arg, msb, lsb)            ((arg) & CREATE_MASK(msb, lsb))
-#define EXTRACT_BITS(arg, msb, lsb)         (MASK_BITS(arg, msb, lsb) >> (lsb))
-#define INSERT_BITS(arg, msb, lsb, value) \
-    ((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb)))
-
-#define MASK_FIELD(arg, field)              MASK_BITS(arg, field##_MSB, field##_LSB)
-#define EXTRACT_FIELD(arg, field)           EXTRACT_BITS(arg, field##_MSB, field##_LSB)
-#define INSERT_FIELD(arg, field, value)     INSERT_BITS(arg, field##_MSB, field##_LSB, value)
-
-#define SET_BIT(arg, bit)                   ((arg) |= (1 << (bit)))
-#define CLEAR_BIT(arg, bit)                 ((arg) &= ~(1 << (bit)))
-#define TEST_BIT(arg, bit)                  ((arg) & (1 << (bit)))
-
-#ifndef NoOfElements
-#define NoOfElements(array) (sizeof(array) / sizeof(array[0]))
-#endif
 
 #endif /* __SMM_MPS2_H */
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
new file mode 100644
index 0000000000..e157314325
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2016 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File                      ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00400000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x140) (0x400000-0x140)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
new file mode 100644
index 0000000000..8ff44c3bd8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
@@ -0,0 +1,358 @@
+; MPS2 CMSIS Library
+;
+; Copyright (c) 2006-2016 ARM Limited
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;******************************************************************************
+; @file     startup_CMSDK_BEID.s
+; @brief    CMSIS Core Device Startup File for
+;           CMSDK_BEID Device
+;
+;******************************************************************************
+;
+;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00004000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00001000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     UART0_IRQHandler        ;   0:UART 0 RX and TX Combined Interrupt
+                DCD     Spare_IRQHandler        ;   1:Undefined
+                DCD     UART1_IRQHandler        ;   2:UART 1 RX and TX Combined Interrupt
+                DCD     I2C0_IRQHandler         ;   3:I2C 0 Interrupt
+                DCD     I2C1_IRQHandler         ;   4:I2C 1 Interrupt
+                DCD     RTC_IRQHandler          ;   5:RTC Interrupt
+                DCD     PORT0_IRQHandler        ;   6:GPIO Port 0 combined Interrupt
+                DCD     PORT1_ALL_IRQHandler    ;   7:GPIO Port 1 combined Interrupt
+                DCD     TIMER0_IRQHandler       ;   8:TIMER 0 Interrupt
+                DCD     TIMER1_IRQHandler       ;   9:TIMER 1 Interrupt
+                DCD     DUALTIMER_IRQHandler    ;   10:Dual Timer Interrupt
+                DCD     SPI0_IRQHandler         ;   11:SPI 0 Interrupt
+                DCD     UARTOVF_IRQHandler      ;   12:UART 0,1,2 Overflow Interrupt
+                DCD     SPI1_IRQHandler         ;   13:SPI 1 Interrupt
+                DCD     RESERVED0_IRQHandler    ;   14:Reserved
+                DCD     TSC_IRQHandler          ;   15:Touch Screen Interrupt
+                DCD     PORT01_0_IRQHandler     ;   16:GPIO Port 0 pin 0 Handler
+                DCD     PORT01_1_IRQHandler     ;   17:GPIO Port 0 pin 1 Handler
+                DCD     PORT01_2_IRQHandler     ;   18:GPIO Port 0 pin 2 Handler
+                DCD     PORT01_3_IRQHandler     ;   19:GPIO Port 0 pin 3 Handler
+                DCD     PORT01_4_IRQHandler     ;   20:GPIO Port 0 pin 4 Handler
+                DCD     PORT01_5_IRQHandler     ;   21:GPIO Port 0 pin 5 Handler
+                DCD     PORT01_6_IRQHandler     ;   22:GPIO Port 0 pin 6 Handler
+                DCD     PORT01_7_IRQHandler     ;   23:GPIO Port 0 pin 7 Handler
+                DCD     PORT01_8_IRQHandler     ;   24:GPIO Port 0 pin 8 Handler
+                DCD     PORT01_9_IRQHandler     ;   25:GPIO Port 0 pin 9 Handler
+                DCD     PORT01_10_IRQHandler    ;   26:GPIO Port 0 pin 10 Handler
+                DCD     PORT01_11_IRQHandler    ;   27:GPIO Port 0 pin 11 Handler
+                DCD     PORT01_12_IRQHandler    ;   28:GPIO Port 0 pin 12 Handler
+                DCD     PORT01_13_IRQHandler    ;   29:GPIO Port 0 pin 13 Handler
+                DCD     PORT01_14_IRQHandler    ;   30:GPIO Port 0 pin 14 Handler
+                DCD     PORT01_15_IRQHandler    ;   31:GPIO Port 0 pin 15 Handler
+                DCD     SYSERROR_IRQHandler     ;   32:System Error Interrupt
+                DCD     EFLASH_IRQHandler       ;   33:Embedded Flash Interrupt
+                DCD     RESERVED1_IRQHandler    ;   34:Reserved
+                DCD     RESERVED2_IRQHandler    ;   35:Reserved
+                DCD     RESERVED3_IRQHandler    ;   36:Reserved
+                DCD     RESERVED4_IRQHandler    ;   37:Reserved
+                DCD     RESERVED5_IRQHandler    ;   38:Reserved
+                DCD     RESERVED6_IRQHandler    ;   39:Reserved
+                DCD     RESERVED7_IRQHandler    ;   40:Reserved
+                DCD     RESERVED8_IRQHandler    ;   41:Reserved
+                DCD     PORT2_ALL_IRQHandler    ;   42:GPIO Port 2 combined Interrupt
+                DCD     PORT3_ALL_IRQHandler    ;   43:GPIO Port 3 combined Interrupt
+                DCD     TRNG_IRQHandler         ;   44:Random number generator Interrupt
+                DCD     UART2_IRQHandler        ;   45:UART 2 RX and TX Combined Interrupt
+                DCD     UART3_IRQHandler        ;   46:UART 3 RX and TX Combined Interrupt
+                DCD     ETHERNET_IRQHandler     ;   47:Ethernet interrupt     t.b.a.
+                DCD     I2S_IRQHandler          ;   48:I2S Interrupt
+                DCD     MPS2_SPI0_IRQHandler    ;   49:SPI Interrupt (spi header)
+                DCD     MPS2_SPI1_IRQHandler    ;   50:SPI Interrupt (clcd)
+                DCD     MPS2_SPI2_IRQHandler    ;   51:SPI Interrupt (spi 1 ADC replacement)
+                DCD     MPS2_SPI3_IRQHandler    ;   52:SPI Interrupt (spi 0 shield 0 replacement)
+                DCD     MPS2_SPI4_IRQHandler    ;   53:SPI Interrupt  (shield 1)
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT     UART0_IRQHandler        [WEAK]       ;   0:UART 0 RX and TX Combined Interrupt
+                EXPORT     Spare_IRQHandler        [WEAK]       ;   1:Undefined
+                EXPORT     UART1_IRQHandler        [WEAK]       ;   2:UART 1 RX and TX Combined Interrupt
+                EXPORT     I2C0_IRQHandler         [WEAK]       ;   3:I2C 0 Interrupt
+                EXPORT     I2C1_IRQHandler         [WEAK]       ;   4:I2C 1 Interrupt
+                EXPORT     RTC_IRQHandler          [WEAK]       ;   5:RTC Interrupt
+                EXPORT     PORT0_IRQHandler        [WEAK]       ;   6:GPIO Port 0 combined Interrupt
+                EXPORT     PORT1_ALL_IRQHandler    [WEAK]       ;   7:GPIO Port 1 combined Interrupt
+                EXPORT     TIMER0_IRQHandler       [WEAK]       ;   8:TIMER 0 Interrupt
+                EXPORT     TIMER1_IRQHandler       [WEAK]       ;   9:TIMER 1 Interrupt
+                EXPORT     DUALTIMER_IRQHandler    [WEAK]       ;   10:Dual Timer Interrupt
+                EXPORT     SPI0_IRQHandler         [WEAK]       ;   11:SPI 0 Interrupt
+                EXPORT     UARTOVF_IRQHandler      [WEAK]       ;   12:UART 0,1,2 Overflow Interrupt
+                EXPORT     SPI1_IRQHandler         [WEAK]       ;   13:SPI 1 Interrupt
+                EXPORT     RESERVED0_IRQHandler    [WEAK]       ;   14:Reserved
+                EXPORT     TSC_IRQHandler          [WEAK]       ;   15:Touch Screen Interrupt
+                EXPORT     PORT01_0_IRQHandler     [WEAK]       ;   16:GPIO Port 0 pin 0 Handler
+                EXPORT     PORT01_1_IRQHandler     [WEAK]       ;   17:GPIO Port 0 pin 1 Handler
+                EXPORT     PORT01_2_IRQHandler     [WEAK]       ;   18:GPIO Port 0 pin 2 Handler
+                EXPORT     PORT01_3_IRQHandler     [WEAK]       ;   19:GPIO Port 0 pin 3 Handler
+                EXPORT     PORT01_4_IRQHandler     [WEAK]       ;   20:GPIO Port 0 pin 4 Handler
+                EXPORT     PORT01_5_IRQHandler     [WEAK]       ;   21:GPIO Port 0 pin 5 Handler
+                EXPORT     PORT01_6_IRQHandler     [WEAK]       ;   22:GPIO Port 0 pin 6 Handler
+                EXPORT     PORT01_7_IRQHandler     [WEAK]       ;   23:GPIO Port 0 pin 7 Handler
+                EXPORT     PORT01_8_IRQHandler     [WEAK]       ;   24:GPIO Port 0 pin 8 Handler
+                EXPORT     PORT01_9_IRQHandler     [WEAK]       ;   25:GPIO Port 0 pin 9 Handler
+                EXPORT     PORT01_10_IRQHandler    [WEAK]       ;   26:GPIO Port 0 pin 10 Handler
+                EXPORT     PORT01_11_IRQHandler    [WEAK]       ;   27:GPIO Port 0 pin 11 Handler
+                EXPORT     PORT01_12_IRQHandler    [WEAK]       ;   28:GPIO Port 0 pin 12 Handler
+                EXPORT     PORT01_13_IRQHandler    [WEAK]       ;   29:GPIO Port 0 pin 13 Handler
+                EXPORT     PORT01_14_IRQHandler    [WEAK]       ;   30:GPIO Port 0 pin 14 Handler
+                EXPORT     PORT01_15_IRQHandler    [WEAK]       ;   31:GPIO Port 0 pin 15 Handler
+                EXPORT     SYSERROR_IRQHandler     [WEAK]       ;   32:System Error Interrupt
+                EXPORT     EFLASH_IRQHandler       [WEAK]       ;   33:Embedded Flash Interrupt
+                EXPORT     RESERVED1_IRQHandler    [WEAK]       ;   34:Reserved
+                EXPORT     RESERVED2_IRQHandler    [WEAK]       ;   35:Reserved
+                EXPORT     RESERVED3_IRQHandler    [WEAK]       ;   36:Reserved
+                EXPORT     RESERVED4_IRQHandler    [WEAK]       ;   37:Reserved
+                EXPORT     RESERVED5_IRQHandler    [WEAK]       ;   38:Reserved
+                EXPORT     RESERVED6_IRQHandler    [WEAK]       ;   39:Reserved
+                EXPORT     RESERVED7_IRQHandler    [WEAK]       ;   40:Reserved
+                EXPORT     RESERVED8_IRQHandler    [WEAK]       ;   41:Reserved
+                EXPORT     PORT2_ALL_IRQHandler    [WEAK]       ;   42:GPIO Port 2 combined Interrupt
+                EXPORT     PORT3_ALL_IRQHandler    [WEAK]       ;   43:GPIO Port 3 combined Interrupt
+                EXPORT     TRNG_IRQHandler         [WEAK]       ;   44:Random number generator Interrupt
+                EXPORT     UART2_IRQHandler        [WEAK]       ;   45:UART 2 RX and TX Combined Interrupt
+                EXPORT     UART3_IRQHandler        [WEAK]       ;   46:UART 3 RX and TX Combined Interrupt
+                EXPORT     ETHERNET_IRQHandler     [WEAK]       ;   47:Ethernet interrupt     t.b.a.
+                EXPORT     I2S_IRQHandler          [WEAK]       ;   48:I2S Interrupt
+                EXPORT     MPS2_SPI0_IRQHandler    [WEAK]       ;   49:SPI Interrupt (spi header)
+                EXPORT     MPS2_SPI1_IRQHandler    [WEAK]       ;   50:SPI Interrupt (clcd)
+                EXPORT     MPS2_SPI2_IRQHandler    [WEAK]       ;   51:SPI Interrupt (spi 1 ADC replacement)
+                EXPORT     MPS2_SPI3_IRQHandler    [WEAK]       ;   52:SPI Interrupt (spi 0 shield 0 replacement)
+                EXPORT     MPS2_SPI4_IRQHandler    [WEAK]       ;   53:SPI Interrupt  (shield 1)
+
+UART0_IRQHandler
+Spare_IRQHandler
+UART1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+RTC_IRQHandler
+PORT0_IRQHandler
+PORT1_ALL_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+DUALTIMER_IRQHandler
+SPI0_IRQHandler
+UARTOVF_IRQHandler
+SPI1_IRQHandler
+RESERVED0_IRQHandler
+TSC_IRQHandler
+PORT01_0_IRQHandler
+PORT01_1_IRQHandler
+PORT01_2_IRQHandler
+PORT01_3_IRQHandler
+PORT01_4_IRQHandler
+PORT01_5_IRQHandler
+PORT01_6_IRQHandler
+PORT01_7_IRQHandler
+PORT01_8_IRQHandler
+PORT01_9_IRQHandler
+PORT01_10_IRQHandler
+PORT01_11_IRQHandler
+PORT01_12_IRQHandler
+PORT01_13_IRQHandler
+PORT01_14_IRQHandler
+PORT01_15_IRQHandler
+SYSERROR_IRQHandler
+EFLASH_IRQHandler
+RESERVED1_IRQHandler
+RESERVED2_IRQHandler
+RESERVED3_IRQHandler
+RESERVED4_IRQHandler
+RESERVED5_IRQHandler
+RESERVED6_IRQHandler
+RESERVED7_IRQHandler
+RESERVED8_IRQHandler
+PORT2_ALL_IRQHandler
+PORT3_ALL_IRQHandler
+TRNG_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+ETHERNET_IRQHandler
+I2S_IRQHandler
+MPS2_SPI0_IRQHandler
+MPS2_SPI1_IRQHandler
+MPS2_SPI2_IRQHandler
+MPS2_SPI3_IRQHandler
+MPS2_SPI4_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h
new file mode 100644
index 0000000000..428ddfafad
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h
@@ -0,0 +1,42 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* A generic CMSIS include header, pulling in MPS2 specifics
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "CMSDK_BEID.h"
+#include "SMM_MPS2.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c
new file mode 100644
index 0000000000..9ac558cceb
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c
@@ -0,0 +1,58 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h
new file mode 100644
index 0000000000..f8c6e871cb
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS      (16 + 64)
+#define NVIC_USER_IRQ_OFFSET  16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h
new file mode 100644
index 0000000000..9527c3e132
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h
@@ -0,0 +1,45 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* Name:    Device.h
+* Purpose: Include the correct device header file
+*******************************************************************************/
+
+#ifndef __DEVICE_H
+#define __DEVICE_H
+
+#if defined CMSDK_BEID
+  #include "CMSDK_BEID.h"                         /* device specific header file */
+#else
+  #warning "no appropriate header file found!"
+#endif
+
+#endif /* __DEVICE_H */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c
new file mode 100644
index 0000000000..fe1c3c7f46
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c
@@ -0,0 +1,95 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file     system_CMSDK_BEID.c
+* @brief    CMSIS Device System Source File for
+*           CMSDK_BEID Device
+*
+*******************************************************************************/
+
+
+#include "CMSDK_BEID.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL            (48000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+    // Enable AHB and APB clock
+    CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;  // GPIO
+    CMSDK_SYSCON->APBCLKCFG0SET = 0xF9B7;    // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h
new file mode 100644
index 0000000000..568afdf144
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h
@@ -0,0 +1,76 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2016 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file     system_CMSDK_BEID.h
+* @brief    CMSIS Device Peripheral Access Layer Header File for
+*           CMSDK_BEID Device
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_BEID_H
+#define SYSTEM_CMSDK_BEID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_BEID_H */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
deleted file mode 100644
index 2afd726abe..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
+++ /dev/null
@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File                      ***
-; *************************************************************
-
- LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
-   ER_IROM1 +0  {  ; load address = execution address
-    *.o (RESET, +FIRST)
-    *(InRoot$$Sections)
-    .ANY (+RO)
-   }
-   RW_IRAM1 +0  {  ; RW data
-    .ANY (+RW +ZI)
-   }
- }
-
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
deleted file mode 100644
index e67bee5a75..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
+++ /dev/null
@@ -1,291 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_CMSDK_CM3.s
-; * @brief    CMSIS Core Device Startup File for
-; *           CMSDK_CM3 Device
-; * @version  V3.02
-; * @date     15. November 2013
-; *
-; * @note
-; * Copyright (C) 2014 ARM Limited. All rights reserved.
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2011 - 2013 ARM LIMITED
-;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-; *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00004000
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00001000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     UARTRX0_Handler           ; UART 0 RX Handler
-                DCD     UARTTX0_Handler           ; UART 0 TX Handler
-                DCD     UARTRX1_Handler           ; UART 1 RX Handler
-                DCD     UARTTX1_Handler           ; UART 1 TX Handler
-                DCD     UARTRX2_Handler           ; UART 2 RX Handler
-                DCD     UARTTX2_Handler           ; UART 2 TX Handler
-                DCD     PORT0_COMB_Handler        ; GPIO Port 0 Combined Handler
-                DCD     PORT1_COMB_Handler        ; GPIO Port 1 Combined Handler
-                DCD     TIMER0_Handler            ; TIMER 0 handler
-                DCD     TIMER1_Handler            ; TIMER 1 handler
-                DCD     DUALTIMER_HANDLER         ; Dual timer handler
-                DCD     SPI_Handler               ; SPI exceptions Handler
-                DCD     UARTOVF_Handler           ; UART 0,1,2 Overflow Handler
-                DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
-                DCD     I2S_Handler               ; I2S Handler
-                DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT UARTRX0_Handler            [WEAK]
-                EXPORT UARTTX0_Handler            [WEAK]
-                EXPORT UARTRX1_Handler            [WEAK]
-                EXPORT UARTTX1_Handler            [WEAK]
-                EXPORT UARTRX2_Handler            [WEAK]
-                EXPORT UARTTX2_Handler            [WEAK]
-                EXPORT PORT0_COMB_Handler         [WEAK]
-                EXPORT PORT1_COMB_Handler         [WEAK]
-                EXPORT TIMER0_Handler             [WEAK]
-                EXPORT TIMER1_Handler             [WEAK]
-                EXPORT DUALTIMER_HANDLER          [WEAK]
-                EXPORT SPI_Handler                [WEAK]
-                EXPORT UARTOVF_Handler            [WEAK]
-                EXPORT ETHERNET_Handler           [WEAK]
-                EXPORT I2S_Handler                [WEAK]
-                EXPORT TSC_Handler                [WEAK]
-                EXPORT PORT0_0_Handler            [WEAK]
-                EXPORT PORT0_1_Handler            [WEAK]
-                EXPORT PORT0_2_Handler            [WEAK]
-                EXPORT PORT0_3_Handler            [WEAK]
-                EXPORT PORT0_4_Handler            [WEAK]
-                EXPORT PORT0_5_Handler            [WEAK]
-                EXPORT PORT0_6_Handler            [WEAK]
-                EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
-
-UARTRX0_Handler
-UARTTX0_Handler
-UARTRX1_Handler
-UARTTX1_Handler
-UARTRX2_Handler
-UARTTX2_Handler
-PORT0_COMB_Handler
-PORT1_COMB_Handler
-TIMER0_Handler
-TIMER1_Handler
-DUALTIMER_HANDLER
-SPI_Handler
-UARTOVF_Handler
-ETHERNET_Handler
-I2S_Handler
-TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h
deleted file mode 100644
index f34873c269..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC1768 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "CMSDK_BEID.h"
-#include "SMM_MPS2.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c
deleted file mode 100644
index 6b8c4a27d5..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LCP1768
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Location of vectors in RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h
deleted file mode 100644
index 600de99554..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_NUM_VECTORS      (16 + 32)
-#define NVIC_USER_IRQ_OFFSET  16
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h
deleted file mode 100644
index 6f031cd4ae..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*-----------------------------------------------------------------------------
- * Name:    Device.h
- * Purpose: Include the correct device header file
- *-----------------------------------------------------------------------------
- * This file is part of the uVision/ARM development tools.
- * This software may only be used under the terms of a valid, current,
- * end user licence from KEIL for a compatible version of KEIL software
- * development tools. Nothing else gives you the right to use this software.
- *
- * This software is supplied "AS IS" without warranties of any kind.
- *
- * Copyright (c) 2013 KEIL - An ARM Company. All rights reserved.
- *----------------------------------------------------------------------------*/
-
-#ifndef __DEVICE_H
-#define __DEVICE_H
-
-#if   defined CMSDK_CM0
-  #include "CMSDK_CM0.h"                         /* device specific header file */
-#elif defined CMSDK_CM0plus
-  #include "CMSDK_CM0plus.h"                     /* device specific header file */
-#elif defined CMSDK_CM3
-  #include "CMSDK_CM3.h"                         /* device specific header file */
-#elif defined CMSDK_CM4
-  #include "CMSDK_CM4.h"                         /* device specific header file */
-#elif defined CMSDK_CM7
-  #include "CMSDK_CM7.h"                         /* device specific header file */
-#elif defined CMSDK_BEID
-  #include "CMSDK_BEID.h"                         /* device specific header file */
-#else
-  #warning "no appropriate header file found!"
-#endif
-
-#endif /* __DEVICE_H */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c
deleted file mode 100644
index 02946c0cfe..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/**************************************************************************//**
- * @file     system_CMSDK_BEID.c
- * @brief    CMSIS Device System Source File for
- *           CMSDK_M3 Device
- * @version  V3.02
- * @date     15. November 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#include "CMSDK_BEID.h"
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL            (50000000UL)    /* Oscillator frequency             */
-
-#define __SYSTEM_CLOCK    (__XTAL / 2)
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-void SystemCoreClockUpdate (void)
-{
-
-  SystemCoreClock = __SYSTEM_CLOCK;
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-  SystemCoreClock = __SYSTEM_CLOCK;
-
-    // Enable AHB and APB clock
-    CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;  // GPIO
-    CMSDK_SYSCON->APBCLKCFG0SET = 0x37;	// UART0, UART1, TIMER0, TIMER1, DUAL TIMER
-}
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h
deleted file mode 100644
index c61fc631f5..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**************************************************************************//**
- * @file     system_CMSDK_BEID.h
- * @brief    CMSIS Device Peripheral Access Layer Header File for
- *           CMSDK_BEID Device
- * @version  V3.02
- * @date     15. March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef SYSTEM_CMSDK_BEID_H
-#define SYSTEM_CMSDK_BEID_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_CMSDK_BEID_H */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h
index b07dfc6a6b..6b547b020c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     CMSDK_CM0.h
 * @brief    CMSIS Core Peripheral Access Layer Header File for
 *           CMSDK_CM0 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note     configured for CM7 without FPU
 *
 *******************************************************************************/
 
@@ -52,51 +48,48 @@
 
 typedef enum IRQn
 {
-/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
-  NonMaskableInt_IRQn           = -14,      /*  2 Non Maskable Interrupt            */
-  HardFault_IRQn                = -13,      /*  3 HardFault Interrupt               */
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
 
-
-
-  SVCall_IRQn                   =  -5,      /* 11 SV Call Interrupt                 */
-
-  PendSV_IRQn                   =  -2,      /* 14 Pend SV Interrupt                 */
-  SysTick_IRQn                  =  -1,      /* 15 System Tick Interrupt             */
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Cortex-M0 Non Maskable Interrupt              */
+  HardFault_IRQn                = -13,      /*!<  3 Cortex-M0 Hard Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SV Call Interrupt                   */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt               */
 
 /* ----------------------  CMSDK_CM0 Specific Interrupt Numbers  ------------------ */
-  UARTRX0_IRQn                  = 0,       /* UART 0 RX Interrupt                   */
-  UARTTX0_IRQn                  = 1,       /* UART 0 TX Interrupt                   */
-  UARTRX1_IRQn                  = 2,       /* UART 1 RX Interrupt                   */
-  UARTTX1_IRQn                  = 3,       /* UART 1 TX Interrupt                   */
-  UARTRX2_IRQn                  = 4,       /* UART 2 RX Interrupt                   */
-  UARTTX2_IRQn                  = 5,       /* UART 2 TX Interrupt                   */
-  PORT0_ALL_IRQn                = 6,       /* Port 1 combined Interrupt             */
-  PORT1_ALL_IRQn                = 7,       /* Port 1 combined Interrupt             */
-  TIMER0_IRQn                   = 8,       /* TIMER 0 Interrupt                     */
-  TIMER1_IRQn                   = 9,       /* TIMER 1 Interrupt                     */
-  DUALTIMER_IRQn                = 10,      /* Dual Timer Interrupt                  */
-  SPI_IRQn                      = 11,      /* SPI Interrupt                         */
-  UARTOVF_IRQn                  = 12,      /* UART 0,1,2 Overflow Interrupt         */
-  ETHERNET_IRQn                 = 13,      /* Ethernet Interrupt                    */
-  I2S_IRQn                      = 14,      /* I2S Interrupt                         */
-  TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /* All P0 I/O pins used as irq source    */
-  PORT0_1_IRQn                  = 17,      /* There are 16 pins in total            */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+  UARTRX0_IRQn                  = 0,       /*!< UART 0 RX Interrupt                               */
+  UARTTX0_IRQn                  = 1,       /*!< UART 0 TX Interrupt                               */
+  UARTRX1_IRQn                  = 2,       /*!< UART 1 RX Interrupt                               */
+  UARTTX1_IRQn                  = 3,       /*!< UART 1 TX Interrupt                               */
+  UARTRX2_IRQn                  = 4,       /*!< UART 2 RX Interrupt                               */
+  UARTTX2_IRQn                  = 5,       /*!< UART 2 TX Interrupt                               */
+  PORT0_ALL_IRQn                = 6,       /*!< Port 0 combined Interrupt                         */
+  PORT1_ALL_IRQn                = 7,       /*!< Port 1 combined Interrupt                         */
+  TIMER0_IRQn                   = 8,       /*!< TIMER 0 Interrupt                                 */
+  TIMER1_IRQn                   = 9,       /*!< TIMER 1 Interrupt                                 */
+  DUALTIMER_IRQn                = 10,      /*!< Dual Timer Interrupt                              */
+  SPI_IRQn                      = 11,      /*!< SPI Interrupt                                     */
+  UARTOVF_IRQn                  = 12,      /*!< UART 0,1,2 Overflow Interrupt                     */
+  ETHERNET_IRQn                 = 13,      /*!< Ethernet Interrupt                                */
+  I2S_IRQn                      = 14,      /*!< I2S Interrupt                                     */
+  TSC_IRQn                      = 15,      /*!< Touch Screen Interrupt                            */
+  PORT2_ALL_IRQn                = 16,      /*!< Port 2 combined Interrupt                         */
+  PORT3_ALL_IRQn                = 17,      /*!< Port 3 combined Interrupt                         */
+  UARTRX3_IRQn                  = 18,      /*!< UART 3 RX Interrupt                               */
+  UARTTX3_IRQn                  = 19,      /*!< UART 3 TX Interrupt                               */
+  UARTRX4_IRQn                  = 20,      /*!< UART 4 RX Interrupt                               */
+  UARTTX4_IRQn                  = 21,      /*!< UART 4 TX Interrupt                               */
+  ADCSPI_IRQn                   = 22,      /*!< SHIELD ADC SPI Interrupt                          */
+  SHIELDSPI_IRQn                = 23,      /*!< SHIELD SPI Combined Interrupt                     */
+  PORT0_0_IRQn                  = 24,      /*!<  GPIO Port 0 pin 0 Interrupt                      */
+  PORT0_1_IRQn                  = 25,      /*!<  GPIO Port 0 pin 1 Interrupt                      */
+  PORT0_2_IRQn                  = 26,      /*!<  GPIO Port 0 pin 2 Interrupt                      */
+  PORT0_3_IRQn                  = 27,      /*!<  GPIO Port 0 pin 3 Interrupt                      */
+  PORT0_4_IRQn                  = 28,      /*!<  GPIO Port 0 pin 4 Interrupt                      */
+  PORT0_5_IRQn                  = 29,      /*!<  GPIO Port 0 pin 5 Interrupt                      */
+  PORT0_6_IRQn                  = 30,      /*!<  GPIO Port 0 pin 6 Interrupt                      */
+  PORT0_7_IRQn                  = 31,      /*!<  GPIO Port 0 pin 7 Interrupt                      */
 } IRQn_Type;
 
 
@@ -686,7 +679,9 @@ typedef struct
 #define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
 #define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
 #define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE        (CMSDK_APB_BASE + 0x9000UL)
 #define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals                                                                  */
@@ -704,6 +699,8 @@ typedef struct
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE   )
 #define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE   )
+#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
+#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE   )
 #define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
 #define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE  )
 #define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h
index 910d5abd97..f0d07a3c30 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h
@@ -1,36 +1,36 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * File:     smm_mps2.h
-* Release:  Version 1.0
+* Release:  Version 1.1
 *******************************************************************************/
 
 #ifndef __SMM_MPS2_H
@@ -46,7 +46,7 @@
 /*                          FPGA System Register declaration                  */
 /******************************************************************************/
 
-typedef struct                   
+typedef struct                  
 {
   __IO uint32_t LED;             // Offset: 0x000 (R/W)  LED connections
                                  //                         [31:2] : Reserved
@@ -65,11 +65,14 @@ typedef struct
                                  //                         Bit[31:0] : reload value for prescale counter
   __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
        uint32_t RESERVED4[9];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
-                                 //                         [31:7] : Reserved
+                                 //                         [31:10] : Reserved
+                                 //                            [9] : SHIELD_1_SPI_nCS
+                                 //                            [8] : SHIELD_0_SPI_nCS
+                                 //                            [7] : ADC_SPI_nCS
                                  //                            [6] : CLCD_BL_CTRL
                                  //                            [5] : CLCD_RD
                                  //                            [4] : CLCD_RS
@@ -93,12 +96,18 @@ typedef struct
 #define CLCD_RD_Msk        (1UL<<CLCD_RD_Pos)
 #define CLCD_BL_Pos        6
 #define CLCD_BL_Msk        (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos        7
+#define ADC_nCS_Msk        (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos        8
+#define SHIELD_0_nCS_Msk        (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos        9
+#define SHIELD_1_nCS_Msk        (1UL<<SHIELD_1_nCS_Pos)
 
 /******************************************************************************/
 /*                        SCC Register declaration                            */
 /******************************************************************************/
 
-typedef struct                   // 
+typedef struct                   //
 {
   __IO uint32_t CFG_REG0;        // Offset: 0x000 (R/W)  Remaps block RAM to ZBT
                                  //                         [31:1] : Reserved
@@ -308,10 +317,10 @@ typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
 typedef struct
 {
   union {
-  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W) 
-  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ ) 
+  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W)
+  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ )
   };
-  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)  
+  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W) 
 } MPS2_I2C_TypeDef;
 
 #define SDA                1 << 1
@@ -346,7 +355,7 @@ typedef struct
                               //     <4=> Undefined!
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined! 
                               //   <o.14..12> RX Buffer Water Level
                               //     <0=> Undefined!
                               //     <1=> / IRQ triggers when less than 1 space available
@@ -355,7 +364,7 @@ typedef struct
                               //     <4=> / IRQ triggers when less than 4 space available
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined! 
                               //   <o.16> FIFO reset
                               //     <0=> Normal operation
                               //     <1=> FIFO reset
@@ -363,12 +372,12 @@ typedef struct
                               //     <0=> Normal operation
                               //     <1=> Assert audio Codec reset
   /*!< Offset: 0x004 STATUS Register     (R/ ) */
-  __I    uint32_t  STATUS;  // <h> STATUS </h> 
+  __I    uint32_t  STATUS;  // <h> STATUS </h>
                               //   <o.0> TX Buffer alert
                               //     <0=> TX buffer don't need service yet
                               //     <1=> TX buffer need service
                               //   <o.1> RX Buffer alert
-                              //     <0=> RX buffer don't need service yet 
+                              //     <0=> RX buffer don't need service yet
                               //     <1=> RX buffer need service
                               //   <o.2> TX Buffer Empty
                               //     <0=> TX buffer have data
@@ -383,33 +392,33 @@ typedef struct
                               //     <0=> RX buffer not full
                               //     <1=> RX buffer full
   union {
-   /*!< Offset: 0x008 Error Status Register (R/ ) */  
-    __I    uint32_t  ERROR;  // <h> ERROR </h> 
+   /*!< Offset: 0x008 Error Status Register (R/ ) */ 
+    __I    uint32_t  ERROR;  // <h> ERROR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> TX overrun/underrun
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> RX overrun/underrun
-   /*!< Offset: 0x008 Error Clear Register  ( /W) */    
-    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h> 
+   /*!< Offset: 0x008 Error Clear Register  ( /W) */   
+    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> Clear TX error
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> Clear RX error
     };
-   /*!< Offset: 0x00C Divide ratio Register (R/W) */  
-  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+   /*!< Offset: 0x00C Divide ratio Register (R/W) */ 
+  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h>
+                              //   <o.9..0> TX error (default 0x80)                 
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
-  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h>
+                              //   <o.15..0> Right channel                 
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
-  __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __I    uint32_t  RXBUF;  // <h> Receive buffer </h>
+                              //   <o.15..0> Right channel                 
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -556,7 +565,12 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_TSC_I2C_BASE       (0x40022000ul)       /* Touch Screen I2C Base Address */
 #define MPS2_AAIC_I2C_BASE      (0x40023000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_AAIC_I2S_BASE      (0x40024000ul)       /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE          (0x40025000ul)       /* adc SSP Base Address   */
+#define MPS2_SSP3_BASE          (0x40026000ul)       /* Shield 0 SSP Base Address   */
+#define MPS2_SSP4_BASE          (0x40027000ul)       /* Shield 1 SSP Base Address   */
 #define MPS2_FPGAIO_BASE        (0x40028000ul)       /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE   (0x40029000ul)       /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Shield 1 I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
 #ifdef CORTEX_M7
@@ -565,8 +579,8 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220_BASE           (0x40200000ul)       /* Ethernet SMSC9220 Base Address   */
 #endif
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -575,11 +589,16 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220                ((SMSC9220_TypeDef      *) SMSC9220_BASE )
 #define MPS2_TS_I2C             ((MPS2_I2C_TypeDef      *) MPS2_TSC_I2C_BASE )
 #define MPS2_AAIC_I2C           ((MPS2_I2C_TypeDef      *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD1_I2C_BASE )
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef      *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef   *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )    
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )    
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )    
 
 /******************************************************************************/
 /*                     General Function Definitions                           */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct
index 24f887bcd9..625a92a2db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -1,33 +1,33 @@
 ;* MPS2 CMSIS Library
 ;*
-;* Copyright (c) 2006-2015 ARM Limited
+;* Copyright (c) 2006-2016 ARM Limited
 ;* All rights reserved.
-;* 
-;* Redistribution and use in source and binary forms, with or without 
+;*
+;* Redistribution and use in source and binary forms, with or without
 ;* modification, are permitted provided that the following conditions are met:
-;* 
-;* 1. Redistributions of source code must retain the above copyright notice, 
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
 ;* this list of conditions and the following disclaimer.
-;* 
-;* 2. Redistributions in binary form must reproduce the above copyright notice, 
-;* this list of conditions and the following disclaimer in the documentation 
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
 ;* and/or other materials provided with the distribution.
-;* 
-;* 3. Neither the name of the copyright holder nor the names of its contributors 
-;* may be used to endorse or promote products derived from this software without 
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
 ;* specific prior written permission.
-;* 
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-;* POSSIBILITY OF SUCH DAMAGE. 
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
 ;*
 ; *************************************************************
 ; *** Scatter-Loading Description File                      ***
@@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0)  {  ; RW data
+  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s
index 49c71305a7..71dff7dabf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s
@@ -1,43 +1,42 @@
-;/**************************************************************************//**
-; * @file     startup_CMSDK_CM0.s
-; * @brief    CMSIS Core Device Startup File for
-; *           CMSDK_CM0 Device
-; * @version  V3.02
-; * @date     04. February 2015
-; *
-; * @note
-; * Copyright (C) 2015 ARM Limited. All rights reserved.
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2011 - 2015 ARM LIMITED
+; MPS2 CMSIS Library
+;
+; Copyright (c) 2006-2016 ARM Limited
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;******************************************************************************
+; @file     startup_CMSDK_CM0.s
+; @brief    CMSIS Core Device Startup File for
+;           CMSDK_CM0 Device
+;
+;******************************************************************************
+;
+;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 ;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-;   *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
 ; <h> Stack Configuration
@@ -108,22 +107,22 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
                 DCD     I2S_Handler               ; I2S Handler
                 DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
+                DCD     PORT2_COMB_Handler        ; GPIO Port 2 Combined Handler
+                DCD     PORT3_COMB_Handler        ; GPIO Port 3 Combined Handler
+                DCD     UARTRX3_Handler           ; UART 3 RX Handler
+                DCD     UARTTX3_Handler           ; UART 3 TX Handler
+                DCD     UARTRX4_Handler           ; UART 4 RX Handler
+                DCD     UARTTX4_Handler           ; UART 4 TX Handler
+                DCD     ADCSPI_Handler            ; SHIELD ADC SPI exceptions Handler
+                DCD     SHIELDSPI_Handler         ; SHIELD SPI exceptions Handler
+                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler                                    
+                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler                                    
+                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler                                    
+                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler                                    
+                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler                                    
+                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler                                    
+                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler                                    
+                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler                                    
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -185,6 +184,14 @@ Default_Handler PROC
                 EXPORT ETHERNET_Handler           [WEAK]
                 EXPORT I2S_Handler                [WEAK]
                 EXPORT TSC_Handler                [WEAK]
+                EXPORT PORT2_COMB_Handler         [WEAK]
+                EXPORT PORT3_COMB_Handler         [WEAK]
+                EXPORT UARTRX3_Handler            [WEAK]
+                EXPORT UARTTX3_Handler            [WEAK]
+                EXPORT UARTRX4_Handler            [WEAK]
+                EXPORT UARTTX4_Handler            [WEAK]
+                EXPORT ADCSPI_Handler             [WEAK]
+                EXPORT SHIELDSPI_Handler          [WEAK]
                 EXPORT PORT0_0_Handler            [WEAK]
                 EXPORT PORT0_1_Handler            [WEAK]
                 EXPORT PORT0_2_Handler            [WEAK]
@@ -193,14 +200,6 @@ Default_Handler PROC
                 EXPORT PORT0_5_Handler            [WEAK]
                 EXPORT PORT0_6_Handler            [WEAK]
                 EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
 
 UARTRX0_Handler
 UARTTX0_Handler
@@ -218,22 +217,22 @@ UARTOVF_Handler
 ETHERNET_Handler
 I2S_Handler
 TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
+PORT2_COMB_Handler       
+PORT3_COMB_Handler       
+UARTRX3_Handler          
+UARTTX3_Handler          
+UARTRX4_Handler          
+UARTTX4_Handler          
+ADCSPI_Handler           
+SHIELDSPI_Handler        
+PORT0_0_Handler                                   
+PORT0_1_Handler                                   
+PORT0_2_Handler                                   
+PORT0_3_Handler                                   
+PORT0_4_Handler                                   
+PORT0_5_Handler                                   
+PORT0_6_Handler                                   
+PORT0_7_Handler                                   
                 B       .
 
                 ENDP
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h
index 14cc79d7b5..843f1e4811 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * A generic CMSIS include header, pulling in MPS2 specifics
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c
index 837273baf7..159fce69ae 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
     // Space for dynamic vectors, initialised to allocate in R/W
     static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
 
-    // Set the vector 
-    vectors[IRQn + 16] = vector; 
+    // Set the vector
+    vectors[IRQn + 16] = vector;
 }
 
 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
     // We can always read vectors at 0x0, as the addresses are remapped
-    uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; 
+    uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
 
     // Return the vector
     return vectors[IRQn + 16];
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h
index 3d3a3e2fd9..8ad5fdcd63 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -37,7 +37,7 @@
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 32)
+#define NVIC_NUM_VECTORS      (16 + 48)
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h
index 94c315ae03..80541d90d3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * Name:    Device.h
 * Purpose: Include the correct device header file
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c
index f1c17e2f62..4adf1e4a11 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     system_CMSDK_CM0.c
 * @brief    CMSIS Device System Source File for
 *           CMSDK_M0 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note
 *
 *******************************************************************************/
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h
index e6bd21b0c8..cdbd132242 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h
@@ -1,42 +1,38 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************
 * @file     system_CMSDK_CM0.h
 * @brief    CMSIS Device Peripheral Access Layer Header File for
 *           CMSDK_CM0 Device
-* @version  V3.02
-* @date     15. March 2013
-*
-* @note
 *
 ******************************************************************************/
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h
index 4689f19695..3c062956e4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     CMSDK_CM0plus.h
 * @brief    CMSIS Core Peripheral Access Layer Header File for
 *           CMSDK_CM0plus Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note     configured for CM7 without FPU
 *
 *******************************************************************************/
 
@@ -52,51 +48,48 @@
 
 typedef enum IRQn
 {
-/* -------------------  Cortex-M0+ Processor Exceptions Numbers  ------------------ */
-  NonMaskableInt_IRQn           = -14,      /*  2 Non Maskable Interrupt            */
-  HardFault_IRQn                = -13,      /*  3 HardFault Interrupt               */
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
 
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Cortex-M0 Non Maskable Interrupt              */
+  HardFault_IRQn                = -13,      /*!<  3 Cortex-M0 Hard Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SV Call Interrupt                   */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt               */
 
-
-  SVCall_IRQn                   =  -5,      /* 11 SV Call Interrupt                 */
-
-  PendSV_IRQn                   =  -2,      /* 14 Pend SV Interrupt                 */
-  SysTick_IRQn                  =  -1,      /* 15 System Tick Interrupt             */
-
-/* ----------------------  CMSDK_CM0plus Specific Interrupt Numbers  -------------- */
-  UARTRX0_IRQn                  = 0,       /* UART 0 RX Interrupt                   */
-  UARTTX0_IRQn                  = 1,       /* UART 0 TX Interrupt                   */
-  UARTRX1_IRQn                  = 2,       /* UART 1 RX Interrupt                   */
-  UARTTX1_IRQn                  = 3,       /* UART 1 TX Interrupt                   */
-  UARTRX2_IRQn                  = 4,       /* UART 2 RX Interrupt                   */
-  UARTTX2_IRQn                  = 5,       /* UART 2 TX Interrupt                   */
-  PORT0_ALL_IRQn                = 6,       /* Port 1 combined Interrupt             */
-  PORT1_ALL_IRQn                = 7,       /* Port 1 combined Interrupt             */
-  TIMER0_IRQn                   = 8,       /* TIMER 0 Interrupt                     */
-  TIMER1_IRQn                   = 9,       /* TIMER 1 Interrupt                     */
-  DUALTIMER_IRQn                = 10,      /* Dual Timer Interrupt                  */
-  SPI_IRQn                      = 11,      /* SPI Interrupt                         */
-  UARTOVF_IRQn                  = 12,      /* UART 0,1,2 Overflow Interrupt         */
-  ETHERNET_IRQn                 = 13,      /* Ethernet Interrupt                    */
-  I2S_IRQn                      = 14,      /* I2S Interrupt                         */
-  TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /* All P0 I/O pins used as irq source    */
-  PORT0_1_IRQn                  = 17,      /* There are 16 pins in total            */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+/* ----------------------  CMSDK_CM0 Specific Interrupt Numbers  ------------------ */
+  UARTRX0_IRQn                  = 0,       /*!< UART 0 RX Interrupt                               */
+  UARTTX0_IRQn                  = 1,       /*!< UART 0 TX Interrupt                               */
+  UARTRX1_IRQn                  = 2,       /*!< UART 1 RX Interrupt                               */
+  UARTTX1_IRQn                  = 3,       /*!< UART 1 TX Interrupt                               */
+  UARTRX2_IRQn                  = 4,       /*!< UART 2 RX Interrupt                               */
+  UARTTX2_IRQn                  = 5,       /*!< UART 2 TX Interrupt                               */
+  PORT0_ALL_IRQn                = 6,       /*!< Port 0 combined Interrupt                         */
+  PORT1_ALL_IRQn                = 7,       /*!< Port 1 combined Interrupt                         */
+  TIMER0_IRQn                   = 8,       /*!< TIMER 0 Interrupt                                 */
+  TIMER1_IRQn                   = 9,       /*!< TIMER 1 Interrupt                                 */
+  DUALTIMER_IRQn                = 10,      /*!< Dual Timer Interrupt                              */
+  SPI_IRQn                      = 11,      /*!< SPI Interrupt                                     */
+  UARTOVF_IRQn                  = 12,      /*!< UART 0,1,2 Overflow Interrupt                     */
+  ETHERNET_IRQn                 = 13,      /*!< Ethernet Interrupt                                */
+  I2S_IRQn                      = 14,      /*!< I2S Interrupt                                     */
+  TSC_IRQn                      = 15,      /*!< Touch Screen Interrupt                            */
+  PORT2_ALL_IRQn                = 16,      /*!< Port 2 combined Interrupt                         */
+  PORT3_ALL_IRQn                = 17,      /*!< Port 3 combined Interrupt                         */
+  UARTRX3_IRQn                  = 18,      /*!< UART 3 RX Interrupt                               */
+  UARTTX3_IRQn                  = 19,      /*!< UART 3 TX Interrupt                               */
+  UARTRX4_IRQn                  = 20,      /*!< UART 4 RX Interrupt                               */
+  UARTTX4_IRQn                  = 21,      /*!< UART 4 TX Interrupt                               */
+  ADCSPI_IRQn                   = 22,      /*!< SHIELD ADC SPI Interrupt                          */
+  SHIELDSPI_IRQn                = 23,      /*!< SHIELD SPI Combined Interrupt                     */
+  PORT0_0_IRQn                  = 24,      /*!<  GPIO Port 0 pin 0 Interrupt                      */
+  PORT0_1_IRQn                  = 25,      /*!<  GPIO Port 0 pin 1 Interrupt                      */
+  PORT0_2_IRQn                  = 26,      /*!<  GPIO Port 0 pin 2 Interrupt                      */
+  PORT0_3_IRQn                  = 27,      /*!<  GPIO Port 0 pin 3 Interrupt                      */
+  PORT0_4_IRQn                  = 28,      /*!<  GPIO Port 0 pin 4 Interrupt                      */
+  PORT0_5_IRQn                  = 29,      /*!<  GPIO Port 0 pin 5 Interrupt                      */
+  PORT0_6_IRQn                  = 30,      /*!<  GPIO Port 0 pin 6 Interrupt                      */
+  PORT0_7_IRQn                  = 31,      /*!<  GPIO Port 0 pin 7 Interrupt                      */
 } IRQn_Type;
 
 
@@ -687,7 +680,9 @@ typedef struct
 #define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
 #define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
 #define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE        (CMSDK_APB_BASE + 0x9000UL)
 #define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals                                                                  */
@@ -705,6 +700,8 @@ typedef struct
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE   )
 #define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE   )
+#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
+#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE   )
 #define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
 #define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE  )
 #define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h
index 910d5abd97..34f1a94dd9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h
@@ -1,36 +1,36 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * File:     smm_mps2.h
-* Release:  Version 1.0
+* Release:  Version 1.1
 *******************************************************************************/
 
 #ifndef __SMM_MPS2_H
@@ -46,7 +46,7 @@
 /*                          FPGA System Register declaration                  */
 /******************************************************************************/
 
-typedef struct                   
+typedef struct                 
 {
   __IO uint32_t LED;             // Offset: 0x000 (R/W)  LED connections
                                  //                         [31:2] : Reserved
@@ -65,11 +65,14 @@ typedef struct
                                  //                         Bit[31:0] : reload value for prescale counter
   __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
        uint32_t RESERVED4[9];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
-                                 //                         [31:7] : Reserved
+                                 //                         [31:10] : Reserved
+                                 //                            [9] : SHIELD_1_SPI_nCS
+                                 //                            [8] : SHIELD_0_SPI_nCS
+                                 //                            [7] : ADC_SPI_nCS
                                  //                            [6] : CLCD_BL_CTRL
                                  //                            [5] : CLCD_RD
                                  //                            [4] : CLCD_RS
@@ -93,12 +96,18 @@ typedef struct
 #define CLCD_RD_Msk        (1UL<<CLCD_RD_Pos)
 #define CLCD_BL_Pos        6
 #define CLCD_BL_Msk        (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos        7
+#define ADC_nCS_Msk        (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos        8
+#define SHIELD_0_nCS_Msk        (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos        9
+#define SHIELD_1_nCS_Msk        (1UL<<SHIELD_1_nCS_Pos)
 
 /******************************************************************************/
 /*                        SCC Register declaration                            */
 /******************************************************************************/
 
-typedef struct                   // 
+typedef struct                   //
 {
   __IO uint32_t CFG_REG0;        // Offset: 0x000 (R/W)  Remaps block RAM to ZBT
                                  //                         [31:1] : Reserved
@@ -308,10 +317,10 @@ typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
 typedef struct
 {
   union {
-  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W) 
-  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ ) 
+  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W)
+  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ )
   };
-  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)  
+  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)
 } MPS2_I2C_TypeDef;
 
 #define SDA                1 << 1
@@ -346,7 +355,7 @@ typedef struct
                               //     <4=> Undefined!
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.14..12> RX Buffer Water Level
                               //     <0=> Undefined!
                               //     <1=> / IRQ triggers when less than 1 space available
@@ -355,7 +364,7 @@ typedef struct
                               //     <4=> / IRQ triggers when less than 4 space available
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.16> FIFO reset
                               //     <0=> Normal operation
                               //     <1=> FIFO reset
@@ -363,12 +372,12 @@ typedef struct
                               //     <0=> Normal operation
                               //     <1=> Assert audio Codec reset
   /*!< Offset: 0x004 STATUS Register     (R/ ) */
-  __I    uint32_t  STATUS;  // <h> STATUS </h> 
+  __I    uint32_t  STATUS;  // <h> STATUS </h>
                               //   <o.0> TX Buffer alert
                               //     <0=> TX buffer don't need service yet
                               //     <1=> TX buffer need service
                               //   <o.1> RX Buffer alert
-                              //     <0=> RX buffer don't need service yet 
+                              //     <0=> RX buffer don't need service yet
                               //     <1=> RX buffer need service
                               //   <o.2> TX Buffer Empty
                               //     <0=> TX buffer have data
@@ -383,33 +392,33 @@ typedef struct
                               //     <0=> RX buffer not full
                               //     <1=> RX buffer full
   union {
-   /*!< Offset: 0x008 Error Status Register (R/ ) */  
-    __I    uint32_t  ERROR;  // <h> ERROR </h> 
+   /*!< Offset: 0x008 Error Status Register (R/ ) */
+    __I    uint32_t  ERROR;  // <h> ERROR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> TX overrun/underrun
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> RX overrun/underrun
-   /*!< Offset: 0x008 Error Clear Register  ( /W) */    
-    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h> 
+   /*!< Offset: 0x008 Error Clear Register  ( /W) */  
+    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> Clear TX error
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> Clear RX error
     };
-   /*!< Offset: 0x00C Divide ratio Register (R/W) */  
-  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+   /*!< Offset: 0x00C Divide ratio Register (R/W) */
+  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h>
+                              //   <o.9..0> TX error (default 0x80)                
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
-  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h>
+                              //   <o.15..0> Right channel                
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
-  __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __I    uint32_t  RXBUF;  // <h> Receive buffer </h>
+                              //   <o.15..0> Right channel                
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -556,7 +565,12 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_TSC_I2C_BASE       (0x40022000ul)       /* Touch Screen I2C Base Address */
 #define MPS2_AAIC_I2C_BASE      (0x40023000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_AAIC_I2S_BASE      (0x40024000ul)       /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE          (0x40025000ul)       /* adc SSP Base Address   */
+#define MPS2_SSP3_BASE          (0x40026000ul)       /* Shield 0 SSP Base Address   */
+#define MPS2_SSP4_BASE          (0x40027000ul)       /* Shield 1 SSP Base Address   */
 #define MPS2_FPGAIO_BASE        (0x40028000ul)       /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE   (0x40029000ul)       /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Shield 1 I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
 #ifdef CORTEX_M7
@@ -565,8 +579,8 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220_BASE           (0x40200000ul)       /* Ethernet SMSC9220 Base Address   */
 #endif
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -575,11 +589,16 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220                ((SMSC9220_TypeDef      *) SMSC9220_BASE )
 #define MPS2_TS_I2C             ((MPS2_I2C_TypeDef      *) MPS2_TSC_I2C_BASE )
 #define MPS2_AAIC_I2C           ((MPS2_I2C_TypeDef      *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD1_I2C_BASE )
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef      *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef   *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )  
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )  
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )  
 
 /******************************************************************************/
 /*                     General Function Definitions                           */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct
index 24f887bcd9..625a92a2db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -1,33 +1,33 @@
 ;* MPS2 CMSIS Library
 ;*
-;* Copyright (c) 2006-2015 ARM Limited
+;* Copyright (c) 2006-2016 ARM Limited
 ;* All rights reserved.
-;* 
-;* Redistribution and use in source and binary forms, with or without 
+;*
+;* Redistribution and use in source and binary forms, with or without
 ;* modification, are permitted provided that the following conditions are met:
-;* 
-;* 1. Redistributions of source code must retain the above copyright notice, 
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
 ;* this list of conditions and the following disclaimer.
-;* 
-;* 2. Redistributions in binary form must reproduce the above copyright notice, 
-;* this list of conditions and the following disclaimer in the documentation 
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
 ;* and/or other materials provided with the distribution.
-;* 
-;* 3. Neither the name of the copyright holder nor the names of its contributors 
-;* may be used to endorse or promote products derived from this software without 
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
 ;* specific prior written permission.
-;* 
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-;* POSSIBILITY OF SUCH DAMAGE. 
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
 ;*
 ; *************************************************************
 ; *** Scatter-Loading Description File                      ***
@@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0)  {  ; RW data
+  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s
index 005952b80e..df56e011ee 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s
@@ -1,43 +1,42 @@
-;/**************************************************************************//**
-; * @file     startup_CMSDK_CM0.s
-; * @brief    CMSIS Core Device Startup File for
-; *           CMSDK_CM0 Device
-; * @version  V3.02
-; * @date     15. November 2013
-; *
-; * @note
-; * Copyright (C) 2014 ARM Limited. All rights reserved.
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2011 - 2013 ARM LIMITED
+; MPS2 CMSIS Library
+;
+; Copyright (c) 2006-2016 ARM Limited
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;******************************************************************************
+; @file     startup_CMSDK_CM0P.s
+; @brief    CMSIS Core Device Startup File for
+;           CMSDK_CM0P Device
+;
+;******************************************************************************
+;
+;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 ;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-;   *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
 ; <h> Stack Configuration
@@ -108,22 +107,22 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
                 DCD     I2S_Handler               ; I2S Handler
                 DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
+                DCD     PORT2_COMB_Handler        ; GPIO Port 2 Combined Handler
+                DCD     PORT3_COMB_Handler        ; GPIO Port 3 Combined Handler
+                DCD     UARTRX3_Handler           ; UART 3 RX Handler
+                DCD     UARTTX3_Handler           ; UART 3 TX Handler
+                DCD     UARTRX4_Handler           ; UART 4 RX Handler
+                DCD     UARTTX4_Handler           ; UART 4 TX Handler
+                DCD     ADCSPI_Handler            ; SHIELD ADC SPI exceptions Handler
+                DCD     SHIELDSPI_Handler         ; SHIELD SPI exceptions Handler
+                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler                                   
+                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler                                   
+                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler                                   
+                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler                                   
+                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler                                   
+                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler                                   
+                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler                                   
+                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler                                   
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -164,9 +163,9 @@ PendSV_Handler  PROC
                 B       .
                 ENDP
 SysTick_Handler PROC
-               EXPORT  SysTick_Handler            [WEAK]
-               B       .
-               ENDP
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
 
 Default_Handler PROC
                 EXPORT UARTRX0_Handler            [WEAK]
@@ -185,6 +184,14 @@ Default_Handler PROC
                 EXPORT ETHERNET_Handler           [WEAK]
                 EXPORT I2S_Handler                [WEAK]
                 EXPORT TSC_Handler                [WEAK]
+                EXPORT PORT2_COMB_Handler         [WEAK]
+                EXPORT PORT3_COMB_Handler         [WEAK]
+                EXPORT UARTRX3_Handler            [WEAK]
+                EXPORT UARTTX3_Handler            [WEAK]
+                EXPORT UARTRX4_Handler            [WEAK]
+                EXPORT UARTTX4_Handler            [WEAK]
+                EXPORT ADCSPI_Handler             [WEAK]
+                EXPORT SHIELDSPI_Handler          [WEAK]
                 EXPORT PORT0_0_Handler            [WEAK]
                 EXPORT PORT0_1_Handler            [WEAK]
                 EXPORT PORT0_2_Handler            [WEAK]
@@ -193,14 +200,6 @@ Default_Handler PROC
                 EXPORT PORT0_5_Handler            [WEAK]
                 EXPORT PORT0_6_Handler            [WEAK]
                 EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
 
 UARTRX0_Handler
 UARTTX0_Handler
@@ -218,22 +217,22 @@ UARTOVF_Handler
 ETHERNET_Handler
 I2S_Handler
 TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
+PORT2_COMB_Handler      
+PORT3_COMB_Handler      
+UARTRX3_Handler         
+UARTTX3_Handler         
+UARTRX4_Handler         
+UARTTX4_Handler         
+ADCSPI_Handler          
+SHIELDSPI_Handler       
+PORT0_0_Handler                                  
+PORT0_1_Handler                                  
+PORT0_2_Handler                                  
+PORT0_3_Handler                                  
+PORT0_4_Handler                                  
+PORT0_5_Handler                                  
+PORT0_6_Handler                                  
+PORT0_7_Handler                                  
                 B       .
 
                 ENDP
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h
index 4ecd6c9f5f..42a187b43e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * A generic CMSIS include header, pulling in MPS2 specifics
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c
index 837273baf7..159fce69ae 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
     // Space for dynamic vectors, initialised to allocate in R/W
     static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
 
-    // Set the vector 
-    vectors[IRQn + 16] = vector; 
+    // Set the vector
+    vectors[IRQn + 16] = vector;
 }
 
 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
     // We can always read vectors at 0x0, as the addresses are remapped
-    uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; 
+    uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
 
     // Return the vector
     return vectors[IRQn + 16];
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h
index 3d3a3e2fd9..8ad5fdcd63 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -37,7 +37,7 @@
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 32)
+#define NVIC_NUM_VECTORS      (16 + 48)
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h
index 94c315ae03..80541d90d3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * Name:    Device.h
 * Purpose: Include the correct device header file
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c
index 8f05cb753d..2150db57af 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c
@@ -1,46 +1,41 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     system_CMSDK_CM0plus.c
 * @brief    CMSIS Device System Source File for
 *           CMSDK_M0 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note
 *
 *******************************************************************************/
 
 
-
 #include "CMSDK_CM0plus.h"
 
 /*----------------------------------------------------------------------------
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h
index 4010c8cca5..8dce0ba0a5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h
@@ -1,42 +1,38 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************
 * @file     system_CMSDK_CM0plus.h
 * @brief    CMSIS Device Peripheral Access Layer Header File for
 *           CMSDK_CM0plus Device
-* @version  V3.02
-* @date     15. March 2013
-*
-* @note
 *
 ******************************************************************************/
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h
index e4c64b9628..c9db03f941 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     CMSDK_CM3.h
 * @brief    CMSIS Core Peripheral Access Layer Header File for
 *           CMSDK_CM3 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note     configured for CM7 without FPU
 *
 *******************************************************************************/
 
@@ -63,40 +59,39 @@ typedef enum IRQn
   PendSV_IRQn                   =  -2,        /* 14 Pend SV Interrupt               */
   SysTick_IRQn                  =  -1,        /* 15 System Tick Interrupt           */
 
-/* ----------------------  CMSDK_CM3 Specific Interrupt Numbers  ------------------ */
-  UARTRX0_IRQn                  = 0,       /* UART 0 RX Interrupt                   */
-  UARTTX0_IRQn                  = 1,       /* UART 0 TX Interrupt                   */
-  UARTRX1_IRQn                  = 2,       /* UART 1 RX Interrupt                   */
-  UARTTX1_IRQn                  = 3,       /* UART 1 TX Interrupt                   */
-  UARTRX2_IRQn                  = 4,       /* UART 2 RX Interrupt                   */
-  UARTTX2_IRQn                  = 5,       /* UART 2 TX Interrupt                   */
-  PORT0_ALL_IRQn                = 6,       /* Port 1 combined Interrupt             */
-  PORT1_ALL_IRQn                = 7,       /* Port 1 combined Interrupt             */
-  TIMER0_IRQn                   = 8,       /* TIMER 0 Interrupt                     */
-  TIMER1_IRQn                   = 9,       /* TIMER 1 Interrupt                     */
-  DUALTIMER_IRQn                = 10,      /* Dual Timer Interrupt                  */
-  SPI_IRQn                      = 11,      /* SPI Interrupt                         */
-  UARTOVF_IRQn                  = 12,      /* UART 0,1,2 Overflow Interrupt         */
-  ETHERNET_IRQn                 = 13,      /* Ethernet Interrupt                    */
-  I2S_IRQn                      = 14,      /* I2S Interrupt                         */
-  TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /* All P0 I/O pins used as irq source    */
-  PORT0_1_IRQn                  = 17,      /* There are 16 pins in total            */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+/******  CMSDK Specific Interrupt Numbers *********************************************************/
+  UARTRX0_IRQn                  = 0,       /*!< UART 0 RX Interrupt                               */
+  UARTTX0_IRQn                  = 1,       /*!< UART 0 TX Interrupt                               */
+  UARTRX1_IRQn                  = 2,       /*!< UART 1 RX Interrupt                               */
+  UARTTX1_IRQn                  = 3,       /*!< UART 1 TX Interrupt                               */
+  UARTRX2_IRQn                  = 4,       /*!< UART 2 RX Interrupt                               */
+  UARTTX2_IRQn                  = 5,       /*!< UART 2 TX Interrupt                               */
+  PORT0_ALL_IRQn                = 6,       /*!< Port 0 combined Interrupt                         */
+  PORT1_ALL_IRQn                = 7,       /*!< Port 1 combined Interrupt                         */
+  TIMER0_IRQn                   = 8,       /*!< TIMER 0 Interrupt                                 */
+  TIMER1_IRQn                   = 9,       /*!< TIMER 1 Interrupt                                 */
+  DUALTIMER_IRQn                = 10,      /*!< Dual Timer Interrupt                              */
+  SPI_IRQn                      = 11,      /*!< SPI Interrupt                                     */
+  UARTOVF_IRQn                  = 12,      /*!< UART 0,1,2 Overflow Interrupt                     */
+  ETHERNET_IRQn                 = 13,      /*!< Ethernet Interrupt                                */
+  I2S_IRQn                      = 14,      /*!< I2S Interrupt                                     */
+  TSC_IRQn                      = 15,      /*!< Touch Screen Interrupt                            */
+  PORT2_ALL_IRQn                = 16,      /*!< Port 2 combined Interrupt                         */
+  PORT3_ALL_IRQn                = 17,      /*!< Port 3 combined Interrupt                         */
+  UARTRX3_IRQn                  = 18,      /*!< UART 3 RX Interrupt                               */
+  UARTTX3_IRQn                  = 19,      /*!< UART 3 TX Interrupt                               */
+  UARTRX4_IRQn                  = 20,      /*!< UART 4 RX Interrupt                               */
+  UARTTX4_IRQn                  = 21,      /*!< UART 4 TX Interrupt                               */
+  ADCSPI_IRQn                   = 22,      /*!< SHIELD ADC SPI Interrupt                          */
+  SHIELDSPI_IRQn                = 23,      /*!< SHIELD SPI Combined Interrupt                     */
+  PORT0_0_IRQn                  = 24,      /*!<  GPIO Port 0 pin 0 Interrupt                      */
+  PORT0_1_IRQn                  = 25,      /*!<  GPIO Port 0 pin 1 Interrupt                      */
+  PORT0_2_IRQn                  = 26,      /*!<  GPIO Port 0 pin 2 Interrupt                      */
+  PORT0_3_IRQn                  = 27,      /*!<  GPIO Port 0 pin 3 Interrupt                      */
+  PORT0_4_IRQn                  = 28,      /*!<  GPIO Port 0 pin 4 Interrupt                      */
+  PORT0_5_IRQn                  = 29,      /*!<  GPIO Port 0 pin 5 Interrupt                      */
+  PORT0_6_IRQn                  = 30,      /*!<  GPIO Port 0 pin 6 Interrupt                      */
+  PORT0_7_IRQn                  = 31,      /*!<  GPIO Port 0 pin 7 Interrupt                      */
 } IRQn_Type;
 
 
@@ -686,7 +681,9 @@ typedef struct
 #define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
 #define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
 #define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE        (CMSDK_APB_BASE + 0x9000UL)
 #define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals                                                                  */
@@ -704,6 +701,8 @@ typedef struct
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE   )
 #define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE   )
+#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
+#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE   )
 #define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
 #define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE  )
 #define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h
index 910d5abd97..f0d07a3c30 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h
@@ -1,36 +1,36 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * File:     smm_mps2.h
-* Release:  Version 1.0
+* Release:  Version 1.1
 *******************************************************************************/
 
 #ifndef __SMM_MPS2_H
@@ -46,7 +46,7 @@
 /*                          FPGA System Register declaration                  */
 /******************************************************************************/
 
-typedef struct                   
+typedef struct                  
 {
   __IO uint32_t LED;             // Offset: 0x000 (R/W)  LED connections
                                  //                         [31:2] : Reserved
@@ -65,11 +65,14 @@ typedef struct
                                  //                         Bit[31:0] : reload value for prescale counter
   __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
        uint32_t RESERVED4[9];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
-                                 //                         [31:7] : Reserved
+                                 //                         [31:10] : Reserved
+                                 //                            [9] : SHIELD_1_SPI_nCS
+                                 //                            [8] : SHIELD_0_SPI_nCS
+                                 //                            [7] : ADC_SPI_nCS
                                  //                            [6] : CLCD_BL_CTRL
                                  //                            [5] : CLCD_RD
                                  //                            [4] : CLCD_RS
@@ -93,12 +96,18 @@ typedef struct
 #define CLCD_RD_Msk        (1UL<<CLCD_RD_Pos)
 #define CLCD_BL_Pos        6
 #define CLCD_BL_Msk        (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos        7
+#define ADC_nCS_Msk        (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos        8
+#define SHIELD_0_nCS_Msk        (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos        9
+#define SHIELD_1_nCS_Msk        (1UL<<SHIELD_1_nCS_Pos)
 
 /******************************************************************************/
 /*                        SCC Register declaration                            */
 /******************************************************************************/
 
-typedef struct                   // 
+typedef struct                   //
 {
   __IO uint32_t CFG_REG0;        // Offset: 0x000 (R/W)  Remaps block RAM to ZBT
                                  //                         [31:1] : Reserved
@@ -308,10 +317,10 @@ typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
 typedef struct
 {
   union {
-  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W) 
-  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ ) 
+  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W)
+  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ )
   };
-  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)  
+  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W) 
 } MPS2_I2C_TypeDef;
 
 #define SDA                1 << 1
@@ -346,7 +355,7 @@ typedef struct
                               //     <4=> Undefined!
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined! 
                               //   <o.14..12> RX Buffer Water Level
                               //     <0=> Undefined!
                               //     <1=> / IRQ triggers when less than 1 space available
@@ -355,7 +364,7 @@ typedef struct
                               //     <4=> / IRQ triggers when less than 4 space available
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined! 
                               //   <o.16> FIFO reset
                               //     <0=> Normal operation
                               //     <1=> FIFO reset
@@ -363,12 +372,12 @@ typedef struct
                               //     <0=> Normal operation
                               //     <1=> Assert audio Codec reset
   /*!< Offset: 0x004 STATUS Register     (R/ ) */
-  __I    uint32_t  STATUS;  // <h> STATUS </h> 
+  __I    uint32_t  STATUS;  // <h> STATUS </h>
                               //   <o.0> TX Buffer alert
                               //     <0=> TX buffer don't need service yet
                               //     <1=> TX buffer need service
                               //   <o.1> RX Buffer alert
-                              //     <0=> RX buffer don't need service yet 
+                              //     <0=> RX buffer don't need service yet
                               //     <1=> RX buffer need service
                               //   <o.2> TX Buffer Empty
                               //     <0=> TX buffer have data
@@ -383,33 +392,33 @@ typedef struct
                               //     <0=> RX buffer not full
                               //     <1=> RX buffer full
   union {
-   /*!< Offset: 0x008 Error Status Register (R/ ) */  
-    __I    uint32_t  ERROR;  // <h> ERROR </h> 
+   /*!< Offset: 0x008 Error Status Register (R/ ) */ 
+    __I    uint32_t  ERROR;  // <h> ERROR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> TX overrun/underrun
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> RX overrun/underrun
-   /*!< Offset: 0x008 Error Clear Register  ( /W) */    
-    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h> 
+   /*!< Offset: 0x008 Error Clear Register  ( /W) */   
+    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> Clear TX error
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> Clear RX error
     };
-   /*!< Offset: 0x00C Divide ratio Register (R/W) */  
-  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+   /*!< Offset: 0x00C Divide ratio Register (R/W) */ 
+  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h>
+                              //   <o.9..0> TX error (default 0x80)                 
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
-  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h>
+                              //   <o.15..0> Right channel                 
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
-  __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __I    uint32_t  RXBUF;  // <h> Receive buffer </h>
+                              //   <o.15..0> Right channel                 
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -556,7 +565,12 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_TSC_I2C_BASE       (0x40022000ul)       /* Touch Screen I2C Base Address */
 #define MPS2_AAIC_I2C_BASE      (0x40023000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_AAIC_I2S_BASE      (0x40024000ul)       /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE          (0x40025000ul)       /* adc SSP Base Address   */
+#define MPS2_SSP3_BASE          (0x40026000ul)       /* Shield 0 SSP Base Address   */
+#define MPS2_SSP4_BASE          (0x40027000ul)       /* Shield 1 SSP Base Address   */
 #define MPS2_FPGAIO_BASE        (0x40028000ul)       /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE   (0x40029000ul)       /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Shield 1 I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
 #ifdef CORTEX_M7
@@ -565,8 +579,8 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220_BASE           (0x40200000ul)       /* Ethernet SMSC9220 Base Address   */
 #endif
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -575,11 +589,16 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220                ((SMSC9220_TypeDef      *) SMSC9220_BASE )
 #define MPS2_TS_I2C             ((MPS2_I2C_TypeDef      *) MPS2_TSC_I2C_BASE )
 #define MPS2_AAIC_I2C           ((MPS2_I2C_TypeDef      *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD1_I2C_BASE )
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef      *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef   *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )    
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )    
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )    
 
 /******************************************************************************/
 /*                     General Function Definitions                           */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct
index 24f887bcd9..625a92a2db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -1,33 +1,33 @@
 ;* MPS2 CMSIS Library
 ;*
-;* Copyright (c) 2006-2015 ARM Limited
+;* Copyright (c) 2006-2016 ARM Limited
 ;* All rights reserved.
-;* 
-;* Redistribution and use in source and binary forms, with or without 
+;*
+;* Redistribution and use in source and binary forms, with or without
 ;* modification, are permitted provided that the following conditions are met:
-;* 
-;* 1. Redistributions of source code must retain the above copyright notice, 
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
 ;* this list of conditions and the following disclaimer.
-;* 
-;* 2. Redistributions in binary form must reproduce the above copyright notice, 
-;* this list of conditions and the following disclaimer in the documentation 
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
 ;* and/or other materials provided with the distribution.
-;* 
-;* 3. Neither the name of the copyright holder nor the names of its contributors 
-;* may be used to endorse or promote products derived from this software without 
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
 ;* specific prior written permission.
-;* 
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-;* POSSIBILITY OF SUCH DAMAGE. 
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
 ;*
 ; *************************************************************
 ; *** Scatter-Loading Description File                      ***
@@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0)  {  ; RW data
+  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s
index e67bee5a75..282a082057 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s
@@ -1,43 +1,42 @@
-;/**************************************************************************//**
-; * @file     startup_CMSDK_CM3.s
-; * @brief    CMSIS Core Device Startup File for
-; *           CMSDK_CM3 Device
-; * @version  V3.02
-; * @date     15. November 2013
-; *
-; * @note
-; * Copyright (C) 2014 ARM Limited. All rights reserved.
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2011 - 2013 ARM LIMITED
+; MPS2 CMSIS Library
+;
+; Copyright (c) 2006-2016 ARM Limited
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;******************************************************************************
+; @file     startup_CMSDK_CM3.s
+; @brief    CMSIS Core Device Startup File for
+;           CMSDK_CM3 Device
+;
+;******************************************************************************
+;
+;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 ;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-; *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
 ; <h> Stack Configuration
@@ -108,22 +107,22 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
                 DCD     I2S_Handler               ; I2S Handler
                 DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
+                DCD     PORT2_COMB_Handler        ; GPIO Port 2 Combined Handler
+                DCD     PORT3_COMB_Handler        ; GPIO Port 3 Combined Handler
+                DCD     UARTRX3_Handler           ; UART 3 RX Handler
+                DCD     UARTTX3_Handler           ; UART 3 TX Handler
+                DCD     UARTRX4_Handler           ; UART 4 RX Handler
+                DCD     UARTTX4_Handler           ; UART 4 TX Handler
+                DCD     ADCSPI_Handler            ; SHIELD ADC SPI exceptions Handler
+                DCD     SHIELDSPI_Handler         ; SHIELD SPI exceptions Handler
+                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler                                    
+                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler                                    
+                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler                                    
+                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler                                    
+                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler                                    
+                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler                                    
+                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler                                    
+                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler                                    
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -205,6 +204,14 @@ Default_Handler PROC
                 EXPORT ETHERNET_Handler           [WEAK]
                 EXPORT I2S_Handler                [WEAK]
                 EXPORT TSC_Handler                [WEAK]
+                EXPORT PORT2_COMB_Handler         [WEAK]
+                EXPORT PORT3_COMB_Handler         [WEAK]
+                EXPORT UARTRX3_Handler            [WEAK]
+                EXPORT UARTTX3_Handler            [WEAK]
+                EXPORT UARTRX4_Handler            [WEAK]
+                EXPORT UARTTX4_Handler            [WEAK]
+                EXPORT ADCSPI_Handler             [WEAK]
+                EXPORT SHIELDSPI_Handler          [WEAK]
                 EXPORT PORT0_0_Handler            [WEAK]
                 EXPORT PORT0_1_Handler            [WEAK]
                 EXPORT PORT0_2_Handler            [WEAK]
@@ -213,14 +220,6 @@ Default_Handler PROC
                 EXPORT PORT0_5_Handler            [WEAK]
                 EXPORT PORT0_6_Handler            [WEAK]
                 EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
 
 UARTRX0_Handler
 UARTTX0_Handler
@@ -238,22 +237,22 @@ UARTOVF_Handler
 ETHERNET_Handler
 I2S_Handler
 TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
+PORT2_COMB_Handler       
+PORT3_COMB_Handler       
+UARTRX3_Handler          
+UARTTX3_Handler          
+UARTRX4_Handler          
+UARTTX4_Handler          
+ADCSPI_Handler           
+SHIELDSPI_Handler        
+PORT0_0_Handler                                   
+PORT0_1_Handler                                   
+PORT0_2_Handler                                   
+PORT0_3_Handler                                   
+PORT0_4_Handler                                   
+PORT0_5_Handler                                   
+PORT0_6_Handler                                   
+PORT0_7_Handler                                   
                 B       .
 
                 ENDP
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h
index fa013eff79..9f5e192376 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * A generic CMSIS include header, pulling in MPS2 specifics
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c
index f42fb77ad2..9ac558cceb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h
index 3d3a3e2fd9..8ad5fdcd63 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -37,7 +37,7 @@
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 32)
+#define NVIC_NUM_VECTORS      (16 + 48)
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h
index 94c315ae03..80541d90d3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * Name:    Device.h
 * Purpose: Include the correct device header file
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c
index cef3beecb7..06ee46c710 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     system_CMSDK_CM3.c
 * @brief    CMSIS Device System Source File for
 *           CMSDK_M3 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note
 *
 *******************************************************************************/
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h
index 7581fd5b63..15b2192f35 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h
@@ -1,42 +1,38 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************
 * @file     system_CMSDK_CM3.h
 * @brief    CMSIS Device Peripheral Access Layer Header File for
 *           CMSDK_CM3 Device
-* @version  V3.02
-* @date     15. March 2013
-*
-* @note
 *
 ******************************************************************************/
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
index 6e2c0a5f6e..ca7b64a7ac 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
@@ -1,41 +1,37 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     CMSDK_CM4.h
 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
 *           Device CMSDK_CM4
-* @version  V3.01
-* @date     06. March 2012
-*
-* @note     configured for CM7 without FPU
 *
 *******************************************************************************/
 
@@ -45,80 +41,57 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
-
-/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions
-  This file defines all structures and symbols for CMSDK_CM4:
-    - registers and bitfields
-    - peripheral base address
-    - peripheral ID
-    - Peripheral definitions
-  @{
-*/
+#endif
 
 
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions
-  Configuration of the Cortex-M4 Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
+/* -------------------------  Interrupt Number Definition  ------------------------ */
 
 typedef enum IRQn
 {
-/******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!<  2 Cortex-M4 Non Maskable Interrupt              */
-  MemoryManagement_IRQn         = -12,      /*!<  4 Cortex-M4 Memory Management Interrupt         */
-  BusFault_IRQn                 = -11,      /*!<  5 Cortex-M4 Bus Fault Interrupt                 */
-  UsageFault_IRQn               = -10,      /*!<  6 Cortex-M4 Usage Fault Interrupt               */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M4 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M4 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M4 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M4 System Tick Interrupt               */
+/* -------------------  Cortex-M3 Processor Exceptions Numbers  ------------------- */
+  NonMaskableInt_IRQn           = -14,        /*  2 Non Maskable Interrupt          */
+  HardFault_IRQn                = -13,        /*  3 HardFault Interrupt             */
+  MemoryManagement_IRQn         = -12,        /*  4 Memory Management Interrupt     */
+  BusFault_IRQn                 = -11,        /*  5 Bus Fault Interrupt             */
+  UsageFault_IRQn               = -10,        /*  6 Usage Fault Interrupt           */
+  SVCall_IRQn                   =  -5,        /* 11 SV Call Interrupt               */
+  DebugMonitor_IRQn             =  -4,        /* 12 Debug Monitor Interrupt         */
+  PendSV_IRQn                   =  -2,        /* 14 Pend SV Interrupt               */
+  SysTick_IRQn                  =  -1,        /* 15 System Tick Interrupt           */
 
-/******  CMSDK Specific Interrupt Numbers *******************************************************/
-  UARTRX0_IRQn                  = 0,       /*!< UART 0 RX Interrupt                              */
-  UARTTX0_IRQn                  = 1,       /*!< UART 0 TX Interrupt                              */
-  UARTRX1_IRQn                  = 2,       /*!< UART 1 RX Interrupt                              */
-  UARTTX1_IRQn                  = 3,       /*!< UART 1 TX Interrupt                              */
-  UARTRX2_IRQn                  = 4,       /*!< UART 2 RX Interrupt                              */
-  UARTTX2_IRQn                  = 5,       /*!< UART 2 TX Interrupt                              */
-//  UARTRX3_IRQn                  = 6,       /*!< UART 2 RX Interrupt //only used in extended version                             */
-//  UARTTX3_IRQn                  = 7,       /*!< UART 2 TX Interrupt //only used in extended version                             */
-  PORT0_ALL_IRQn                = 6,       /*!< Port 1 combined Interrupt                        */
-  PORT1_ALL_IRQn                = 7,       /*!< Port 1 combined Interrupt                        */
-  TIMER0_IRQn                   = 8,       /*!< TIMER 0 Interrupt                                */
-  TIMER1_IRQn                   = 9,       /*!< TIMER 1 Interrupt                                */
-  DUALTIMER_IRQn                = 10,      /*!< Dual Timer Interrupt                             */
-  SPI_IRQn                      = 11,      /*!< SPI Interrupt                                    */
-  UARTOVF_IRQn                  = 12,      /*!< UART 0,1,2 Overflow Interrupt                    */
-  ETHERNET_IRQn                 = 13,      /*!< Ethernet Interrupt                               */
-  I2S_IRQn                      = 14,      /*!< I2S Interrupt                                    */
-  TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /*!< All P0 I/O pins can be used as interrupt source. */
-  PORT0_1_IRQn                  = 17,      /*!< There are 16 pins in total                       */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+/******  CMSDK Specific Interrupt Numbers *********************************************************/
+  UARTRX0_IRQn                  = 0,       /*!< UART 0 RX Interrupt                               */
+  UARTTX0_IRQn                  = 1,       /*!< UART 0 TX Interrupt                               */
+  UARTRX1_IRQn                  = 2,       /*!< UART 1 RX Interrupt                               */
+  UARTTX1_IRQn                  = 3,       /*!< UART 1 TX Interrupt                               */
+  UARTRX2_IRQn                  = 4,       /*!< UART 2 RX Interrupt                               */
+  UARTTX2_IRQn                  = 5,       /*!< UART 2 TX Interrupt                               */
+  PORT0_ALL_IRQn                = 6,       /*!< Port 0 combined Interrupt                         */
+  PORT1_ALL_IRQn                = 7,       /*!< Port 1 combined Interrupt                         */
+  TIMER0_IRQn                   = 8,       /*!< TIMER 0 Interrupt                                 */
+  TIMER1_IRQn                   = 9,       /*!< TIMER 1 Interrupt                                 */
+  DUALTIMER_IRQn                = 10,      /*!< Dual Timer Interrupt                              */
+  SPI_IRQn                      = 11,      /*!< SPI Interrupt                                     */
+  UARTOVF_IRQn                  = 12,      /*!< UART 0,1,2 Overflow Interrupt                     */
+  ETHERNET_IRQn                 = 13,      /*!< Ethernet Interrupt                                */
+  I2S_IRQn                      = 14,      /*!< I2S Interrupt                                     */
+  TSC_IRQn                      = 15,      /*!< Touch Screen Interrupt                            */
+  PORT2_ALL_IRQn                = 16,      /*!< Port 2 combined Interrupt                         */
+  PORT3_ALL_IRQn                = 17,      /*!< Port 3 combined Interrupt                         */
+  UARTRX3_IRQn                  = 18,      /*!< UART 3 RX Interrupt                               */
+  UARTTX3_IRQn                  = 19,      /*!< UART 3 TX Interrupt                               */
+  UARTRX4_IRQn                  = 20,      /*!< UART 4 RX Interrupt                               */
+  UARTTX4_IRQn                  = 21,      /*!< UART 4 TX Interrupt                               */
+  ADCSPI_IRQn                   = 22,      /*!< SHIELD ADC SPI Interrupt                          */
+  SHIELDSPI_IRQn                = 23,      /*!< SHIELD SPI Combined Interrupt                     */
+  PORT0_0_IRQn                  = 24,      /*!<  GPIO Port 0 pin 0 Interrupt                      */
+  PORT0_1_IRQn                  = 25,      /*!<  GPIO Port 0 pin 1 Interrupt                      */
+  PORT0_2_IRQn                  = 26,      /*!<  GPIO Port 0 pin 2 Interrupt                      */
+  PORT0_3_IRQn                  = 27,      /*!<  GPIO Port 0 pin 3 Interrupt                      */
+  PORT0_4_IRQn                  = 28,      /*!<  GPIO Port 0 pin 4 Interrupt                      */
+  PORT0_5_IRQn                  = 29,      /*!<  GPIO Port 0 pin 5 Interrupt                      */
+  PORT0_6_IRQn                  = 30,      /*!<  GPIO Port 0 pin 6 Interrupt                      */
+  PORT0_7_IRQn                  = 31,      /*!<  GPIO Port 0 pin 7 Interrupt                      */
 } IRQn_Type;
 
 
@@ -285,23 +258,23 @@ typedef struct
   __IO uint32_t Timer1Load;                  /* Offset: 0x000 (R/W) Timer 1 Load */
   __I  uint32_t Timer1Value;                 /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
   __IO uint32_t Timer1Control;               /* Offset: 0x008 (R/W) Timer 1 Control */
-                              //   <o.7> TimerEn: Timer Enable
-                              //   <o.6> TimerMode: Timer Mode
-                              //     <0=> Freerunning-mode
-                              //     <1=> Periodic mode
-                              //   <o.5> IntEnable: Interrupt Enable
-                              //   <o.2..3> TimerPre: Timer Prescale
-                              //     <0=> / 1
-                              //     <1=> / 16
-                              //     <2=> / 256
-                              //     <3=> Undefined!
-                              //   <o.1> TimerSize: Timer Size
-                              //     <0=> 16-bit counter
-                              //     <1=> 32-bit counter
-                              //   <o.0> OneShot: One-shoot mode
-                              //     <0=> Wrapping mode
-                              //     <1=> One-shot mode
-                              // </h>
+                                             /* <o.7> TimerEn: Timer Enable         */
+                                             /* <o.6> TimerMode: Timer Mode         */
+                                             /*   <0=> Freerunning-mode             */
+                                             /*   <1=> Periodic mode                */
+                                             /* <o.5> IntEnable: Interrupt Enable   */
+                                             /* <o.2..3> TimerPre: Timer Prescale   */
+                                             /*   <0=> / 1                          */
+                                             /*   <1=> / 16                         */
+                                             /*   <2=> / 256                        */
+                                             /*   <3=> Undefined!                   */
+                                             /* <o.1> TimerSize: Timer Size         */
+                                             /*   <0=> 16-bit counter               */
+                                             /*   <1=> 32-bit counter               */
+                                             /* <o.0> OneShot: One-shoot mode       */
+                                             /*   <0=> Wrapping mode                */
+                                             /*   <1=> One-shot mode                */
+                                             /* </h>                                */
   __O  uint32_t Timer1IntClr;                /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
   __I  uint32_t Timer1RIS;                   /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
   __I  uint32_t Timer1MIS;                   /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
@@ -310,23 +283,23 @@ typedef struct
   __IO uint32_t Timer2Load;                  /* Offset: 0x020 (R/W) Timer 2 Load */
   __I  uint32_t Timer2Value;                 /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
   __IO uint32_t Timer2Control;               /* Offset: 0x028 (R/W) Timer 2 Control */
-                              //   <o.7> TimerEn: Timer Enable
-                              //   <o.6> TimerMode: Timer Mode
-                              //     <0=> Freerunning-mode
-                              //     <1=> Periodic mode
-                              //   <o.5> IntEnable: Interrupt Enable
-                              //   <o.2..3> TimerPre: Timer Prescale
-                              //     <0=> / 1
-                              //     <1=> / 16
-                              //     <2=> / 256
-                              //     <3=> Undefined!
-                              //   <o.1> TimerSize: Timer Size
-                              //     <0=> 16-bit counter
-                              //     <1=> 32-bit counter
-                              //   <o.0> OneShot: One-shoot mode
-                              //     <0=> Wrapping mode
-                              //     <1=> One-shot mode
-                              // </h>
+                                             /* <o.7> TimerEn: Timer Enable         */
+                                             /* <o.6> TimerMode: Timer Mode         */
+                                             /*   <0=> Freerunning-mode             */
+                                             /*   <1=> Periodic mode                */
+                                             /* <o.5> IntEnable: Interrupt Enable   */
+                                             /* <o.2..3> TimerPre: Timer Prescale   */
+                                             /*   <0=> / 1                          */
+                                             /*   <1=> / 16                         */
+                                             /*   <2=> / 256                        */
+                                             /*   <3=> Undefined!                   */
+                                             /* <o.1> TimerSize: Timer Size         */
+                                             /*   <0=> 16-bit counter               */
+                                             /*   <1=> 32-bit counter               */
+                                             /* <o.0> OneShot: One-shoot mode       */
+                                             /*   <0=> Wrapping mode                */
+                                             /*   <1=> One-shot mode                */
+                                             /* </h>                                */
   __O  uint32_t Timer2IntClr;                /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
   __I  uint32_t Timer2RIS;                   /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
   __I  uint32_t Timer2MIS;                   /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
@@ -413,23 +386,23 @@ typedef struct
   __IO uint32_t TimerLoad;                   /* Offset: 0x000 (R/W) Timer Load */
   __I  uint32_t TimerValue;                  /* Offset: 0x000 (R/W) Timer Counter Current Value */
   __IO uint32_t TimerControl;                /* Offset: 0x000 (R/W) Timer Control */
-                              //   <o.7> TimerEn: Timer Enable
-                              //   <o.6> TimerMode: Timer Mode
-                              //     <0=> Freerunning-mode
-                              //     <1=> Periodic mode
-                              //   <o.5> IntEnable: Interrupt Enable
-                              //   <o.2..3> TimerPre: Timer Prescale
-                              //     <0=> / 1
-                              //     <1=> / 16
-                              //     <2=> / 256
-                              //     <3=> Undefined!
-                              //   <o.1> TimerSize: Timer Size
-                              //     <0=> 16-bit counter
-                              //     <1=> 32-bit counter
-                              //   <o.0> OneShot: One-shoot mode
-                              //     <0=> Wrapping mode
-                              //     <1=> One-shot mode
-                              // </h>
+                                             /* <o.7> TimerEn: Timer Enable         */
+                                             /* <o.6> TimerMode: Timer Mode         */
+                                             /*   <0=> Freerunning-mode             */
+                                             /*   <1=> Periodic mode                */
+                                             /* <o.5> IntEnable: Interrupt Enable   */
+                                             /* <o.2..3> TimerPre: Timer Prescale   */
+                                             /*   <0=> / 1                          */
+                                             /*   <1=> / 16                         */
+                                             /*   <2=> / 256                        */
+                                             /*   <3=> Undefined!                   */
+                                             /* <o.1> TimerSize: Timer Size         */
+                                             /*   <0=> 16-bit counter               */
+                                             /*   <1=> 32-bit counter               */
+                                             /* <o.0> OneShot: One-shoot mode       */
+                                             /*   <0=> Wrapping mode                */
+                                             /*   <1=> One-shot mode                */
+                                             /* </h>                                */
   __O  uint32_t TimerIntClr;                 /* Offset: 0x000 (R/W) Timer Interrupt Clear */
   __I  uint32_t TimerRIS;                    /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
   __I  uint32_t TimerMIS;                    /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
@@ -1146,9 +1119,9 @@ typedef struct
   __IO    uint32_t  LOAD;                   /* Offset: 0x000 (R/W) Watchdog Load Register */
   __I     uint32_t  VALUE;                  /* Offset: 0x004 (R/ ) Watchdog Value Register */
   __IO    uint32_t  CTRL;                   /* Offset: 0x008 (R/W) Watchdog Control Register */
-                                   //   <o.1>    RESEN: Reset enable
-                                   //   <o.0>    INTEN: Interrupt enable
-                                   // </h>
+                                            /*    <o.1>    RESEN: Reset enable               */
+                                            /*    <o.0>    INTEN: Interrupt enable           */
+                                            /*    </h>                                       */
   __O     uint32_t  INTCLR;                 /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
   __I     uint32_t  RAWINTSTAT;             /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
   __I     uint32_t  MASKINTSTAT;            /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
@@ -1278,8 +1251,9 @@ __IO    uint32_t  MODECTRL;
 #define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
 #define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
 #define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
-//#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL) //only used in extended version
+#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE        (CMSDK_APB_BASE + 0x9000UL)
 #define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals                                                           */
@@ -1301,9 +1275,10 @@ __IO    uint32_t  MODECTRL;
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE )
 #define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE )
-//#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE ) //only used in extended version
-#define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE )
-#define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE )
+#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
+#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE   )
+#define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
+#define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE  )
 #define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
 #define CMSDK_DUALTIMER1        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_1_BASE )
 #define CMSDK_DUALTIMER2        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_2_BASE )
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h
index 910d5abd97..3b51430235 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h
@@ -1,36 +1,36 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * File:     smm_mps2.h
-* Release:  Version 1.0
+* Release:  Version 1.1
 *******************************************************************************/
 
 #ifndef __SMM_MPS2_H
@@ -46,7 +46,7 @@
 /*                          FPGA System Register declaration                  */
 /******************************************************************************/
 
-typedef struct                   
+typedef struct
 {
   __IO uint32_t LED;             // Offset: 0x000 (R/W)  LED connections
                                  //                         [31:2] : Reserved
@@ -65,11 +65,14 @@ typedef struct
                                  //                         Bit[31:0] : reload value for prescale counter
   __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
        uint32_t RESERVED4[9];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
-                                 //                         [31:7] : Reserved
+                                 //                         [31:10] : Reserved
+                                 //                            [9] : SHIELD_1_SPI_nCS
+                                 //                            [8] : SHIELD_0_SPI_nCS
+                                 //                            [7] : ADC_SPI_nCS
                                  //                            [6] : CLCD_BL_CTRL
                                  //                            [5] : CLCD_RD
                                  //                            [4] : CLCD_RS
@@ -93,12 +96,18 @@ typedef struct
 #define CLCD_RD_Msk        (1UL<<CLCD_RD_Pos)
 #define CLCD_BL_Pos        6
 #define CLCD_BL_Msk        (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos        7
+#define ADC_nCS_Msk        (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos        8
+#define SHIELD_0_nCS_Msk        (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos        9
+#define SHIELD_1_nCS_Msk        (1UL<<SHIELD_1_nCS_Pos)
 
 /******************************************************************************/
 /*                        SCC Register declaration                            */
 /******************************************************************************/
 
-typedef struct                   // 
+typedef struct                   //
 {
   __IO uint32_t CFG_REG0;        // Offset: 0x000 (R/W)  Remaps block RAM to ZBT
                                  //                         [31:1] : Reserved
@@ -308,10 +317,10 @@ typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
 typedef struct
 {
   union {
-  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W) 
-  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ ) 
+  __O   uint32_t  CONTROLS;     // Offset: 0x000 CONTROL Set Register     ( /W)
+  __I   uint32_t  CONTROL;      // Offset: 0x000 CONTROL Status Register  (R/ )
   };
-  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)  
+  __O    uint32_t  CONTROLC;     // Offset: 0x004 CONTROL Clear Register    ( /W)
 } MPS2_I2C_TypeDef;
 
 #define SDA                1 << 1
@@ -346,7 +355,7 @@ typedef struct
                               //     <4=> Undefined!
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.14..12> RX Buffer Water Level
                               //     <0=> Undefined!
                               //     <1=> / IRQ triggers when less than 1 space available
@@ -355,7 +364,7 @@ typedef struct
                               //     <4=> / IRQ triggers when less than 4 space available
                               //     <5=> Undefined!
                               //     <6=> Undefined!
-                              //     <7=> Undefined!  
+                              //     <7=> Undefined!
                               //   <o.16> FIFO reset
                               //     <0=> Normal operation
                               //     <1=> FIFO reset
@@ -363,12 +372,12 @@ typedef struct
                               //     <0=> Normal operation
                               //     <1=> Assert audio Codec reset
   /*!< Offset: 0x004 STATUS Register     (R/ ) */
-  __I    uint32_t  STATUS;  // <h> STATUS </h> 
+  __I    uint32_t  STATUS;  // <h> STATUS </h>
                               //   <o.0> TX Buffer alert
                               //     <0=> TX buffer don't need service yet
                               //     <1=> TX buffer need service
                               //   <o.1> RX Buffer alert
-                              //     <0=> RX buffer don't need service yet 
+                              //     <0=> RX buffer don't need service yet
                               //     <1=> RX buffer need service
                               //   <o.2> TX Buffer Empty
                               //     <0=> TX buffer have data
@@ -383,33 +392,33 @@ typedef struct
                               //     <0=> RX buffer not full
                               //     <1=> RX buffer full
   union {
-   /*!< Offset: 0x008 Error Status Register (R/ ) */  
-    __I    uint32_t  ERROR;  // <h> ERROR </h> 
+   /*!< Offset: 0x008 Error Status Register (R/ ) */
+    __I    uint32_t  ERROR;  // <h> ERROR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> TX overrun/underrun
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> RX overrun/underrun
-   /*!< Offset: 0x008 Error Clear Register  ( /W) */    
-    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h> 
+   /*!< Offset: 0x008 Error Clear Register  ( /W) */
+    __O    uint32_t  ERRORCLR;  // <h> ERRORCLR </h>
                               //   <o.0> TX error
                               //     <0=> Okay
                               //     <1=> Clear TX error
                               //   <o.1> RX error
-                              //     <0=> Okay 
+                              //     <0=> Okay
                               //     <1=> Clear RX error
     };
-   /*!< Offset: 0x00C Divide ratio Register (R/W) */  
-  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+   /*!< Offset: 0x00C Divide ratio Register (R/W) */
+  __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h>
+                              //   <o.9..0> TX error (default 0x80)
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
-  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __O    uint32_t  TXBUF;  // <h> Transmit buffer </h>
+                              //   <o.15..0> Right channel
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
-  __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+  __I    uint32_t  RXBUF;  // <h> Receive buffer </h>
+                              //   <o.15..0> Right channel
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -556,7 +565,12 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_TSC_I2C_BASE       (0x40022000ul)       /* Touch Screen I2C Base Address */
 #define MPS2_AAIC_I2C_BASE      (0x40023000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_AAIC_I2S_BASE      (0x40024000ul)       /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE          (0x40025000ul)       /* adc SSP Base Address   */
+#define MPS2_SSP3_BASE          (0x40026000ul)       /* Shield 0 SSP Base Address   */
+#define MPS2_SSP4_BASE          (0x40027000ul)       /* Shield 1 SSP Base Address   */
 #define MPS2_FPGAIO_BASE        (0x40028000ul)       /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE   (0x40029000ul)       /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Shield 1 I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
 #ifdef CORTEX_M7
@@ -565,8 +579,8 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220_BASE           (0x40200000ul)       /* Ethernet SMSC9220 Base Address   */
 #endif
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -575,11 +589,16 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220                ((SMSC9220_TypeDef      *) SMSC9220_BASE )
 #define MPS2_TS_I2C             ((MPS2_I2C_TypeDef      *) MPS2_TSC_I2C_BASE )
 #define MPS2_AAIC_I2C           ((MPS2_I2C_TypeDef      *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD1_I2C_BASE )
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef      *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef   *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )
 
 /******************************************************************************/
 /*                     General Function Definitions                           */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct
index 24f887bcd9..625a92a2db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -1,33 +1,33 @@
 ;* MPS2 CMSIS Library
 ;*
-;* Copyright (c) 2006-2015 ARM Limited
+;* Copyright (c) 2006-2016 ARM Limited
 ;* All rights reserved.
-;* 
-;* Redistribution and use in source and binary forms, with or without 
+;*
+;* Redistribution and use in source and binary forms, with or without
 ;* modification, are permitted provided that the following conditions are met:
-;* 
-;* 1. Redistributions of source code must retain the above copyright notice, 
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
 ;* this list of conditions and the following disclaimer.
-;* 
-;* 2. Redistributions in binary form must reproduce the above copyright notice, 
-;* this list of conditions and the following disclaimer in the documentation 
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
 ;* and/or other materials provided with the distribution.
-;* 
-;* 3. Neither the name of the copyright holder nor the names of its contributors 
-;* may be used to endorse or promote products derived from this software without 
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
 ;* specific prior written permission.
-;* 
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-;* POSSIBILITY OF SUCH DAMAGE. 
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
 ;*
 ; *************************************************************
 ; *** Scatter-Loading Description File                      ***
@@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0)  {  ; RW data
+  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s
index 53fc0f0a55..29a1f3285f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s
@@ -1,41 +1,38 @@
 ; MPS2 CMSIS Library
 ;
-; Copyright (c) 2006-2015 ARM Limited
+; Copyright (c) 2006-2016 ARM Limited
 ; All rights reserved.
-; 
-; Redistribution and use in source and binary forms, with or without 
+;
+; Redistribution and use in source and binary forms, with or without
 ; modification, are permitted provided that the following conditions are met:
-; 
-; 1. Redistributions of source code must retain the above copyright notice, 
+;
+; 1. Redistributions of source code must retain the above copyright notice,
 ; this list of conditions and the following disclaimer.
-; 
-; 2. Redistributions in binary form must reproduce the above copyright notice, 
-; this list of conditions and the following disclaimer in the documentation 
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
 ; and/or other materials provided with the distribution.
-; 
-; 3. Neither the name of the copyright holder nor the names of its contributors 
-; may be used to endorse or promote products derived from this software without 
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
 ; specific prior written permission.
-; 
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-; POSSIBILITY OF SUCH DAMAGE. 
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
 ;******************************************************************************
 ; @file     startup_CMSDK_CM4.s
 ; @brief    CMSIS Core Device Startup File for
 ;           CMSDK_CM4 Device
-; @version  V3.03
-; @date     04. February 2015
 ;
-; @note
 ;******************************************************************************
 ;
 ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@@ -110,22 +107,22 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
                 DCD     I2S_Handler               ; I2S Handler
                 DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
+                DCD     PORT2_COMB_Handler        ; GPIO Port 2 Combined Handler
+                DCD     PORT3_COMB_Handler        ; GPIO Port 3 Combined Handler
+                DCD     UARTRX3_Handler           ; UART 3 RX Handler
+                DCD     UARTTX3_Handler           ; UART 3 TX Handler
+                DCD     UARTRX4_Handler           ; UART 4 RX Handler
+                DCD     UARTTX4_Handler           ; UART 4 TX Handler
+                DCD     ADCSPI_Handler            ; SHIELD ADC SPI exceptions Handler
+                DCD     SHIELDSPI_Handler         ; SHIELD SPI exceptions Handler
+                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler                                    
+                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler                                    
+                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler                                    
+                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler                                    
+                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler                                    
+                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler                                    
+                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler                                    
+                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler                                    
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -207,6 +204,14 @@ Default_Handler PROC
                 EXPORT ETHERNET_Handler           [WEAK]
                 EXPORT I2S_Handler                [WEAK]
                 EXPORT TSC_Handler                [WEAK]
+                EXPORT PORT2_COMB_Handler         [WEAK]
+                EXPORT PORT3_COMB_Handler         [WEAK]
+                EXPORT UARTRX3_Handler            [WEAK]
+                EXPORT UARTTX3_Handler            [WEAK]
+                EXPORT UARTRX4_Handler            [WEAK]
+                EXPORT UARTTX4_Handler            [WEAK]
+                EXPORT ADCSPI_Handler             [WEAK]
+                EXPORT SHIELDSPI_Handler          [WEAK]
                 EXPORT PORT0_0_Handler            [WEAK]
                 EXPORT PORT0_1_Handler            [WEAK]
                 EXPORT PORT0_2_Handler            [WEAK]
@@ -215,14 +220,6 @@ Default_Handler PROC
                 EXPORT PORT0_5_Handler            [WEAK]
                 EXPORT PORT0_6_Handler            [WEAK]
                 EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
 
 UARTRX0_Handler
 UARTTX0_Handler
@@ -240,22 +237,22 @@ UARTOVF_Handler
 ETHERNET_Handler
 I2S_Handler
 TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
+PORT2_COMB_Handler       
+PORT3_COMB_Handler       
+UARTRX3_Handler          
+UARTTX3_Handler          
+UARTRX4_Handler          
+UARTTX4_Handler          
+ADCSPI_Handler           
+SHIELDSPI_Handler        
+PORT0_0_Handler                                   
+PORT0_1_Handler                                   
+PORT0_2_Handler                                   
+PORT0_3_Handler                                   
+PORT0_4_Handler                                   
+PORT0_5_Handler                                   
+PORT0_6_Handler                                   
+PORT0_7_Handler                                   
                 B       .
 
                 ENDP
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h
index 8ac8c691a2..562e9abd11 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * A generic CMSIS include header, pulling in MPS2 specifics
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c
index f42fb77ad2..9ac558cceb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h
index 3d3a3e2fd9..8ad5fdcd63 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * CMSIS-style functionality to support dynamic vectors
 *******************************************************************************/
@@ -37,7 +37,7 @@
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 32)
+#define NVIC_NUM_VECTORS      (16 + 48)
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h
index 94c315ae03..80541d90d3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h
@@ -1,33 +1,33 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * Name:    Device.h
 * Purpose: Include the correct device header file
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c
index a2c37a4105..2b528a92c4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c
@@ -1,46 +1,41 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************
 * @file     system_CMSDK_CM4.c
 * @brief    CMSIS Device System Source File for
 *           CMSDK_M4 Device
-* @version  V3.02
-* @date     15. November 2013
-*
-* @note
 *
 *******************************************************************************/
 
 
-
 #include "CMSDK_CM4.h"
 
 /*----------------------------------------------------------------------------
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h
index b71521e761..c1cb7e25fc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h
@@ -1,42 +1,38 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
-* 
-* Redistribution and use in source and binary forms, with or without 
+*
+* Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice, 
+*
+* 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice, 
-* this list of conditions and the following disclaimer in the documentation 
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
-* 
-* 3. Neither the name of the copyright holder nor the names of its contributors 
-* may be used to endorse or promote products derived from this software without 
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
 * specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
-* POSSIBILITY OF SUCH DAMAGE. 
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************
 * @file     system_CMSDK_CM4.h
 * @brief    CMSIS Device Peripheral Access Layer Header File for
 *           CMSDK_CM4 Device
-* @version  V3.02
-* @date     15. March 2013
-*
-* @note
 *
 ******************************************************************************/
 
@@ -76,5 +72,4 @@ extern void SystemCoreClockUpdate (void);
 #ifdef __cplusplus
 }
 #endif
-
 #endif /* SYSTEM_CMSDK_CM4_H */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h
index ec6cbf16ea..bccd748bc8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h
@@ -1,6 +1,6 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
@@ -32,10 +32,6 @@
 * @file     CMSDK_CM7.h
 * @brief    CMSIS Core Peripheral Access Layer Header File for
 *           CMSDK_CM7 Device
-* @version  V1.00
-* @date     27. August 2014
-*
-* @note     configured for CM7 without FPU
 *
 *******************************************************************************/
 
@@ -52,16 +48,16 @@ extern "C" {
 
 typedef enum IRQn
 {
-/* -------------------  CM7 Processor Exceptions Numbers  --------------------- */
-  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt             */
-//  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt                */
-  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt        */
-  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt                */
-  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt              */
-  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt                  */
-  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt            */
-  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt                  */
-  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt              */
+/* -------------------  Cortex-M7 Processor Exceptions Numbers  ------------------- */
+  NonMaskableInt_IRQn           = -14,        /*  2 Non Maskable Interrupt          */
+  HardFault_IRQn                = -13,        /*  3 HardFault Interrupt             */
+  MemoryManagement_IRQn         = -12,        /*  4 Memory Management Interrupt     */
+  BusFault_IRQn                 = -11,        /*  5 Bus Fault Interrupt             */
+  UsageFault_IRQn               = -10,        /*  6 Usage Fault Interrupt           */
+  SVCall_IRQn                   =  -5,        /* 11 SV Call Interrupt               */
+  DebugMonitor_IRQn             =  -4,        /* 12 Debug Monitor Interrupt         */
+  PendSV_IRQn                   =  -2,        /* 14 Pend SV Interrupt               */
+  SysTick_IRQn                  =  -1,        /* 15 System Tick Interrupt           */
 
 /* ----------------------  CMSDK_CM7 Specific Interrupt Numbers  -------------- */
   UARTRX0_IRQn                  = 0,       /* UART 0 RX Interrupt                   */
@@ -80,23 +76,22 @@ typedef enum IRQn
   ETHERNET_IRQn                 = 13,      /* Ethernet Interrupt                    */
   I2S_IRQn                      = 14,      /* I2S Interrupt                         */
   TSC_IRQn                      = 15,      /* Touch Screen Interrupt                */
-//  DMA_IRQn                      = 15,      /* PL230 DMA Done + Error Interrupt      */
-  PORT0_0_IRQn                  = 16,      /* All P0 I/O pins used as irq source    */
-  PORT0_1_IRQn                  = 17,      /* There are 16 pins in total            */
-  PORT0_2_IRQn                  = 18,
-  PORT0_3_IRQn                  = 19,
-  PORT0_4_IRQn                  = 20,
-  PORT0_5_IRQn                  = 21,
-  PORT0_6_IRQn                  = 22,
-  PORT0_7_IRQn                  = 23,
-  PORT0_8_IRQn                  = 24,
-  PORT0_9_IRQn                  = 25,
-  PORT0_10_IRQn                 = 26,
-  PORT0_11_IRQn                 = 27,
-  PORT0_12_IRQn                 = 28,
-  PORT0_13_IRQn                 = 29,
-  PORT0_14_IRQn                 = 30,
-  PORT0_15_IRQn                 = 31,
+  PORT2_ALL_IRQn                = 16,      /*< Port 2 combined Interrupt                         */
+  PORT3_ALL_IRQn                = 17,      /*< Port 3 combined Interrupt                         */
+  UARTRX3_IRQn                  = 18,      /*< UART 3 RX Interrupt                               */
+  UARTTX3_IRQn                  = 19,      /*< UART 3 TX Interrupt                               */
+  UARTRX4_IRQn                  = 20,      /*< UART 4 RX Interrupt                               */
+  UARTTX4_IRQn                  = 21,      /*< UART 4 TX Interrupt                               */
+  ADCSPI_IRQn                   = 22,      /*< SHIELD ADC SPI Interrupt                          */
+  SHIELDSPI_IRQn                = 23,      /*< SHIELD SPI Combined Interrupt                     */
+  PORT0_0_IRQn                  = 24,      /*<  GPIO Port 0 pin 0 Interrupt                      */
+  PORT0_1_IRQn                  = 25,      /*<  GPIO Port 0 pin 1 Interrupt                      */
+  PORT0_2_IRQn                  = 26,      /*<  GPIO Port 0 pin 2 Interrupt                      */
+  PORT0_3_IRQn                  = 27,      /*<  GPIO Port 0 pin 3 Interrupt                      */
+  PORT0_4_IRQn                  = 28,      /*<  GPIO Port 0 pin 4 Interrupt                      */
+  PORT0_5_IRQn                  = 29,      /*<  GPIO Port 0 pin 5 Interrupt                      */
+  PORT0_6_IRQn                  = 30,      /*<  GPIO Port 0 pin 6 Interrupt                      */
+  PORT0_7_IRQn                  = 31,      /*<  GPIO Port 0 pin 7 Interrupt                      */
 } IRQn_Type;
 
 
@@ -105,12 +100,12 @@ typedef enum IRQn
 /* ================================================================================ */
 
 /* --------  Configuration of the CM7 Processor and Core Peripherals  --------- */
-#define __CM4_REV                 0x0000      /* Core revision r0p0                              */
+#define __CM7_REV                 0x0101      /* Core revision r1p1                              */
 #define __MPU_PRESENT             1           /* MPU present or not                              */
 #define __NVIC_PRIO_BITS          3           /* Number of Bits used for Priority Levels         */
 #define __Vendor_SysTickConfig    0           /* Set to 1 if different SysTick Config is used    */
 #define __FPU_PRESENT             1           /* no FPU present                                  */
-#define __FPU_DP                  1          /* unused                                          */
+#define __FPU_DP                  1           /* unused                                          */
 #define __ICACHE_PRESENT          1
 #define __DCACHE_PRESENT          1
 
@@ -694,7 +689,9 @@ typedef struct
 #define CMSDK_UART0_BASE        (CMSDK_APB_BASE + 0x4000UL)
 #define CMSDK_UART1_BASE        (CMSDK_APB_BASE + 0x5000UL)
 #define CMSDK_UART2_BASE        (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_UART3_BASE        (CMSDK_APB_BASE + 0x7000UL)
 #define CMSDK_WATCHDOG_BASE     (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE        (CMSDK_APB_BASE + 0x9000UL)
 #define CMSDK_PL230_BASE        (CMSDK_APB_BASE + 0xF000UL)
 
 /* AHB peripherals */
@@ -712,6 +709,8 @@ typedef struct
 #define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE   )
 #define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
 #define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE   )
+#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE   )
+#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE   )
 #define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE  )
 #define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE  )
 #define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
index a7a3bc1cc6..5ccbd0a4d0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
@@ -1,6 +1,6 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
 * POSSIBILITY OF SUCH DAMAGE. 
 *******************************************************************************
 * File:     smm_mps2.h
-* Release:  Version 1.0
+* Release:  Version 1.1
 *******************************************************************************/
 
 #ifndef __SMM_MPS2_H
@@ -65,11 +65,14 @@ typedef struct
                                  //                         Bit[31:0] : reload value for prescale counter
   __IO uint32_t PSCNTR;          // Offset: 0x024 (R/W)  32-bit Prescale counter
                                  //                         current value of the pre-scaler counter
-								 //                         The Cycle Up Counter increment when the prescale down counter reach 0
-								 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+                                 //                         The Cycle Up Counter increment when the prescale down counter reach 0
+                                 //                         The pre-scaler counter is reloaded with PRESCALE after reaching 0.
        uint32_t RESERVED4[9];
   __IO uint32_t MISC;            // Offset: 0x04C (R/W)  Misc control */
-                                 //                         [31:7] : Reserved
+                                 //                         [31:10] : Reserved
+                                 //                            [9] : SHIELD_1_SPI_nCS
+                                 //                            [8] : SHIELD_0_SPI_nCS
+                                 //                            [7] : ADC_SPI_nCS
                                  //                            [6] : CLCD_BL_CTRL
                                  //                            [5] : CLCD_RD
                                  //                            [4] : CLCD_RS
@@ -93,6 +96,12 @@ typedef struct
 #define CLCD_RD_Msk        (1UL<<CLCD_RD_Pos)
 #define CLCD_BL_Pos        6
 #define CLCD_BL_Msk        (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos        7
+#define ADC_nCS_Msk        (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos        8
+#define SHIELD_0_nCS_Msk        (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos        9
+#define SHIELD_1_nCS_Msk        (1UL<<SHIELD_1_nCS_Pos)
 
 /******************************************************************************/
 /*                        SCC Register declaration                            */
@@ -402,14 +411,14 @@ typedef struct
     };
    /*!< Offset: 0x00C Divide ratio Register (R/W) */  
   __IO   uint32_t  DIVIDE;  // <h> Divide ratio for Left/Right clock </h> 
-                              //   <o.9..0> TX error (default 0x80)			      
+                              //   <o.9..0> TX error (default 0x80)                  
    /*!< Offset: 0x010 Transmit Buffer       ( /W) */
   __O    uint32_t  TXBUF;  // <h> Transmit buffer </h> 
-                              //   <o.15..0> Right channel			      
+                              //   <o.15..0> Right channel                  
                               //   <o.31..16> Left channel
    /*!< Offset: 0x014 Receive Buffer        (R/ ) */
   __I    uint32_t  RXBUF;  // <h> Receive buffer </h> 
-                              //   <o.15..0> Right channel			      
+                              //   <o.15..0> Right channel                  
                               //   <o.31..16> Left channel
          uint32_t  RESERVED1[186];
   __IO uint32_t ITCR;         // <h> Integration Test Control Register </h>
@@ -556,13 +565,18 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define MPS2_TSC_I2C_BASE       (0x40022000ul)       /* Touch Screen I2C Base Address */
 #define MPS2_AAIC_I2C_BASE      (0x40023000ul)       /* Audio Interface I2C Base Address */
 #define MPS2_AAIC_I2S_BASE      (0x40024000ul)       /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE          (0x40025000ul)       /* adc SSP Base Address   */
+#define MPS2_SSP3_BASE          (0x40026000ul)       /* Shield 0 SSP Base Address   */
+#define MPS2_SSP4_BASE          (0x40027000ul)       /* Shield 1 SSP Base Address   */
 #define MPS2_FPGAIO_BASE        (0x40028000ul)       /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE   (0x40029000ul)       /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE   (0x4002A000ul)       /* Shield 1 I2C Base Address */
 #define MPS2_SCC_BASE           (0x4002F000ul)       /* SCC Base Address    */
 
 #define SMSC9220_BASE           (0xA0000000ul)       /* Ethernet SMSC9220 Base Address   */
 
-#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 #define MPS2_VGA_TEXT_BUFFER    (0x41000000ul)       /* VGA Text Buffer Address */
+#define MPS2_VGA_BUFFER         (0x41100000ul)       /* VGA Buffer Base Address */
 
 /******************************************************************************/
 /*                         Peripheral declaration                             */
@@ -571,11 +585,16 @@ __IO  uint32_t  E2P_DATA;              //   EEPROM Data (offset 0xB4)
 #define SMSC9220                ((SMSC9220_TypeDef      *) SMSC9220_BASE )
 #define MPS2_TS_I2C             ((MPS2_I2C_TypeDef      *) MPS2_TSC_I2C_BASE )
 #define MPS2_AAIC_I2C           ((MPS2_I2C_TypeDef      *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C        ((MPS2_I2C_TypeDef      *) MPS2_SHIELD1_I2C_BASE )
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef      *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef   *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef      *) MPS2_SCC_BASE )
 #define MPS2_SSP0               ((MPS2_SSP_TypeDef      *) MPS2_SSP0_BASE )
 #define MPS2_SSP1               ((MPS2_SSP_TypeDef      *) MPS2_SSP1_BASE )
+#define MPS2_SSP2               ((MPS2_SSP_TypeDef      *) MPS2_SSP2_BASE )    
+#define MPS2_SSP3               ((MPS2_SSP_TypeDef      *) MPS2_SSP3_BASE )    
+#define MPS2_SSP4               ((MPS2_SSP_TypeDef      *) MPS2_SSP4_BASE )    
 
 /******************************************************************************/
 /*                     General Function Definitions                           */
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct
index 24f887bcd9..d81707aa5f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -1,6 +1,6 @@
 ;* MPS2 CMSIS Library
 ;*
-;* Copyright (c) 2006-2015 ARM Limited
+;* Copyright (c) 2006-2016 ARM Limited
 ;* All rights reserved.
 ;* 
 ;* Redistribution and use in source and binary forms, with or without 
@@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0)  {  ; RW data
+  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s
index 2714b21b71..d1192892d0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s
@@ -1,6 +1,6 @@
 ; MPS2 CMSIS Library
 ;
-; Copyright (c) 2006-2015 ARM Limited
+; Copyright (c) 2006-2016 ARM Limited
 ; All rights reserved.
 ; 
 ; Redistribution and use in source and binary forms, with or without 
@@ -32,10 +32,7 @@
 ; @file     startup_CMSDK_CM7.s
 ; @brief    CMSIS Core Device Startup File for
 ;           CMSDK_CM7 Device
-; @version  V1.00
-; @date     04. February 2015
 ;
-; @note
 ;******************************************************************************
 ;
 ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@@ -110,22 +107,22 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     ETHERNET_Handler          ; Ethernet Overflow Handler
                 DCD     I2S_Handler               ; I2S Handler
                 DCD     TSC_Handler               ; Touch Screen handler
-                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler
-                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler
-                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler
-                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler
-                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler
-                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler
-                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler
-                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler
-                DCD     PORT0_8_Handler           ; GPIO Port 0 pin 8 Handler
-                DCD     PORT0_9_Handler           ; GPIO Port 0 pin 9 Handler
-                DCD     PORT0_10_Handler          ; GPIO Port 0 pin 10 Handler
-                DCD     PORT0_11_Handler          ; GPIO Port 0 pin 11 Handler
-                DCD     PORT0_12_Handler          ; GPIO Port 0 pin 12 Handler
-                DCD     PORT0_13_Handler          ; GPIO Port 0 pin 13 Handler
-                DCD     PORT0_14_Handler          ; GPIO Port 0 pin 14 Handler
-                DCD     PORT0_15_Handler          ; GPIO Port 0 pin 15 Handler
+                DCD     PORT2_COMB_Handler        ; GPIO Port 2 Combined Handler
+                DCD     PORT3_COMB_Handler        ; GPIO Port 3 Combined Handler
+                DCD     UARTRX3_Handler           ; UART 3 RX Handler
+                DCD     UARTTX3_Handler           ; UART 3 TX Handler
+                DCD     UARTRX4_Handler           ; UART 4 RX Handler
+                DCD     UARTTX4_Handler           ; UART 4 TX Handler
+                DCD     ADCSPI_Handler            ; SHIELD ADC SPI exceptions Handler
+                DCD     SHIELDSPI_Handler         ; SHIELD SPI exceptions Handler
+                DCD     PORT0_0_Handler           ; GPIO Port 0 pin 0 Handler                                     
+                DCD     PORT0_1_Handler           ; GPIO Port 0 pin 1 Handler                                     
+                DCD     PORT0_2_Handler           ; GPIO Port 0 pin 2 Handler                                     
+                DCD     PORT0_3_Handler           ; GPIO Port 0 pin 3 Handler                                     
+                DCD     PORT0_4_Handler           ; GPIO Port 0 pin 4 Handler                                     
+                DCD     PORT0_5_Handler           ; GPIO Port 0 pin 5 Handler                                     
+                DCD     PORT0_6_Handler           ; GPIO Port 0 pin 6 Handler                                     
+                DCD     PORT0_7_Handler           ; GPIO Port 0 pin 7 Handler                                     
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -207,6 +204,14 @@ Default_Handler PROC
                 EXPORT ETHERNET_Handler           [WEAK]
                 EXPORT I2S_Handler                [WEAK]
                 EXPORT TSC_Handler                [WEAK]
+                EXPORT PORT2_COMB_Handler         [WEAK]
+                EXPORT PORT3_COMB_Handler         [WEAK]
+                EXPORT UARTRX3_Handler            [WEAK]
+                EXPORT UARTTX3_Handler            [WEAK]
+                EXPORT UARTRX4_Handler            [WEAK]
+                EXPORT UARTTX4_Handler            [WEAK]
+                EXPORT ADCSPI_Handler             [WEAK]
+                EXPORT SHIELDSPI_Handler          [WEAK]
                 EXPORT PORT0_0_Handler            [WEAK]
                 EXPORT PORT0_1_Handler            [WEAK]
                 EXPORT PORT0_2_Handler            [WEAK]
@@ -215,14 +220,6 @@ Default_Handler PROC
                 EXPORT PORT0_5_Handler            [WEAK]
                 EXPORT PORT0_6_Handler            [WEAK]
                 EXPORT PORT0_7_Handler            [WEAK]
-                EXPORT PORT0_8_Handler            [WEAK]
-                EXPORT PORT0_9_Handler            [WEAK]
-                EXPORT PORT0_10_Handler           [WEAK]
-                EXPORT PORT0_11_Handler           [WEAK]
-                EXPORT PORT0_12_Handler           [WEAK]
-                EXPORT PORT0_13_Handler           [WEAK]
-                EXPORT PORT0_14_Handler           [WEAK]
-                EXPORT PORT0_15_Handler           [WEAK]
 
 UARTRX0_Handler
 UARTTX0_Handler
@@ -240,22 +237,22 @@ UARTOVF_Handler
 ETHERNET_Handler
 I2S_Handler
 TSC_Handler
-PORT0_0_Handler
-PORT0_1_Handler
-PORT0_2_Handler
-PORT0_3_Handler
-PORT0_4_Handler
-PORT0_5_Handler
-PORT0_6_Handler
-PORT0_7_Handler
-PORT0_8_Handler
-PORT0_9_Handler
-PORT0_10_Handler
-PORT0_11_Handler
-PORT0_12_Handler
-PORT0_13_Handler
-PORT0_14_Handler
-PORT0_15_Handler
+PORT2_COMB_Handler        
+PORT3_COMB_Handler        
+UARTRX3_Handler           
+UARTTX3_Handler           
+UARTRX4_Handler           
+UARTTX4_Handler           
+ADCSPI_Handler            
+SHIELDSPI_Handler         
+PORT0_0_Handler                                    
+PORT0_1_Handler                                    
+PORT0_2_Handler                                    
+PORT0_3_Handler                                    
+PORT0_4_Handler                                    
+PORT0_5_Handler                                    
+PORT0_6_Handler                                    
+PORT0_7_Handler                                    
                 B       .
 
                 ENDP
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld
deleted file mode 100644
index cf28eac6bc..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000   /* 256k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x08000   /*  32k */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s
deleted file mode 100644
index 0d49a64b35..0000000000
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s
+++ /dev/null
@@ -1,314 +0,0 @@
-/* File: startup_ARMCM7.S
- * Purpose: startup file for Cortex-M7 devices. Should use with
- *   GCC for ARM Embedded Processors
- * Version: V1.00
- * Date: 22 August 2014
- *
- */
-/* Copyright (c) 2011 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-	.syntax	unified
-	.arch	armv7-m
-
-	.section .stack
-	.align	3
-#ifdef __STACK_SIZE
-	.equ	Stack_Size, __STACK_SIZE
-#else
-	.equ	Stack_Size, 0x00000400
-#endif
-	.globl	__StackTop
-	.globl	__StackLimit
-__StackLimit:
-	.space	Stack_Size
-	.size	__StackLimit, . - __StackLimit
-__StackTop:
-	.size	__StackTop, . - __StackTop
-
-	.section .heap
-	.align	3
-#ifdef __HEAP_SIZE
-	.equ	Heap_Size, __HEAP_SIZE
-#else
-	.equ	Heap_Size, 0x00000C00
-#endif
-	.globl	__HeapBase
-	.globl	__HeapLimit
-__HeapBase:
-	.if	Heap_Size
-	.space	Heap_Size
-	.endif
-	.size	__HeapBase, . - __HeapBase
-__HeapLimit:
-	.size	__HeapLimit, . - __HeapLimit
-
-	.section .vectors
-	.align	2
-	.globl	__Vectors
-__Vectors:
-	.long	__StackTop            /* Top of Stack */
-	.long	Reset_Handler         /* Reset Handler */
-	.long	NMI_Handler           /* NMI Handler */
-	.long	HardFault_Handler     /* Hard Fault Handler */
-	.long	MemManage_Handler     /* MPU Fault Handler */
-	.long	BusFault_Handler      /* Bus Fault Handler */
-	.long	UsageFault_Handler    /* Usage Fault Handler */
-	.long	0                     /* Reserved */
-	.long	0                     /* Reserved */
-	.long	0                     /* Reserved */
-	.long	0                     /* Reserved */
-	.long	SVC_Handler           /* SVCall Handler */
-	.long	DebugMon_Handler      /* Debug Monitor Handler */
-	.long	0                     /* Reserved */
-	.long	PendSV_Handler        /* PendSV Handler */
-	.long	SysTick_Handler       /* SysTick Handler */
-
-	/* External interrupts */
-	.long	WDT_IRQHandler        /*  0:  Watchdog Timer            */
-	.long	RTC_IRQHandler        /*  1:  Real Time Clock           */
-	.long	TIM0_IRQHandler       /*  2:  Timer0 / Timer1           */
-	.long	TIM2_IRQHandler       /*  3:  Timer2 / Timer3           */
-	.long	MCIA_IRQHandler       /*  4:  MCIa                      */
-	.long	MCIB_IRQHandler       /*  5:  MCIb                      */
-	.long	UART0_IRQHandler      /*  6:  UART0 - DUT FPGA          */
-	.long	UART1_IRQHandler      /*  7:  UART1 - DUT FPGA          */
-	.long	UART2_IRQHandler      /*  8:  UART2 - DUT FPGA          */
-	.long	UART4_IRQHandler      /*  9:  UART4 - not connected     */
-	.long	AACI_IRQHandler       /* 10: AACI / AC97                */
-	.long	CLCD_IRQHandler       /* 11: CLCD Combined Interrupt    */
-	.long	ENET_IRQHandler       /* 12: Ethernet                   */
-	.long	USBDC_IRQHandler      /* 13: USB Device                 */
-	.long	USBHC_IRQHandler      /* 14: USB Host Controller        */
-	.long	CHLCD_IRQHandler      /* 15: Character LCD              */
-	.long	FLEXRAY_IRQHandler    /* 16: Flexray                    */
-	.long	CAN_IRQHandler        /* 17: CAN                        */
-	.long	LIN_IRQHandler        /* 18: LIN                        */
-	.long	I2C_IRQHandler        /* 19: I2C ADC/DAC                */
-	.long	0                     /* 20: Reserved                   */
-	.long	0                     /* 21: Reserved                   */
-	.long	0                     /* 22: Reserved                   */
-	.long	0                     /* 23: Reserved                   */
-	.long	0                     /* 24: Reserved                   */
-	.long	0                     /* 25: Reserved                   */
-	.long	0                     /* 26: Reserved                   */
-	.long	0                     /* 27: Reserved                   */
-	.long	CPU_CLCD_IRQHandler   /* 28: Reserved - CPU FPGA CLCD   */
-	.long	0                     /* 29: Reserved - CPU FPGA        */
-	.long	UART3_IRQHandler      /* 30: UART3    - CPU FPGA        */
-	.long	SPI_IRQHandler        /* 31: SPI Touchscreen - CPU FPGA */
-
-	.size	__Vectors, . - __Vectors
-
-	.text
-	.thumb
-	.thumb_func
-	.align	2
-	.globl	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-	ldr	r4, =__copy_table_start__
-	ldr	r5, =__copy_table_end__
-
-.L_loop0:
-	cmp	r4, r5
-	bge	.L_loop0_done
-	ldr	r1, [r4]
-	ldr	r2, [r4, #4]
-	ldr	r3, [r4, #8]
-
-.L_loop0_0:
-	subs	r3, #4
-	ittt	ge
-	ldrge	r0, [r1, r3]
-	strge	r0, [r2, r3]
-	bge	.L_loop0_0
-
-	adds	r4, #12
-	b	.L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-	ldr	r1, =__etext
-	ldr	r2, =__data_start__
-	ldr	r3, =__data_end__
-
-.L_loop1:
-	cmp	r2, r3
-	ittt	lt
-	ldrlt	r0, [r1], #4
-	strlt	r0, [r2], #4
-	blt	.L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-	ldr	r3, =__zero_table_start__
-	ldr	r4, =__zero_table_end__
-
-.L_loop2:
-	cmp	r3, r4
-	bge	.L_loop2_done
-	ldr	r1, [r3]
-	ldr	r2, [r3, #4]
-	movs	r0, 0
-
-.L_loop2_0:
-	subs	r2, #4
-	itt	ge
-	strge	r0, [r1, r2]
-	bge	.L_loop2_0
-
-	adds	r3, #8
-	b	.L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-	ldr	r1, =__bss_start__
-	ldr	r2, =__bss_end__
-
-	movs	r0, 0
-.L_loop3:
-	cmp	r1, r2
-	itt	lt
-	strlt	r0, [r1], #4
-	blt	.L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-#ifndef __NO_SYSTEM_INIT
-	bl	SystemInit
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	bl	__START
-
-	.pool
-	.size	Reset_Handler, . - Reset_Handler
-
-	.align	1
-	.thumb_func
-	.weak	Default_Handler
-	.type	Default_Handler, %function
-Default_Handler:
-	b	.
-	.size	Default_Handler, . - Default_Handler
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-	.macro	def_irq_handler	handler_name
-	.weak	\handler_name
-	.set	\handler_name, Default_Handler
-	.endm
-
-	def_irq_handler	NMI_Handler
-	def_irq_handler	HardFault_Handler
-	def_irq_handler	MemManage_Handler
-	def_irq_handler	BusFault_Handler
-	def_irq_handler	UsageFault_Handler
-	def_irq_handler	SVC_Handler
-	def_irq_handler	DebugMon_Handler
-	def_irq_handler	PendSV_Handler
-	def_irq_handler	SysTick_Handler
-
-	def_irq_handler	WDT_IRQHandler
-	def_irq_handler	RTC_IRQHandler
-	def_irq_handler	TIM0_IRQHandler
-	def_irq_handler	TIM2_IRQHandler
-	def_irq_handler	MCIA_IRQHandler
-	def_irq_handler	MCIB_IRQHandler
-	def_irq_handler	UART0_IRQHandler
-	def_irq_handler	UART1_IRQHandler
-	def_irq_handler	UART2_IRQHandler
-	def_irq_handler	UART3_IRQHandler
-	def_irq_handler	UART4_IRQHandler
-	def_irq_handler	AACI_IRQHandler
-	def_irq_handler	CLCD_IRQHandler
-	def_irq_handler	ENET_IRQHandler
-	def_irq_handler	USBDC_IRQHandler
-	def_irq_handler	USBHC_IRQHandler
-	def_irq_handler	CHLCD_IRQHandler
-	def_irq_handler	FLEXRAY_IRQHandler
-	def_irq_handler	CAN_IRQHandler
-	def_irq_handler	LIN_IRQHandler
-	def_irq_handler	I2C_IRQHandler
-	def_irq_handler	CPU_CLCD_IRQHandler
-	def_irq_handler	SPI_IRQHandler
-
-	.end
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h
index 3d3a3e2fd9..04f376f4e4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h
@@ -37,7 +37,7 @@
 
 #include "cmsis.h"
 
-#define NVIC_NUM_VECTORS      (16 + 32)
+#define NVIC_NUM_VECTORS      (16 + 48)
 #define NVIC_USER_IRQ_OFFSET  16
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c
index 975e536c56..0424906a53 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c
@@ -1,6 +1,6 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
@@ -32,10 +32,6 @@
 * @file     system_CMSDK_CM7.c
 * @brief    CMSIS Device System Source File for
 *           CMSDK_CM7 Device
-* @version  V1.00
-* @date     27. August 2014
-*
-* @note
 *
 *******************************************************************************/
 
@@ -64,6 +60,9 @@
 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency      */
 
 
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
 /**
  * Update SystemCoreClock variable
  *
diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h
index 6992de1ddf..09301b37ed 100644
--- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h
+++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h
@@ -1,6 +1,6 @@
 /* MPS2 CMSIS Library
 *
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
@@ -33,10 +33,6 @@
 * @file     system_CMSDK_CM7.h
 * @brief    CMSIS Device Peripheral Access Layer Header File for
 *           CMSDK_CM7 Device
-* @version  V1.00
-* @date     27. August 2014
-*
-* @note
 *
 ******************************************************************************/
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h
new file mode 100644
index 0000000000..86bba4b274
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)CMSDK_UART1_BASE,
+    UART_1 = (int)CMSDK_UART3_BASE,
+    UART_2 = (int)CMSDK_UART0_BASE,
+    UART_3 = (int)CMSDK_UART2_BASE
+} UARTName;
+
+typedef enum {
+    I2C_0 = (int)MPS2_TSC_I2C_BASE,
+    I2C_1 = (int)MPS2_AAIC_I2C_BASE,
+    I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, 
+    I2C_3 = (int)MPS2_SHIELD1_I2C_BASE 
+        
+} I2CName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7,
+    ADC0_8,
+    ADC0_9,
+    ADC0_10,
+    ADC0_11
+} ADCName;
+
+typedef enum {
+    SPI_0 = (int)MPS2_SSP0_BASE,
+    SPI_1 = (int)MPS2_SSP1_BASE,
+      SPI_2 = (int)MPS2_SSP2_BASE,
+    SPI_3 = (int)MPS2_SSP3_BASE,
+    SPI_4 = (int)MPS2_SSP4_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    PWM_7,
+    PWM_8,
+    PWM_9,
+    PWM_10,
+    PWM_11
+} PWMName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+#define MBED_UART0        USBTX, USBRX
+#define MBED_UART1        XB_TX, XB_RX
+#define MBED_UART2        SH0_TX, SH0_RX
+#define MBED_UART3        SH1_TX, SH1_RX
+#define MBED_UARTUSB      USBTX, USBRX
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h
new file mode 100644
index 0000000000..53f7769428
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h
@@ -0,0 +1,241 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+        PIN_INPUT,
+        PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // MPS2 EXP Pin Names
+        EXP0 = 0 ,
+        EXP1 = 4 ,
+        EXP2 = 2 ,
+        EXP3 = 3 ,
+        EXP4 = 1 ,
+        EXP5 = 15,
+        EXP6 = 5 ,
+        EXP7 = 6 ,
+        EXP8 = 7 ,
+        EXP9 = 8 ,
+        EXP10 =9 ,
+        EXP11 =13,
+        EXP12 =10,
+        EXP13 =11,
+        EXP14 =12,
+        EXP15 =14,
+        EXP16 =18,
+        EXP17 =19,
+        EXP18 =20,
+        EXP19 =21,
+        EXP20 =52,
+        EXP21 =53,
+        EXP22 =54,
+        EXP23 =55,
+        EXP24 =56,
+        EXP25 =57,
+        
+        EXP26 =16,
+        EXP27 =25,
+        EXP28 =24,
+        EXP29 =31,
+        EXP30 =17,
+        EXP31 =23,
+        EXP32 =27,
+        EXP33 =30,
+        EXP34 =26,
+        EXP35 =28,
+        EXP36 =29,
+        EXP37 =58,
+        EXP38 =48,
+        EXP39 =49,
+        EXP40 =50,
+        EXP41 =22,
+        EXP42 =59,
+        EXP43 =60,
+        EXP44 =51,
+        EXP45 =61,
+        EXP46 =62,
+        EXP47 =63,
+        EXP48 =64,
+        EXP49 =65,
+        EXP50 =66,
+        EXP51 =67,
+        
+// Other mbed Pin Names
+
+        //LEDs on mps2
+        //user leds
+        USERLED1 = 100,
+        USERLED2 = 101,
+        //user switches
+        USERSW1  = 110,
+        USERSW2  = 111,
+        
+        //mcc leds
+        LED1 = 200,
+        LED2 = 201,
+        LED3 = 202,
+        LED4 = 203,
+        LED5 = 204,
+        LED6 = 205,
+        LED7 = 206,
+        LED8 = 207,
+        
+        //MCC Switches
+        SW1 = 210,
+        SW2 = 211,
+        SW3 = 212,
+        SW4 = 213,
+        SW5 = 214,
+        SW6 = 215,
+        SW7 = 216,
+        SW8 = 217,
+        
+        //MPS2 SPI header pins j21
+        MOSI_SPI = 300,
+        MISO_SPI = 301,
+        SCLK_SPI = 302,
+        SSEL_SPI = 303,
+        
+        //MPS2 CLCD SPI
+        CLCD_MOSI = 304,
+        CLCD_MISO = 305,
+        CLCD_SCLK = 306,
+        CLCD_SSEL = 307,
+        CLCD_RESET = 308,
+        CLCD_RS = 309,
+        CLCD_RD = 310,
+        CLCD_BL_CTRL = 311,
+        
+        //MPS2 shield 0 SPI
+        SHIELD_0_SPI_SCK = 320, 
+        SHIELD_0_SPI_MOSI = 321,
+        SHIELD_0_SPI_MISO = 322,
+        SHIELD_0_SPI_nCS = 323, 
+
+        //MPS2 shield 1 SPI
+        SHIELD_1_SPI_SCK = 331, 
+        SHIELD_1_SPI_MOSI = 332,
+        SHIELD_1_SPI_MISO = 333,
+        SHIELD_1_SPI_nCS = 334, 
+        
+        //MPS2 shield ADC SPI
+        ADC_MOSI = 650,
+        ADC_MISO = 651,
+        ADC_SCLK = 652,
+        ADC_SSEL = 653,
+        
+        //MPS2 Uart
+        USBTX  = 400,
+        USBRX  = 401,
+        XB_TX = 402,
+        XB_RX = 403,
+        SH0_TX = 404,
+        SH0_RX = 405,
+        SH1_TX = 406,
+        SH1_RX = 407,
+        
+        //MPS2 I2C touchscreen and audio
+        TSC_SDA = 500,
+        TSC_SCL = 501,
+        AUD_SDA = 502,
+        AUD_SCL = 503,
+    
+        //MPS2 I2C for shield
+        SHIELD_0_SDA = 504, 
+        SHIELD_0_SCL = 505, 
+        SHIELD_1_SDA = 506,
+        SHIELD_1_SCL = 507,
+        
+        //MPS2 shield Analog pins
+        A0_0 = 600,
+        A0_1 = 601,
+        A0_2 = 602,
+        A0_3 = 603,
+        A0_4 = 604,
+        A0_5 = 605,
+        A1_0 = 606,
+        A1_1 = 607,
+        A1_2 = 608,
+        A1_3 = 609,
+        A1_4 = 610,
+        A1_5 = 611,
+        //MPS2 Shield Digital pins
+        D0_0  = EXP0,
+        D0_1  = EXP4,
+        D0_2  = EXP2,
+        D0_3  = EXP3,
+        D0_4  = EXP1,
+        D0_5  = EXP6,
+        D0_6  = EXP7,
+        D0_7  = EXP8,
+        D0_8  = EXP9,
+        D0_9  = EXP10,
+        D0_10 = EXP12,
+        D0_11 = EXP13,
+        D0_12 = EXP14,
+        D0_13 = EXP11,
+        D0_14 = EXP15,
+        D0_15 = EXP5,
+    
+        D1_0  = EXP26,
+        D1_1  = EXP30,
+        D1_2  = EXP28,
+        D1_3  = EXP29,
+        D1_4  = EXP27,
+        D1_5  = EXP32,
+        D1_6  = EXP33,
+        D1_7  = EXP34,
+        D1_8  = EXP35,
+        D1_9  = EXP36,
+        D1_10 = EXP38,
+        D1_11 = EXP39,
+        D1_12 = EXP40,
+        D1_13 = EXP44,
+        D1_14 = EXP41,
+        D1_15 = EXP31,
+        
+        // Not connected
+        NC = (int)0xFFFFFFFF,
+} PinName;
+
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h
new file mode 100644
index 0000000000..b8a39a0143
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c
new file mode 100644
index 0000000000..68337ffac5
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c
@@ -0,0 +1,450 @@
+/* MPS2 Peripheral Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice, 
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice, 
+* this list of conditions and the following disclaimer in the documentation 
+* and/or other materials provided with the distribution.
+* 
+* 3. Neither the name of the copyright holder nor the names of its contributors 
+* may be used to endorse or promote products derived from this software without 
+* specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+* POSSIBILITY OF SUCH DAMAGE. 
+*/
+
+/*
+ * Code implementation file for the LAN Ethernet interface.
+ */
+
+#include <stdio.h>
+#include "wait_api.h"
+#include "ETH_MPS2.h"
+
+// SMSC9220 low-level operations
+unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
+{
+    unsigned int val, maccmd;
+    int timedout;
+    int error;
+
+    error = 0;
+    val = SMSC9220->MAC_CSR_CMD;
+    if(!(val & ((unsigned int)1 << 31))) {    // Make sure there's no pending operation
+        maccmd = 0;
+        maccmd |= regoffset;
+        maccmd |= ((unsigned int)1 << 30);     // Indicates read
+        maccmd |= ((unsigned int)1 << 31);     // Start bit
+        SMSC9220->MAC_CSR_CMD = maccmd;        // Start operation
+
+        timedout = 50;
+        do {
+            val = SMSC9220->BYTE_TEST;  // A no-op read.
+            wait_ms(1); //Sleepms(1);
+            timedout--;
+        } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
+
+        if(!timedout) {
+            error = 1;
+        }
+        else
+            *data = SMSC9220->MAC_CSR_DATA;
+    } else {
+        *data = 0;
+    }
+    return error;
+}
+
+unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
+{
+    unsigned int read, maccmd;
+    int timedout;
+    int error;
+
+    error = 0;
+    read = SMSC9220->MAC_CSR_CMD;
+    if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
+        SMSC9220->MAC_CSR_DATA = data;      // Store data.
+        maccmd = 0;
+        maccmd |= regoffset;
+        maccmd &= ~((unsigned int)1 << 30); // Clear indicates write
+        maccmd |= ((unsigned int)1 << 31);  // Indicate start of operation
+        SMSC9220->MAC_CSR_CMD = maccmd;
+
+        timedout = 50;
+        do {
+            read = SMSC9220->BYTE_TEST;     // A no-op read.
+            wait_ms(1); //Sleepms(1);
+            timedout--;
+        } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
+
+        if(!timedout) {
+            error = 1;
+        }
+    } else {
+       printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
+    }
+    return error;
+}
+
+unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
+{
+    unsigned int val, phycmd; int error;
+    int timedout;
+
+    error = 0;
+
+    smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
+
+    if(!(val & 1)) {    // Not busy
+        phycmd = 0;
+        phycmd |= (1 << 11);                 // 1 to [15:11]
+        phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
+        phycmd &= ~(1 << 1);                 // Clear [1] indicates read.
+        phycmd |= (1 << 0);                  // Set [0] indicates operation start
+
+        smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);
+
+        val = 0;
+        timedout = 50;
+        do {
+            wait_ms(1); //Sleepms(1);
+            timedout--;
+            smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
+        } while(timedout && (val & ((unsigned int)1 << 0)));
+
+        if(!timedout) {
+            error = 1;
+        }
+        else
+            smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
+
+    } else {
+        *data = 0;
+    }
+    return error;
+}
+
+unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
+{
+    unsigned int val, phycmd; int error;
+    int timedout;
+
+    error = 0;
+
+    smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
+
+    if(!(val & 1)) {    // Not busy
+        smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
+        phycmd = 0;
+        phycmd |= (1 << 11);                    // 1 to [15:11]
+        phycmd |= ((regoffset & 0x1F) << 6);     // Put regoffset to [10:6]
+        phycmd |= (1 << 1);                     // Set [1] indicates write.
+        phycmd |= (1 << 0);                     // Set [0] indicates operation start
+        smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);   // Start operation
+
+        phycmd = 0;
+        timedout = 50;
+
+        do {
+
+            wait_ms(1); //Sleepms(1);
+            timedout--;
+            smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
+        } while(timedout && (phycmd & (1 << 0)));
+
+        if(!timedout) {
+            error = 1;
+        }
+
+    } else {
+        printf("Warning: SMSC9220 MAC MII is busy. No data written.\n");
+    }
+    return error;
+}
+
+// Returns smsc9220 id.
+unsigned int smsc9220_read_id(void)
+{
+    return SMSC9220->ID_REV;
+}
+
+// Initiates a soft reset, returns failure or success.
+unsigned int smsc9220_soft_reset(void)
+{
+    int timedout;
+
+    timedout = 10;
+    // Soft reset
+    SMSC9220->HW_CFG |= 1;
+
+    do {
+        wait_ms(1); //Sleepms(1);
+        timedout--;
+    } while(timedout && (SMSC9220->HW_CFG & 1));
+
+    if(!timedout)
+        return 1;
+
+    return 0;
+}
+
+void smsc9220_set_txfifo(unsigned int val)
+{
+    // 2kb minimum, 14kb maximum
+    if(val < 2 || val > 14)
+        return;
+
+    SMSC9220->HW_CFG = val << 16;
+}
+
+
+unsigned int smsc9220_wait_eeprom(void)
+{
+    int timedout;
+
+    timedout = 50;
+
+    do {
+        wait_ms(1); //Sleepms(1);
+        timedout--;
+
+    } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
+
+    if(!timedout)
+        return 1;
+
+    return 0;
+}
+
+/* initialise irqs */
+void smsc9220_init_irqs(void)
+{
+    SMSC9220->INT_EN    = 0x0;
+    SMSC9220->INT_STS   = 0xFFFFFFFF;   // clear all interrupts
+    SMSC9220->IRQ_CFG   = 0x22000100;   // irq deassertion at 220 usecs and master IRQ enable.
+}
+
+unsigned int smsc9220_check_phy(void)
+{
+    unsigned short phyid1, phyid2;
+
+    smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1);
+    smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2);
+    return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
+            (phyid1 == 0x0 && phyid2 == 0x0));
+}
+
+unsigned int smsc9220_reset_phy(void)
+{
+    unsigned short read;
+    int error;
+
+    error = 0;
+    if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
+        error = 1;
+        return error;
+    }
+
+    read |= (1 << 15);
+    if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
+        error = 1;
+        return error;
+    }
+    return 0;
+}
+
+/* Advertise all speeds and pause capabilities */
+void smsc9220_advertise_cap(void)
+{
+    unsigned short aneg_adv;
+    aneg_adv = 0;
+
+
+    smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
+    aneg_adv |= 0xDE0;
+
+    smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
+    smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
+    return;
+}
+
+void smsc9220_establish_link(void)
+{
+    unsigned short bcr;
+
+    smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
+    bcr |= (1 << 12) | (1 << 9);
+    smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
+    smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
+
+    {
+        unsigned int hw_cfg;
+
+        hw_cfg = 0;
+        hw_cfg = SMSC9220->HW_CFG;
+
+        hw_cfg &= 0xF0000;
+        hw_cfg |= (1 << 20);
+        SMSC9220->HW_CFG = hw_cfg;
+    }
+
+    return;
+}
+
+void smsc9220_enable_xmit(void)
+{
+    SMSC9220->TX_CFG = 0x2; // Enable trasmission
+    return;
+}
+
+void smsc9220_enable_mac_xmit(void)
+{
+    unsigned int mac_cr;
+
+    mac_cr = 0;
+    smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
+
+    mac_cr |= (1 << 3);     // xmit enable
+    mac_cr |= (1 << 28);    // Heartbeat disable
+
+    smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
+    return;
+}
+
+void smsc9220_enable_mac_recv(void)
+{
+    unsigned int mac_cr;
+
+    mac_cr = 0;
+    smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
+    mac_cr |= (1 << 2);     // Recv enable
+    smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
+
+    return;
+}
+
+
+unsigned int smsc9220_check_ready(void)
+{
+    return !(SMSC9220->PMT_CTRL & 1);
+}
+
+/* Generate a soft irq */
+void smsc9220_set_soft_int(void)
+{
+    SMSC9220->INT_EN |= 0x80000000;
+}
+
+/* clear soft irq */
+void smsc9220_clear_soft_int(void)
+{
+    SMSC9220->INT_STS |= 0x80000000;
+}
+
+
+unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
+{
+    unsigned int rxfifo_inf;    // Tells us the status of rx payload and status fifos.
+    unsigned int rxfifo_stat;
+
+    unsigned int pktsize;
+    unsigned int dwords_to_read;
+
+    rxfifo_inf = SMSC9220->RX_FIFO_INF;
+
+    if(rxfifo_inf & 0xFFFF) { // If there's data
+        rxfifo_stat = SMSC9220->RX_STAT_PORT;
+        if(rxfifo_stat != 0) {   // Fetch status of this packet
+            pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
+            if(rxfifo_stat & (1 << 15)) {
+                printf("Error occured during receiving of packets on the bus.\n");
+                return 1;
+            } else {
+                /* Below formula (recommended by SMSC9220 code)
+                 * gives 1 more than required. This is perhaps because
+                 * a last word is needed for not word aligned packets.
+                 */
+                dwords_to_read = (pktsize + 3) >> 2;
+                // PIO copy of data received:
+                while(dwords_to_read > 0) {
+                    recvbuf[*index] = SMSC9220->RX_DATA_PORT;
+                    (*index)++;
+                    dwords_to_read--;
+                }
+            }
+        } else {
+            return 1;
+        }
+    } else {
+        return 1;
+    }
+
+    rxfifo_stat = SMSC9220->RX_STAT_PORT;
+    rxfifo_inf = SMSC9220->RX_FIFO_INF;
+
+    return 0;
+}
+
+
+// Does the actual transfer of data to FIFO, note it does no
+// fifo availability checking. This should be done by caller.
+// Assumes the whole frame is transferred at once as a single segment
+void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
+{
+    unsigned int txcmd_a, txcmd_b;
+    unsigned int dwords_to_write;
+    volatile unsigned int dwritten;
+    unsigned int *pktptr;
+    volatile unsigned int xmit_stat, xmit_stat2, xmit_inf;
+    int i;
+
+    pktptr = (unsigned int *) pkt;
+    txcmd_a = 0;
+    txcmd_b = 0;
+
+    txcmd_a |= (1 << 12) | (1 << 13);   // First and last segments
+    txcmd_a |= length & 0x7FF;          // [10:0] contains length
+
+    txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length
+    txcmd_b |= length & 0x7FF;          // [10:0] also contains length
+
+
+    SMSC9220->TX_DATA_PORT = txcmd_a;
+    SMSC9220->TX_DATA_PORT = txcmd_b;
+    dwritten = dwords_to_write = (length + 3) >> 2;
+
+    // PIO Copy to FIFO. Could replace this with DMA.
+    while(dwords_to_write > 0) {
+         SMSC9220->TX_DATA_PORT = *pktptr;
+         pktptr++;
+         dwords_to_write--;
+    }
+
+    xmit_stat = SMSC9220->TX_STAT_PORT;
+    xmit_stat2 = SMSC9220->TX_STAT_PORT;
+    xmit_inf = SMSC9220->TX_FIFO_INF;
+
+    if(xmit_stat2 != 0 ) {
+        for(i = 0; i < 6; i++) {
+            xmit_stat2 = SMSC9220->TX_STAT_PORT;
+        }
+    }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h
new file mode 100644
index 0000000000..10033b773f
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h
@@ -0,0 +1,65 @@
+/* MPS2 Peripheral Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice, 
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice, 
+* this list of conditions and the following disclaimer in the documentation 
+* and/or other materials provided with the distribution.
+* 
+* 3. Neither the name of the copyright holder nor the names of its contributors 
+* may be used to endorse or promote products derived from this software without 
+* specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+* POSSIBILITY OF SUCH DAMAGE. 
+*/
+
+#ifndef _ETH_MPS2_H_
+#define _ETH_MPS2_H_
+
+#include "SMM_MPS2.h"
+
+// Function declarations
+
+unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data);
+unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data);
+unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data);
+unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data);
+
+unsigned int smsc9220_read_id(void);
+unsigned int smsc9220_soft_reset(void);
+void smsc9220_set_txfifo(unsigned int val);
+unsigned int smsc9220_wait_eeprom(void);
+void smsc9220_init_irqs(void);
+unsigned int smsc9220_check_phy(void);
+unsigned int smsc9220_reset_phy(void);
+
+void smsc9220_advertise_cap(void);
+void smsc9220_establish_link(void);
+void smsc9220_enable_xmit(void);
+void smsc9220_enable_mac_xmit(void);
+void smsc9220_enable_mac_recv(void);
+unsigned int smsc9220_check_ready(void);
+void smsc9220_set_soft_int(void);
+void smsc9220_clear_soft_int(void);
+
+unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index);
+void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length);
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c
new file mode 100644
index 0000000000..a0111474c6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * ----------------------------------------------------------------
+ * File:     fpga.c
+ * Release:  Version 1.0
+ * ----------------------------------------------------------------
+ */
+
+/*
+ * Code implementation file for the fpga functions.
+ */
+
+#include "SMM_MPS2.h"                   // MPS2 common header
+
+// Function to delay n*ticks (25MHz = 40nS per tick)
+// Used for I2C drivers
+void i2c_delay(unsigned int tick)
+{
+    unsigned int end;
+    unsigned int start;
+
+    start = MPS2_FPGAIO->COUNTER;
+    end   = start + (tick);
+
+    if(end >= start)
+    {
+        while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+    }
+    else
+    {
+        while (MPS2_FPGAIO->COUNTER >= start);
+        while (MPS2_FPGAIO->COUNTER < end);
+    }
+}
+
+/* Sleep function to delay n*mS
+ * Uses FPGA counter.
+ */
+void Sleepms(unsigned int msec)
+{
+    unsigned int end;
+    unsigned int start;
+
+    start = MPS2_FPGAIO->COUNTER;
+    end   = start + (25 * msec * 1000);
+
+    if(end >= start)
+    {
+        while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+    }
+    else
+    {
+        while (MPS2_FPGAIO->COUNTER >= start);
+        while (MPS2_FPGAIO->COUNTER < end);
+    }
+}
+
+/* Sleep function to delay n*uS
+ */
+void Sleepus(unsigned int usec)
+{
+    unsigned int end;
+    unsigned int start;
+
+    start = MPS2_FPGAIO->COUNTER;
+    end   = start + (25 * usec);
+
+    if(end >= start)
+    {
+        while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+    }
+    else
+    {
+        while (MPS2_FPGAIO->COUNTER >= start);
+        while (MPS2_FPGAIO->COUNTER < end);
+    }
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h
new file mode 100644
index 0000000000..e4a055cfc0
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Code implementation file for the fpga functions.
+ */
+
+#include "SMM_MPS2.h"                   // MPS2 common header
+
+// Function to delay n*ticks (25MHz = 40nS per tick)
+// Used for I2C drivers
+void i2c_delay(unsigned int tick);
+
+/* Sleep function to delay n*mS
+ * Uses FPGA counter.
+ */
+void Sleepms(unsigned int msec);
+
+/* Sleep function to delay n*uS
+ */
+void Sleepus(unsigned int usec);
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c
new file mode 100644
index 0000000000..1461ff5995
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c
@@ -0,0 +1,166 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "mps2_ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "ETH_MPS2.h"
+#include "wait_api.h"
+
+#define TX_PKT_SIZE 256
+#define RX_PKT_SIZE 300
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE   0
+#define TRUE    1
+
+
+int smsc9220_check_id(void)
+{
+    int error;
+    unsigned int id;
+    error = 0;
+
+    id = smsc9220_read_id();
+
+    // If bottom and top halves of the word are the same
+    if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
+        error = 1;
+        return error;
+    }
+    switch(((id >> 16) & 0xFFFF)) {
+        case 0x9220:
+            break;
+
+        default:
+            error = 1;
+            break;
+    }
+
+    return error;
+}
+
+int smsc9220_check_macaddress(void)
+{
+    int error;
+    const unsigned int mac_valid_high = 0xC00A;
+    const unsigned int mac_valid_low = 0x00F70200;
+    unsigned int mac_low;
+    unsigned int mac_high;
+
+    error = 0;
+
+    // Read current mac address.
+    smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
+    smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
+
+    // Writing temporary address:
+    smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high);
+    smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low);
+
+    // Verify write was correct:
+    smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
+    smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
+
+
+    if(mac_high != mac_valid_high || mac_low != mac_valid_low) {
+        error = TRUE;
+        return error;
+    }
+
+    return error;
+}
+
+void smsc9220_print_mac_registers()
+{
+    unsigned int read;
+    int i;
+
+    i = 0;
+    read = 0;
+
+    for(i = 1; i <= 0xC; i++) {
+        smsc9220_mac_regread(i, &read);
+    }
+    return;
+}
+
+
+void smsc9220_print_phy_registers()
+{
+    unsigned short read;
+    unsigned int i;
+
+    i = 0;
+    read = 0;
+    for(i = 0; i <= 6; i++) {
+        smsc9220_phy_regread(i, &read);
+    }
+    smsc9220_phy_regread(i = 17, &read);
+
+    smsc9220_phy_regread(i = 18, &read);
+
+    smsc9220_phy_regread(i = 27, &read);
+
+    smsc9220_phy_regread(i = 29, &read);
+
+    smsc9220_phy_regread(i = 30, &read);
+
+    smsc9220_phy_regread(i = 31, &read);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------
+  Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+
+int ethernet_transmission(unsigned char * pkt, unsigned int length)
+{
+    smsc9220_xmit_packet(pkt, length);
+    return 0;
+}
+
+int ethernet_reception(unsigned int *recvbuf, unsigned int *index) 
+{
+    return smsc9220_recv_packet((unsigned int *)recvbuf, index);
+}
+
+int ethernet_mac_address(char *mac) 
+{
+    return smsc9220_check_macaddress();
+}
+
+unsigned int ethernet_check_ready(void)
+{
+    return smsc9220_check_ready();
+}
+
+unsigned int ethernet_intf()
+{
+  unsigned int txfifo_inf;
+ 
+    txfifo_inf = SMSC9220->TX_FIFO_INF;
+    
+    return txfifo_inf;
+
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h
new file mode 100644
index 0000000000..2a15b24a6c
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MPS2_ETHERNET_API_H
+#define MPS2_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_transmission(unsigned char * pkt, unsigned int length);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
+
+// get the ethernet address
+int ethernet_mac_address(char *mac);
+
+unsigned int ethernet_check_ready(void);
+
+unsigned int ethernet_intf(void);
+
+int smsc9220_check_id(void);
+
+int smsc9220_check_macaddress(void);
+
+void smsc9220_print_mac_registers(void);
+void smsc9220_print_phy_registers(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c
new file mode 100644
index 0000000000..bef3fb5f5f
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#define ADC_12BIT_RANGE             0xFFF
+
+static const PinMap PinMap_ADC[] = {
+    {A0_0, ADC0_0,  0},
+    {A0_1, ADC0_1,  0},
+    {A0_2, ADC0_2,  0},
+    {A0_3, ADC0_3,  0},
+    {A0_4, ADC0_4,  0},
+    {A0_5, ADC0_5,  0},
+    {A1_0, ADC0_6,  0},
+    {A1_1, ADC0_7,  0},
+    {A1_2, ADC0_8,  0},
+    {A1_3, ADC0_9,  0},
+    {A1_4, ADC0_10, 0},
+    {A1_5, ADC0_11, 0},
+    {NC,    NC,     0}
+};
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {ADC_SCLK , SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {ADC_MOSI, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {ADC_MISO, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {ADC_SSEL, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+#define ADC_RANGE    ADC_12BIT_RANGE
+int analog_spi_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+  MBED_ASSERT(obj->adc != (ADCName)NC);
+  obj->pin = pin;
+    obj->pin_number = pin-600;
+    obj->address = (0x0000 | (pin-600));
+    
+    SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
+  SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
+  SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
+  SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
+  SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
+  SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
+  obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl);
+  
+    if(analog_spi_inited == 0){
+    obj->adc_spi->CR1       = 0;
+    obj->adc_spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
+    obj->adc_spi->CPSR      = SSP_CPSR_DFLT; 
+    obj->adc_spi->IMSC      = 0x8; 
+    obj->adc_spi->DMACR     = 0;
+    obj->adc_spi->CR1       = SSP_CR1_SSE_Msk;
+    obj->adc_spi->ICR       = 0x3;  
+    analog_spi_inited = 1;
+    }
+    
+  pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
+  pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
+  pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
+  pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
+  pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    return 0;
+}
+
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read(obj);
+    return 0;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    return 0;
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
new file mode 100644
index 0000000000..52cebb2dd8
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+#define DEVICE_SERIAL_FC        1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CLCD             1
+
+#define DEVICE_TSC              1
+
+#define DEVICE_AACI             1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         1
+
+#define DEVICE_PWMOUT           0
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+
+#define DEVICE_SLEEP            0
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   0
+
+#define DEVICE_ERROR_RED        0
+
+#include "objects.h"
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c
new file mode 100644
index 0000000000..e59c210243
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "mps2_ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "ETH_MPS2.h"
+#include "wait_api.h"
+
+#define TX_PKT_SIZE 256
+#define RX_PKT_SIZE 300
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE   0
+#define TRUE    1
+
+/*----------------------------------------------------------------------------
+  Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init()
+{
+      int error;
+    error = 0;
+
+    if(smsc9220_check_id()) {
+        error = TRUE;
+    }
+
+    if(smsc9220_soft_reset()) {
+        error = TRUE;
+    }
+
+    smsc9220_set_txfifo(5);
+
+    // Sets automatic flow control thresholds, and backpressure
+    // threshold to defaults specified.
+    SMSC9220->AFC_CFG = 0x006E3740;
+
+    if(smsc9220_wait_eeprom()) {
+        error = TRUE;
+    }
+
+    // Configure GPIOs as LED outputs.
+    SMSC9220->GPIO_CFG = 0x70070000;
+
+    smsc9220_init_irqs();
+
+    /* Configure MAC addresses here if needed. */
+
+    if(smsc9220_check_phy()) {
+        error = TRUE;
+    }
+
+    if(smsc9220_reset_phy()) {
+        error = TRUE;
+        return error;
+    }
+
+    wait_ms(100);
+    // Checking whether phy reset completed successfully.
+    {
+        unsigned short phyreset;
+        phyreset = 0;
+        smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
+        if(phyreset & (1 << 15)) {
+            error = TRUE;
+            return error;
+        }
+    }
+
+    /* Advertise capabilities */
+    smsc9220_advertise_cap();
+
+
+    /* Begin to establish link */
+    smsc9220_establish_link();      // bit [12] of BCONTROL seems self-clearing.
+                                    // Although it's not so in the manual.
+
+    /* Interrupt threshold */
+    SMSC9220->FIFO_INT = 0xFF000000;
+
+    smsc9220_enable_mac_xmit();
+
+    smsc9220_enable_xmit();
+
+    SMSC9220->RX_CFG = 0;
+
+    smsc9220_enable_mac_recv();
+
+    // Rx status FIFO level irq threshold
+    SMSC9220->FIFO_INT &= ~(0xFF);  // Clear 2 bottom nibbles
+
+    // This sleep is compulsory otherwise txmit/receive will fail.
+    wait_ms(2000);
+    return error;
+
+}
+
+/*----------------------------------------------------------------------------
+  Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+}
+
+int ethernet_write(const char *data, int size)
+{
+        return 0;
+}
+
+int ethernet_send() 
+{
+ return 0;
+}
+
+int ethernet_receive() 
+{
+    return 0;
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) 
+{
+    return 0;
+}
+
+void ethernet_address(char *mac) {
+    mbed_mac_address(mac);
+}
+
+int ethernet_link(void) 
+{
+    return 0;
+}
+
+void ethernet_set_link(int speed, int duplex)
+{
+    smsc9220_establish_link();
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c
new file mode 100644
index 0000000000..b80fcbacd1
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c
@@ -0,0 +1,140 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+// function to enable the GPIO pin
+uint32_t gpio_set(PinName pin) {
+    return (1);
+}
+
+//function to initialise the gpio pin
+// this links the board control bits for each pin 
+// with the object created for the pin
+void gpio_init(gpio_t *obj, PinName pin) {
+        if(pin == NC){ return;}
+        else {
+        int pin_value = 0;
+        obj->pin = pin;
+        if(pin <=15){
+            pin_value = pin;
+        }else if (pin >= 16 && pin <= 31){
+            pin_value = pin-16;
+        }else if (pin >= 32 && pin <= 47){
+            pin_value = pin-32;
+        }else if (pin >= 48 && pin <= 51){
+            pin_value = pin-48;
+        }else if (pin == 100 || pin == 101){
+            pin_value = pin-100;
+        }else if (pin == 110 || pin == 111){
+            pin_value = pin-110;
+        }else if (pin >= 200 && pin <= 207){
+            pin_value = pin-200;
+        }else if (pin >= 210 && pin <= 217){
+            pin_value = pin-210;
+        }else if (pin == 303){
+            pin_value = pin-302;
+        }else if (pin == 307){
+            pin_value = pin-307;
+        }else if (pin == 308){
+            pin_value = pin-305;
+        }else if (pin == 309){
+            pin_value = pin-305;
+        }else if (pin == 310){
+            pin_value = pin-305;
+        }else if (pin == 311){
+            pin_value = pin-305;
+        }else if (pin == 323){
+            pin_value = pin-315;
+        }else if (pin == 334){
+            pin_value = pin-325;
+        }else if (pin == 653){
+            pin_value = pin-646;
+        }
+        
+        obj->mask = 0x1 << pin_value;
+        obj->pin_number = pin;
+        if(pin <=15) {
+            obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
+            obj->reg_in  =         &CMSDK_GPIO0->DATA ;
+            obj->reg_dir =         &CMSDK_GPIO0->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
+        } else if (pin >= 16 && pin <= 31){
+            obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
+            obj->reg_in  =         &CMSDK_GPIO1->DATA ;
+            obj->reg_dir =         &CMSDK_GPIO1->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
+        } else if (pin >= 32 && pin <= 47){
+            obj->reg_data = &CMSDK_GPIO2->DATAOUT;
+            obj->reg_in  =         &CMSDK_GPIO2->DATA;
+            obj->reg_dir =         &CMSDK_GPIO2->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
+        }    else if (pin >= 48 && pin <= 51){
+            obj->reg_data = &CMSDK_GPIO3->DATAOUT;
+            obj->reg_in  =         &CMSDK_GPIO3->DATA;
+            obj->reg_dir =         &CMSDK_GPIO3->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
+        } else if (pin == 100 || pin == 101){
+            obj->reg_data = &MPS2_FPGAIO->LED; //user leds
+            obj->reg_in  =  &MPS2_FPGAIO->LED;
+        } else if (pin == 110 || pin == 111){
+            obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
+            obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
+        }else if (pin >= 200 && pin <= 207){
+            obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
+            obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
+        }else if (pin >= 210 && pin <= 217){
+            obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
+        }else if (pin == 303 || pin == 307){
+            obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
+        }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
+            obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
+        }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
+            obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
+        }
+        
+        if (pin == 323){
+            CMSDK_GPIO0->ALTFUNCSET |= 0x0400;
+        }else if (pin == 334){
+            CMSDK_GPIO4->ALTFUNCSET |= 0x0001;
+        }else if (pin == 653){
+            CMSDK_GPIO1->ALTFUNCSET |= 0x0004;
+        }
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+        pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+        if(obj->pin >= 0 && obj->pin <= 51)
+            {        
+        switch (direction) {
+          case PIN_INPUT : *obj->reg_dirclr = obj->mask;  break;
+          case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+        }
+    } else {return;}
+}
+
+int gpio_is_connected(const gpio_t *obj){
+    if(obj->pin != (PinName)NC){
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c
new file mode 100644
index 0000000000..bedf723bfc
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c
@@ -0,0 +1,241 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+
+#define CHANNEL_NUM    32
+#define CMSDK_GPIO_0 CMSDK_GPIO0
+#define CMSDK_GPIO_1 CMSDK_GPIO1
+#define PININT_IRQ 0
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+        uint32_t ch_bit = (1 << channel);
+        // Return immediately if:
+        //   * The interrupt was already served
+        //   * There is no user handler
+        //   * It is a level interrupt, not an edge interrupt
+    if (ch_bit <16){
+        if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
+
+        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_RISE);
+                CMSDK_GPIO_0->INTPOLSET = ch_bit;
+        }
+        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_FALL);
+        }
+        CMSDK_GPIO_0->INTCLEAR = ch_bit;
+    }
+    
+    if (ch_bit>=16) {
+        if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
+
+        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_RISE);
+                CMSDK_GPIO_1->INTPOLSET = ch_bit;
+        }
+        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_FALL);
+        }
+        CMSDK_GPIO_1->INTCLEAR = ch_bit;
+    }
+}
+
+void gpio0_irq0(void)  {handle_interrupt_in(0);}
+void gpio0_irq1(void)  {handle_interrupt_in(1);}
+void gpio0_irq2(void)  {handle_interrupt_in(2);}
+void gpio0_irq3(void)  {handle_interrupt_in(3);}
+void gpio0_irq4(void)  {handle_interrupt_in(4);}
+void gpio0_irq5(void)  {handle_interrupt_in(5);}
+void gpio0_irq6(void)  {handle_interrupt_in(6);}
+void gpio0_irq7(void)  {handle_interrupt_in(7);}
+void gpio0_irq8(void)  {handle_interrupt_in(8);}
+void gpio0_irq9(void)  {handle_interrupt_in(9);}
+void gpio0_irq10(void) {handle_interrupt_in(10);}
+void gpio0_irq11(void) {handle_interrupt_in(11);}
+void gpio0_irq12(void) {handle_interrupt_in(12);}
+void gpio0_irq13(void) {handle_interrupt_in(13);}
+void gpio0_irq14(void) {handle_interrupt_in(14);}
+void gpio0_irq15(void) {handle_interrupt_in(15);}
+void gpio1_irq0(void)  {handle_interrupt_in(16);}
+void gpio1_irq1(void)  {handle_interrupt_in(17);}
+void gpio1_irq2(void)  {handle_interrupt_in(18);}
+void gpio1_irq3(void)  {handle_interrupt_in(19);}
+void gpio1_irq4(void)  {handle_interrupt_in(20);}
+void gpio1_irq5(void)  {handle_interrupt_in(21);}
+void gpio1_irq6(void)  {handle_interrupt_in(22);}
+void gpio1_irq7(void)  {handle_interrupt_in(23);}
+void gpio1_irq8(void)  {handle_interrupt_in(24);}
+void gpio1_irq9(void)  {handle_interrupt_in(25);}
+void gpio1_irq10(void) {handle_interrupt_in(26);}
+void gpio1_irq11(void) {handle_interrupt_in(27);}
+void gpio1_irq12(void) {handle_interrupt_in(28);}
+void gpio1_irq13(void) {handle_interrupt_in(29);}
+void gpio1_irq14(void) {handle_interrupt_in(30);}
+void gpio1_irq15(void) {handle_interrupt_in(31);}
+
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+        if (pin == NC) {return -1;}
+        else {
+        
+        irq_handler = handler;
+        
+        int found_free_channel = 0;
+        int i = 0;
+        for (i=0; i<CHANNEL_NUM; i++) {
+                if (channel_ids[i] == 0) {
+                        channel_ids[i] = id;
+                        obj->ch = i;
+                        found_free_channel = 1;
+                        break;
+                }
+        }
+        if (!found_free_channel) return -1;
+        
+        
+        /* To select a pin for any of the eight pin interrupts, write the pin number
+         * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
+         * @see: mbed_capi/PinNames.h
+         */
+        if (pin <16)
+        {
+        CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
+        }
+        
+        if (pin >= 16)
+        {
+        CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
+        }
+
+        void (*channels_irq)(void) = NULL;
+        switch (obj->ch) {
+                case 0: channels_irq = &gpio0_irq0; break;
+                case 1: channels_irq = &gpio0_irq1; break;
+                case 2: channels_irq = &gpio0_irq2; break;
+                case 3: channels_irq = &gpio0_irq3; break;
+                case 4: channels_irq = &gpio0_irq4; break;
+                case 5: channels_irq = &gpio0_irq5; break;
+                case 6: channels_irq = &gpio0_irq6; break;
+                case 7: channels_irq = &gpio0_irq7; break;
+                case 8: channels_irq = &gpio0_irq8; break;
+                case 9: channels_irq = &gpio0_irq9; break;
+                case 10: channels_irq = &gpio0_irq10; break;
+                case 11: channels_irq = &gpio0_irq11; break;
+                case 12: channels_irq = &gpio0_irq12; break;
+                case 13: channels_irq = &gpio0_irq13; break;
+                case 14: channels_irq = &gpio0_irq14; break;
+                case 15: channels_irq = &gpio0_irq15; break;
+                case 16: channels_irq = &gpio1_irq0; break;
+                case 17: channels_irq = &gpio1_irq1; break;
+                case 18: channels_irq = &gpio1_irq2; break;
+                case 19: channels_irq = &gpio1_irq3; break;
+                case 20: channels_irq = &gpio1_irq4; break;
+                case 21: channels_irq = &gpio1_irq5; break;
+                case 22: channels_irq = &gpio1_irq6; break;
+                case 23: channels_irq = &gpio1_irq7; break;
+                case 24: channels_irq = &gpio1_irq8; break;
+                case 25: channels_irq = &gpio1_irq9; break;
+                case 26: channels_irq = &gpio1_irq10; break;
+                case 27: channels_irq = &gpio1_irq11; break;
+                case 28: channels_irq = &gpio1_irq12; break;
+                case 29: channels_irq = &gpio1_irq13; break;
+                case 30: channels_irq = &gpio1_irq14; break;
+                case 31: channels_irq = &gpio1_irq15; break;
+            
+        }
+        NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+        NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    
+        return 0;
+    }
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+        unsigned int ch_bit = (1 << obj->ch);
+        
+        // Clear interrupt
+        if (obj->ch <16)
+        {
+                if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
+                {
+                    CMSDK_GPIO_0->INTCLEAR = ch_bit;
+                }
+        }
+        if (obj->ch >= 16)
+        {
+                if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
+                {
+                    CMSDK_GPIO_1->INTCLEAR = ch_bit;
+                }
+        }
+        
+        // Edge trigger
+        if (obj->ch <16)
+        {
+                CMSDK_GPIO_0->INTTYPESET &= ch_bit;
+                if (event == IRQ_RISE) {
+                        CMSDK_GPIO_0->INTPOLSET |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_0->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_0->INTENCLR |= ch_bit;
+                        }
+                } else {
+                        CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_0->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_0->INTENCLR |= ch_bit;
+                        }
+                }
+        }
+        if (obj->ch >= 16)
+        {
+                CMSDK_GPIO_1->INTTYPESET &= ch_bit;
+                if (event == IRQ_RISE) {
+                        CMSDK_GPIO_1->INTPOLSET |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_1->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_1->INTENCLR |= ch_bit;
+                        }
+                } else {
+                        CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_1->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_1->INTENCLR |= ch_bit;
+                        }
+                }
+        }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+        NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+        NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h
new file mode 100644
index 0000000000..c5885431a6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+    
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+        uint32_t pin_number;
+    
+    __IO uint32_t *reg_dir;
+        __IO uint32_t *reg_dirclr;
+    __IO uint32_t *reg_data;
+    __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value){
+                *obj->reg_data |= (obj->mask); 
+        } else {
+                *obj->reg_data &= ~(obj->mask); 
+        }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
new file mode 100644
index 0000000000..dabc3ac33c
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
@@ -0,0 +1,542 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "SMM_MPS2.h"
+#include "wait_api.h"
+#include "fpga.h"
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE   0
+#define TRUE    1
+
+// TSC I2C controller
+#define TSC_I2C_ADDR          0x82
+// AACI I2C controller I2C address
+#define AAIC_I2C_ADDR          0x96
+// LM75B I2C address
+#define LM75_I2C_ADDR          0x90
+// MMA7660 I2C address
+#define MMA7660_I2C_ADDR          0x98
+
+// Timing Delays
+#define TSC_TSU            15          // Setup delay 600nS min
+#define AAIC_TSU            25           // Setup delay 1000nS min
+#define SHIELD_TSU            25           // Setup delay 1000nS min
+
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {TSC_SDA, I2C_0, 0},
+    {AUD_SDA, I2C_1, 0},
+    {SHIELD_0_SDA, I2C_2, 0},
+    {SHIELD_1_SDA, I2C_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {TSC_SCL, I2C_0, 0},
+    {AUD_SCL, I2C_1, 0},
+    {SHIELD_0_SCL, I2C_2, 0},
+    {SHIELD_1_SCL, I2C_3, 0},
+    {NC   , NC,    0}
+};
+
+static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
+{
+    int loop;
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            obj->i2c->CONTROLC = SCL;
+            i2c_delay(TSC_TSU);
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(TSC_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(TSC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(TSC_TSU);
+            }
+
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(TSC_TSU);
+        break;
+        case I2C_1:
+            for (loop = 0; loop < 8; loop++) {
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(AAIC_TSU);
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+            }
+
+            i2c_delay(AAIC_TSU);
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(AAIC_TSU);
+        break;
+        case I2C_2: 
+        case I2C_3: 
+            obj->i2c->CONTROLC = SCL;
+            i2c_delay(SHIELD_TSU);
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(SHIELD_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(SHIELD_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(SHIELD_TSU);
+            }
+
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(SHIELD_TSU);
+        break;
+    }
+}
+
+static inline unsigned char i2c_receive_byte(i2c_t *obj)
+{
+    int data_receive_byte, loop;
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(TSC_TSU);
+
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(TSC_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(TSC_TSU);
+            }
+
+            obj->i2c->CONTROLC = SDA;
+            i2c_delay(TSC_TSU);
+        break;
+        case I2C_1:
+            obj->i2c->CONTROLS = SDA;
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++) {
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLS = SCL | SDA;
+                i2c_delay(AAIC_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+            }
+
+            i2c_delay(AAIC_TSU);
+            obj->i2c->CONTROLC = SDA;
+            i2c_delay(AAIC_TSU);
+        break;
+        case I2C_2: 
+        case I2C_3:
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(SHIELD_TSU);
+
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(SHIELD_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(SHIELD_TSU);
+            }
+
+            obj->i2c->CONTROLC = SDA;
+            i2c_delay(SHIELD_TSU);
+        break;
+    }
+    return data_receive_byte;
+}
+
+static inline int i2c_receive_ack(i2c_t *obj)
+{
+    int nack;
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    nack = obj->i2c->CONTROL & SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA;
+    i2c_delay(delay_value);
+    if(nack==0)
+        return 1;
+
+    return 0;
+}
+
+
+static inline void i2c_send_nack(i2c_t *obj) 
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+
+}
+
+static inline void i2c_send_ack(i2c_t *obj) 
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+    
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+        
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+        
+    switch ((int)obj->i2c) {
+        case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0xC000; break;
+        case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x00C0; break;
+    }
+        
+        
+}
+
+int i2c_start(i2c_t *obj)
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA | SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+
+    return 0;
+}
+
+int i2c_start_tsc(i2c_t *obj)
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
+
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{    
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    // Actual stop bit
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA;
+    i2c_delay(delay_value);
+
+    return 0;
+}
+
+
+
+void i2c_frequency(i2c_t *obj, int hz) {
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    unsigned int loop, rxdata;
+    int sadr, ack, bytes_read;
+    rxdata=0;
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            sadr = TSC_I2C_ADDR; 
+            break;
+        case I2C_1: 
+            sadr = AAIC_I2C_ADDR; 
+            break;
+        case I2C_2: 
+        case I2C_3: 
+            sadr = address;     //LM75_I2C_ADDR; or MMA7660_I2C_ADDR;
+            break;
+         }
+    bytes_read = 0;
+    // Start bit
+    i2c_start(obj);
+
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            // Set serial and register address
+            i2c_send_byte(obj,sadr);
+            ack += i2c_receive_ack(obj);
+            i2c_send_byte(obj, address);
+            ack += i2c_receive_ack(obj);
+
+            // Stop bit
+            i2c_stop(obj);
+
+            // Start bit
+            i2c_start_tsc(obj);
+
+            // Read from I2C address
+            i2c_send_byte(obj,sadr | 1);
+            ack += i2c_receive_ack(obj);
+
+            rxdata = (i2c_receive_byte(obj) & 0xFF);
+            data[((length-1)-bytes_read)] = (char)rxdata;
+            bytes_read++;
+            // Read multiple bytes
+            if ((length > 1) && (length < 5))
+            {
+                for (loop = 1; loop <= (length - 1); loop++)
+                {
+                    // Send ACK
+                    i2c_send_ack(obj);
+
+                    // Next byte
+                    //rxdata = ((rxdata << 8) & 0xFFFFFF00);
+                    //rxdata |= (i2c_receive_byte(obj) & 0xFF);
+                    rxdata = i2c_receive_byte(obj);
+                    data[(length-1)-bytes_read] = (char)rxdata;
+                    bytes_read++;
+                            
+                }
+            }
+            break;
+        case I2C_1:
+            // Set serial and register address
+            i2c_send_byte(obj,sadr);
+            ack += i2c_receive_ack(obj);
+            i2c_send_byte(obj, address);
+            ack += i2c_receive_ack(obj);
+
+            // Stop bit
+            i2c_stop(obj);
+
+            // Start bit
+            i2c_start_tsc(obj);
+            // Fall through to read data
+        case I2C_2:
+        case I2C_3:
+            // Read from preset register address pointer
+            i2c_send_byte(obj,sadr | 1);
+            ack += i2c_receive_ack(obj);
+
+            rxdata = i2c_receive_byte(obj);
+            data[bytes_read] = (char)rxdata;
+            bytes_read++;
+            // Read multiple bytes
+            if ((length > 1) && (length < 5))
+            {
+                for (loop = 1; loop <= (length - 1); loop++)
+                {
+                    // Send ACK
+                    i2c_send_ack(obj);
+
+                    // Next byte
+                    rxdata = i2c_receive_byte(obj);
+                    data[loop] = (char)rxdata;
+                    bytes_read++;
+                            
+                }
+            }
+            break;
+    }
+    i2c_send_nack(obj);  
+
+    i2c_stop(obj);    // Actual stop bit
+
+    return bytes_read;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    int ack=0;
+    int sadr;
+    char * ptr;
+    char addr;
+    ptr = (char*)data;
+    switch ((int)obj->i2c)
+    {
+        case I2C_0: 
+            sadr = TSC_I2C_ADDR;
+            addr = address;
+            break;
+        case I2C_1: 
+            sadr = AAIC_I2C_ADDR; 
+            addr = address;
+            break;
+        case I2C_2: 
+        case I2C_3: 
+            sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR;
+            addr = *ptr++;
+            break;
+     }
+    
+//    printf("adr = %x, reg = %x\n",sadr, address);
+    i2c_start(obj);
+
+    // Set serial and register address
+    i2c_send_byte(obj,sadr);
+    ack += i2c_receive_ack(obj);
+    i2c_send_byte(obj, addr);
+    ack += i2c_receive_ack(obj);
+
+    for(int i = 1; i<length; i++)
+    {
+        i2c_send_byte(obj, *ptr++);
+        ack += i2c_receive_ack(obj);
+    }
+
+    i2c_stop(obj);
+    if(ack==3) { return 1; }
+    else{ return 0; }
+
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return 0;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    return 0;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    return 0;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    return 0;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    return 0;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h
new file mode 100644
index 0000000000..b7653f86b4
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+        __IO uint32_t *reg_dirclr;
+    __IO uint32_t *reg_out;
+    __IO  uint32_t *reg_in;
+    PortName port;
+    uint32_t mask;
+};
+
+struct serial_s {
+    CMSDK_UART_TypeDef *uart;
+    int index;
+};
+
+struct i2c_s {
+    MPS2_I2C_TypeDef *i2c;
+};
+
+struct tsc_s {
+    MPS2_I2C_TypeDef *tsc;
+};
+
+struct audio_s {
+    MPS2_I2S_TypeDef *audio_I2S;
+        MPS2_I2C_TypeDef *audio_I2C;
+};
+
+
+struct spi_s {
+    MPS2_SSP_TypeDef *spi;
+};
+
+struct clcd_s {
+    MPS2_SSP_TypeDef *clcd;
+};
+
+struct analogin_s {
+    ADCName adc;
+        MPS2_SSP_TypeDef *adc_spi;
+    PinName  pin;
+        uint32_t pin_number;
+    __IO uint32_t address;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c
new file mode 100644
index 0000000000..1e0bbc6143
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+
+void pin_function(PinName pin, int function) {
+        MBED_ASSERT(pin != (PinName)NC);
+
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+        MBED_ASSERT(pin != (PinName)NC);
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c
new file mode 100644
index 0000000000..aafcc483d6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10));    
+
+    obj->reg_in  = &port_reg->DATAOUT;
+    obj->reg_dir = &port_reg->OUTENABLESET;
+    obj->reg_dirclr = &port_reg->OUTENABLECLR;
+ 
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<16; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+    
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_in = value;
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in);
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c
new file mode 100644
index 0000000000..d8b281afa4
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c
@@ -0,0 +1,367 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_api.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+
+static const PinMap PinMap_UART_TX[] = {
+    {USBTX     , UART_0, 0},
+    {XB_TX   , UART_1, 0},
+    {SH0_TX  , UART_2, 0},
+    {SH1_TX  , UART_3, 0},
+    {NC      , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {USBRX     , UART_0, 0},
+    {XB_RX   , UART_1, 0},
+    {SH0_RX  , UART_2, 0},
+    {SH1_RX  , UART_3, 0},
+    {NC      , NC    , 0}
+};
+
+#define UART_NUM    4
+
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+struct serial_global_data_s {
+    uint32_t serial_irq_id;
+    gpio_t sw_rts, sw_cts;
+    uint8_t count, rx_irq_set_flow, rx_irq_set_api;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+    
+    obj->uart = (CMSDK_UART_TypeDef *)uart;
+    //set baud rate and enable Uart in normarl mode (RX and TX enabled)
+    switch (uart)
+    {
+        case UART_0:     //UART HEADER
+        {
+          CMSDK_UART1->CTRL = 0x0;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART1->CTRL |= 0x01;   // TX enable 
+          } else {
+            CMSDK_UART1->CTRL &= 0xFFFE;  // TX disable
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART1->CTRL |= 0x02;  // RX enable
+          } else {
+            CMSDK_UART1->CTRL &= 0xFFFD;  // RX disable
+          } 
+        }
+        break;
+        case UART_1:     //XBEE SOCKET UART
+        {
+          CMSDK_UART3->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART3->CTRL = 0x1;   // TX enable 
+            CMSDK_GPIO4->ALTFUNCSET |= 0x0100;
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART3->CTRL |= 0x2;  // RX enable 
+            CMSDK_GPIO4->ALTFUNCSET |= 0x0080;
+          }
+        }
+        break;
+        case UART_2:     //Sheild0 UART
+        {
+          CMSDK_UART0->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)uart_tx != NC)
+          {
+            CMSDK_UART0->CTRL |= 0x01;  // TX enable 
+                        CMSDK_GPIO0->ALTFUNCSET |= 0x0002;
+          }
+          
+          if((int)uart_rx != NC)
+          {
+                        CMSDK_UART0->CTRL |= 0x02;  // RX enable  
+                        CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
+          }
+        }
+        break;
+        case UART_3:     //Sheild1 UART
+        {     
+          CMSDK_UART2->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART2->CTRL = 0x1;   // TX enable 
+                        CMSDK_GPIO1->ALTFUNCSET |= 0x0002;
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART2->CTRL |= 0x2;  // RX enable 
+                        CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
+          }
+        } 
+        break;
+    }
+
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+        case UART_1: obj->index = 1; break;
+        case UART_2: obj->index = 2; break;
+        case UART_3: obj->index = 3; break;
+    }
+    uart_data[obj->index].sw_rts.pin = NC;
+    uart_data[obj->index].sw_cts.pin = NC;
+    serial_set_flow_control(obj, FlowControlNone, NC, NC);
+    
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+      uart_data[obj->index].serial_irq_id = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    // The MPS2 has a simple divider to control the baud rate. The formula is:
+    //
+    // Baudrate = PCLK / BAUDDIV
+        //
+        // PCLK = 24 Mhz
+        // so for a desired baud rate of 9600 
+        //  24000000 / 9600 = 2500
+    //
+    //check to see if minimum baud value entered
+    int baudrate_div = 0;
+    baudrate_div = SystemCoreClock / baudrate;
+    if(baudrate >= 16){
+    switch ((int)obj->uart) {
+        case UART_0: CMSDK_UART1->BAUDDIV = baudrate_div; break;
+        case UART_1: CMSDK_UART3->BAUDDIV = baudrate_div; break;
+        case UART_2: CMSDK_UART0->BAUDDIV = baudrate_div; break;
+        case UART_3: CMSDK_UART2->BAUDDIV = baudrate_div; break;
+        default: error("serial_baud"); break;
+    }
+    } else {
+        error("serial_baud");
+    }
+
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) {
+    SerialIrq irq_type;
+    switch (intstatus)
+    {
+        case 1:
+        {
+            irq_type = TxIrq;
+        }
+        break;
+
+        case 2:
+        {
+            irq_type = RxIrq;
+        }
+        break;
+
+        default: return;
+    }   /* End of Switch */
+
+    if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) 
+    {
+        gpio_write(&uart_data[index].sw_rts, 1);
+        // Disable interrupt if it wasn't enabled by other part of the application
+        if (!uart_data[index].rx_irq_set_api)
+        {
+            /* Disable Rx interrupt */
+            puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
+        }
+    }
+
+    if (uart_data[index].serial_irq_id != 0)
+    {
+        if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
+        {
+            irq_handler(uart_data[index].serial_irq_id, irq_type);
+        }
+    }
+
+    if( irq_type == TxIrq )
+    {
+        /* Clear the TX interrupt Flag */
+        puart->INTCLEAR |= 0x01;
+    }
+    else
+    {
+        /* Clear the Rx interupt Flag */
+        puart->INTCLEAR |= 0x02;
+    }
+}
+
+void uart0_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART1);}
+void uart1_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART3);}
+void uart2_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART0);}
+void uart3_irq() {uart_irq(CMSDK_UART2->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    uart_data[obj->index].serial_irq_id = id;
+}
+
+static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart)
+    {
+        case UART_0:
+            irq_n = UART0_IRQn;
+            vector = (uint32_t)&uart0_irq;
+        break;
+        case UART_1:
+            irq_n = UART1_IRQn;
+            vector = (uint32_t)&uart1_irq;
+        break;
+        case UART_2:
+        {
+            irq_n = UART2_IRQn;
+            vector  = (uint32_t)&uart2_irq;
+        }
+        break;
+        case UART_3:
+        {
+            irq_n = UART3_IRQn;
+            vector  = (uint32_t)&uart3_irq;
+        }
+        break;
+    }
+
+    if (enable)
+    {
+        if (irq == TxIrq)
+        {
+            /* set TX interrupt enable in CTRL REG */
+            obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
+        }
+        else
+        {
+            /* set Rx interrupt on in CTRL REG */
+            obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
+        }
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    }
+    else if ((irq == TxIrq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0))
+    {   /*      Disable   IRQ   */
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        
+        obj->uart->CTRL &= ~(1 << (irq + 2));
+
+        all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0;
+        
+        if (all_disabled)
+        {
+            NVIC_DisableIRQ(irq_n);   
+        }
+    }
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    if (RxIrq == irq)
+        uart_data[obj->index].rx_irq_set_api = enable;
+    serial_irq_set_internal(obj, irq, enable);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (serial_readable(obj) == 0);
+    int data = obj->uart->DATA;
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (serial_writable(obj));
+    obj->uart->DATA = c;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->STATE & 0x2;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->STATE & 0x1;
+}
+
+void serial_clear(serial_t *obj) {
+    obj->uart->DATA = 0x00;
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+}
+
+void serial_break_clear(serial_t *obj) {
+}
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c
new file mode 100644
index 0000000000..99e501a4ab
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c
@@ -0,0 +1,286 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "spi_def.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "wait_api.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {SCLK_SPI , SPI_0, 0},
+    {CLCD_SCLK , SPI_1, 0},
+    {ADC_SCLK , SPI_2, 0},
+    {SHIELD_0_SPI_SCK , SPI_3, 0},
+    {SHIELD_1_SPI_SCK , SPI_4, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {MOSI_SPI, SPI_0, 0},
+    {CLCD_MOSI, SPI_1, 0},
+    {ADC_MOSI, SPI_2, 0},
+    {SHIELD_0_SPI_MOSI, SPI_3, 0},
+    {SHIELD_1_SPI_MOSI, SPI_4, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {MISO_SPI, SPI_0, 0},
+    {CLCD_MISO, SPI_1, 0},
+    {ADC_MISO, SPI_2, 0},
+    {SHIELD_0_SPI_MISO, SPI_3, 0},
+    {SHIELD_1_SPI_MISO, SPI_4, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {SSEL_SPI, SPI_0, 0},
+    {CLCD_SSEL, SPI_1, 0},
+    {ADC_SSEL, SPI_2, 0},
+    {SHIELD_0_SPI_nCS, SPI_3, 0},
+    {SHIELD_1_SPI_nCS, SPI_4, 0},
+    {NC   , NC   , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    
+        int altfunction[4];
+        // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+      case (int)SPI_0: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+      case (int)SPI_1:
+                      /* Configure SSP used for LCD                                               */
+            obj->spi->CR1   =   0;                 /* Synchronous serial port disable  */
+            obj->spi->DMACR =   0;                 /* Disable FIFO DMA                 */
+            obj->spi->IMSC  =   0;                 /* Mask all FIFO/IRQ interrupts     */
+            obj->spi->ICR   = ((1ul <<  0) |       /* Clear SSPRORINTR interrupt       */
+                                (1ul <<  1) );      /* Clear SSPRTINTR interrupt        */
+              obj->spi->CR0   = ((7ul <<  0) |       /* 8 bit data size                  */
+                                (0ul <<  4) |       /* Motorola frame format            */
+                                (0ul <<  6) |       /* CPOL = 0                         */
+                                (0ul <<  7) |       /* CPHA = 0                         */
+                                (1ul <<  8) );      /* Set serial clock rate            */
+            obj->spi->CPSR  =  (2ul <<  0);        /* set SSP clk to 6MHz (6.6MHz max) */
+            obj->spi->CR1   = ((1ul <<  1) |       /* Synchronous serial port enable   */
+                                (0ul <<  2) );      /* Device configured as master      */
+            break;
+      case (int)SPI_2: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+      case (int)SPI_3: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+      case (int)SPI_4: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+    }
+    
+        if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
+        if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
+        if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
+        if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
+        
+    // enable alt function
+    switch ((int)obj->spi) {
+      case (int)SPI_2:
+                CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2);
+            break;
+      case (int)SPI_3:
+                CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10);
+            break;
+      case (int)SPI_4:
+                CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]);
+            break;
+        }
+        
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+   
+    uint32_t PCLK = SystemCoreClock;
+    
+        int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = PCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & SSP_SR_BSY_Msk;
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    obj->spi->DR = value;
+    while (ssp_writeable(obj));
+}
+static inline int ssp_read(spi_t *obj) {
+    int read_DR = obj->spi->DR;
+    return read_DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    while (obj->spi->SR & SSP_SR_BSY_Msk);  /* Wait for send to finish      */
+    return (ssp_read(obj));
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h
new file mode 100644
index 0000000000..c6d61b8480
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h
@@ -0,0 +1,174 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * ----------------------------------------------------------------
+ * File:     apspi.h
+ * Release:  Version 2.0
+ * ----------------------------------------------------------------
+ *  
+ *            SSP interface Support
+ *            =====================
+ */
+
+#define SSPCS_BASE          (0x4002804C)  // SSP chip select register
+#define SSP_BASE            (0x40020000)  // SSP Prime Cell
+
+#define SSPCR0              ((volatile unsigned int *)(SSP_BASE + 0x00))
+#define SSPCR1              ((volatile unsigned int *)(SSP_BASE + 0x04))
+#define SSPDR               ((volatile unsigned int *)(SSP_BASE + 0x08))
+#define SSPSR               ((volatile unsigned int *)(SSP_BASE + 0x0C))
+#define SSPCPSR             ((volatile unsigned int *)(SSP_BASE + 0x10))
+#define SSPIMSC             ((volatile unsigned int *)(SSP_BASE + 0x14))
+#define SSPRIS              ((volatile unsigned int *)(SSP_BASE + 0x18))
+#define SSPMIS              ((volatile unsigned int *)(SSP_BASE + 0x1C))
+#define SSPICR              ((volatile unsigned int *)(SSP_BASE + 0x20))
+#define SSPDMACR            ((volatile unsigned int *)(SSP_BASE + 0x24))
+#define SSPCS               ((volatile unsigned int *)(SSPCS_BASE))
+
+// SSPCR0 Control register 0
+#define SSPCR0_SCR_DFLT     0x0300      // Serial Clock Rate (divide), default set at 3
+#define SSPCR0_SPH          0x0080      // SSPCLKOUT phase
+#define SSPCR0_SPO          0x0040      // SSPCLKOUT polarity
+#define SSPCR0_FRF_MOT      0x0000      // Frame format, Motorola
+#define SSPCR0_DSS_8        0x0007      // Data packet size, 8bits
+#define SSPCR0_DSS_16       0x000F      // Data packet size, 16bits
+
+// SSPCR1 Control register 1
+#define SSPCR1_SOD          0x0008      // Slave Output mode Disable
+#define SSPCR1_MS           0x0004      // Master or Slave mode
+#define SSPCR1_SSE          0x0002      // Serial port enable
+#define SSPCR1_LBM          0x0001      // Loop Back Mode
+
+// SSPSR Status register
+#define SSPSR_BSY           0x0010      // Busy
+#define SSPSR_RFF           0x0008      // Receive  FIFO full
+#define SSPSR_RNE           0x0004      // Receive  FIFO not empty
+#define SSPSR_TNF           0x0002      // Transmit FIFO not full
+#define SSPSR_TFE           0x0001      // Transmit FIFO empty
+
+// SSPCPSR Clock prescale register
+#define SSPCPSR_DFLT        0x0008      // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSPIMSC_TXIM        0x0008      // Transmit FIFO not Masked
+#define SSPIMSC_RXIM        0x0004      // Receive  FIFO not Masked
+#define SSPIMSC_RTIM        0x0002      // Receive timeout not Masked
+#define SSPIMSC_RORIM       0x0001      // Receive overrun not Masked
+
+// SSPRIS Raw interrupt status register
+#define SSPRIS_TXRIS        0x0008      // Raw Transmit interrupt flag
+#define SSPRIS_RXRIS        0x0004      // Raw Receive  interrupt flag
+#define SSPRIS_RTRIS        0x0002      // Raw Timemout interrupt flag
+#define SSPRIS_RORRIS       0x0001      // Raw Overrun  interrupt flag
+
+// SSPMIS Masked interrupt status register
+#define SSPMIS_TXMIS        0x0008      // Masked Transmit interrupt flag
+#define SSPMIS_RXMIS        0x0004      // Masked Receive  interrupt flag
+#define SSPMIS_RTMIS        0x0002      // Masked Timemout interrupt flag
+#define SSPMIS_RORMIS       0x0001      // Masked Overrun  interrupt flag
+
+// SSPICR Interrupt clear register
+#define SSPICR_RTIC         0x0002      // Clears Timeout interrupt flag
+#define SSPICR_RORIC        0x0001      // Clears Overrun interrupt flag
+
+// SSPDMACR DMA control register
+#define SSPDMACR_TXDMAE     0x0002      // Enable Transmit FIFO DMA
+#define SSPDMACR_RXDMAE     0x0001      // Enable Receive  FIFO DMA
+
+// SPICS register (0=Chip Select low)
+#define SSPCS_nCS1          0x0002      // nCS1  (SPI_nSS)
+
+// SPI defaults
+#define SSPMAXTIME          1000        // Maximum time to wait for SSP (10*10uS)
+
+// EEPROM instruction set
+#define EEWRSR              0x0001      // Write status
+#define EEWRITE             0x0002      // Write data
+#define EEREAD              0x0003      // Read data
+#define EEWDI               0x0004      // Write disable
+#define EEWREN              0x0006      // Write enable
+#define EERDSR              0x0005      // Read status
+
+// EEPROM status register flags
+#define EERDSR_WIP          0x0001      // Write in process
+#define EERDSR_WEL          0x0002      // Write enable latch
+#define EERDSR_BP0          0x0004      // Block protect 0
+#define EERDSR_BP1          0x0008      // Block protect 1
+#define EERDSR_WPEN         0x0080      // Write protect enable
+
+ /* ----------------------------------------------------------------
+ *
+ *            Color LCD Support
+ *            =================
+ */
+
+// Color LCD Controller Internal Register addresses
+#define LSSPCS_BASE          (0x4002804C)  // LSSP chip select register
+#define LSSP_BASE            (0x40021000)  // LSSP Prime Cell
+
+#define LSSPCR0              ((volatile unsigned int *)(LSSP_BASE + 0x00))
+#define LSSPCR1              ((volatile unsigned int *)(LSSP_BASE + 0x04))
+#define LSSPDR               ((volatile unsigned int *)(LSSP_BASE + 0x08))
+#define LSSPSR               ((volatile unsigned int *)(LSSP_BASE + 0x0C))
+#define LSSPCPSR             ((volatile unsigned int *)(LSSP_BASE + 0x10))
+#define LSSPIMSC             ((volatile unsigned int *)(LSSP_BASE + 0x14))
+#define LSSPRIS              ((volatile unsigned int *)(LSSP_BASE + 0x18))
+#define LSSPMIS              ((volatile unsigned int *)(LSSP_BASE + 0x1C))
+#define LSSPICR              ((volatile unsigned int *)(LSSP_BASE + 0x20))
+#define LSSPDMACR            ((volatile unsigned int *)(LSSP_BASE + 0x24))
+#define LSSPCS               ((volatile unsigned int *)(LSSPCS_BASE))
+
+// LSSPCR0 Control register 0
+#define LSSPCR0_SCR_DFLT    0x0100      // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
+#define LSSPCR0_SPH         0x0080      // LSSPCLKOUT phase
+#define LSSPCR0_SPO         0x0040      // LSSPCLKOUT polarity
+#define LSSPCR0_FRF_MOT     0x0000      // Frame format, Motorola
+#define LSSPCR0_DSS_8       0x0007      // Data packet size, 8bits
+#define LSSPCR0_DSS_16      0x000F      // Data packet size, 16bits
+
+// LSSPCR1 Control register 1
+#define LSSPCR1_SOD         0x0008      // Slave Output mode Disable
+#define LSSPCR1_MS          0x0004      // Master or Slave mode
+#define LSSPCR1_SSE         0x0002      // Serial port enable
+#define LSSPCR1_LBM         0x0001      // Loop Back Mode
+
+// LSSPSR Status register
+#define LSSPSR_BSY          0x0010      // Busy
+#define LSSPSR_RFF          0x0008      // Receive  FIFO full
+#define LSSPSR_RNE          0x0004      // Receive  FIFO not empty
+#define LSSPSR_TNF          0x0002      // Transmit FIFO not full
+#define LSSPSR_TFE          0x0001      // Transmit FIFO empty
+
+// LSSPCPSR Clock prescale register
+#define LSSPCPSR_DFLT       0x0002      // Clock prescale (use with SCR)
+
+// SPICS register
+#define LSSPCS_nCS0         0x0001      // nCS0      (CLCD_CS)
+#define LSSPCS_nCS2         0x0004      // nCS2      (CLCD_T_CS)
+#define LCD_RESET           0x0008      // RESET     (CLCD_RESET)
+#define LCD_RS              0x0010      // RS        (CLCD_RS)
+#define LCD_RD              0x0020      // RD        (CLCD_RD)
+#define LCD_BL              0x0040      // Backlight (CLCD_BL_CTRL)
+
+// SPI defaults
+#define LSSPMAXTIME         10000       // Maximum time to wait for LSSP (10*10uS)
+#define LSPI_START          (0x70)      // Start byte for SPI transfer
+#define LSPI_RD             (0x01)      // WR bit 1 within start
+#define LSPI_WR             (0x00)      // WR bit 0 within start
+#define LSPI_DATA           (0x02)      // RS bit 1 within start byte
+#define LSPI_INDEX          (0x00)      // RS bit 0 within start byte
+
+// Screen size
+#define LCD_WIDTH           320         // Screen Width (in pixels)
+#define LCD_HEIGHT          240         // Screen Height (in pixels)
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c
new file mode 100644
index 0000000000..4197d3eb39
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER1      CMSDK_DUALTIMER1
+#define US_TICKER_TIMER2      CMSDK_DUALTIMER2
+#define US_TICKER_TIMER_IRQn  DUALTIMER_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
+    US_TICKER_TIMER2->TimerControl = 0x00; // disable timer
+    US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
+    US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
+    
+    US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
+    US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter
+    
+    US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter
+    US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    uint32_t return_value = 0;
+
+    if (!us_ticker_inited)
+        us_ticker_init();
+    return_value = ((~US_TICKER_TIMER2->TimerValue)/24);
+    return return_value;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+    int delta = 0;
+
+    if (!us_ticker_inited)
+        us_ticker_init();
+    delta = (int)(timestamp - us_ticker_read());
+    if (delta <= 0) {
+        // This event was in the past:
+        us_ticker_irq_handler();
+        return;
+    }
+    // enable interrupt
+    US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
+    US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
+    US_TICKER_TIMER1->TimerLoad = (delta)*24; //initialise the timer value
+    US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
+}
+
+void us_ticker_disable_interrupt(void) {
+    
+    US_TICKER_TIMER1->TimerControl &= 0xDF;
+    US_TICKER_TIMER2->TimerControl &= 0xDF;
+
+}
+
+void us_ticker_clear_interrupt(void) {
+
+    US_TICKER_TIMER1->TimerIntClr = 0x1;
+    US_TICKER_TIMER2->TimerIntClr = 0x1;
+
+}
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h
index 5664025837..1fc24e238c 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h
@@ -24,13 +24,17 @@ extern "C" {
 
 typedef enum {
     UART_0 = (int)CMSDK_UART0_BASE,
-    UART_1 = (int)CMSDK_UART1_BASE
+    UART_1 = (int)CMSDK_UART1_BASE,
+    UART_2 = (int)CMSDK_UART3_BASE,
+    UART_3 = (int)CMSDK_UART4_BASE
 } UARTName;
 
 typedef enum {
-    I2C_0 = (int)MPS2_TS_I2C,
-    I2C_1 = (int)MPS2_AAIC_I2C
-		
+    I2C_0 = (int)MPS2_TSC_I2C_BASE,
+    I2C_1 = (int)MPS2_AAIC_I2C_BASE,
+    I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, 
+    I2C_3 = (int)MPS2_SHIELD1_I2C_BASE 
+        
 } I2CName;
 
 typedef enum {
@@ -41,12 +45,19 @@ typedef enum {
     ADC0_4,
     ADC0_5,
     ADC0_6,
-    ADC0_7
+    ADC0_7,
+    ADC0_8,
+    ADC0_9,
+    ADC0_10,
+    ADC0_11
 } ADCName;
 
 typedef enum {
-    SPI_0 = (int)MPS2_SSP1,
-    SPI_1 = (int)MPS2_SSP0
+    SPI_0 = (int)MPS2_SSP1_BASE,
+    SPI_1 = (int)MPS2_SSP0_BASE,
+      SPI_2 = (int)MPS2_SSP2_BASE,
+    SPI_3 = (int)MPS2_SSP3_BASE,
+    SPI_4 = (int)MPS2_SSP4_BASE
 } SPIName;
 
 typedef enum {
@@ -68,8 +79,9 @@ typedef enum {
 #define STDIO_UART        UART_0
 
 #define MBED_UART0        USBTX, USBRX
-#define MBED_UART1        UART_TX1, UART_RX1
-#define MBED_UART2        UART_TX2, UART_RX2
+#define MBED_UART1        XB_TX, XB_RX
+#define MBED_UART2        SH0_TX, SH0_RX
+#define MBED_UART3        SH1_TX, SH1_RX
 #define MBED_UARTUSB      USBTX, USBRX
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h
index 453aa53c1a..544e17fbbb 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h
@@ -23,131 +23,206 @@ extern "C" {
 #endif
 
 typedef enum {
-		PIN_INPUT,
-		PIN_OUTPUT
+        PIN_INPUT,
+        PIN_OUTPUT
 } PinDirection;
 
 #define PORT_SHIFT  5
 
 typedef enum {
     // MPS2 EXP Pin Names
-		EXP0 = 0,
-		EXP1 = 1,
-		EXP2 = 2,
-		EXP3 = 3,
-		EXP4 = 4,
-		EXP5 = 5,
-		EXP6 = 6,
-		EXP7 = 7,
-		EXP8 = 8,
-		EXP9 = 9,
-		EXP10 = 10,
-		EXP11 = 11,
-		EXP12 = 12,
-		EXP13 = 13,
-		EXP14 = 14,
-		EXP15 = 15,
-		EXP16 = 16,
-		EXP17 = 17,
-		EXP18 = 18,
-		EXP19 = 19,
-		EXP20 = 20,
-		EXP21 = 21,
-		EXP22 = 22,
-		EXP23 = 23,
-		EXP24 = 24,
-		EXP25 = 25,
-		
-		EXP26 = 26,
-		EXP27 = 27,
-		EXP28 = 28,
-		EXP29 = 29,
-		EXP30 = 30,
-		EXP31 = 31,
-		EXP32 = 32, 
-		EXP33 = 33, 
-		EXP34 = 34, 
-		EXP35 = 35, 
-		EXP36 = 36, 
-		EXP37 = 37, 
-		EXP38 = 38, 
-		EXP39 = 39, 
-		EXP40 = 40, 
-		EXP41 = 41, 
-		EXP42 = 42, 
-		EXP43 = 43, 
-		EXP44 = 44, 
-		EXP45 = 45, 
-		EXP46 = 46, 
-		EXP47 = 47, 
-		EXP48 = 48, 
-		EXP49 = 49, 
-		EXP50 = 50, 
-		EXP51 = 51, 
-		
+        EXP0 = 0,
+        EXP1 = 1,
+        EXP2 = 2,
+        EXP3 = 3,
+        EXP4 = 4,
+        EXP5 = 5,
+        EXP6 = 6,
+        EXP7 = 7,
+        EXP8 = 8,
+        EXP9 = 9,
+        EXP10 = 10,
+        EXP11 = 11,
+        EXP12 = 12,
+        EXP13 = 13,
+        EXP14 = 14,
+        EXP15 = 15,
+        EXP16 = 16,
+        EXP17 = 17,
+        EXP18 = 18,
+        EXP19 = 19,
+        EXP20 = 20,
+        EXP21 = 21,
+        EXP22 = 22,
+        EXP23 = 23,
+        EXP24 = 24,
+        EXP25 = 25,
+        
+        EXP26 = 26,
+        EXP27 = 27,
+        EXP28 = 28,
+        EXP29 = 29,
+        EXP30 = 30,
+        EXP31 = 31,
+        EXP32 = 32, 
+        EXP33 = 33, 
+        EXP34 = 34, 
+        EXP35 = 35, 
+        EXP36 = 36, 
+        EXP37 = 37, 
+        EXP38 = 38, 
+        EXP39 = 39, 
+        EXP40 = 40, 
+        EXP41 = 41, 
+        EXP42 = 42, 
+        EXP43 = 43, 
+        EXP44 = 44, 
+        EXP45 = 45, 
+        EXP46 = 46, 
+        EXP47 = 47, 
+        EXP48 = 48, 
+        EXP49 = 49, 
+        EXP50 = 50, 
+        EXP51 = 51, 
+        
 // Other mbed Pin Names
 
-		//LEDs on mps2
-		//user leds
-		USERLED1 = 100,
-		USERLED2 = 101,
-		//user switches
-		USERSW1  = 110,
-		USERSW2  = 111,
-		
-		//mcc leds
-		LED1 = 200,
-		LED2 = 201,
-		LED3 = 202,
-		LED4 = 203,
-		LED5 = 204,
-		LED6 = 205,
-		LED7 = 206,
-		LED8 = 207,
-		
-		//MCC Switches
-		SW1 = 210,
-		SW2 = 211,
-		SW3 = 212,
-		SW4 = 213,
-		SW5 = 214,
-		SW6 = 215,
-		SW7 = 216,
-		SW8 = 217,
-		
-		//MPS2 SPI header pins j21
-		MOSI_SPI = 300,
-		MISO_SPI = 301,
-		SCLK_SPI = 302,
-		SSEL_SPI = 303,
-		
-		//MPS2 CLCD SPI
-		CLCD_MOSI = 304,
-		CLCD_MISO = 305,
-		CLCD_SCLK = 306,
-		CLCD_SSEL = 307,
-    	CLCD_RESET = 308,
-    	CLCD_RS = 309,
-    	CLCD_RD = 310,
-    	CLCD_BL_CTRL = 311,
-		
-		
-		//MPS2 Uart
-		USBTX  = 400,
-		USBRX  = 401,
-		UART_TX1 = 402,
-		UART_RX1 = 403,
-		UART_TX2 = 404,
-		UART_RX2 = 405,
-		
-		//MPS2 I2C touchscreen and audio
-		TSC_SDA = 500,
-		TSC_SCL = 501,
-		AUD_SDA = 502,
-		AUD_SCL = 503,
-		
-		// Not connected
-		NC = (int)0xFFFFFFFF,
+        //LEDs on mps2
+        //user leds
+        USERLED1 = 100,
+        USERLED2 = 101,
+        //user switches
+        USERSW1  = 110,
+        USERSW2  = 111,
+        
+        //mcc leds
+        LED1 = 200,
+        LED2 = 201,
+        LED3 = 202,
+        LED4 = 203,
+        LED5 = 204,
+        LED6 = 205,
+        LED7 = 206,
+        LED8 = 207,
+        
+        //MCC Switches
+        SW1 = 210,
+        SW2 = 211,
+        SW3 = 212,
+        SW4 = 213,
+        SW5 = 214,
+        SW6 = 215,
+        SW7 = 216,
+        SW8 = 217,
+        
+        //MPS2 SPI header pins j21
+        MOSI_SPI = 300,
+        MISO_SPI = 301,
+        SCLK_SPI = 302,
+        SSEL_SPI = 303,
+        
+        //MPS2 CLCD SPI
+        CLCD_MOSI = 304,
+        CLCD_MISO = 305,
+        CLCD_SCLK = 306,
+        CLCD_SSEL = 307,
+        CLCD_RESET = 308,
+        CLCD_RS = 309,
+        CLCD_RD = 310,
+        CLCD_BL_CTRL = 311,
+        
+        //MPS2 shield 0 SPI
+        SHIELD_0_SPI_SCK = 320, 
+        SHIELD_0_SPI_MOSI = 321,
+        SHIELD_0_SPI_MISO = 322,
+        SHIELD_0_SPI_nCS = 323, 
+
+        //MPS2 shield 1 SPI
+        SHIELD_1_SPI_SCK = 331, 
+        SHIELD_1_SPI_MOSI = 332,
+        SHIELD_1_SPI_MISO = 333,
+        SHIELD_1_SPI_nCS = 334, 
+        
+        //MPS2 shield ADC SPI
+        ADC_MOSI = 650,
+        ADC_MISO = 651,
+        ADC_SCLK = 652,
+        ADC_SSEL = 653,
+        
+        //MPS2 Uart
+        USBTX  = 400,
+        USBRX  = 401,
+        XB_TX = 402,
+        XB_RX = 403,
+        UART_TX2 = 404,
+        UART_RX2 = 405,
+        SH0_TX = 406,
+        SH0_RX = 407,
+        SH1_TX = 408,
+        SH1_RX = 409,
+        
+        //MPS2 I2C touchscreen and audio
+        TSC_SDA = 500,
+        TSC_SCL = 501,
+        AUD_SDA = 502,
+        AUD_SCL = 503,
+    
+        //MPS2 I2C for shield
+        SHIELD_0_SDA = 504, 
+        SHIELD_0_SCL = 505, 
+        SHIELD_1_SDA = 506,
+        SHIELD_1_SCL = 507,
+        
+        //MPS2 shield Analog pins
+        A0_0 = 600,
+        A0_1 = 601,
+        A0_2 = 602,
+        A0_3 = 603,
+        A0_4 = 604,
+        A0_5 = 605,
+        A1_0 = 606,
+        A1_1 = 607,
+        A1_2 = 608,
+        A1_3 = 609,
+        A1_4 = 610,
+        A1_5 = 611,
+        //MPS2 Shield Digital pins
+        D0_0  = EXP0,
+        D0_1  = EXP4,
+        D0_2  = EXP2,
+        D0_3  = EXP3,
+        D0_4  = EXP1,
+        D0_5  = EXP6,
+        D0_6  = EXP7,
+        D0_7  = EXP8,
+        D0_8  = EXP9,
+        D0_9  = EXP10,
+        D0_10 = EXP12,
+        D0_11 = EXP13,
+        D0_12 = EXP14,
+        D0_13 = EXP11,
+        D0_14 = EXP15,
+        D0_15 = EXP5,
+    
+        D1_0  = EXP26,
+        D1_1  = EXP30,
+        D1_2  = EXP28,
+        D1_3  = EXP29,
+        D1_4  = EXP27,
+        D1_5  = EXP32,
+        D1_6  = EXP33,
+        D1_7  = EXP34,
+        D1_8  = EXP35,
+        D1_9  = EXP36,
+        D1_10 = EXP38,
+        D1_11 = EXP39,
+        D1_12 = EXP40,
+        D1_13 = EXP44,
+        D1_14 = EXP41,
+        D1_15 = EXP31,
+        
+        // Not connected
+        NC = (int)0xFFFFFFFF,
 } PinName;
 
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c
index d2d703ae51..67abb13220 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c
@@ -35,9 +35,8 @@
  */
 
 #include <stdio.h>
-
+#include "wait_api.h"
 #include "ETH_MPS2.h"
-#include "fpga.h"
 
 // SMSC9220 low-level operations
 unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
@@ -58,7 +57,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
         timedout = 50;
         do {
             val = SMSC9220->BYTE_TEST;  // A no-op read.
-            Sleepms(1);
+            wait_ms(1);
             timedout--;
         } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
 
@@ -92,7 +91,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
         timedout = 50;
         do {
             read = SMSC9220->BYTE_TEST;     // A no-op read.
-            Sleepms(1);
+            wait_ms(1);
             timedout--;
         } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
 
@@ -126,7 +125,7 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
         val = 0;
         timedout = 50;
         do {
-            Sleepms(1);
+            wait_ms(1);
             timedout--;
             smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
         } while(timedout && (val & ((unsigned int)1 << 0)));
@@ -166,7 +165,7 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
 
         do {
 
-            Sleepms(1);
+            wait_ms(1);
             timedout--;
             smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
         } while(timedout && (phycmd & (1 << 0)));
@@ -197,7 +196,7 @@ unsigned int smsc9220_soft_reset(void)
     SMSC9220->HW_CFG |= 1;
 
     do {
-        Sleepms(1);
+        wait_ms(1);
         timedout--;
     } while(timedout && (SMSC9220->HW_CFG & 1));
 
@@ -224,7 +223,7 @@ unsigned int smsc9220_wait_eeprom(void)
     timedout = 50;
 
     do {
-        Sleepms(1);
+        wait_ms(1);
         timedout--;
 
     } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
@@ -238,9 +237,9 @@ unsigned int smsc9220_wait_eeprom(void)
 /* initialise irqs */
 void smsc9220_init_irqs(void)
 {
-	SMSC9220->INT_EN    = 0x0;
-	SMSC9220->INT_STS   = 0xFFFFFFFF;   // clear all interrupts
-	SMSC9220->IRQ_CFG   = 0x22000100;   // irq deassertion at 220 usecs and master IRQ enable.
+    SMSC9220->INT_EN    = 0x0;
+    SMSC9220->INT_STS   = 0xFFFFFFFF;   // clear all interrupts
+    SMSC9220->IRQ_CFG   = 0x22000100;   // irq deassertion at 220 usecs and master IRQ enable.
 }
 
 unsigned int smsc9220_check_phy(void)
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c
index 9f3de7e4ae..a0111474c6 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c
@@ -28,8 +28,8 @@
 // Used for I2C drivers
 void i2c_delay(unsigned int tick)
 {
-	unsigned int end;
-	unsigned int start;
+    unsigned int end;
+    unsigned int start;
 
     start = MPS2_FPGAIO->COUNTER;
     end   = start + (tick);
@@ -50,8 +50,8 @@ void i2c_delay(unsigned int tick)
  */
 void Sleepms(unsigned int msec)
 {
-	unsigned int end;
-	unsigned int start;
+    unsigned int end;
+    unsigned int start;
 
     start = MPS2_FPGAIO->COUNTER;
     end   = start + (25 * msec * 1000);
@@ -71,8 +71,8 @@ void Sleepms(unsigned int msec)
  */
 void Sleepus(unsigned int usec)
 {
-	unsigned int end;
-	unsigned int start;
+    unsigned int end;
+    unsigned int start;
 
     start = MPS2_FPGAIO->COUNTER;
     end   = start + (25 * usec);
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c
index 44fad222c4..1461ff5995 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c
@@ -89,6 +89,45 @@ int smsc9220_check_macaddress(void)
     return error;
 }
 
+void smsc9220_print_mac_registers()
+{
+    unsigned int read;
+    int i;
+
+    i = 0;
+    read = 0;
+
+    for(i = 1; i <= 0xC; i++) {
+        smsc9220_mac_regread(i, &read);
+    }
+    return;
+}
+
+
+void smsc9220_print_phy_registers()
+{
+    unsigned short read;
+    unsigned int i;
+
+    i = 0;
+    read = 0;
+    for(i = 0; i <= 6; i++) {
+        smsc9220_phy_regread(i, &read);
+    }
+    smsc9220_phy_regread(i = 17, &read);
+
+    smsc9220_phy_regread(i = 18, &read);
+
+    smsc9220_phy_regread(i = 27, &read);
+
+    smsc9220_phy_regread(i = 29, &read);
+
+    smsc9220_phy_regread(i = 30, &read);
+
+    smsc9220_phy_regread(i = 31, &read);
+
+    return;
+}
 
 /*----------------------------------------------------------------------------
   Ethernet Device initialize
@@ -96,13 +135,13 @@ int smsc9220_check_macaddress(void)
 
 int ethernet_transmission(unsigned char * pkt, unsigned int length)
 {
-	smsc9220_xmit_packet(pkt, length);
-	return 0;
+    smsc9220_xmit_packet(pkt, length);
+    return 0;
 }
 
 int ethernet_reception(unsigned int *recvbuf, unsigned int *index) 
 {
-	return smsc9220_recv_packet((unsigned int *)recvbuf, index);
+    return smsc9220_recv_packet((unsigned int *)recvbuf, index);
 }
 
 int ethernet_mac_address(char *mac) 
@@ -112,16 +151,16 @@ int ethernet_mac_address(char *mac)
 
 unsigned int ethernet_check_ready(void)
 {
-	return smsc9220_check_ready();
+    return smsc9220_check_ready();
 }
 
 unsigned int ethernet_intf()
 {
   unsigned int txfifo_inf;
  
-	txfifo_inf = SMSC9220->TX_FIFO_INF;
-	
-	return txfifo_inf;
+    txfifo_inf = SMSC9220->TX_FIFO_INF;
+    
+    return txfifo_inf;
 
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c
new file mode 100644
index 0000000000..bef3fb5f5f
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#define ADC_12BIT_RANGE             0xFFF
+
+static const PinMap PinMap_ADC[] = {
+    {A0_0, ADC0_0,  0},
+    {A0_1, ADC0_1,  0},
+    {A0_2, ADC0_2,  0},
+    {A0_3, ADC0_3,  0},
+    {A0_4, ADC0_4,  0},
+    {A0_5, ADC0_5,  0},
+    {A1_0, ADC0_6,  0},
+    {A1_1, ADC0_7,  0},
+    {A1_2, ADC0_8,  0},
+    {A1_3, ADC0_9,  0},
+    {A1_4, ADC0_10, 0},
+    {A1_5, ADC0_11, 0},
+    {NC,    NC,     0}
+};
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {ADC_SCLK , SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {ADC_MOSI, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {ADC_MISO, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {ADC_SSEL, SPI_3, 0},
+    {NC   , NC   , 0}
+};
+
+#define ADC_RANGE    ADC_12BIT_RANGE
+int analog_spi_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+  MBED_ASSERT(obj->adc != (ADCName)NC);
+  obj->pin = pin;
+    obj->pin_number = pin-600;
+    obj->address = (0x0000 | (pin-600));
+    
+    SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
+  SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
+  SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
+  SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
+  SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
+  SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
+  obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl);
+  
+    if(analog_spi_inited == 0){
+    obj->adc_spi->CR1       = 0;
+    obj->adc_spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
+    obj->adc_spi->CPSR      = SSP_CPSR_DFLT; 
+    obj->adc_spi->IMSC      = 0x8; 
+    obj->adc_spi->DMACR     = 0;
+    obj->adc_spi->CR1       = SSP_CR1_SSE_Msk;
+    obj->adc_spi->ICR       = 0x3;  
+    analog_spi_inited = 1;
+    }
+    
+  pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
+  pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
+  pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
+  pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
+  pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    return 0;
+}
+
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read(obj);
+    return 0;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    return 0;
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h
index 32e61e943e..6dd951b618 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h
@@ -22,14 +22,14 @@
 
 #define DEVICE_INTERRUPTIN      1
 
-#define DEVICE_ANALOGIN         0
+#define DEVICE_ANALOGIN         1
 #define DEVICE_ANALOGOUT        0
 
 #define DEVICE_SERIAL           1
 #define DEVICE_SERIAL_FC        1
 
 #define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
+#define DEVICE_I2CSLAVE         0
 
 #define DEVICE_SPI              1
 #define DEVICE_SPISLAVE         1
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c
index b55de8a3e3..e59c210243 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c
@@ -38,7 +38,7 @@
  *----------------------------------------------------------------------------*/
 int ethernet_init()
 {
-	  int error;
+      int error;
     error = 0;
 
     if(smsc9220_check_id()) {
@@ -123,7 +123,7 @@ void ethernet_free() {
 
 int ethernet_write(const char *data, int size)
 {
-		return 0;
+        return 0;
 }
 
 int ethernet_send() 
@@ -145,7 +145,7 @@ int ethernet_receive()
 
 int ethernet_read(char *data, int dlen) 
 {
-	return 0;
+    return 0;
 }
 
 void ethernet_address(char *mac) {
@@ -154,11 +154,11 @@ void ethernet_address(char *mac) {
 
 int ethernet_link(void) 
 {
-	return 0;
+    return 0;
 }
 
 void ethernet_set_link(int speed, int duplex)
 {
-	smsc9220_establish_link();
+    smsc9220_establish_link();
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c
index ce17cbed2e..66caa5e5dd 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c
@@ -18,95 +18,111 @@
 
 // function to enable the GPIO pin
 uint32_t gpio_set(PinName pin) {
-	return (1);
+    return (1);
 }
 
 //function to initialise the gpio pin
 // this links the board control bits for each pin 
 // with the object created for the pin
 void gpio_init(gpio_t *obj, PinName pin) {
-		if(pin == NC){ return;}
-		else {
-		int pin_value = 0;
-		obj->pin = pin;
-		if(pin <=15){
-			pin_value = pin;
-		}else if (pin >= 16 && pin <= 31){
-			pin_value = pin-16;
-		}else if (pin >= 32 && pin <= 47){
-			pin_value = pin-32;
-		}else if (pin >= 48 && pin <= 51){
-			pin_value = pin-48;
-		}else if (pin == 100 || pin == 101){
-			pin_value = pin-100;
-		}else if (pin == 110 || pin == 111){
-			pin_value = pin-110;
-		}else if (pin >= 200 && pin <= 207){
-			pin_value = pin-200;
-		}else if (pin >= 210 && pin <= 217){
-			pin_value = pin-210;
-		}else if (pin == 303){
-			pin_value = pin-302;
-		}else if (pin == 307){
-			pin_value = pin-307;
-		}else if (pin == 308){
-			pin_value = pin-305;
-		}else if (pin == 309){
-			pin_value = pin-305;
-		}else if (pin == 310){
-			pin_value = pin-305;
-		}else if (pin == 311){
-			pin_value = pin-305;
-		}
-		
-		obj->mask = 0x1 << pin_value;
-		obj->pin_number = pin;
-		if(pin <=15) {
-			obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
-			obj->reg_in  = 		&CMSDK_GPIO0->DATA ;
-			obj->reg_dir = 		&CMSDK_GPIO0->OUTENABLESET ;
-			obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
-		} else if (pin >= 16 && pin <= 31){
-			obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
-			obj->reg_in  = 		&CMSDK_GPIO1->DATA ;
-			obj->reg_dir = 		&CMSDK_GPIO1->OUTENABLESET ;
-			obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
-		} else if (pin >= 32 && pin <= 47){
-			obj->reg_data = &CMSDK_GPIO2->DATAOUT;
-			obj->reg_in  = 		&CMSDK_GPIO2->DATA;
-			obj->reg_dir = 		&CMSDK_GPIO2->OUTENABLESET ;
-			obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
-		}	else if (pin >= 48 && pin <= 51){
-			obj->reg_data = &CMSDK_GPIO3->DATAOUT;
-			obj->reg_in  = 		&CMSDK_GPIO3->DATA;
-			obj->reg_dir = 		&CMSDK_GPIO3->OUTENABLESET ;
-			obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
-		} else if (pin == 100 || pin == 101){
-			obj->reg_data = &MPS2_FPGAIO->LED; //user leds
-			obj->reg_in  =  &MPS2_FPGAIO->LED;
-		} else if (pin == 110 || pin == 111){
-			obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
-			obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
-		}else if (pin >= 200 && pin <= 207){
-			obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
-			obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
-		}else if (pin >= 210 && pin <= 217){
-			obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
-		}else if (pin == 303 || pin == 307){
-			obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
-		}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
-			obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
-		}
-	}
+        if(pin == NC){ return;}
+        else {
+        int pin_value = 0;
+        obj->pin = pin;
+        if(pin <=15){
+            pin_value = pin;
+        }else if (pin >= 16 && pin <= 31){
+            pin_value = pin-16;
+        }else if (pin >= 32 && pin <= 47){
+            pin_value = pin-32;
+        }else if (pin >= 48 && pin <= 51){
+            pin_value = pin-48;
+        }else if (pin == 100 || pin == 101){
+            pin_value = pin-100;
+        }else if (pin == 110 || pin == 111){
+            pin_value = pin-110;
+        }else if (pin >= 200 && pin <= 207){
+            pin_value = pin-200;
+        }else if (pin >= 210 && pin <= 217){
+            pin_value = pin-210;
+        }else if (pin == 303){
+            pin_value = pin-302;
+        }else if (pin == 307){
+            pin_value = pin-307;
+        }else if (pin == 308){
+            pin_value = pin-305;
+        }else if (pin == 309){
+            pin_value = pin-305;
+        }else if (pin == 310){
+            pin_value = pin-305;
+        }else if (pin == 311){
+            pin_value = pin-305;
+        }else if (pin == 323){
+            pin_value = pin-315;
+        }else if (pin == 334){
+            pin_value = pin-325;
+        }else if (pin == 653){
+            pin_value = pin-646;
+        }
+        
+        obj->mask = 0x1 << pin_value;
+        obj->pin_number = pin;
+        if(pin <=15) {
+            obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
+            obj->reg_in  =         &CMSDK_GPIO0->DATA ;
+            obj->reg_dir =         &CMSDK_GPIO0->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
+        } else if (pin >= 16 && pin <= 31){
+            obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
+            obj->reg_in  =         &CMSDK_GPIO1->DATA ;
+            obj->reg_dir =         &CMSDK_GPIO1->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
+        } else if (pin >= 32 && pin <= 47){
+            obj->reg_data = &CMSDK_GPIO2->DATAOUT;
+            obj->reg_in  =         &CMSDK_GPIO2->DATA;
+            obj->reg_dir =         &CMSDK_GPIO2->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
+        }    else if (pin >= 48 && pin <= 51){
+            obj->reg_data = &CMSDK_GPIO3->DATAOUT;
+            obj->reg_in  =         &CMSDK_GPIO3->DATA;
+            obj->reg_dir =         &CMSDK_GPIO3->OUTENABLESET ;
+            obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
+        } else if (pin == 100 || pin == 101){
+            obj->reg_data = &MPS2_FPGAIO->LED; //user leds
+            obj->reg_in  =  &MPS2_FPGAIO->LED;
+        } else if (pin == 110 || pin == 111){
+            obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
+            obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
+        }else if (pin >= 200 && pin <= 207){
+            obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
+            obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
+        }else if (pin >= 210 && pin <= 217){
+            obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
+        }else if (pin == 303 || pin == 307){
+            obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
+        }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
+            obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
+        }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
+            obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
+        }
+        
+        if (pin == 323){
+            CMSDK_GPIO0->ALTFUNCSET |= 0x1000;
+        }else if (pin == 334){
+            CMSDK_GPIO2->ALTFUNCSET |= 0x0040;
+        }else if (pin == 653){
+            CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
+        }
+    }
 }
 
 void gpio_mode(gpio_t *obj, PinMode mode) {
-		pin_mode(obj->pin, mode);
+        pin_mode(obj->pin, mode);
 }
 
 void gpio_dir(gpio_t *obj, PinDirection direction) {
-		if(obj->pin >= 0 && obj->pin <= 51)
-			{		
+        if(obj->pin >= 0 && obj->pin <= 51)
+            {        
         switch (direction) {
           case PIN_INPUT : *obj->reg_dirclr = obj->mask;  break;
           case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
@@ -115,10 +131,10 @@ void gpio_dir(gpio_t *obj, PinDirection direction) {
 }
 
 int gpio_is_connected(const gpio_t *obj){
-	if(obj->pin != (PinName)NC){
-		return 1;
-	} else {
-		return 0;
-	}
+    if(obj->pin != (PinName)NC){
+        return 1;
+    } else {
+        return 0;
+    }
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c
index 8aa125a4b0..bedf723bfc 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c
@@ -27,36 +27,36 @@ static uint32_t channel_ids[CHANNEL_NUM] = {0};
 static gpio_irq_handler irq_handler;
 
 static inline void handle_interrupt_in(uint32_t channel) {
-		uint32_t ch_bit = (1 << channel);
-		// Return immediately if:
-		//   * The interrupt was already served
-		//   * There is no user handler
-		//   * It is a level interrupt, not an edge interrupt
-	if (ch_bit <16){
-		if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
+        uint32_t ch_bit = (1 << channel);
+        // Return immediately if:
+        //   * The interrupt was already served
+        //   * There is no user handler
+        //   * It is a level interrupt, not an edge interrupt
+    if (ch_bit <16){
+        if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
 
-		if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
-				irq_handler(channel_ids[channel], IRQ_RISE);
-				CMSDK_GPIO_0->INTPOLSET = ch_bit;
-		}
-		if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
-				irq_handler(channel_ids[channel], IRQ_FALL);
-		}
-		CMSDK_GPIO_0->INTCLEAR = ch_bit;
-	}
-	
-	if (ch_bit>=16) {
-		if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
+        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_RISE);
+                CMSDK_GPIO_0->INTPOLSET = ch_bit;
+        }
+        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_FALL);
+        }
+        CMSDK_GPIO_0->INTCLEAR = ch_bit;
+    }
+    
+    if (ch_bit>=16) {
+        if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
 
-		if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
-				irq_handler(channel_ids[channel], IRQ_RISE);
-				CMSDK_GPIO_1->INTPOLSET = ch_bit;
-		}
-		if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
-				irq_handler(channel_ids[channel], IRQ_FALL);
-		}
-		CMSDK_GPIO_1->INTCLEAR = ch_bit;
-	}
+        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_RISE);
+                CMSDK_GPIO_1->INTPOLSET = ch_bit;
+        }
+        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+                irq_handler(channel_ids[channel], IRQ_FALL);
+        }
+        CMSDK_GPIO_1->INTCLEAR = ch_bit;
+    }
 }
 
 void gpio0_irq0(void)  {handle_interrupt_in(0);}
@@ -94,148 +94,148 @@ void gpio1_irq15(void) {handle_interrupt_in(31);}
 
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-		if (pin == NC) {return -1;}
-		else {
-		
-		irq_handler = handler;
-		
-		int found_free_channel = 0;
-		int i = 0;
-		for (i=0; i<CHANNEL_NUM; i++) {
-				if (channel_ids[i] == 0) {
-						channel_ids[i] = id;
-						obj->ch = i;
-						found_free_channel = 1;
-						break;
-				}
-		}
-		if (!found_free_channel) return -1;
-		
-		
-		/* To select a pin for any of the eight pin interrupts, write the pin number
-		 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
-		 * @see: mbed_capi/PinNames.h
-		 */
-		if (pin <16)
-		{
-		CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
-		}
-		
-		if (pin >= 16)
-		{
-		CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
-		}
+        if (pin == NC) {return -1;}
+        else {
+        
+        irq_handler = handler;
+        
+        int found_free_channel = 0;
+        int i = 0;
+        for (i=0; i<CHANNEL_NUM; i++) {
+                if (channel_ids[i] == 0) {
+                        channel_ids[i] = id;
+                        obj->ch = i;
+                        found_free_channel = 1;
+                        break;
+                }
+        }
+        if (!found_free_channel) return -1;
+        
+        
+        /* To select a pin for any of the eight pin interrupts, write the pin number
+         * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
+         * @see: mbed_capi/PinNames.h
+         */
+        if (pin <16)
+        {
+        CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
+        }
+        
+        if (pin >= 16)
+        {
+        CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
+        }
 
-		void (*channels_irq)(void) = NULL;
-		switch (obj->ch) {
-				case 0: channels_irq = &gpio0_irq0; break;
-				case 1: channels_irq = &gpio0_irq1; break;
-				case 2: channels_irq = &gpio0_irq2; break;
-				case 3: channels_irq = &gpio0_irq3; break;
-				case 4: channels_irq = &gpio0_irq4; break;
-				case 5: channels_irq = &gpio0_irq5; break;
-				case 6: channels_irq = &gpio0_irq6; break;
-				case 7: channels_irq = &gpio0_irq7; break;
-				case 8: channels_irq = &gpio0_irq8; break;
-				case 9: channels_irq = &gpio0_irq9; break;
-				case 10: channels_irq = &gpio0_irq10; break;
-				case 11: channels_irq = &gpio0_irq11; break;
-				case 12: channels_irq = &gpio0_irq12; break;
-				case 13: channels_irq = &gpio0_irq13; break;
-				case 14: channels_irq = &gpio0_irq14; break;
-				case 15: channels_irq = &gpio0_irq15; break;
-				case 16: channels_irq = &gpio1_irq0; break;
-				case 17: channels_irq = &gpio1_irq1; break;
-				case 18: channels_irq = &gpio1_irq2; break;
-				case 19: channels_irq = &gpio1_irq3; break;
-				case 20: channels_irq = &gpio1_irq4; break;
-				case 21: channels_irq = &gpio1_irq5; break;
-				case 22: channels_irq = &gpio1_irq6; break;
-				case 23: channels_irq = &gpio1_irq7; break;
-				case 24: channels_irq = &gpio1_irq8; break;
-				case 25: channels_irq = &gpio1_irq9; break;
-				case 26: channels_irq = &gpio1_irq10; break;
-				case 27: channels_irq = &gpio1_irq11; break;
-				case 28: channels_irq = &gpio1_irq12; break;
-				case 29: channels_irq = &gpio1_irq13; break;
-				case 30: channels_irq = &gpio1_irq14; break;
-				case 31: channels_irq = &gpio1_irq15; break;
-			
-		}
-		NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
-		NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
-	
-		return 0;
-	}
+        void (*channels_irq)(void) = NULL;
+        switch (obj->ch) {
+                case 0: channels_irq = &gpio0_irq0; break;
+                case 1: channels_irq = &gpio0_irq1; break;
+                case 2: channels_irq = &gpio0_irq2; break;
+                case 3: channels_irq = &gpio0_irq3; break;
+                case 4: channels_irq = &gpio0_irq4; break;
+                case 5: channels_irq = &gpio0_irq5; break;
+                case 6: channels_irq = &gpio0_irq6; break;
+                case 7: channels_irq = &gpio0_irq7; break;
+                case 8: channels_irq = &gpio0_irq8; break;
+                case 9: channels_irq = &gpio0_irq9; break;
+                case 10: channels_irq = &gpio0_irq10; break;
+                case 11: channels_irq = &gpio0_irq11; break;
+                case 12: channels_irq = &gpio0_irq12; break;
+                case 13: channels_irq = &gpio0_irq13; break;
+                case 14: channels_irq = &gpio0_irq14; break;
+                case 15: channels_irq = &gpio0_irq15; break;
+                case 16: channels_irq = &gpio1_irq0; break;
+                case 17: channels_irq = &gpio1_irq1; break;
+                case 18: channels_irq = &gpio1_irq2; break;
+                case 19: channels_irq = &gpio1_irq3; break;
+                case 20: channels_irq = &gpio1_irq4; break;
+                case 21: channels_irq = &gpio1_irq5; break;
+                case 22: channels_irq = &gpio1_irq6; break;
+                case 23: channels_irq = &gpio1_irq7; break;
+                case 24: channels_irq = &gpio1_irq8; break;
+                case 25: channels_irq = &gpio1_irq9; break;
+                case 26: channels_irq = &gpio1_irq10; break;
+                case 27: channels_irq = &gpio1_irq11; break;
+                case 28: channels_irq = &gpio1_irq12; break;
+                case 29: channels_irq = &gpio1_irq13; break;
+                case 30: channels_irq = &gpio1_irq14; break;
+                case 31: channels_irq = &gpio1_irq15; break;
+            
+        }
+        NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+        NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    
+        return 0;
+    }
 }
 
 void gpio_irq_free(gpio_irq_t *obj) {
 }
 
 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-		unsigned int ch_bit = (1 << obj->ch);
-		
-		// Clear interrupt
-		if (obj->ch <16)
-		{
-				if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
-				{
-					CMSDK_GPIO_0->INTCLEAR = ch_bit;
-				}
-		}
-		if (obj->ch >= 16)
-		{
-				if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
-				{
-					CMSDK_GPIO_1->INTCLEAR = ch_bit;
-				}
-		}
-		
-		// Edge trigger
-		if (obj->ch <16)
-		{
-				CMSDK_GPIO_0->INTTYPESET &= ch_bit;
-				if (event == IRQ_RISE) {
-						CMSDK_GPIO_0->INTPOLSET |= ch_bit;
-						if (enable) {
-								CMSDK_GPIO_0->INTENSET |= ch_bit;
-						} else {
-								CMSDK_GPIO_0->INTENCLR |= ch_bit;
-						}
-				} else {
-						CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
-						if (enable) {
-								CMSDK_GPIO_0->INTENSET |= ch_bit;
-						} else {
-								CMSDK_GPIO_0->INTENCLR |= ch_bit;
-						}
-				}
-		}
-		if (obj->ch >= 16)
-		{
-				CMSDK_GPIO_1->INTTYPESET &= ch_bit;
-				if (event == IRQ_RISE) {
-						CMSDK_GPIO_1->INTPOLSET |= ch_bit;
-						if (enable) {
-								CMSDK_GPIO_1->INTENSET |= ch_bit;
-						} else {
-								CMSDK_GPIO_1->INTENCLR |= ch_bit;
-						}
-				} else {
-						CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
-						if (enable) {
-								CMSDK_GPIO_1->INTENSET |= ch_bit;
-						} else {
-								CMSDK_GPIO_1->INTENCLR |= ch_bit;
-						}
-				}
-		}
+        unsigned int ch_bit = (1 << obj->ch);
+        
+        // Clear interrupt
+        if (obj->ch <16)
+        {
+                if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
+                {
+                    CMSDK_GPIO_0->INTCLEAR = ch_bit;
+                }
+        }
+        if (obj->ch >= 16)
+        {
+                if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
+                {
+                    CMSDK_GPIO_1->INTCLEAR = ch_bit;
+                }
+        }
+        
+        // Edge trigger
+        if (obj->ch <16)
+        {
+                CMSDK_GPIO_0->INTTYPESET &= ch_bit;
+                if (event == IRQ_RISE) {
+                        CMSDK_GPIO_0->INTPOLSET |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_0->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_0->INTENCLR |= ch_bit;
+                        }
+                } else {
+                        CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_0->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_0->INTENCLR |= ch_bit;
+                        }
+                }
+        }
+        if (obj->ch >= 16)
+        {
+                CMSDK_GPIO_1->INTTYPESET &= ch_bit;
+                if (event == IRQ_RISE) {
+                        CMSDK_GPIO_1->INTPOLSET |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_1->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_1->INTENCLR |= ch_bit;
+                        }
+                } else {
+                        CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
+                        if (enable) {
+                                CMSDK_GPIO_1->INTENSET |= ch_bit;
+                        } else {
+                                CMSDK_GPIO_1->INTENCLR |= ch_bit;
+                        }
+                }
+        }
 }
 
 void gpio_irq_enable(gpio_irq_t *obj) {
-		NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+        NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
 }
 
 void gpio_irq_disable(gpio_irq_t *obj) {
-		NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+        NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
 }
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h
index 8ff7b3a770..c5885431a6 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h
@@ -24,24 +24,24 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-	
+    
 typedef struct {
     PinName  pin;
     uint32_t mask;
-		uint32_t pin_number;
-	
+        uint32_t pin_number;
+    
     __IO uint32_t *reg_dir;
-		__IO uint32_t *reg_dirclr;
+        __IO uint32_t *reg_dirclr;
     __IO uint32_t *reg_data;
     __I uint32_t *reg_in;
 } gpio_t;
 
 static inline void gpio_write(gpio_t *obj, int value) {
-    if (value == 1){
-				*obj->reg_data |= (obj->mask); 
-		} else if (value == 0){
-				*obj->reg_data &= ~(obj->mask); 
-		}
+    if (value){
+                *obj->reg_data |= (obj->mask); 
+        } else {
+                *obj->reg_data &= ~(obj->mask); 
+        }
 }
 
 static inline int gpio_read(gpio_t *obj) {
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
index 45b5a25c93..f2c979ed4f 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
@@ -48,111 +48,161 @@
 
 #define TSC_TSU            15          // Setup delay 600nS min
 #define AAIC_TSU            25           // Setup delay 1000nS min
+#define SHIELD_TSU            25           // Setup delay 1000nS min
 
 
 static const PinMap PinMap_I2C_SDA[] = {
     {TSC_SDA, I2C_0, 0},
     {AUD_SDA, I2C_1, 0},
-//    {EXP_SDA, I2C_2, 0},		//only used in extended version
+    {SHIELD_0_SDA, I2C_2, 0},
+    {SHIELD_1_SDA, I2C_3, 0},
     {NC   , NC   , 0}
 };
 
 static const PinMap PinMap_I2C_SCL[] = {
     {TSC_SCL, I2C_0, 0},
     {AUD_SCL, I2C_1, 0},
-//    {EXP_SCL, I2C_2, 0},		//only used in extended version
+    {SHIELD_0_SCL, I2C_2, 0},
+    {SHIELD_1_SCL, I2C_3, 0},
     {NC   , NC,    0}
 };
 
 static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
 {
     int loop;
-		switch ((int)obj->i2c) {
-			case I2C_0: 
-        obj->i2c->CONTROLC = SCL;
-        i2c_delay(TSC_TSU);
-    
-        for (loop = 0; loop < 8; loop++)
-        {
-            if (c & (1 << (7 - loop)))
-                obj->i2c->CONTROLS = SDA;
-            else
-                obj->i2c->CONTROLC = SDA;
-            i2c_delay(TSC_TSU);
-            obj->i2c->CONTROLS = SCL;
-            i2c_delay(TSC_TSU);
+    switch ((int)obj->i2c) {
+        case I2C_0: 
             obj->i2c->CONTROLC = SCL;
             i2c_delay(TSC_TSU);
-        }
-    
-        obj->i2c->CONTROLS = SDA;
-        i2c_delay(TSC_TSU);
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(TSC_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(TSC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(TSC_TSU);
+            }
+
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(TSC_TSU);
         break;
-      case I2C_1:
-        for (loop = 0; loop < 8; loop++) {
+        case I2C_1:
+            for (loop = 0; loop < 8; loop++) {
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(AAIC_TSU);
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+            }
+
             i2c_delay(AAIC_TSU);
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(AAIC_TSU);
+        break;
+        case I2C_2: 
+        case I2C_3: 
             obj->i2c->CONTROLC = SCL;
-            i2c_delay(AAIC_TSU);
-            if (c & (1 << (7 - loop)))
-                obj->i2c->CONTROLS = SDA;
-            else
-                obj->i2c->CONTROLC = SDA;
-            i2c_delay(AAIC_TSU);
-            obj->i2c->CONTROLS = SCL;
-            i2c_delay(AAIC_TSU);
-            obj->i2c->CONTROLC = SCL;
-        }
-     
-        i2c_delay(AAIC_TSU);
-        obj->i2c->CONTROLS = SDA;
-        i2c_delay(AAIC_TSU);
-				break;
+            i2c_delay(SHIELD_TSU);
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                if (c & (1 << (7 - loop)))
+                    obj->i2c->CONTROLS = SDA;
+                else
+                    obj->i2c->CONTROLC = SDA;
+                
+                i2c_delay(SHIELD_TSU);
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(SHIELD_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(SHIELD_TSU);
+            }
+
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(SHIELD_TSU);
+        break;
     }
 }
 
 static inline unsigned char i2c_receive_byte(i2c_t *obj)
 {
-		int data_receive_byte, loop;
-		switch ((int)obj->i2c) {
-			case I2C_0: 
-        obj->i2c->CONTROLS = SDA;
-        i2c_delay(TSC_TSU);
-    
-        data_receive_byte = 0;
-    
-        for (loop = 0; loop < 8; loop++)
-        {
-            obj->i2c->CONTROLS = SCL;
+    int data_receive_byte, loop;
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            obj->i2c->CONTROLS = SDA;
             i2c_delay(TSC_TSU);
-            if ((obj->i2c->CONTROL & SDA))
-            	data_receive_byte += (1 << (7 - loop));
-            obj->i2c->CONTROLC = SCL;
+
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(TSC_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(TSC_TSU);
+            }
+
+            obj->i2c->CONTROLC = SDA;
             i2c_delay(TSC_TSU);
-        }
-    
-        obj->i2c->CONTROLC = SDA;
-        i2c_delay(TSC_TSU);
         break;
-      case I2C_1:
-        obj->i2c->CONTROLS = SDA;
-        data_receive_byte = 0;
-    
-        for (loop = 0; loop < 8; loop++) {
+        case I2C_1:
+            obj->i2c->CONTROLS = SDA;
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++) {
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLS = SCL | SDA;
+                i2c_delay(AAIC_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                i2c_delay(AAIC_TSU);
+                obj->i2c->CONTROLC = SCL;
+            }
+
             i2c_delay(AAIC_TSU);
-            obj->i2c->CONTROLC = SCL;
+            obj->i2c->CONTROLC = SDA;
             i2c_delay(AAIC_TSU);
-            obj->i2c->CONTROLS = SCL | SDA;
-            i2c_delay(AAIC_TSU);
-            if ((obj->i2c->CONTROL & SDA))
-            	data_receive_byte += (1 << (7 - loop));
-            i2c_delay(AAIC_TSU);
-            obj->i2c->CONTROLC = SCL;
-        }
-    
-        i2c_delay(AAIC_TSU);
-        obj->i2c->CONTROLC = SDA;
-        i2c_delay(AAIC_TSU);
-    		break;
+        break;
+        case I2C_2: 
+        case I2C_3:
+            obj->i2c->CONTROLS = SDA;
+            i2c_delay(SHIELD_TSU);
+
+            data_receive_byte = 0;
+
+            for (loop = 0; loop < 8; loop++)
+            {
+                obj->i2c->CONTROLS = SCL;
+                i2c_delay(SHIELD_TSU);
+                if ((obj->i2c->CONTROL & SDA))
+                    data_receive_byte += (1 << (7 - loop));
+                
+                obj->i2c->CONTROLC = SCL;
+                i2c_delay(SHIELD_TSU);
+            }
+
+            obj->i2c->CONTROLC = SDA;
+            i2c_delay(SHIELD_TSU);
+        break;
     }
     return data_receive_byte;
 }
@@ -160,11 +210,13 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj)
 static inline int i2c_receive_ack(i2c_t *obj)
 {
     int nack;
-		int delay_value;
-		switch ((int)obj->i2c) {
-			case I2C_0: delay_value = TSC_TSU; break;
-      case I2C_1: delay_value = AAIC_TSU; break;
-		}
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
 
     i2c_delay(delay_value);
     obj->i2c->CONTROLS = SDA;
@@ -186,13 +238,15 @@ static inline int i2c_receive_ack(i2c_t *obj)
 }
 
 
-static inline void i2c_send_ack(i2c_t *obj) 
+static inline void i2c_send_nack(i2c_t *obj) 
 {
-		int delay_value;
-		switch ((int)obj->i2c) {
-			case I2C_0: delay_value = TSC_TSU; break;
-      case I2C_1: delay_value = AAIC_TSU; break;
-		}
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
 
     i2c_delay(delay_value);
     obj->i2c->CONTROLC = SCL;
@@ -208,10 +262,28 @@ static inline void i2c_send_ack(i2c_t *obj)
 
 }
 
+static inline void i2c_send_ack(i2c_t *obj) 
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
 
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-	
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
 
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
     // determine the SPI to use
     I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
     I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@@ -220,62 +292,76 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
     if ((int)obj->i2c == NC) {
         error("I2C pin mapping failed");
     }
-		
+        
     pinmap_pinout(sda, PinMap_I2C_SDA);
     pinmap_pinout(scl, PinMap_I2C_SCL);
+        
+    switch ((int)obj->i2c) {
+        case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break;
+        case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; 
+                                        CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break;
+    }
+        
+        
 }
 
-int i2c_start(i2c_t *obj) {
-
-		int delay_value;
-		switch ((int)obj->i2c) {
-			case I2C_0: delay_value = TSC_TSU; break;
-      case I2C_1: delay_value = AAIC_TSU; break;
-		}
-				i2c_delay(delay_value);
-				obj->i2c->CONTROLS = SDA | SCL;
-				i2c_delay(delay_value);
-				obj->i2c->CONTROLC = SDA;
-				i2c_delay(delay_value);
-
-
+int i2c_start(i2c_t *obj)
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA | SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
 
     return 0;
 }
 
-int i2c_start_tsc(i2c_t *obj) {
-
-		int delay_value;
-		switch ((int)obj->i2c) {
-			case I2C_0: delay_value = TSC_TSU; break;
-      case I2C_1: delay_value = AAIC_TSU; break;
-		}
-				i2c_delay(delay_value);
-				obj->i2c->CONTROLC = SDA;
-				i2c_delay(delay_value);
-				obj->i2c->CONTROLC = SCL;
-				i2c_delay(delay_value);
+int i2c_start_tsc(i2c_t *obj)
+{
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SCL;
+    i2c_delay(delay_value);
 
     return 0;
 }
 
-int i2c_stop(i2c_t *obj) {
-	
-		int delay_value;
-		switch ((int)obj->i2c) {
-			case I2C_0: delay_value = TSC_TSU; break;
-      case I2C_1: delay_value = AAIC_TSU; break;
-		}
-		// Actual stop bit
-		i2c_delay(delay_value);
-		obj->i2c->CONTROLC = SDA;
-		i2c_delay(delay_value);
-		obj->i2c->CONTROLS = SCL;
-		i2c_delay(delay_value);
-		obj->i2c->CONTROLS = SDA;
-		i2c_delay(delay_value);
+int i2c_stop(i2c_t *obj)
+{    
+    int delay_value;
+    switch ((int)obj->i2c) {
+        case I2C_0: delay_value = TSC_TSU; break;
+        case I2C_1: delay_value = AAIC_TSU; break;
+        case I2C_2: delay_value = SHIELD_TSU; break;
+        case I2C_3: delay_value = SHIELD_TSU; break;
+    }
+    // Actual stop bit
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLC = SDA;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SCL;
+    i2c_delay(delay_value);
+    obj->i2c->CONTROLS = SDA;
+    i2c_delay(delay_value);
 
-		return 0;
+    return 0;
 }
 
 
@@ -283,103 +369,154 @@ int i2c_stop(i2c_t *obj) {
 void i2c_frequency(i2c_t *obj, int hz) {
 }
 
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-		unsigned int loop, rxdata;
-		int delay_value, sadr, ack, bytes_read;
-		rxdata=0;
-		switch ((int)obj->i2c) {
-			case I2C_0: 
-				delay_value = TSC_TSU; 
-				sadr = TSC_I2C_ADDR; 
-				break;
-      case I2C_1: 
-				delay_value = AAIC_TSU; 
-				sadr = AAIC_I2C_ADDR; 
-				break;
-		}
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    unsigned int loop, rxdata;
+    int sadr, ack, bytes_read;
+    rxdata=0;
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            sadr = TSC_I2C_ADDR; 
+            break;
+        case I2C_1: 
+            sadr = AAIC_I2C_ADDR; 
+            break;
+        case I2C_2: 
+        case I2C_3: 
+            sadr = address;     //LM75_I2C_ADDR; or MMA7660_I2C_ADDR;
+            break;
+         }
+    bytes_read = 0;
     // Start bit
-		i2c_start(obj);
+    i2c_start(obj);
 
-    // Set serial and register address
-		i2c_send_byte(obj,sadr);
-		ack += i2c_receive_ack(obj);
-		i2c_send_byte(obj, address);
-		ack += i2c_receive_ack(obj);
+    switch ((int)obj->i2c) {
+        case I2C_0: 
+            // Set serial and register address
+            i2c_send_byte(obj,sadr);
+            ack += i2c_receive_ack(obj);
+            i2c_send_byte(obj, address);
+            ack += i2c_receive_ack(obj);
 
-    // Stop bit
-		i2c_stop(obj);
+            // Stop bit
+            i2c_stop(obj);
 
-    // Start bit
-		i2c_start_tsc(obj);
-		
-    // Read from serial address
-    i2c_send_byte(obj,sadr | 1);
-		ack += i2c_receive_ack(obj);
-		bytes_read = 0;
-		
-		switch ((int)obj->i2c) {
-			case I2C_0: 
-        rxdata = (i2c_receive_byte(obj) & 0xFF);
-				data[((length-1)-bytes_read)] = (char)rxdata;
-				bytes_read++;
-        // Read multiple bytes
-        if ((length > 1) && (length < 5))
-        {
-          for (loop = 1; loop <= (length - 1); loop++)
-          {
-              // Send ACK
-                i2c_delay(delay_value);
-                obj->i2c->CONTROLC = SDA;
-                i2c_delay(delay_value);
-                obj->i2c->CONTROLS = SCL;
-                i2c_delay(delay_value);
-                obj->i2c->CONTROLC = SCL;
-                i2c_delay(delay_value);
-     
-              rxdata = i2c_receive_byte(obj);
-							data[(length-1)-bytes_read] = (char)rxdata;
-							bytes_read++;
-						
-          }
-        }
-        break;
-      case I2C_1:
-        rxdata = i2c_receive_byte(obj);
-				data[bytes_read] = (char)rxdata;
-				bytes_read++;
-    		break;
+            // Start bit
+            i2c_start_tsc(obj);
+
+            // Read from I2C address
+            i2c_send_byte(obj,sadr | 1);
+            ack += i2c_receive_ack(obj);
+
+            rxdata = (i2c_receive_byte(obj) & 0xFF);
+            data[((length-1)-bytes_read)] = (char)rxdata;
+            bytes_read++;
+            // Read multiple bytes
+            if ((length > 1) && (length < 5))
+            {
+                for (loop = 1; loop <= (length - 1); loop++)
+                {
+                    // Send ACK
+                    i2c_send_ack(obj);
+
+                    // Next byte
+                    //rxdata = ((rxdata << 8) & 0xFFFFFF00);
+                    //rxdata |= (i2c_receive_byte(obj) & 0xFF);
+                    rxdata = i2c_receive_byte(obj);
+                    data[(length-1)-bytes_read] = (char)rxdata;
+                    bytes_read++;
+                            
+                }
+            }
+            break;
+        case I2C_1:
+            // Set serial and register address
+            i2c_send_byte(obj,sadr);
+            ack += i2c_receive_ack(obj);
+            i2c_send_byte(obj, address);
+            ack += i2c_receive_ack(obj);
+
+            // Stop bit
+            i2c_stop(obj);
+
+            // Start bit
+            i2c_start_tsc(obj);
+            // Fall through to read data
+        case I2C_2:
+        case I2C_3:
+            // Read from preset register address pointer
+            i2c_send_byte(obj,sadr | 1);
+            ack += i2c_receive_ack(obj);
+
+            rxdata = i2c_receive_byte(obj);
+            data[bytes_read] = (char)rxdata;
+            bytes_read++;
+            // Read multiple bytes
+            if ((length > 1) && (length < 5))
+            {
+                for (loop = 1; loop <= (length - 1); loop++)
+                {
+                    // Send ACK
+                    i2c_send_ack(obj);
+
+                    // Next byte
+                    rxdata = i2c_receive_byte(obj);
+                    data[loop] = (char)rxdata;
+                    bytes_read++;
+                            
+                }
+            }
+            break;
     }
-    i2c_send_ack(obj);
+    i2c_send_nack(obj);  
 
-    // Actual stop bit
-		i2c_stop(obj);
+    i2c_stop(obj);    // Actual stop bit
 
     return bytes_read;
 }
 
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-		int ack=0;
-		int sadr;
-		switch ((int)obj->i2c) {
-			case I2C_0: sadr = TSC_I2C_ADDR; break;
-      case I2C_1: sadr = AAIC_I2C_ADDR; break;
-		}
-		for(int i = 1; i<=length; i++)
-		{
-			i2c_start(obj);
-		
-			// Set serial and register address
-			i2c_send_byte(obj,sadr);
-			ack += i2c_receive_ack(obj);
-			i2c_send_byte(obj, address);
-			ack += i2c_receive_ack(obj);
-			i2c_send_byte(obj, *data);
-			ack += i2c_receive_ack(obj);
-		}
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    int ack=0;
+    int sadr;
+    char * ptr;
+    char addr;
+    ptr = (char*)data;
+    switch ((int)obj->i2c)
+    {
+        case I2C_0: 
+            sadr = TSC_I2C_ADDR;
+            addr = address;
+            break;
+        case I2C_1: 
+            sadr = AAIC_I2C_ADDR; 
+            addr = address;
+            break;
+        case I2C_2: 
+        case I2C_3: 
+            sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR;
+            addr = *ptr++;
+            break;
+     }
+    
+//    printf("adr = %x, reg = %x\n",sadr, address);
+    i2c_start(obj);
 
-		i2c_stop(obj);
-		if(ack==3) { return 1; }
-		else{ return 0; }
+    // Set serial and register address
+    i2c_send_byte(obj,sadr);
+    ack += i2c_receive_ack(obj);
+    i2c_send_byte(obj, addr);
+    ack += i2c_receive_ack(obj);
+
+    for(int i = 1; i<length; i++)
+    {
+        i2c_send_byte(obj, *ptr++);
+        ack += i2c_receive_ack(obj);
+    }
+
+    i2c_stop(obj);
+    if(ack==3) { return 1; }
+    else{ return 0; }
 
 }
 
@@ -399,15 +536,15 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
 }
 
 int i2c_slave_receive(i2c_t *obj) {
-	return 0;
+    return 0;
 }
 
 int i2c_slave_read(i2c_t *obj, char *data, int length) {
-	return 0;
+    return 0;
 }
 
 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-	return 0;
+    return 0;
 }
 
 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h
index 6aa9a111fa..b7653f86b4 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h
@@ -31,7 +31,7 @@ struct gpio_irq_s {
 
 struct port_s {
     __IO uint32_t *reg_dir;
-		__IO uint32_t *reg_dirclr;
+        __IO uint32_t *reg_dirclr;
     __IO uint32_t *reg_out;
     __IO  uint32_t *reg_in;
     PortName port;
@@ -53,7 +53,7 @@ struct tsc_s {
 
 struct audio_s {
     MPS2_I2S_TypeDef *audio_I2S;
-		MPS2_I2C_TypeDef *audio_I2C;
+        MPS2_I2C_TypeDef *audio_I2C;
 };
 
 
@@ -65,6 +65,14 @@ struct clcd_s {
     MPS2_SSP_TypeDef *clcd;
 };
 
+struct analogin_s {
+    ADCName adc;
+        MPS2_SSP_TypeDef *adc_spi;
+    PinName  pin;
+        uint32_t pin_number;
+    __IO uint32_t address;
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c
index b71b511b64..1e0bbc6143 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c
@@ -19,10 +19,10 @@
 
 
 void pin_function(PinName pin, int function) {
-	    MBED_ASSERT(pin != (PinName)NC);
+        MBED_ASSERT(pin != (PinName)NC);
 
 }
 
 void pin_mode(PinName pin, PinMode mode) {
-	    MBED_ASSERT(pin != (PinName)NC);
+        MBED_ASSERT(pin != (PinName)NC);
 }
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c
index eba797338d..fc2625c9c1 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c
@@ -30,18 +30,22 @@
  ******************************************************************************/
 
 static const PinMap PinMap_UART_TX[] = {
-    {USBTX	 , UART_0, 0},
-    {UART_TX1, UART_1, 0},
+    {USBTX     , UART_0, 0},
+    {XB_TX   , UART_1, 0},
+    {SH0_TX  , UART_2, 0},
+    {SH1_TX  , UART_3, 0},
     {NC      , NC    , 0}
 };
 
 static const PinMap PinMap_UART_RX[] = {
-    {USBRX	 , UART_0, 0},
-    {UART_RX1, UART_1, 0},
-    {NC , NC      , 0}
+    {USBRX     , UART_0, 0},
+    {XB_RX   , UART_1, 0},
+    {SH0_RX  , UART_2, 0},
+    {SH1_RX  , UART_3, 0},
+    {NC      , NC    , 0}
 };
 
-#define UART_NUM    3
+#define UART_NUM    4
 
 static uart_irq_handler irq_handler;
 
@@ -69,13 +73,73 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
     
     obj->uart = (CMSDK_UART_TypeDef *)uart;
     //set baud rate and enable Uart in normarl mode (RX and TX enabled)
-    switch (uart) {
-        case UART_0: 	CMSDK_UART0->CTRL = 0;         // Disable UART when changing configuration 
-											CMSDK_UART0->CTRL    = 0x3;  // Normal mode 
-											break;
-        case UART_1: 	CMSDK_UART1->CTRL = 0;         // Disable UART when changing configuration 
-											CMSDK_UART1->CTRL    = 0x3;  // Normal mode 
-											break;
+    switch (uart)
+    {
+        case UART_0:
+        {
+          CMSDK_UART0->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)uart_tx != NC)
+          {
+            CMSDK_UART0->CTRL |= 0x01;  // TX enable 
+          } else {
+            CMSDK_UART0->CTRL &= 0xFFFE;  // TX disable
+          } 
+          
+          
+          if((int)uart_rx != NC)
+          {
+            CMSDK_UART0->CTRL |= 0x02;  // RX enable  
+          } else {
+            CMSDK_UART0->CTRL &= 0xFFFD;  // RX disable
+          } 
+
+        }
+        break;
+        case UART_1:     //XBEE SOCKET UART
+                {
+          CMSDK_UART1->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART1->CTRL = 0x1;   // TX enable 
+             CMSDK_GPIO1->ALTFUNCSET |= 0x0100;
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART1->CTRL |= 0x2;  // RX enable
+            CMSDK_GPIO1->ALTFUNCSET |= 0x0080;
+          } 
+        }
+        break;
+        case UART_2:     //Sheild0 UART
+        {     
+          CMSDK_UART3->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART3->CTRL = 0x1;   // TX enable 
+            CMSDK_GPIO0->ALTFUNCSET |= 0x0010;
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART3->CTRL |= 0x2;  // RX enable 
+            CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
+          }
+        } 
+        break;
+        case UART_3:     //Sheild1 UART
+        {
+          CMSDK_UART4->CTRL = 0x00;    // Disable UART when changing configuration
+          if((int)tx != NC)
+          {
+            CMSDK_UART4->CTRL = 0x1;   // TX enable 
+             CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
+          }
+          if((int)rx != NC)
+          {
+            CMSDK_UART4->CTRL |= 0x2;  // RX enable 
+            CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
+          }
+        }
+        break;
     }
 
     // set default baud rate and format
@@ -88,6 +152,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
     switch (uart) {
         case UART_0: obj->index = 0; break;
         case UART_1: obj->index = 1; break;
+        case UART_2: obj->index = 2; break;
+        case UART_3: obj->index = 3; break;
     }
     uart_data[obj->index].sw_rts.pin = NC;
     uart_data[obj->index].sw_cts.pin = NC;
@@ -102,6 +168,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
 }
 
 void serial_free(serial_t *obj) {
+      uart_data[obj->index].serial_irq_id = 0;
 }
 
 // serial_baud
@@ -110,24 +177,26 @@ void serial_baud(serial_t *obj, int baudrate) {
     // The MPS2 has a simple divider to control the baud rate. The formula is:
     //
     // Baudrate = PCLK / BAUDDIV
-		//
-		// PCLK = 25 Mhz
-		// so for a desired baud rate of 9600 
-		//  25000000 / 9600 = 2604
+        //
+        // PCLK = 25 Mhz
+        // so for a desired baud rate of 9600
+        //  25000000 / 9600 = 2604
     //
-	//check to see if minimum baud value entered
-	int baudrate_div = 0;
-	baudrate_div = 25000000 / baudrate;
-	if(baudrate >= 16){
+    //check to see if minimum baud value entered
+    int baudrate_div = 0;
+    baudrate_div = SystemCoreClock / baudrate;
+    if(baudrate >= 16){
     switch ((int)obj->uart) {
         case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break;
         case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break;
+        case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break;
+        case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break;
         default: error("serial_baud"); break;
     }
-	} else {
-		error("serial_baud");
-	}
-    
+    } else {
+        error("serial_baud");
+    }
+
 }
 
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
@@ -138,24 +207,58 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
  ******************************************************************************/
 static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) {
     SerialIrq irq_type;
-    switch (intstatus) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
+    switch (intstatus)
+    {
+        case 1:
+        {
+            irq_type = TxIrq;
+        }
+        break;
+
+        case 2:
+        {
+            irq_type = RxIrq;
+        }
+        break;
+
         default: return;
-    }
-    if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
+    }   /* End of Switch */
+
+    if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) 
+    {
         gpio_write(&uart_data[index].sw_rts, 1);
         // Disable interrupt if it wasn't enabled by other part of the application
         if (!uart_data[index].rx_irq_set_api)
-            puart->CTRL &= ~(1 << RxIrq);
+        {
+            /* Disable Rx interrupt */
+            puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
+        }
     }
+
     if (uart_data[index].serial_irq_id != 0)
+    {
         if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
+        {
             irq_handler(uart_data[index].serial_irq_id, irq_type);
+        }
+    }
+
+    if( irq_type == TxIrq )
+    {
+        /* Clear the TX interrupt Flag */
+        puart->INTCLEAR |= 0x01;
+    }
+    else
+    {
+        /* Clear the Rx interupt Flag */
+        puart->INTCLEAR |= 0x02;
+    }
 }
 
 void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);}
 void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);}
+void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);}
+void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);}
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
     irq_handler = handler;
@@ -163,30 +266,66 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
 }
 
 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    /* Declare a variable of type IRQn, initialise to 0  */
     IRQn_Type irq_n = (IRQn_Type)0;
     uint32_t vector = 0;
-    switch ((int)obj->uart) {
-		case UART_0: irq_n=((irq>> 2) ? UARTRX0_IRQn : UARTTX0_IRQn); vector = (uint32_t)&uart0_irq; break;
-		case UART_1: irq_n=((irq>> 2) ? UARTRX1_IRQn : UARTTX1_IRQn); vector = (uint32_t)&uart1_irq; break;
+    switch ((int)obj->uart)
+        {
+            case UART_0:
+            {
+                irq_n   = (( irq == TxIrq ) ?  UARTTX0_IRQn : UARTRX0_IRQn);
+                vector  = (uint32_t)&uart0_irq;
+            }
+            break;
+
+            case UART_1:
+            {
+                irq_n   = (( irq == TxIrq ) ?  UARTTX1_IRQn : UARTRX1_IRQn);
+                vector  = (uint32_t)&uart1_irq;
+            }
+            break;
+            case UART_2:
+            {
+                irq_n   = (( irq == TxIrq ) ?  UARTTX3_IRQn : UARTRX3_IRQn);
+                vector  = (uint32_t)&uart2_irq;
+            }
+            break;
+            case UART_3:
+            {
+                irq_n   = (( irq == TxIrq ) ?  UARTTX4_IRQn : UARTRX4_IRQn);
+            vector  = (uint32_t)&uart3_irq;
+            }
+            break;
     }
-    
-    if (enable) {
-        obj->uart->CTRL |= 1 << irq;
+
+    if (enable)
+    {
+        if( irq == TxIrq )
+        {
+            /* Transmit IRQ, set appripriate enable */
+
+            /* set TX interrupt enable in CTRL REG */
+            obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
+        }
+        else
+        {
+            /* set Rx interrupt on in CTRL REG */
+            obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
+        }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
-    } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->CTRL &= ~(1 << irq);
-        all_disabled = (obj->uart->CTRL & (1 << other_irq)) == 0;
-        if (all_disabled)
+
+    }
+    else 
+    {   /*      Disable   IRQ   */
+        
+        obj->uart->CTRL &= ~(1 << (irq + 2));
+
             NVIC_DisableIRQ(irq_n);
     }
 }
 
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    if (RxIrq == irq)
-        uart_data[obj->index].rx_irq_set_api = enable;
     serial_irq_set_internal(obj, irq, enable);
 }
 
@@ -205,11 +344,11 @@ void serial_putc(serial_t *obj, int c) {
 }
 
 int serial_readable(serial_t *obj) {
-    return obj->uart->STATE & 2;
+    return obj->uart->STATE & 0x2;
 }
 
 int serial_writable(serial_t *obj) {
-		return obj->uart->STATE & 1;
+    return obj->uart->STATE & 0x1;
 }
 
 void serial_clear(serial_t *obj) {
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c
index 4f83ceac4c..9aaf23bfe6 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c
@@ -25,24 +25,36 @@
 static const PinMap PinMap_SPI_SCLK[] = {
     {SCLK_SPI , SPI_0, 0},
     {CLCD_SCLK , SPI_1, 0},
+    {ADC_SCLK , SPI_2, 0},
+    {SHIELD_0_SPI_SCK , SPI_3, 0},
+    {SHIELD_1_SPI_SCK , SPI_4, 0},
     {NC   , NC   , 0}
 };
 
 static const PinMap PinMap_SPI_MOSI[] = {
     {MOSI_SPI, SPI_0, 0},
     {CLCD_MOSI, SPI_1, 0},
+    {ADC_MOSI, SPI_2, 0},
+    {SHIELD_0_SPI_MOSI, SPI_3, 0},
+    {SHIELD_1_SPI_MOSI, SPI_4, 0},
     {NC   , NC   , 0}
 };
 
 static const PinMap PinMap_SPI_MISO[] = {
     {MISO_SPI, SPI_0, 0},
     {CLCD_MISO, SPI_1, 0},
+    {ADC_MISO, SPI_2, 0},
+    {SHIELD_0_SPI_MISO, SPI_3, 0},
+    {SHIELD_1_SPI_MISO, SPI_4, 0},
     {NC   , NC   , 0}
 };
 
 static const PinMap PinMap_SPI_SSEL[] = {
     {SSEL_SPI, SPI_0, 0},
     {CLCD_SSEL, SPI_1, 0},
+    {ADC_SSEL, SPI_2, 0},
+    {SHIELD_0_SPI_nCS, SPI_3, 0},
+    {SHIELD_1_SPI_nCS, SPI_4, 0},
     {NC   , NC   , 0}
 };
 
@@ -50,7 +62,9 @@ static inline int ssp_disable(spi_t *obj);
 static inline int ssp_enable(spi_t *obj);
 
 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
+    
+        int altfunction[4];
+        // determine the SPI to use
     SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
     SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
     SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
@@ -64,33 +78,78 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     
     // enable power and clocking
     switch ((int)obj->spi) {
-        case (int)SPI_0: 
-			obj->spi->CR1   	= 0;
-			obj->spi->CR0   	= SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
-			obj->spi->CPSR  	= SSP_CPSR_DFLT; 
-			obj->spi->IMSC  	= 0x8; 
-			obj->spi->DMACR 	= 0;
-			obj->spi->CR1   	= SSP_CR1_SSE_Msk;
-			obj->spi->ICR   	= 0x3;  
-			break;
+      case (int)SPI_0: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
       case (int)SPI_1:
-					  /* Configure SSP used for LCD                                               */
-			obj->spi->CR1   =   0;                 /* Synchronous serial port disable  */
-			obj->spi->DMACR =   0;                 /* Disable FIFO DMA                 */
-			obj->spi->IMSC  =   0;                 /* Mask all FIFO/IRQ interrupts     */
-			obj->spi->ICR   = ((1ul <<  0) |       /* Clear SSPRORINTR interrupt       */
-								(1ul <<  1) );      /* Clear SSPRTINTR interrupt        */
-          	obj->spi->CR0   = ((7ul <<  0) |       /* 8 bit data size                  */
-								(0ul <<  4) |       /* Motorola frame format            */
-								(0ul <<  6) |       /* CPOL = 0                         */
-								(0ul <<  7) |       /* CPHA = 0                         */
-								(1ul <<  8) );      /* Set serial clock rate            */
-			obj->spi->CPSR  =  (2ul <<  0);        /* set SSP clk to 6MHz (6.6MHz max) */
-			obj->spi->CR1   = ((1ul <<  1) |       /* Synchronous serial port enable   */
-								(0ul <<  2) );      /* Device configured as master      */
-			break;
+                      /* Configure SSP used for LCD                                               */
+            obj->spi->CR1   =   0;                 /* Synchronous serial port disable  */
+            obj->spi->DMACR =   0;                 /* Disable FIFO DMA                 */
+            obj->spi->IMSC  =   0;                 /* Mask all FIFO/IRQ interrupts     */
+            obj->spi->ICR   = ((1ul <<  0) |       /* Clear SSPRORINTR interrupt       */
+                                (1ul <<  1) );      /* Clear SSPRTINTR interrupt        */
+              obj->spi->CR0   = ((7ul <<  0) |       /* 8 bit data size                  */
+                                (0ul <<  4) |       /* Motorola frame format            */
+                                (0ul <<  6) |       /* CPOL = 0                         */
+                                (0ul <<  7) |       /* CPHA = 0                         */
+                                (1ul <<  8) );      /* Set serial clock rate            */
+            obj->spi->CPSR  =  (2ul <<  0);        /* set SSP clk to 6MHz (6.6MHz max) */
+            obj->spi->CR1   = ((1ul <<  1) |       /* Synchronous serial port enable   */
+                                (0ul <<  2) );      /* Device configured as master      */
+            break;
+      case (int)SPI_2: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+      case (int)SPI_3: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
+      case (int)SPI_4: 
+            obj->spi->CR1       = 0;
+            obj->spi->CR0       = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+            obj->spi->CPSR      = SSP_CPSR_DFLT; 
+            obj->spi->IMSC      = 0x8; 
+            obj->spi->DMACR     = 0;
+            obj->spi->CR1       = SSP_CR1_SSE_Msk;
+            obj->spi->ICR       = 0x3;  
+            break;
     }
     
+        if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
+        if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
+        if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
+        if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
+        
+    // enable alt function
+    switch ((int)obj->spi) {
+      case (int)SPI_2:
+                CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]);
+            break;
+      case (int)SPI_3:
+                CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11);
+            break;
+      case (int)SPI_4:
+                CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6);
+            break;
+        }
+        
     // set default format and frequency
     if (ssel == NC) {
         spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
@@ -151,7 +210,7 @@ void spi_frequency(spi_t *obj, int hz) {
    
     uint32_t PCLK = SystemCoreClock;
     
-	    int prescaler;
+        int prescaler;
     
     for (prescaler = 2; prescaler <= 254; prescaler += 2) {
         int prescale_hz = PCLK / prescaler;
@@ -195,7 +254,7 @@ static inline void ssp_write(spi_t *obj, int value) {
     while (ssp_writeable(obj));
 }
 static inline int ssp_read(spi_t *obj) {
-	int read_DR = obj->spi->DR;
+    int read_DR = obj->spi->DR;
     return read_DR;
 }
 
@@ -205,7 +264,7 @@ static inline int ssp_busy(spi_t *obj) {
 
 int spi_master_write(spi_t *obj, int value) {
     ssp_write(obj, value);
-    while (MPS2_SSP0->SR & SSP_SR_BSY_Msk);  /* Wait for send to finish      */
+    while (obj->spi->SR & SSP_SR_BSY_Msk);  /* Wait for send to finish      */
     return (ssp_read(obj));
 }
 
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c
index 0de4335b91..66fd616d8d 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c
@@ -19,7 +19,7 @@
 
 #define US_TICKER_TIMER1      CMSDK_DUALTIMER1
 #define US_TICKER_TIMER2      CMSDK_DUALTIMER2
-#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn
+#define US_TICKER_TIMER_IRQn  DUALTIMER_IRQn
 
 int us_ticker_inited = 0;
 
@@ -29,9 +29,9 @@ void us_ticker_init(void) {
     
     US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
     US_TICKER_TIMER2->TimerControl = 0x00; // disable timer
-	US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
-	US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
-	
+    US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
+    US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
+    
     US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
     US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter
     
@@ -47,11 +47,10 @@ uint32_t return_value = 0;
     if (!us_ticker_inited)
         us_ticker_init();
     return_value = ((~US_TICKER_TIMER2->TimerValue)/25);
-	return return_value;
+    return return_value;
 }
 
 void us_ticker_set_interrupt(timestamp_t timestamp) {
-uint32_t timer_value = 0;
 int delta = 0;
     if (!us_ticker_inited)
         us_ticker_init();
@@ -61,24 +60,23 @@ int delta = 0;
         us_ticker_irq_handler();
         return;
     }
-		timer_value = (delta)*25;
-		// enable interrupt
+        // enable interrupt
     US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
     US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
-	US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value
-	US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
+    US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value
+    US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
 }
 
 void us_ticker_disable_interrupt(void) {
     
-	US_TICKER_TIMER1->TimerControl &= 0xDF;
-	US_TICKER_TIMER2->TimerControl &= 0xDF;
+    US_TICKER_TIMER1->TimerControl &= 0xDF;
+    US_TICKER_TIMER2->TimerControl &= 0xDF;
 
 }
 
 void us_ticker_clear_interrupt(void) {
 
-	US_TICKER_TIMER1->TimerIntClr = 0x1;
-	US_TICKER_TIMER2->TimerIntClr = 0x1;
+    US_TICKER_TIMER1->TimerIntClr = 0x1;
+    US_TICKER_TIMER2->TimerIntClr = 0x1;
 
 }
diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index d402812bb3..d18f457770 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -153,6 +153,12 @@ class Uvision4(Exporter):
         'SAMD21J18A',
         'SAMD21G18A',
         'SAML21J18A',
+        'ARM_IOTSS_BEID',
+        'ARM_MPS2_M0',
+        'ARM_MPS2_M0P',
+        'ARM_MPS2_M3',
+        'ARM_MPS2_M4',
+        'ARM_MPS2_M7',
     ]
 
     FILE_TYPES = {
diff --git a/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl b/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl
new file mode 100644
index 0000000000..a42d20f13a
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 BEID</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl b/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl
new file mode 100644
index 0000000000..e5642db411
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 BEID</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M3</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M3") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_BEID.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl
new file mode 100644
index 0000000000..deee830189
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 M0</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m0.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0.uvproj.tmpl
new file mode 100644
index 0000000000..32da679116
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m0.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 M0</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M0</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M0") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_CM0.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm0>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm0>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m0p.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0p.uvopt.tmpl
new file mode 100644
index 0000000000..1bd0cb2076
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m0p.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 M0P</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM0P</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM0P</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl
new file mode 100644
index 0000000000..f6e934b05f
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 M0P</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M0P</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M0P") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_CM0P.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0P</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0P</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0P"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm0p>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm0p>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl
new file mode 100644
index 0000000000..b5a0fe5dbb
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 M3</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m3.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m3.uvproj.tmpl
new file mode 100644
index 0000000000..4d874dcd82
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m3.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 M3</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M3</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M3") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_CM3.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m4.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m4.uvopt.tmpl
new file mode 100644
index 0000000000..153f486d57
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m4.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 M4</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m4.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m4.uvproj.tmpl
new file mode 100644
index 0000000000..efd8d1f6ac
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m4.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 M4</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M4</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M4") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_CM4.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl
new file mode 100644
index 0000000000..6504d2f403
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ARM MPS2 M7</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>0</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>1</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl
new file mode 100644
index 0000000000..cfb747e235
--- /dev/null
+++ b/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ARM MPS2 M7</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M7</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M7") CLOCK(25000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>5125</DeviceId>
+          <RegisterFile>CMSDK_CM7.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm7>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            --entry=Reset_Handler
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py
index 1d99f6e945..bcfe1d7340 100644
--- a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py
+++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py
@@ -129,16 +129,16 @@ class HostTestPluginCopyMethod_MPS2(HostTestPluginBase):
             """ Add a delay in case there a test just finished
                 Prevents interface firmware hiccups
             """
-            sleep(10)
+            sleep(20)
             if capabilitity == 'mps2-copy' and self.copy_file(file, disk):
-                sleep(1)
+                sleep(3)
                 if self.touch_file(disk + 'reboot.txt'):
                     """ Add a delay after the board was rebooted.
                         The actual reboot time is 20 seconds, but using 15 seconds
                         allows us to open the COM port and save a board reset.
                         This also prevents interface firmware hiccups.
                     """
-                    sleep(16)
+                    sleep(7)
                     result = True
                     
         return result
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index d0f20933c2..e2c135891a 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -1739,24 +1739,24 @@ class ARM_MPS2_M4(ARM_MPS2_Target):
 class ARM_MPS2_M7(ARM_MPS2_Target):
     def __init__(self):
         ARM_MPS2_Target.__init__(self)
-        self.core = "Cortex-M4F"
+        self.core = "Cortex-M7"
         self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M7']
         self.macros = ['CMSDK_CM7']
         self.supported_toolchains = ["ARM"]
         self.default_toolchain = "ARM"
-
-class ARM_MPS2_BEID(ARM_MPS2_Target):
+        
+class ARM_IOTSS_Target(Target):
     def __init__(self):
-        ARM_MPS2_Target.__init__(self)
+        Target.__init__(self)
+class ARM_IOTSS_BEID(ARM_IOTSS_Target):
+    def __init__(self):
+        ARM_IOTSS_Target.__init__(self)
         self.core = "Cortex-M3"
-        self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_BEID']
+        self.extra_labels = ['ARM_SSG', 'IOTSS', 'IOTSS_BEID']
         self.macros = ['CMSDK_BEID']
         self.supported_toolchains = ["ARM"]
         self.default_toolchain = "ARM"
 
-class ARM_MPS2(ARM_MPS2_M4):
-    pass
-
 
 ### Renesas ###
 
@@ -2091,8 +2091,8 @@ TARGETS = [
     ARM_MPS2_M3(),
     ARM_MPS2_M4(),
     ARM_MPS2_M7(),
-    ARM_MPS2_BEID(),
-    ARM_MPS2(),
+
+    ARM_IOTSS_BEID(),
 
     ### Renesas ###
     RZ_A1H(),

From cd524f3d4379512f2c671644db718dc9ee9aceac Mon Sep 17 00:00:00 2001
From: Peter Conheeney <Peter.Conheeney@arm.com>
Date: Mon, 29 Feb 2016 12:23:05 +0000
Subject: [PATCH 59/78] removed empty functions

---
 .../hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c | 19 -------------------
 .../hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c  | 19 -------------------
 2 files changed, 38 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
index dabc3ac33c..fba6a003ab 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c
@@ -521,22 +521,3 @@ int i2c_byte_read(i2c_t *obj, int last) {
 int i2c_byte_write(i2c_t *obj, int data) {
     return 0;
 }
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    return 0;
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    return 0;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    return 0;
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-}
-
diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
index f2c979ed4f..74d4f0190b 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c
@@ -531,22 +531,3 @@ int i2c_byte_read(i2c_t *obj, int last) {
 int i2c_byte_write(i2c_t *obj, int data) {
     return 0;
 }
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    return 0;
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    return 0;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    return 0;
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-}
-

From 052f23a70a352dc4494c9d74129f0153eaa84039 Mon Sep 17 00:00:00 2001
From: bcostm <bco.stm@gmail.com>
Date: Mon, 29 Feb 2016 16:21:24 +0100
Subject: [PATCH 60/78] Add  STM32L073RZ device

---
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h  | 2 +-
 libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
index 3fe584ae10..23697efa1e 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
@@ -274,7 +274,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
 #elif defined(TARGET_STM32F410RB)
 #define INITIAL_SP            (0x20008000UL)
 
-#elif defined(TARGET_STM32F103RB)
+#elif defined(TARGET_STM32F103RB) || defined(TARGET_STM32L073RZ)
 #define INITIAL_SP            (0x20005000UL)
 
 #elif defined(TARGET_STM32F302R8)
diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
index 70ac3c2f16..9dbbd49432 100755
--- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
+++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
@@ -57,7 +57,7 @@
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL26Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
    || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \
-   || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
+   || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
    || defined(TARGET_SSCI824)  || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
 #    define OS_TASKCNT         6
 #  else
@@ -77,7 +77,7 @@
    || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
    || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
 #      define OS_SCHEDULERSTKSIZE    128
-#  elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) ||  defined(TARGET_STM32F303K8) ||  defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8)
+#  elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) ||  defined(TARGET_STM32F303K8) ||  defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ)
 #      define OS_SCHEDULERSTKSIZE    112
 #  else
 #    error "no target defined"
@@ -172,7 +172,7 @@
 #elif defined(TARGET_STM32F302R8)
 #    define OS_CLOCK       72000000
 
-#elif defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8)
+#elif defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ)
 #    define OS_CLOCK       32000000
 
 #elif defined(TARGET_STM32F401VC)

From a36d49aacc6e02c5b63d01ce65f79592fe63ffcd Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Fri, 26 Feb 2016 11:51:35 -0600
Subject: [PATCH 61/78] Adding NOT_SUPPORTED errors to tests

---
 libraries/tests/mbed/analog/main.cpp             |  8 ++++++++
 libraries/tests/mbed/analog_pot/main.cpp         |  8 ++++++--
 libraries/tests/mbed/bus/main.cpp                | 11 +++++++----
 libraries/tests/mbed/can/main.cpp                |  4 ++++
 libraries/tests/mbed/can_interrupt/main.cpp      |  4 ++++
 libraries/tests/mbed/can_loopback/main.cpp       |  4 ++++
 libraries/tests/mbed/dir/main.cpp                |  4 ++++
 libraries/tests/mbed/freopen/main.cpp            |  4 ++++
 libraries/tests/mbed/i2c_master/main.cpp         |  4 ++++
 libraries/tests/mbed/i2c_slave/main.cpp          |  4 ++++
 libraries/tests/mbed/interrupt_chaining/main.cpp |  2 +-
 libraries/tests/mbed/portout/main.cpp            | 12 +++++++++---
 libraries/tests/mbed/pwm/main.cpp                | 16 ++++++++--------
 libraries/tests/mbed/pwm_led/pwm.cpp             |  4 ++--
 libraries/tests/mbed/reset/main.cpp              |  4 ++++
 libraries/tests/mbed/spi/main.cpp                |  4 ++++
 libraries/tests/mbed/spi_master/main.cpp         |  4 ++++
 libraries/tests/mbed/spi_slave/main.cpp          |  4 ++++
 libraries/tests/mbed/stdio_benchmark/main.cpp    |  4 ++++
 19 files changed, 89 insertions(+), 20 deletions(-)

diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp
index b35095c573..8d5316bbe7 100644
--- a/libraries/tests/mbed/analog/main.cpp
+++ b/libraries/tests/mbed/analog/main.cpp
@@ -1,3 +1,11 @@
+#if !DEVICE_ANALOGIN
+  #error [NOT_SUPPORTED] AnalogIn not supported
+#endif
+
+#if !DEVICE_ANALOGOUT
+  #error [NOT_SUPPORTED] AnalogOut not supported
+#endif
+
 #include "test_env.h"
 
 #if defined(TARGET_K64F) | defined (TARGET_K22F)
diff --git a/libraries/tests/mbed/analog_pot/main.cpp b/libraries/tests/mbed/analog_pot/main.cpp
index 2f64bcbb6e..2b141cd45e 100644
--- a/libraries/tests/mbed/analog_pot/main.cpp
+++ b/libraries/tests/mbed/analog_pot/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_ANALOGIN
+  #error [NOT_SUPPORTED] AnalogIn not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
@@ -15,11 +19,11 @@ int main(void) {
 
     bool result = false;
     float val1, val2;
-    
+
     for (int i = 0; i < TEST_ITERATIONS; i++) {
         val1 = pot1.read();
         val2 = pot2.read();
-        
+
         const char *succes_str = val1 > MEASURE_MIN || val2 > MEASURE_MIN ? "[OK]" : "[FAIL]";
         result = result || (val1 > MEASURE_MIN || val2 > MEASURE_MIN);
         printf("Pot values %f, %f\r\n", val1, val2);
diff --git a/libraries/tests/mbed/bus/main.cpp b/libraries/tests/mbed/bus/main.cpp
index 0faa0990a9..b10669e856 100644
--- a/libraries/tests/mbed/bus/main.cpp
+++ b/libraries/tests/mbed/bus/main.cpp
@@ -13,23 +13,26 @@ BusOut bus2(PB03, PB22, PB02, PB23);
 BusOut bus1(PA02, PA03, PA04, PA05, PA06, PA07, PA08, PA09, PA10, PA11, PA16, PA17);
 BusOut bus2(PB10, PB11, PB12, PB13);
 
-#else
+#elif defined(TARGET_FF_ARDUINO)
 BusOut bus1(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15);
 BusOut bus2(A5, A4, A3, A2, A1, A0);
 
+#else
+#error [NOT_SUPPORTED] This test is not supported on this target
+
 #endif
 
 int i;
- 
+
 int main()
 {
     notify_start();
-    
+
     for (i=0; i<=65535; i++) {
         bus1 = i;
         bus2 = i;
         wait(0.0001);
     }
-    
+
     notify_completion(true);
 }
\ No newline at end of file
diff --git a/libraries/tests/mbed/can/main.cpp b/libraries/tests/mbed/can/main.cpp
index 56ebc1f694..2fd716d106 100644
--- a/libraries/tests/mbed/can/main.cpp
+++ b/libraries/tests/mbed/can/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_CAN
+  #error [NOT_SUPPORTED] CAN not supported
+#endif
+
 #include "mbed.h"
 
 Ticker ticker;
diff --git a/libraries/tests/mbed/can_interrupt/main.cpp b/libraries/tests/mbed/can_interrupt/main.cpp
index 17d129a46b..7356bece14 100644
--- a/libraries/tests/mbed/can_interrupt/main.cpp
+++ b/libraries/tests/mbed/can_interrupt/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_CAN
+  #error [NOT_SUPPORTED] CAN not supported
+#endif
+
 #include "mbed.h"
 
 Ticker ticker;
diff --git a/libraries/tests/mbed/can_loopback/main.cpp b/libraries/tests/mbed/can_loopback/main.cpp
index cf786597c9..90664ec57b 100644
--- a/libraries/tests/mbed/can_loopback/main.cpp
+++ b/libraries/tests/mbed/can_loopback/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_CAN
+  #error [NOT_SUPPORTED] CAN not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
diff --git a/libraries/tests/mbed/dir/main.cpp b/libraries/tests/mbed/dir/main.cpp
index feb3241057..500de36e9f 100644
--- a/libraries/tests/mbed/dir/main.cpp
+++ b/libraries/tests/mbed/dir/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_LOCALFILESYSTEM
+  #error [NOT_SUPPORTED] LocalFileSystem not supported
+#endif
+
 #include "mbed.h"
 
 void led_blink(PinName led) {
diff --git a/libraries/tests/mbed/freopen/main.cpp b/libraries/tests/mbed/freopen/main.cpp
index 145a684a7e..3436b54482 100644
--- a/libraries/tests/mbed/freopen/main.cpp
+++ b/libraries/tests/mbed/freopen/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_LOCALFILESYSTEM
+  #error [NOT_SUPPORTED] LocalFileSystem not supported
+#endif
+
 #include "mbed.h"
 #include "TextLCD.h"
 
diff --git a/libraries/tests/mbed/i2c_master/main.cpp b/libraries/tests/mbed/i2c_master/main.cpp
index baac46e66c..67f23acb2c 100644
--- a/libraries/tests/mbed/i2c_master/main.cpp
+++ b/libraries/tests/mbed/i2c_master/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_I2C
+  #error [NOT_SUPPORTED] I2C is not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
diff --git a/libraries/tests/mbed/i2c_slave/main.cpp b/libraries/tests/mbed/i2c_slave/main.cpp
index 5553a28975..7b168b7dde 100644
--- a/libraries/tests/mbed/i2c_slave/main.cpp
+++ b/libraries/tests/mbed/i2c_slave/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_I2CSLAVE
+  #error [NOT_SUPPORTED] I2C Slave is not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
diff --git a/libraries/tests/mbed/interrupt_chaining/main.cpp b/libraries/tests/mbed/interrupt_chaining/main.cpp
index ef5d848836..8a41b9527a 100644
--- a/libraries/tests/mbed/interrupt_chaining/main.cpp
+++ b/libraries/tests/mbed/interrupt_chaining/main.cpp
@@ -16,7 +16,7 @@
 #elif defined(TARGET_SAML21J18A)
 #define TIMER_IRQ       TC0_IRQn
 #else
-#error This test can't run on this target.
+#error [NOT_SUPPORTED] This test can't run on this target.
 #endif
 
 Serial pc(USBTX, USBRX);
diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp
index 3b106c98d6..dbf1f78d23 100644
--- a/libraries/tests/mbed/portout/main.cpp
+++ b/libraries/tests/mbed/portout/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_PORTOUT
+  #error [NOT_SUPPORTED] PortOut is not supported
+#endif
+
 #include "mbed.h"
 
 # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC2460)
@@ -27,8 +31,8 @@
 # elif defined(TARGET_SAMR21G18A)
 #     define LED_PORT   PortA
 #     define LED1       (1 <<  19) /*PA19*/
-#     define LED2       0 
-#     define LED3       0 
+#     define LED2       0
+#     define LED3       0
 #     define LED4       0
 # elif defined(TARGET_SAMD21J18A)
 #     define LED_PORT   PortB
@@ -48,7 +52,9 @@
 #     define LED2       0
 #     define LED3       0
 #     define LED4       0
-# endif
+# else
+  #error [NOT_SUPPORTED] This test can't be ran on this target
+#endif
 
 
 #define LED_MASK    (LED1|LED2|LED3|LED4)
diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp
index 2e5754f790..ebfa0ca57a 100644
--- a/libraries/tests/mbed/pwm/main.cpp
+++ b/libraries/tests/mbed/pwm/main.cpp
@@ -48,7 +48,7 @@ int main() {
     printf("Initialize PWM on pin 24 with duty cycle: %.2f\n", pwm_dp24.read());
     printf("Initialize PWM on pin 18 with duty cycle: %.2f\n", pwm_dp18.read());
 
-#elif defined(TARGET_nRF51822)
+#elif defined(TARGET_NRF51822)
     PwmOut pwm_p24(p24);
     PwmOut pwm_p25(p25);
 
@@ -100,7 +100,7 @@ int main() {
 
     pwm_1.write(value);
     pwm_2.write(0.50);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -111,7 +111,7 @@ int main() {
     PwmOut pwm_1(PA_0);
 
     pwm_1.write(value);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -121,7 +121,7 @@ int main() {
     PwmOut pwm_1(PA_0);
 
     pwm_1.write(value);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -131,7 +131,7 @@ int main() {
     PwmOut pwm_1(PA_0);
 
     pwm_1.write(value);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -141,7 +141,7 @@ int main() {
     PwmOut pwm_1(PA_0);
 
     pwm_1.write(value);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -151,7 +151,7 @@ int main() {
     PwmOut pwm_1(PA_0);
 
     pwm_1.write(value);
-    
+
     float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx
 
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
@@ -177,7 +177,7 @@ int main() {
 
     notify_completion(result == value ? true : false);
 #else
-#error This test is not supported on this target.
+#error [NOT_SUPPORTED] This test is not supported on this target.
 #endif
 
     notify_completion(true);
diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp
index 5739bf57b6..4ef9da3e32 100644
--- a/libraries/tests/mbed/pwm_led/pwm.cpp
+++ b/libraries/tests/mbed/pwm_led/pwm.cpp
@@ -26,14 +26,14 @@
 #elif defined (TARGET_MAXWSNENV)
 #define TEST_LED LED_GREEN
 
-#elif defined (TARGET_DISCO_F407VG) 
+#elif defined (TARGET_DISCO_F407VG)
 #define TEST_LED LED1
 
 #elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A)
 #define TEST_LED LED1
 
 #else
-#error This test is not supported on this target.
+  #error [NOT_SUPPORTED] This test is not supported on this target
 #endif
 
 PwmOut led(TEST_LED);
diff --git a/libraries/tests/mbed/reset/main.cpp b/libraries/tests/mbed/reset/main.cpp
index b38218e706..36a643e31d 100644
--- a/libraries/tests/mbed/reset/main.cpp
+++ b/libraries/tests/mbed/reset/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_SEMIHOST
+  #error [NOT_SUPPORTED] Semihost not supported
+#endif
+
 #include "mbed.h"
 
 Serial pc(USBTX, USBRX);
diff --git a/libraries/tests/mbed/spi/main.cpp b/libraries/tests/mbed/spi/main.cpp
index ceef120f01..cee94e5a92 100644
--- a/libraries/tests/mbed/spi/main.cpp
+++ b/libraries/tests/mbed/spi/main.cpp
@@ -1,5 +1,9 @@
 #include "mbed.h"
 
+#if !DEVICE_SPI
+  #error [NOT_SUPPORTED] SPI is not supported
+#endif
+
 #if defined(TARGET_SAMR21G18A)
 SPI spi(PB22, PB02, PB23);   // mosi, miso, sclk
 DigitalOut latchpin(PB03);
diff --git a/libraries/tests/mbed/spi_master/main.cpp b/libraries/tests/mbed/spi_master/main.cpp
index 835c4af5d8..821cbd2f9a 100644
--- a/libraries/tests/mbed/spi_master/main.cpp
+++ b/libraries/tests/mbed/spi_master/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_SPI
+  #error [NOT_SUPPORTED] SPI not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
diff --git a/libraries/tests/mbed/spi_slave/main.cpp b/libraries/tests/mbed/spi_slave/main.cpp
index 22830d2cf3..b676e29020 100644
--- a/libraries/tests/mbed/spi_slave/main.cpp
+++ b/libraries/tests/mbed/spi_slave/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_SPISLAVE
+  #error [NOT_SUPPORTED] SPI Slave not supported
+#endif
+
 #include "mbed.h"
 
 #if defined(TARGET_KL25Z)
diff --git a/libraries/tests/mbed/stdio_benchmark/main.cpp b/libraries/tests/mbed/stdio_benchmark/main.cpp
index b9179815dc..4d4eaef31b 100644
--- a/libraries/tests/mbed/stdio_benchmark/main.cpp
+++ b/libraries/tests/mbed/stdio_benchmark/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_LOCALFILESYSTEM
+  #error [NOT_SUPPORTED] LocalFileSystem not supported
+#endif
+
 #include "mbed.h"
 
 #define TEST_STDIO 0

From 7b256df1e963d47e90a815c43f33e9de1cb17158 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Mon, 29 Feb 2016 14:25:47 -0600
Subject: [PATCH 62/78] Uploading skipped [NOT_SUPPORTED] tests

---
 workspace_tools/upload_results.py | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/workspace_tools/upload_results.py b/workspace_tools/upload_results.py
index 0c0328e7bc..521f2d166e 100644
--- a/workspace_tools/upload_results.py
+++ b/workspace_tools/upload_results.py
@@ -234,9 +234,13 @@ def add_report(project_run_data, report_file, is_build, build_id, host_os):
 
             project_run_data['names_set'].add(projectRun['project'])
 
-            skipped = test_case.findall('skipped')
+            should_skip = False
+            skips = test_case.findall('skipped')
 
-            if not skipped:
+            if skips:
+                should_skip = skips[0].attrib['message'] == 'SKIP'
+
+            if not should_skip:
                 system_outs = test_case.findall('system-out')
 
                 output = ""
@@ -259,6 +263,9 @@ def add_report(project_run_data, report_file, is_build, build_id, host_os):
                 elif failures:
                     projectRunPass = False
                     result = failures[0].attrib['message']
+                elif skips:
+                    projectRunPass = True
+                    result = skips[0].attrib['message']
                 else:
                     projectRunPass = True
                     result = 'OK'

From 5376c62f3d2502f032eaa86beee84f194eeb9157 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 22 Feb 2016 17:20:27 +0100
Subject: [PATCH 63/78] [STM32F7 family] fix issue with RTC init

the logical test for RTC_ISR_INITS was wronlgy reported from other
STMfamilies.
MBED_16 test works with this modification.
---
 .../hal/TARGET_STM/TARGET_STM32F7/rtc_api.c   | 85 +++++++++----------
 1 file changed, 42 insertions(+), 43 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
index d25acb860f..276c13a176 100644
--- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c
@@ -40,59 +40,58 @@ void rtc_init(void)
     RCC_OscInitTypeDef RCC_OscInitStruct;
     uint32_t rtc_freq = 0;
 
-        RtcHandle.Instance = RTC;
+    RtcHandle.Instance = RTC;
 
-        // Enable Power clock
-        __PWR_CLK_ENABLE();
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
 
-        // Enable access to Backup domain
-        HAL_PWR_EnableBkUpAccess();
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
 
-        // Reset Backup domain
-        __HAL_RCC_BACKUPRESET_FORCE();
-        __HAL_RCC_BACKUPRESET_RELEASE();
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
 
-        // Enable LSE Oscillator
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    // Enable LSE Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        // Connect LSE to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+        rtc_freq = LSE_VALUE;
+    } else {
+        // Enable LSI clock
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
         RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-            // Connect LSE to RTC
-            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-            rtc_freq = LSE_VALUE;
-        } else {
-            // Enable LSI clock
-            RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-            RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-            RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-            RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-            if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-                error("RTC error: LSI clock initialization failed.");
-            }
-            // Connect LSI to RTC
-            __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-            __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-            // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
-            rtc_freq = LSI_VALUE;
+        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+            error("RTC error: LSI clock initialization failed.");
         }
+        // Connect LSI to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+        // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+        rtc_freq = LSI_VALUE;
+    }
 
-    if((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) {     // RTC initialization and status register (RTC_ISR), cold start (with no backup domain power) RTC reset value
+    // Check if RTC is already initialized
+    if ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) return;
 
-        // Enable RTC
-        __HAL_RCC_RTC_ENABLE();
+    // Enable RTC
+    __HAL_RCC_RTC_ENABLE();
 
-        RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-        RtcHandle.Init.AsynchPrediv   = 127;
-        RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-        RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-        RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-        RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-        if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-            error("RTC error: RTC initialization failed.");
-        }
+    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    RtcHandle.Init.AsynchPrediv   = 127;
+    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
+    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
 
+    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+        error("RTC error: RTC initialization failed.");
     }
 }
 

From ca41874978789cd508f8ed400a482e94d8e9633e Mon Sep 17 00:00:00 2001
From: Peter Conheeney <Peter.Conheeney@arm.com>
Date: Tue, 1 Mar 2016 08:51:08 +0000
Subject: [PATCH 64/78] disabled i2c slave

---
 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
index 52cebb2dd8..6dd951b618 100644
--- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
+++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h
@@ -29,7 +29,7 @@
 #define DEVICE_SERIAL_FC        1
 
 #define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
+#define DEVICE_I2CSLAVE         0
 
 #define DEVICE_SPI              1
 #define DEVICE_SPISLAVE         1

From 38f4c1df6b76fd4e8c9db7b0d6f6c86221d4569e Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Wed, 2 Mar 2016 10:29:30 +0100
Subject: [PATCH 65/78] Exporter - progen include dirs fix

mbed scripts copy files, therefore file paths are not valid at the moment of ahe project generation.
Therefore checks like os.path.isdir or isfile fail. If include is set to TARGET/FOLDER, this would be
treated as a file, and added to the project workspace. This commit fixes it, it adds dirs only to
include_paths, as it should.
---
 workspace_tools/export/exporters.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/workspace_tools/export/exporters.py b/workspace_tools/export/exporters.py
index 3697fae0d6..da49230ff8 100644
--- a/workspace_tools/export/exporters.py
+++ b/workspace_tools/export/exporters.py
@@ -62,7 +62,7 @@ class Exporter(object):
                         self.resources.objects + self.resources.libraries,
                 },
                 'includes':  { 
-                    'Include Files': self.resources.headers + self.resources.inc_dirs,
+                    'Include Files': self.resources.headers,
                 },
                 'target': [TARGET_MAP[self.target].progen['target']],
                 'macros': self.get_symbols(),
@@ -76,6 +76,9 @@ class Exporter(object):
         """" Generate project using ProGen Project API """
         settings = ProjectSettings()
         project = Project(self.program_name, [project_data], settings)
+        # TODO: Fix this, the inc_dirs are not valid (our scripts copy files), therefore progen
+        # thinks it is not dict but a file, and adds them to workspace.
+        project.project['common']['include_paths'] = self.resources.inc_dirs
         project.generate(tool_name, copied=True)
 
     def __scan_all(self, path):

From 6915f09663d42eba8f5685db64d121a53532f896 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Wed, 2 Mar 2016 11:01:24 +0100
Subject: [PATCH 66/78] Targets - fix nucleo f410rb

---
 workspace_tools/targets.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index d0f20933c2..b0ce734eca 100755
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -792,7 +792,7 @@ class NUCLEO_F410RB(Target):
         self.supported_form_factors = ["ARDUINO", "MORPHO"]
         self.detect_code = ["0740"]
         self.progen = {
-            "target":"",
+            "target":"nucleo-f410rb",
         }
 
 class NUCLEO_F411RE(Target):

From 67fe82479ab05d62d01d85cc2fd60ec4e14de2c1 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Wed, 2 Mar 2016 11:01:46 +0100
Subject: [PATCH 67/78] Build release - add nucleo f746zg

---
 workspace_tools/build_release.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py
index 2fcb7724d2..372a27bef2 100644
--- a/workspace_tools/build_release.py
+++ b/workspace_tools/build_release.py
@@ -95,6 +95,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
     ('DISCO_F746NG', ('ARM', 'uARM', 'GCC_ARM')),
     ('DISCO_L476VG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
     ('NUCLEO_L476RG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
+    ('NUCLEO_F746ZG', ('ARM', 'uARM', 'GCC_ARM')),
 
     ('MOTE_L152RC', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
 

From b9f6f5c776b399135965fd219030d72a83f4fbe4 Mon Sep 17 00:00:00 2001
From: 0xc0170 <c0170@rocketmail.com>
Date: Wed, 2 Mar 2016 11:02:18 +0100
Subject: [PATCH 68/78] mbed lib revision - 115

---
 libraries/mbed/api/mbed.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h
index f5a9056516..11f9a6f850 100644
--- a/libraries/mbed/api/mbed.h
+++ b/libraries/mbed/api/mbed.h
@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 114
+#define MBED_LIBRARY_VERSION 115
 
 #include "platform.h"
 

From c38209f6d669b22feb24d5321bb35fa0c3128a82 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Wed, 2 Mar 2016 13:13:36 -0600
Subject: [PATCH 69/78] Adding more [NOT_SUPPORTED] messages to tests

---
 libraries/tests/mbed/analog_in/main.cpp      |  2 ++
 libraries/tests/mbed/interruptin/main.cpp    |  6 +++++-
 libraries/tests/mbed/interruptin_2/main.cpp  |  4 ++++
 libraries/tests/mbed/portout_portin/main.cpp | 13 ++++++++++++-
 libraries/tests/mbed/rtc/main.cpp            |  4 ++++
 libraries/tests/mbed/sleep/main.cpp          |  4 ++++
 libraries/tests/mbed/sleep_timeout/main.cpp  |  4 ++++
 7 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/libraries/tests/mbed/analog_in/main.cpp b/libraries/tests/mbed/analog_in/main.cpp
index 157885df36..b422a78fd6 100644
--- a/libraries/tests/mbed/analog_in/main.cpp
+++ b/libraries/tests/mbed/analog_in/main.cpp
@@ -21,6 +21,8 @@ DigitalOut indicator(LED1);
 
 #else
 
+#error [NOT_SUPPORTED] This test is not supported on this target
+
 #endif
 
 uint8_t successes = 0;
diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp
index fc79b978d0..dfe783b6ce 100644
--- a/libraries/tests/mbed/interruptin/main.cpp
+++ b/libraries/tests/mbed/interruptin/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_INTERRUPTIN
+  #error [NOT_SUPPORTED] InterruptIn is not supported
+#endif
+
 #include "test_env.h"
 
 DigitalOut myled(LED1);
@@ -101,7 +105,7 @@ void in_handler() {
 #define PIN_OUT    PB02
 #define PIN_IN     PB03
 
-#elif defined(TARGET_SAML21J18A) 
+#elif defined(TARGET_SAML21J18A)
 #define PIN_OUT    PA02
 #define PIN_IN     PA03
 
diff --git a/libraries/tests/mbed/interruptin_2/main.cpp b/libraries/tests/mbed/interruptin_2/main.cpp
index a418d35755..84d31751ef 100644
--- a/libraries/tests/mbed/interruptin_2/main.cpp
+++ b/libraries/tests/mbed/interruptin_2/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_INTERRUPTIN
+  #error [NOT_SUPPORTED] InterruptIn is not supported
+#endif
+
 #include "mbed.h"
 
 #if defined(TARGET_LPC4088)
diff --git a/libraries/tests/mbed/portout_portin/main.cpp b/libraries/tests/mbed/portout_portin/main.cpp
index 10fcafa79d..95fdb1bbd0 100644
--- a/libraries/tests/mbed/portout_portin/main.cpp
+++ b/libraries/tests/mbed/portout_portin/main.cpp
@@ -1,3 +1,11 @@
+#if !DEVICE_PORTIN
+  #error [NOT_SUPPORTED] PortIn is not supported
+#endif
+
+#if !DEVICE_PORTOUT
+  #error [NOT_SUPPORTED] PortOut is not supported
+#endif
+
 #include "test_env.h"
 
 #if defined(TARGET_K64F) || defined(TARGET_KL05Z)
@@ -90,7 +98,7 @@
 #define P2_1    (1 << 1)  // PA_1
 #define P2_2    (1 << 2)  // PA_2
 #define PORT_2  PortA
-        
+
 #elif defined(TARGET_NUCLEO_F030R8) || \
       defined(TARGET_NUCLEO_F070RB) || \
       defined(TARGET_NUCLEO_F072RB) || \
@@ -176,6 +184,9 @@
 #define P2_2    (1 << 1)  /*PB01*/
 #define PORT_2  PortB
 
+#else
+#error [NOT_SUPPORTED] This test is not supported on this target
+
 #endif
 
 #define MASK_1   (P1_1 | P1_2)
diff --git a/libraries/tests/mbed/rtc/main.cpp b/libraries/tests/mbed/rtc/main.cpp
index 505e70b5af..8185fb1224 100644
--- a/libraries/tests/mbed/rtc/main.cpp
+++ b/libraries/tests/mbed/rtc/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_RTC
+  #error [NOT_SUPPORTED] RTC is not supported
+#endif
+
 #include "mbed.h"
 #include "test_env.h"
 
diff --git a/libraries/tests/mbed/sleep/main.cpp b/libraries/tests/mbed/sleep/main.cpp
index 40d6bbb3a9..bde55d41aa 100644
--- a/libraries/tests/mbed/sleep/main.cpp
+++ b/libraries/tests/mbed/sleep/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_SLEEP
+  #error [NOT_SUPPORTED] Sleep is not supported
+#endif
+
 #include "test_env.h"
 
 #if defined(TARGET_LPC4088)
diff --git a/libraries/tests/mbed/sleep_timeout/main.cpp b/libraries/tests/mbed/sleep_timeout/main.cpp
index 0f8adbfb87..02f8975a52 100644
--- a/libraries/tests/mbed/sleep_timeout/main.cpp
+++ b/libraries/tests/mbed/sleep_timeout/main.cpp
@@ -1,3 +1,7 @@
+#if !DEVICE_SLEEP
+  #error [NOT_SUPPORTED] Sleep is not supported
+#endif
+
 #include "mbed.h"
 
 DigitalOut led1(LED1);

From 6ab159af26ba86372e5a059a7d0f66c031d13e1c Mon Sep 17 00:00:00 2001
From: Toyomasa Watarai <toyomasa.watarai@gmail.com>
Date: Thu, 3 Mar 2016 17:09:35 +0900
Subject: [PATCH 70/78] [LPC824] Fixed PwmOut SCT Bugs

* Fixed period & pulse-width off-by-one errors
* Fixed 0% and 100% duty cycle output
---
 .../hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 48 +++++++++++++------
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
index 38ef6b9f8f..db4b4d6dd3 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
@@ -91,6 +91,7 @@ void pwmout_init(pwmout_t* obj, PinName pin)
     pwm->CTRL &= ~(0x7F << 5);
     pwm->CTRL |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5);
 
+    // Set event number
     pwm->OUT[sct_n].SET = (1 << ((sct_n * 2) + 0));
     pwm->OUT[sct_n].CLR = (1 << ((sct_n * 2) + 1));
 
@@ -99,10 +100,6 @@ void pwmout_init(pwmout_t* obj, PinName pin)
     pwm->EVENT[(sct_n * 2) + 1].CTRL  = (1 << 12) | ((sct_n * 2) + 1);
     pwm->EVENT[(sct_n * 2) + 1].STATE = 0xFFFFFFFF;
 
-    // unhalt the counter:
-    //    - clearing bit 2 of the CTRL register
-    pwm->CTRL &= ~(1 << 2);
-
     // default to 20ms: standard for servos, and fine for e.g. brightness control
     pwmout_period_ms(obj, 20);
     pwmout_write    (obj, 0);
@@ -120,16 +117,27 @@ void pwmout_write(pwmout_t* obj, float value)
     if (value < 0.0f) {
         value = 0.0;
     } else if (value > 1.0f) {
-        value = 1.0;
+        value = 1.0f;
+    }
+    uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2] + 1) * value);
+    if (t_on > 0) {
+        if (value != 1.0f) {
+            obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on - 1;
+            obj->pwm->CTRL &= ~(1 << 2);
+        } else {
+            obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+            obj->pwm->OUTPUT |= (1 << obj->pwm_ch);
+        }
+    } else {
+        obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
     }
-    uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2]) * value);
-    obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on;
 }
 
 float pwmout_read(pwmout_t* obj)
 {
-    uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0];
-    uint32_t t_on  = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1];
+    uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1;
+    uint32_t t_on  = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1;
     float v = (float)t_on/(float)t_off;
     return (v > 1.0f) ? (1.0f) : (v);
 }
@@ -147,11 +155,17 @@ void pwmout_period_ms(pwmout_t* obj, int ms)
 // Set the PWM period, keeping the duty cycle the same.
 void pwmout_period_us(pwmout_t* obj, int us)
 {
-    uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0];
-    uint32_t t_on  = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1];
+    uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1;
+    uint32_t t_on  = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1;
     float v = (float)t_on/(float)t_off;
-    obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us;
-    obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)((float)us * (float)v);
+    obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us - 1;
+    if (us > 0) {
+        obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] =  (uint32_t)((float)us * (float)v) - 1;
+        obj->pwm->CTRL &= ~(1 << 2);
+    } else {
+        obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
+    }
 }
 
 void pwmout_pulsewidth(pwmout_t* obj, float seconds)
@@ -166,7 +180,13 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
 
 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
 {
-    obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us;
+    if (us > 0) {
+        obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us - 1;
+        obj->pwm->CTRL &= ~(1 << 2);
+    } else {
+        obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
+    }
 }
 
 #endif

From 792b359a3676256053a86881df272e015aa5e1a1 Mon Sep 17 00:00:00 2001
From: neilt6 <neilt66@icloud.com>
Date: Thu, 3 Mar 2016 15:28:59 -0700
Subject: [PATCH 71/78] [LPC11U68, LPC1549] Fixed PwmOut SCT Bugs

* 0% duty cycle now reads back correctly
* Period & pulse-width changes now take effect immediately if the timer
is halted
---
 .../TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c   | 24 ++++++++++++++-----
 .../TARGET_NXP/TARGET_LPC15XX/pwmout_api.c    | 24 ++++++++++++++-----
 2 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
index 4e77591483..a8263f7090 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
@@ -137,7 +137,10 @@ void pwmout_write(pwmout_t* obj, float value) {
     uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
     if (t_on > 0) {
         pwm->MATCHREL1 = t_on - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
@@ -145,8 +148,9 @@ void pwmout_write(pwmout_t* obj, float value) {
 }
 
 float pwmout_read(pwmout_t* obj) {
-    uint32_t t_off = obj->pwm->MATCHREL0 + 1;
-    uint32_t t_on  = obj->pwm->MATCHREL1 + 1;
+    LPC_SCT0_Type* pwm = obj->pwm;
+    uint32_t t_off = pwm->MATCHREL0 + 1;
+    uint32_t t_on  = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
     float v = (float)t_on/(float)t_off;
     return (v > 1.0f) ? (1.0f) : (v);
 }
@@ -163,16 +167,21 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
 void pwmout_period_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     uint32_t t_off = pwm->MATCHREL0 + 1;
-    uint32_t t_on  = pwm->MATCHREL1 + 1;
+    uint32_t t_on  = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
     float v = (float)t_on/(float)t_off;
     uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
     uint32_t pulsewidth_ticks = period_ticks * v;
     pwm->MATCHREL0 = period_ticks - 1;
     if (pulsewidth_ticks > 0) {
         pwm->MATCHREL1 = pulsewidth_ticks - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH0 = pwm->MATCHREL0;
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
+        pwm->MATCH0 = pwm->MATCHREL0;
         pwm->OUTPUT = 0x00000000;
     }
 }
@@ -189,7 +198,10 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     if (us > 0) {
         pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
index 323e583425..a8f0c06659 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
@@ -118,7 +118,10 @@ void pwmout_write(pwmout_t* obj, float value) {
     uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
     if (t_on > 0) {
         pwm->MATCHREL1 = t_on - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
@@ -126,8 +129,9 @@ void pwmout_write(pwmout_t* obj, float value) {
 }
 
 float pwmout_read(pwmout_t* obj) {
-    uint32_t t_off = obj->pwm->MATCHREL0 + 1;
-    uint32_t t_on  = obj->pwm->MATCHREL1 + 1;
+    LPC_SCT0_Type* pwm = obj->pwm;
+    uint32_t t_off = pwm->MATCHREL0 + 1;
+    uint32_t t_on  = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
     float v = (float)t_on/(float)t_off;
     return (v > 1.0f) ? (1.0f) : (v);
 }
@@ -144,16 +148,21 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
 void pwmout_period_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     uint32_t t_off = pwm->MATCHREL0 + 1;
-    uint32_t t_on  = pwm->MATCHREL1 + 1;
+    uint32_t t_on  = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
     float v = (float)t_on/(float)t_off;
     uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
     uint32_t pulsewidth_ticks = period_ticks * v;
     pwm->MATCHREL0 = period_ticks - 1;
     if (pulsewidth_ticks > 0) {
         pwm->MATCHREL1 = pulsewidth_ticks - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH0 = pwm->MATCHREL0;
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
+        pwm->MATCH0 = pwm->MATCHREL0;
         pwm->OUTPUT = 0x00000000;
     }
 }
@@ -170,7 +179,10 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     if (us > 0) {
         pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
-        pwm->CTRL &= ~(1 << 2);
+        if (pwm->CTRL & (1 << 2)) {
+            pwm->MATCH1 = pwm->MATCHREL1;
+            pwm->CTRL &= ~(1 << 2);
+        }
     } else {
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;

From a86504d205d833139484fc58d313a29d4e943a97 Mon Sep 17 00:00:00 2001
From: Toyomasa Watarai <toyomasa.watarai@gmail.com>
Date: Fri, 4 Mar 2016 16:00:32 +0900
Subject: [PATCH 72/78] [LPC824] Add more comments for PwmOut fix

---
 .../hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 27 +++++++++++++------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
index db4b4d6dd3..c24057544e 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
@@ -120,16 +120,21 @@ void pwmout_write(pwmout_t* obj, float value)
         value = 1.0f;
     }
     uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2] + 1) * value);
-    if (t_on > 0) {
-        if (value != 1.0f) {
+    if (t_on > 0) { // duty is not 0%
+        if (value != 1.0f) { // duty is not 100%
             obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on - 1;
+            // unhalt the counter
             obj->pwm->CTRL &= ~(1 << 2);
-        } else {
+        } else { // duty is 100%
+            // halt and clear the counter
             obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+            // output level tied to high
             obj->pwm->OUTPUT |= (1 << obj->pwm_ch);
         }
-    } else {
+    } else { // duty is 0%
+        // halt and clear the counter
         obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        // output level tied to low
         obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
     }
 }
@@ -155,15 +160,19 @@ void pwmout_period_ms(pwmout_t* obj, int ms)
 // Set the PWM period, keeping the duty cycle the same.
 void pwmout_period_us(pwmout_t* obj, int us)
 {
+    // The period are off by one for MATCHREL, so +1 to get actual value
     uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1;
     uint32_t t_on  = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1;
     float v = (float)t_on/(float)t_off;
     obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us - 1;
-    if (us > 0) {
+    if (us > 0) { // PWM period is not 0
         obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] =  (uint32_t)((float)us * (float)v) - 1;
+        // unhalt the counter
         obj->pwm->CTRL &= ~(1 << 2);
-    } else {
+    } else { // PWM period is 0
+        // halt and clear the counter
         obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        // output level tied to low
         obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
     }
 }
@@ -180,11 +189,13 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
 
 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
 {
-    if (us > 0) {
+    if (us > 0) { // PWM peried is not 0
         obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us - 1;
         obj->pwm->CTRL &= ~(1 << 2);
-    } else {
+    } else { //PWM period is 0
+        // halt and clear the counter
         obj->pwm->CTRL |= (1 << 2) | (1 << 3);
+        // output level tied to low
         obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
     }
 }

From 0b9cc0972775c3404bd7203585d8608b6178bbbb Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 4 Mar 2016 14:28:07 +0100
Subject: [PATCH 73/78] [STM32F7] Update STM32Cube_FW version

---
 .../Release_Notes_stm32f7xx_hal.html          |  53 +-
 .../TARGET_STM32F7/stm32_hal_legacy.h         | 561 +++++++++++--
 .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c |  16 +-
 .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_adc.c        | 783 ++++++++++++------
 .../TARGET_STM32F7/stm32f7xx_hal_adc.h        | 266 ++++--
 .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.c     | 601 +++++++++-----
 .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.h     | 107 ++-
 .../TARGET_STM32F7/stm32f7xx_hal_can.c        |  22 +-
 .../TARGET_STM32F7/stm32f7xx_hal_can.h        |  29 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cec.c        |  14 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cec.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cortex.c     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cortex.h     |  27 +-
 .../TARGET_STM32F7/stm32f7xx_hal_crc.c        |  79 +-
 .../TARGET_STM32F7/stm32f7xx_hal_crc.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.c     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cryp.c       |  37 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cryp.h       |  10 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c    |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h    |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dac.c        |  22 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dac.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.c     |  16 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dcmi.c       |  19 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dcmi.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_def.h        |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dma.c        | 153 ++--
 .../TARGET_STM32F7/stm32f7xx_hal_dma.h        |   9 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dma2d.c      |  10 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dma2d.h      |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.c     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_eth.c        |  46 +-
 .../TARGET_STM32F7/stm32f7xx_hal_eth.h        |   8 +-
 .../TARGET_STM32F7/stm32f7xx_hal_flash.c      |  18 +-
 .../TARGET_STM32F7/stm32f7xx_hal_flash.h      |  13 +-
 .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.c   |  51 +-
 .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.h   |  21 +-
 .../TARGET_STM32F7/stm32f7xx_hal_gpio.c       |   7 +-
 .../TARGET_STM32F7/stm32f7xx_hal_gpio.h       |  12 +-
 .../TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h    |  14 +-
 .../TARGET_STM32F7/stm32f7xx_hal_hash.c       |  21 +-
 .../TARGET_STM32F7/stm32f7xx_hal_hash.h       |  12 +-
 .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.c    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.h    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_hcd.c        | 142 ++--
 .../TARGET_STM32F7/stm32f7xx_hal_hcd.h        |  16 +-
 .../TARGET_STM32F7/stm32f7xx_hal_i2c.c        | 718 +++++++++-------
 .../TARGET_STM32F7/stm32f7xx_hal_i2c.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c     |  10 +-
 .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h     |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_i2s.c        |  27 +-
 .../TARGET_STM32F7/stm32f7xx_hal_i2s.h        |   8 +-
 .../TARGET_STM32F7/stm32f7xx_hal_irda.c       |  25 +-
 .../TARGET_STM32F7/stm32f7xx_hal_irda.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_irda_ex.h    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_iwdg.c       |   9 +-
 .../TARGET_STM32F7/stm32f7xx_hal_iwdg.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_lptim.c      |  31 +-
 .../TARGET_STM32F7/stm32f7xx_hal_lptim.h      |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_ltdc.c       |  20 +-
 .../TARGET_STM32F7/stm32f7xx_hal_ltdc.h       |   7 +-
 .../TARGET_STM32F7/stm32f7xx_hal_nand.c       |  13 +-
 .../TARGET_STM32F7/stm32f7xx_hal_nand.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_nor.c        |  14 +-
 .../TARGET_STM32F7/stm32f7xx_hal_nor.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pcd.c        | 123 ++-
 .../TARGET_STM32F7/stm32f7xx_hal_pcd.h        |  13 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c     |  24 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h     |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pwr.c        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pwr.h        |   6 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_qspi.c       | 196 +++--
 .../TARGET_STM32F7/stm32f7xx_hal_qspi.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rcc.c        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rcc.h        |  77 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c     | 139 +++-
 .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h     | 369 +++++----
 .../TARGET_STM32F7/stm32f7xx_hal_rng.c        |  16 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rng.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rtc.c        |  13 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rtc.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c     |  22 +-
 .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sai.c        | 377 +++++----
 .../TARGET_STM32F7/stm32f7xx_hal_sai.h        |  57 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.c     |  31 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.h     |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sd.c         |  32 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sd.h         |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sdram.c      |  19 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sdram.h      |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_smartcard.c  |  19 +-
 .../TARGET_STM32F7/stm32f7xx_hal_smartcard.h  |   4 +-
 .../stm32f7xx_hal_smartcard_ex.c              |   4 +-
 .../stm32f7xx_hal_smartcard_ex.h              |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.c    |  35 +-
 .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.h    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_spi.c        |  31 +-
 .../TARGET_STM32F7/stm32f7xx_hal_spi.h        |  10 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sram.c       |  16 +-
 .../TARGET_STM32F7/stm32f7xx_hal_sram.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_tim.c        |  92 +-
 .../TARGET_STM32F7/stm32f7xx_hal_tim.h        |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.c     |  22 +-
 .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.h     |  10 +-
 .../TARGET_STM32F7/stm32f7xx_hal_uart.c       |  34 +-
 .../TARGET_STM32F7/stm32f7xx_hal_uart.h       |   8 +-
 .../TARGET_STM32F7/stm32f7xx_hal_uart_ex.h    |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_usart.c      |  30 +-
 .../TARGET_STM32F7/stm32f7xx_hal_usart.h      |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_usart_ex.h   |   4 +-
 .../TARGET_STM32F7/stm32f7xx_hal_wwdg.c       |  15 +-
 .../TARGET_STM32F7/stm32f7xx_hal_wwdg.h       |   8 +-
 .../TARGET_STM32F7/stm32f7xx_ll_fmc.c         |   6 +-
 .../TARGET_STM32F7/stm32f7xx_ll_fmc.h         |  10 +-
 .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.c       |   6 +-
 .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.h       |   4 +-
 .../TARGET_STM32F7/stm32f7xx_ll_usb.c         |  51 +-
 .../TARGET_STM32F7/stm32f7xx_ll_usb.h         |   4 +-
 127 files changed, 4126 insertions(+), 2098 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
index 0c78c59e5a..d6aa6457e9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
@@ -676,7 +676,58 @@ Notes for STM32F7xx HAL Drivers</span><span style="font-size: 20pt; font-family:
 <tr style="">
 <td style="padding: 0in;" valign="top">
 <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 25-June-2015</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.4 / 09-December-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL 
+weak empty callbacks to prevent unused argument compilation warnings with some 
+compilers by calling the following line:</span>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update&nbsp;</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.3 / 13-November-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates 
+to fix known defects and enhancements implementation</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">One change done on the HAL CRYP requires an update on 
+the application code based on HAL V1.0.2</span></span>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update 
+HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData 
+parameters</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL 
+weak empty callbacks to prevent unused argument compilation warnings with some 
+compilers by calling the following line:</span>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove references to STM32CubeMX and MicroXplorer from stm32f7xx_hal_msp_template.c file<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">Replace ADC_CHANNEL_TEMPSENSOR definition from ADC_CHANNEL_16 to ADC_CHANNEL_18 </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">&nbsp;</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">Update HAL ADC driver state machine for code efficiency</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible 
+value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef 
+structure to select the ADC software trigger mode.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplication 
+for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_IWDG_STOP_ACTIVE definition</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_RDP_LEVEL_x definition by proper values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update values for LSE Drive capability defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PLLN min value 50 instead of 100</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG</span><span style="font-family: Verdana; font-size: 10pt;">&nbsp;</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update for proper management of the external synchronization input selection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update of&nbsp;HAL_SAI_Init () funciton</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_SLOTACTIVE_X &nbsp;defines values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update&nbsp;</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SAI_Init() function for proper companding mode management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_SAI_EnableRxMuteMode() function for proper mute management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_InitPCM() function to support 24bits configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update HAL_SD_Get_CardInfo() to properly support high capacity cards</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPDIFRX </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SPDIFRX_DMARxCplt() function implementation to&nbsp;check on circular mode before disabling the DMA</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update __HAL_UART_CLEAR_IT macro for proper functionning&nbsp;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">add FMC_PAGE_SIZE_512 define</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll SDMMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update SDMMC_SetSDMMCReadWaitMode() function for proper functionning</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 21-September-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f7xx_hal.conf_template.h: update&nbsp;</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HSE_STARTUP_TIMEOUT</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f7xx_hal_def.h: update the</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> quotation marks used in #error"USE_RTOS should be 0 in the current HAL release"</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Overall 
+driver update for code optimization</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add 
+StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef 
+structure</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add 
+DMA_Base_Registers private structure</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add static function 
+DMA_CalcBaseAndBitshift()</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update 
+HAL_DMA_Init() function to use the new added static function</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update 
+HAL_DMA_DeInit() function to optimize clear flag operations</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update 
+HAL_DMA_Start_IT() function to optimize interrupts enable</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update 
+HAL_DMA_PollForTransfer() function to optimize check on flags</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update 
+HAL_DMA_IRQHandler() function to optimize interrupt flag management</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH&nbsp;</span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">remove duplicated macro IS_ETH_RX_MODE()</span><small><span style="font-style: italic;"></span></small></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef</span>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename 
+HAL_HASH_PhaseTypeDef to HAL_HASHPhaseTypeDef</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span><span style="font-weight: bold;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update values for LSE Drive capability defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add __HAL_RCC_MCO1_CONFIG() and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_RCC_MCO2_CONFIG() macros</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified&nbsp;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update the implementation of __HAL_TIM_SET_COMPARE() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">remove useless assert() in&nbsp;HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() </span><span style="font-family: Verdana; font-size: 10pt;">functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">add the clear flag ERRI bit in HAL_CAN_IRQHandler()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update I2S HAL_I2S_Transmit() API&nbsp;to keep the check on busy flag only for the slave</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL QSPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Remove
+enabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and
+remove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD</span></span><span style="font-family: Verdana; font-size: 10pt;"> update</span><span style="font-weight: bold;">&nbsp;</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Clean status phase received interrupt when DMA mode enabled&nbsp;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: Verdana; font-size: 10pt;">update</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"></span></span><span style="font-weight: bold;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local 
+variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">remove return HAL_ERROR from FMC_SDRAM_SendCommand() function</span></li></ul></ul><span style="font-family: Verdana; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 25-June-2015</span></h3>
 <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
 Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates 
 to fix known defects and enhancements implementation</span><span style="font-family: Verdana; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC&nbsp;</span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CEC&nbsp;</span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Cortex </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update HAL_MPU_ConfigRegion() function to be misra compliant</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
index c256044db0..cd4be44396 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
@@ -102,7 +102,15 @@
 #define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
 #define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
 #define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
 /**
   * @}
   */
@@ -121,11 +129,28 @@
   * @{
   */
   
-#define COMP_WINDOWMODE_DISABLED    COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED     COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT  COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT  COMP_EXTI_LINE_COMP2
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+/**
+  * @}
+  */
 
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
 /**
   * @}
   */
@@ -255,7 +280,14 @@
 #define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
 #define OB_WDG_SW                     OB_IWDG_SW
 #define OB_WDG_HW                     OB_IWDG_HW
-
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
 /**
   * @}
   */
@@ -264,14 +296,15 @@
   * @{
   */
   
-#define SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
 /**
   * @}
   */
@@ -330,6 +363,26 @@
 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1) 
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
+#endif /* STM32L1 */
+
+#if defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F3 */
+
 /**
   * @}
   */
@@ -346,6 +399,15 @@
 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+   
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
 /**
   * @}
   */
@@ -804,7 +866,8 @@
 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
   * @{
   */ 
-  
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
 #define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
 #define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
 #define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
@@ -1178,23 +1241,166 @@
 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
   * @{
   */
-
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+   
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
                                                           __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
                                                           __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
 
 /**
@@ -1346,7 +1552,7 @@
 #define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -1355,8 +1561,8 @@
 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
-#define __HAL_PWR_PVM_ENABLE()                                   HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
 #define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
@@ -2015,47 +2221,211 @@
 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
 #define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
 #define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET          __HAL_RCC_CRYP_FORCE_RESET  
-#define __SRAM3_CLK_SLEEP_ENABLE  __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
-#define __CAN2_CLK_SLEEP_ENABLE          __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE  __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
-#define __DAC_CLK_SLEEP_ENABLE          __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE   __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_SLEEP_ENABLE   __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE  __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
-#define __ADC3_CLK_SLEEP_ENABLE          __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE  __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
-#define __FSMC_FORCE_RESET          __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET          __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE          __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE  __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
-#define __SDIO_FORCE_RESET          __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET          __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE  __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE          __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
-#define __DMA2D_CLK_ENABLE          __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE          __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET          __HAL_RCC_DMA2D_FORCE_RESET
+#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
 #define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE  __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
 
 /* alias define maintained for legacy */
 #define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
 #define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
 
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
 #if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
 #define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
 #define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
 #define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
 #define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
 #define Sdmmc1ClockSelection               SdioClockSelection
 #define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
 #define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
@@ -2065,13 +2435,14 @@
 #endif
 
 #if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
 #define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
 #define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
 #define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
 #define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
 #define SdioClockSelection                 Sdmmc1ClockSelection
 #define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
 #define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
@@ -2086,28 +2457,81 @@
 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
 
-#define __RCC_PLLSRC           RCC_GET_PLL_OSCSOURCE
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
 
-#define IS_RCC_MSIRANGE        IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE   IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV      IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV        IS_RCC_PCLK
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
 
-#define IS_RCC_MCOSOURCE       IS_RCC_MCO1SOURCE
-#define RCC_MCO_NODIV          RCC_MCODIV_1
-#define RCC_RTCCLKSOURCE_NONE  RCC_RTCCLKSOURCE_NO_CLK
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#if defined(STM32L0)
+#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
+#define RCC_IT_CSS                 RCC_IT_CSSHSE
+#endif
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
 
 #define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
 #define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
 #define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
 #define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
 #define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
 #define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
 #define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
 #define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
 #define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
 #define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
 #define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
 #define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
 #define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
@@ -2128,9 +2552,18 @@
 #define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
 #define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
 #define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
 #define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
 #define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
 
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
index f610ac0dc8..d9af98f027 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -68,11 +68,11 @@
   * @{
   */
 /**
- * @brief STM32F7xx HAL Driver version number V1.0.1
+ * @brief STM32F7xx HAL Driver version number V1.0.4
    */
 #define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
 #define __STM32F7xx_HAL_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2   (0x04) /*!< [15:8]  sub2 version */
 #define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
                                         |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -213,7 +213,7 @@ __weak void HAL_MspInit(void)
 }
 
 /**
-  * @brief  DeInitializes the MSP.  
+  * @brief  DeInitializes the MSP.
   * @retval None
   */
 __weak void HAL_MspDeInit(void)
@@ -309,7 +309,7 @@ __weak uint32_t HAL_GetTick(void)
   * @note In the default implementation , SysTick timer is the source of time base.
   *       It is used to generate interrupts at regular time intervals where uwTick
   *       is incremented.
-  * @note ThiS function is declared as __weak to be overwritten in case of other
+  * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
   * @param Delay: specifies the delay time length, in milliseconds.
   * @retval None
@@ -327,7 +327,7 @@ __weak void HAL_Delay(__IO uint32_t Delay)
   * @brief Suspend Tick increment.
   * @note In the default implementation , SysTick timer is the source of time base. It is
   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the the SysTick interrupt will be disabled and so Tick increment 
+  *       is called, the SysTick interrupt will be disabled and so Tick increment 
   *       is suspended.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
@@ -343,7 +343,7 @@ __weak void HAL_SuspendTick(void)
   * @brief Resume Tick increment.
   * @note In the default implementation , SysTick timer is the source of time base. It is
   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the the SysTick interrupt will be enabled and so Tick increment 
+  *       is called, the SysTick interrupt will be enabled and so Tick increment 
   *       is resumed.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
index eeb5448572..2a8e66ae9d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
index f1a75f9056..bd135363c8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
@@ -258,10 +258,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
   */
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 {
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
   /* Check ADC handle */
   if(hadc == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
   
   /* Check the parameters */
@@ -284,29 +286,45 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 
   if(hadc->State == HAL_ADC_STATE_RESET)
   {
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
     /* Allocate lock resource and initialize it */
     hadc->Lock = HAL_UNLOCKED;
     /* Init the low level hardware */
     HAL_ADC_MspInit(hadc);
   }
-
-  /* Initialize the ADC state */
-  hadc->State = HAL_ADC_STATE_BUSY;
   
-  /* Set ADC parameters */
-  ADC_Init(hadc);
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Set ADC parameters */
+    ADC_Init(hadc);
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set the ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
   
-  /* Set ADC error code to none */
-  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-  
-  /* Initialize the ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
-
   /* Release Lock */
   __HAL_UNLOCK(hadc);
 
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -317,29 +335,43 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   */
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
 {
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
   /* Check ADC handle */
   if(hadc == NULL)
   {
-     return HAL_ERROR;
-  } 
+    return HAL_ERROR;
+  }
   
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
   
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_BUSY;
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
   
-  /* DeInit the low level hardware */
-  HAL_ADC_MspDeInit(hadc);
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
   
-  /* Set ADC error code to none */
-  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set ADC state */
+    hadc->State = HAL_ADC_STATE_RESET;
+  }
   
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_RESET;
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -350,6 +382,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspInit could be implemented in the user file
    */ 
@@ -363,6 +397,8 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspDeInit could be implemented in the user file
    */ 
@@ -409,18 +445,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Check if an injected conversion is ongoing */
-  if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_REG;
-  } 
-    
+  /* Enable the ADC peripheral */
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
   Tstab time the ADC's stabilization */
   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -436,27 +461,63 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
       counter--;
     }
   }
-	
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Check if Multimode enabled */
-  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    /* if no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
     {
-      /* Enable the selected ADC software conversion for regular group */
-      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
     }
-  }
-  else
-  {
-    /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
     {
-      /* Enable the selected ADC software conversion for regular group */
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
     }
   }
   
@@ -476,11 +537,27 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   */
 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
 {
-  /* Disable the Peripheral */
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
   __HAL_ADC_DISABLE(hadc);
   
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
   return HAL_OK;
@@ -488,6 +565,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Poll for regular conversion complete
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function.
+  * @note   This function cannot be used in a particular setup: ADC configured 
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still 
+  *         be performed on the complete sequence.
   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @param  Timeout: Timeout value in millisecond.  
@@ -507,7 +592,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
   {
     /* Update ADC state machine to error */
-    hadc->State = HAL_ADC_STATE_ERROR;
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
     
     /* Process unlocked */
     __HAL_UNLOCK(hadc);
@@ -521,29 +606,46 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
   /* Check End of conversion flag */
   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
   {
-    /* Check for the Timeout */
+    /* Check if timeout is disabled (set to infinite wait) */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
-        hadc->State= HAL_ADC_STATE_TIMEOUT;
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
         /* Process unlocked */
         __HAL_UNLOCK(hadc);
+        
         return HAL_TIMEOUT;
       }
     }
   }
   
-  /* Check if an injected conversion is ready */
-  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  /* Clear regular group conversion flag */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+  
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+  
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+  /*       The test of scan sequence on going is done either with scan        */
+  /*       sequence disabled or with end of conversion flag set to            */
+  /*       of end of sequence.                                                */
+  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+     (hadc->Init.ContinuousConvMode == DISABLE)            &&
+     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_REG;
+    /* Set ADC state */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+    
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    { 
+      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+    }
   }
   
   /* Return ADC state */
@@ -566,6 +668,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
   uint32_t tickstart = 0;
   
   /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
   assert_param(IS_ADC_EVENT_TYPE(EventType));
 
   /* Get tick */
@@ -577,32 +680,38 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
-        hadc->State= HAL_ADC_STATE_TIMEOUT;
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
         /* Process unlocked */
         __HAL_UNLOCK(hadc);
+        
         return HAL_TIMEOUT;
       }
     }
   }
   
-  /* Check analog watchdog flag */
+  /* Analog watchdog (level out of window) event */
   if(EventType == ADC_AWD_EVENT)
   {
-     /* Change ADC state */
-     hadc->State = HAL_ADC_STATE_AWD;
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
       
-     /* Clear the ADCx's analog watchdog flag */
-     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
   }
+  /* Overrun event */
   else
   {
-     /* Change ADC state */
-     hadc->State = HAL_ADC_STATE_ERROR;
-     
-     /* Clear the ADCx's Overrun flag */
-     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+    /* Set ADC error code to overrun */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
   }
   
   /* Return ADC state */
@@ -622,26 +731,12 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
   
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Check if an injected conversion is ongoing */
-  if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_REG;
-  } 
-  
-  /* Set ADC error code to none */
-  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-  
+  /* Enable the ADC peripheral */
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
      Tstab time the ADC's stabilization */
   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -658,32 +753,65 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     }
   }
   
-  /* Enable the ADC overrun interrupt */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-  
-  /* Enable the ADC end of conversion interrupt for regular group */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
-	
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Check if Multimode enabled */
-  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    /* if no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
     {
-      /* Enable the selected ADC software conversion for regular group */
-      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
     }
-  }
-  else
-  {
-    /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
     {
-      /* Enable the selected ADC software conversion for regular group */
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    
+    /* Enable end of conversion interrupt for regular group */
+    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
     }
   }
   
@@ -702,17 +830,27 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   */
 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
 {
-  /* Disable the ADC end of conversion interrupt for regular group */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
   
-  /* Disable the ADC end of conversion interrupt for injected group */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+  /* Process locked */
+  __HAL_LOCK(hadc);
   
-  /* Enable the Peripheral */
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
   __HAL_ADC_DISABLE(hadc);
   
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
   return HAL_OK;
@@ -738,55 +876,44 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
   /* Check End of conversion flag for regular channels */
   if(tmp1 && tmp2)
   {
-    /* Check if an injected conversion is ready */
-    if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
     {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
     }
-    else
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
     {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_EOC_REG;
-    }
-
-    if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-    {
-      if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
-      { 
-        /* DISABLE the ADC end of conversion interrupt for regular group */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-        
-        /* DISABLE the ADC overrun interrupt */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-      }
-      else
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
       {
-        if (hadc->NbrOfCurrentConversionRank == 0)
-        {
-          hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
-        }
-        
-        /* Decrement the number of conversion when an interrupt occurs */
-        hadc->NbrOfCurrentConversionRank--;
-        
-        /* Check if all conversions are finished */
-        if(hadc->NbrOfCurrentConversionRank == 0)
-        {
-          /* DISABLE the ADC end of conversion interrupt for regular group */
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-          
-          /* DISABLE the ADC overrun interrupt */
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-        }
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
       }
     }
     
     /* Conversion complete callback */ 
     HAL_ADC_ConvCpltCallback(hadc);
     
-   /* Clear the ADCx flag for regular end of conversion */
-    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
   }
   
   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
@@ -794,31 +921,41 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
   /* Check End of conversion flag for injected channels */
   if(tmp1 && tmp2)
   {
-    /* Check if a regular conversion is ready */
-    if(hadc->State == HAL_ADC_STATE_EOC_REG)
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
     {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
     }
-    else
+
+    /* Determine whether any further conversion upcoming on group injected  */
+    /* by external trigger, scan sequence on going or by automatic injected */
+    /* conversion from group regular (same conditions as group regular      */
+    /* interruption disabling above).                                       */
+    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+       (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+       (hadc->Init.ContinuousConvMode == DISABLE))))
     {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_EOC_INJ;
-    }
-    
-    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-    if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
-    {
-      /* DISABLE the ADC end of conversion interrupt for injected group */
+      /* Disable ADC end of single conversion interrupt on group injected */
       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
+
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+      { 
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
     }
-    
+
     /* Conversion complete callback */ 
     HAL_ADCEx_InjectedConvCpltCallback(hadc);
     
-   /* Clear the ADCx flag for injected end of conversion */
-    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
   }
   
   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
@@ -826,14 +963,17 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
   /* Check Analog watchdog flag */
   if(tmp1 && tmp2)
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_AWD;
+    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
       
-    /* Clear the ADCx's Analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
-    
-    /* Level out of window callback */ 
-    HAL_ADC_LevelOutOfWindowCallback(hadc);
+      /* Level out of window callback */ 
+      HAL_ADC_LevelOutOfWindowCallback(hadc);
+      
+      /* Clear the ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+    }
   }
   
   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
@@ -841,17 +981,21 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
   /* Check Overrun flag */
   if(tmp1 && tmp2)
   {
-    /* Change ADC state to overrun state */
-    hadc->State = HAL_ADC_STATE_ERROR;
+    /* Note: On STM32F7, ADC overrun can be set through other parameters    */
+    /*       refer to description of parameter "EOCSelection" for more      */
+    /*       details.                                                       */
     
     /* Set ADC error code to overrun */
-    hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
     
-    /* Clear the Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
     
     /* Error callback */ 
     HAL_ADC_ErrorCallback(hadc);
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
   }
 }
 
@@ -869,35 +1013,12 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
   
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Enable ADC overrun interrupt */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-  
-  /* Enable ADC DMA mode */
-  hadc->Instance->CR2 |= ADC_CR2_DMA;
-  
-  /* Set the DMA transfer complete callback */
-  hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-  
-  /* Set the DMA half transfer complete callback */
-  hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-     
-  /* Set the DMA error callback */
-  hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_BUSY_REG;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
+  /* Enable the ADC peripheral */
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
      Tstab time the ADC's stabilization */
   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -914,11 +1035,85 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     }
   }
   
-  /* if no external trigger present enable software conversion of regular channels */
-  if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    /* Enable the selected ADC software conversion for regular group */
-    hadc->Instance->CR2 |= ADC_CR2_SWSTART;
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);   
+
+    /* Set the DMA transfer complete callback */
+    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+    /* Set the DMA half transfer complete callback */
+    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+    
+    /* Set the DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+    
+    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+    /* start (in case of SW start):                                           */
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+    /* Enable ADC overrun interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Enable ADC DMA mode */
+    hadc->Instance->CR2 |= ADC_CR2_DMA;
+    
+    /* Start the DMA channel */
+    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
   }
   
   /* Return function status */
@@ -933,23 +1128,42 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
   */
 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
 {
-  /* Disable the Peripheral */
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
   __HAL_ADC_DISABLE(hadc);
   
-  /* Disable ADC overrun interrupt */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Disable the selected ADC DMA mode */
+    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* DMA transfer is on going)                                              */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
   
-  /* Disable the selected ADC DMA mode */
-  hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-  
-  /* Disable the ADC DMA Stream */
-  HAL_DMA_Abort(hadc->DMA_Handle);
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -972,6 +1186,8 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvCpltCallback could be implemented in the user file
    */
@@ -985,6 +1201,8 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
    */
@@ -998,6 +1216,8 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
    */
@@ -1011,6 +1231,8 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ErrorCallback could be implemented in the user file
    */
@@ -1056,15 +1278,23 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
   
   /* Process locked */
   __HAL_LOCK(hadc);
-    
-  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-  if (sConfig->Channel > ADC_CHANNEL_9)
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
-    
-    /* Set the new sample time */
-    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+			
+	/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+	if (sConfig->Channel > ADC_CHANNEL_9)
+	{
+		/* Clear the old sample time */
+		hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+
+		if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+		{
+			/* Set the new sample time */
+			hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
+		}
+	  else
+	  {	
+		  /* Set the new sample time */
+		  hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+	  }
   }
   else /* ADC_Channel include in ADC_Channel_[0..9] */
   {
@@ -1110,13 +1340,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
     ADC->CCR |= ADC_CCR_VBATE;
   }
   
-  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+  /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
   if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
   {
     /* Enable the TSVREFE channel*/
     ADC->CCR |= ADC_CCR_TSVREFE;
 
-    if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
     {
       /* Delay for temperature sensor stabilization time */
       /* Compute number of CPU cycles to wait for */
@@ -1137,6 +1367,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
 
 /**
   * @brief  Configures the analog watchdog.
+  * @note   Analog watchdog thresholds can be modified while ADC conversion
+  *         is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure 
@@ -1225,7 +1463,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   *         the configuration information for the specified ADC.
   * @retval HAL state
   */
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
 {
   /* Return ADC state */
   return hadc->State;
@@ -1346,21 +1584,49 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
   */
 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   
 {
+  /* Retrieve ADC handle corresponding to current DMA handle */
   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Check if an injected conversion is ready */
-  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+    {
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+    
+    /* Conversion complete callback */
+    HAL_ADC_ConvCpltCallback(hadc);
   }
   else
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_REG;
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
   }
-    
-  HAL_ADC_ConvCpltCallback(hadc); 
 }
 
 /**
@@ -1385,12 +1651,15 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
 static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
 {
   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hadc->State= HAL_ADC_STATE_ERROR;
+  hadc->State= HAL_ADC_STATE_ERROR_DMA;
   /* Set ADC error code to DMA error */
   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
   HAL_ADC_ErrorCallback(hadc); 
 }
 
+/**
+  * @}
+  */
 
 /**
   * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
index 236178b07c..fd054faa2e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
@@ -58,105 +58,97 @@
 /** @defgroup ADC_Exported_Types ADC Exported Types
   * @{
   */
-   
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_ADC_STATE_RESET                   = 0x00,    /*!< ADC not yet initialized or disabled */
-  HAL_ADC_STATE_READY                   = 0x01,    /*!< ADC peripheral ready for use */
-  HAL_ADC_STATE_BUSY                    = 0x02,    /*!< An internal process is ongoing */ 
-  HAL_ADC_STATE_BUSY_REG                = 0x12,    /*!< Regular conversion is ongoing */
-  HAL_ADC_STATE_BUSY_INJ                = 0x22,    /*!< Injected conversion is ongoing */
-  HAL_ADC_STATE_BUSY_INJ_REG            = 0x32,    /*!< Injected and regular conversion are ongoing */
-  HAL_ADC_STATE_TIMEOUT                 = 0x03,    /*!< Timeout state */
-  HAL_ADC_STATE_ERROR                   = 0x04,    /*!< ADC state error */
-  HAL_ADC_STATE_EOC                     = 0x05,    /*!< Conversion is completed */
-  HAL_ADC_STATE_EOC_REG                 = 0x15,    /*!< Regular conversion is completed */
-  HAL_ADC_STATE_EOC_INJ                 = 0x25,    /*!< Injected conversion is completed */
-  HAL_ADC_STATE_EOC_INJ_REG             = 0x35,    /*!< Injected and regular conversion are completed */
-  HAL_ADC_STATE_AWD                     = 0x06    /*!< ADC state analog watchdog */
-
-}HAL_ADC_StateTypeDef;
 
 /** 
-  * @brief   ADC Init structure definition  
-  */ 
+  * @brief  Structure definition of ADC and regular group initialization 
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
+  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
+  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
+  */
 typedef struct
 {
-  uint32_t ClockPrescaler;        /*!< Select the frequency of the clock to the ADC. The clock is common for 
+  uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for 
                                        all the ADCs.
                                        This parameter can be a value of @ref ADC_ClockPrescaler */
-  uint32_t Resolution;            /*!< Configures the ADC resolution dual mode. 
+  uint32_t Resolution;            /*!< Configures the ADC resolution.
                                        This parameter can be a value of @ref ADC_Resolution */
-  uint32_t DataAlign;             /*!< Specifies whether the ADC data  alignment is left or right.  
+  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
                                        This parameter can be a value of @ref ADC_data_align */
-  uint32_t ScanConvMode;          /*!< Specifies whether the conversion is performed in Scan (multi channels) or 
-                                       Single (one channel) mode.
-                                       This parameter can be set to ENABLE or DISABLE */ 
-  uint32_t EOCSelection;          /*!< Specifies whether the EOC flag is set 
-                                       at the end of single channel conversion or at the end of all conversions.
-                                       This parameter can be a value of @ref ADC_EOCSelection */
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in Continuous or Single mode.
+  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+                                                    Scan direction is upward: from rank1 to rank 'n'. */
+  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+                                       This parameter can be a value of @ref ADC_EOCSelection.
+                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+                                       after the selected trigger occurred (software start or external trigger).
                                        This parameter can be set to ENABLE or DISABLE. */
-  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
-                                       This parameter can be set to ENABLE or DISABLE. */ 
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ADC conversions that will be done using the sequencer for
-                                       regular channel group.
+  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not 
-                                       for regular channels.
+  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
                                        This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of ADC discontinuous conversions that will be done 
-                                       using the sequencer for regular channel group.
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular
-                                       Note: This parameter can be modified only if there is no conversion is ongoing. */
+                                       If set to external trigger source, triggering is on event rising edge by default.
+                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular
-                                       Note: This parameter can be modified only if there is no conversion is ongoing. */
+                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+                                       This parameter can be set to ENABLE or DISABLE. */
 }ADC_InitTypeDef;
 
-/** 
-  * @brief  ADC handle Structure definition
-  */ 
-typedef struct
-{
-  ADC_TypeDef                   *Instance;                   /*!< Register base address */
 
-  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
-
-  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
-
-  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
-
-  __IO HAL_ADC_StateTypeDef     State;                       /*!< ADC communication state */
-
-  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
-}ADC_HandleTypeDef;
 
 /** 
-  * @brief   ADC Configuration regular Channel structure definition
+  * @brief  Structure definition of ADC channel for regular group   
+  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC can be either disabled or enabled without conversion on going on regular group.
   */ 
 typedef struct 
 {
-  uint32_t Channel;        /*!< The ADC channel to configure. 
-                                This parameter can be a value of @ref ADC_channels */
-  uint32_t Rank;           /*!< The rank in the regular group sequencer. 
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-  uint32_t SamplingTime;   /*!< The sample time value to be set for the selected channel.
-                                This parameter can be a value of @ref ADC_sampling_times */
-  uint32_t Offset;         /*!< Reserved for future use, can be set to 0 */
+  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_channels */
+  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
+                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_sampling_times
+                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
 }ADC_ChannelConfTypeDef;
 
 /** 
-  * @brief   ADC Configuration multi-mode structure definition  
+  * @brief ADC Configuration multi-mode structure definition  
   */ 
 typedef struct
 {
@@ -174,30 +166,83 @@ typedef struct
                                    This parameter can be set to ENABLE or DISABLE */
   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
 }ADC_AnalogWDGConfTypeDef;
+
+/** 
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  */ 
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/** 
+  * @brief  ADC handle Structure definition
+  */ 
+typedef struct
+{
+  ADC_TypeDef                   *Instance;                   /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
+
+  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
+
+  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
+
+  __IO uint32_t                 State;                       /*!< ADC communication state */
+
+  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
+}ADC_HandleTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-
 /** @defgroup ADC_Exported_Constants ADC Exported Constants
   * @{
   */
 
-
 /** @defgroup ADC_Error_Code ADC Error Code
   * @{
-  */ 
-
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error             */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x01)   /*!< OVR error            */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x02)   /*!< DMA transfer error   */
+  */
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
+                                                          enable/disable, erroneous state                       */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
 /**
   * @}
-  */  
+  */
 
 
-/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
+/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
   * @{
   */ 
 #define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000)
@@ -258,6 +303,8 @@ typedef struct
   */
 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
 /*       compatibility with other STM32 devices.                              */
+
+
 #define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
@@ -275,11 +322,12 @@ typedef struct
 
 #define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)
 #define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
+
 /**
   * @}
   */ 
 
-/** @defgroup ADC_data_align ADC Data Align 
+/** @defgroup ADC_data_align ADC Data Align
   * @{
   */ 
 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
@@ -533,8 +581,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   * @{
   */
 /* Peripheral State functions ***************************************************/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /**
   * @}
   */
@@ -565,6 +613,52 @@ uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /** @defgroup ADC_Private_Macros ADC Private Macros
   * @{
   */
+/* Macro reserved for internal HAL driver usage, not intended to be used in
+   code of final user */
+
+/**
+  * @brief Verification of ADC state: enabled or disabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_IS_ENABLE(__HANDLE__)                                              \
+  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
+  ) ? SET : RESET)
+
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__: ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__: ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
+
+/**
+  * @brief Simultaneously clears and sets specific bits of the handle State
+  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Clear ADC error code (set it to error code: "no error")
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
+  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
index b985e0ed12..1a2a16575d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions
@@ -131,25 +131,25 @@
 /* Private define ------------------------------------------------------------*/ 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
 /** @addtogroup ADCEx_Private_Functions
   * @{
   */
+/* Private function prototypes -----------------------------------------------*/
 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
-static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
 /**
   * @}
   */
 
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
   * @{
-  */ 
+  */
 
-/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions
- *  @brief    Extended features functions  
- *
+/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions 
+  *  @brief    Extended features functions  
+  *
 @verbatim   
  ===============================================================================
                  ##### Extended features functions #####
@@ -182,17 +182,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Check if a regular conversion is ongoing */
-  if(hadc->State == HAL_ADC_STATE_BUSY_REG)
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ;
-  } 
+  /* Enable the ADC peripheral */
   
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
      Tstab time the ADC's stabilization */
@@ -201,7 +191,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     /* Enable the Peripheral */
     __HAL_ADC_ENABLE(hadc);
     
-    /* Delay for temperature sensor stabilization time */
+    /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
     while(counter != 0)
@@ -210,30 +200,57 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     }
   }
   
-  /* Check if Multimode enabled */
-  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-    if(tmp1 && tmp2)
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to injected group conversion results    */
+    /* - Set state bitfield related to injected operation                     */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                      HAL_ADC_STATE_INJ_BUSY);
+    
+    /* Check if a regular conversion is ongoing */
+    /* Note: On this device, there is no ADC error code fields related to     */
+    /*       conversions on group injected only. In case of conversion on     */
+    /*       going on group regular, no error code is reset.                  */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
     {
-      /* Enable the selected ADC software conversion for injected group */
-      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear injected group conversion flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if(tmp1 && tmp2)
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+    else
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
     }
   }
-  else
-  {
-    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-    if((hadc->Instance == ADC1) && tmp1 && tmp2)  
-    {
-      /* Enable the selected ADC software conversion for injected group */
-      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
   
   /* Return function status */
   return HAL_OK;
@@ -249,25 +266,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
 {
   __IO uint32_t counter = 0;
-  uint32_t tmp1 = 0, tmp2 =0;
+  uint32_t tmp1 = 0, tmp2 = 0;
   
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Check if a regular conversion is ongoing */
-  if(hadc->State == HAL_ADC_STATE_BUSY_REG)
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY_INJ;
-  }
-  
-  /* Set ADC error code to none */
-  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  /* Enable the ADC peripheral */
   
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
      Tstab time the ADC's stabilization */
@@ -276,7 +280,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     /* Enable the Peripheral */
     __HAL_ADC_ENABLE(hadc);
     
-    /* Delay for temperature sensor stabilization time */
+    /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
     while(counter != 0)
@@ -285,60 +289,122 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     }
   }
   
-  /* Enable the ADC end of conversion interrupt for injected group */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-  
-  /* Enable the ADC overrun interrupt */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-  
-  /* Check if Multimode enabled */
-  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-    if(tmp1 && tmp2)
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to injected group conversion results    */
+    /* - Set state bitfield related to injected operation                     */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                      HAL_ADC_STATE_INJ_BUSY);
+    
+    /* Check if a regular conversion is ongoing */
+    /* Note: On this device, there is no ADC error code fields related to     */
+    /*       conversions on group injected only. In case of conversion on     */
+    /*       going on group regular, no error code is reset.                  */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
     {
-      /* Enable the selected ADC software conversion for injected group */
-      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear injected group conversion flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+    
+    /* Enable end of conversion interrupt for injected channels */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if(tmp1 && tmp2)
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+    else
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
     }
   }
-  else
-  {
-    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-    if((hadc->Instance == ADC1) && tmp1 && tmp2)  
-    {
-      /* Enable the selected ADC software conversion for injected group */
-      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
   
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Disables ADC and stop conversion of injected channels.
-  *
-  * @note   Caution: This function will stop also regular channels.  
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
+  * @param  hadc: ADC handle
+  * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
 {
-  /* Disable the Peripheral */
-  __HAL_ADC_DISABLE(hadc);
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+    
+  /* Stop potential conversion and disable ADC peripheral                     */
+  /* Conditioned to:                                                          */
+  /* - No conversion on the other group (regular group) is intended to        */
+  /*   continue (injected and regular groups stop conversion and ADC disable  */
+  /*   are common)                                                            */
+  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
+  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+  {
+    /* Stop potential conversion on going, on regular and injected groups */
+    /* Disable ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -371,16 +437,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
     }
   }
   
-  /* Check if a regular conversion is ready */
-  if(hadc->State == HAL_ADC_STATE_EOC_REG)
+  /* Clear injected group conversion flag */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+    
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+  
+  /* Determine whether any further conversion upcoming on group injected      */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+  /*       The test of scan sequence on going is done either with scan        */
+  /*       sequence disabled or with end of conversion flag set to            */
+  /*       of end of sequence.                                                */
+  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
+     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
+      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-  }
-  else
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_INJ;
+    /* Set ADC state */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    { 
+      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+    }
   }
   
   /* Return ADC state */
@@ -388,30 +470,65 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
 }      
   
 /**
-  * @brief  Disables the interrupt and stop ADC conversion of injected channels.
-  * 
-  * @note   Caution: This function will stop also regular channels.  
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
+  * @brief  Stop conversion of injected channels, disable interruption of 
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @param  hadc: ADC handle
+  * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
 {
-  /* Disable the ADC end of conversion interrupt for regular group */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   
-  /* Disable the ADC end of conversion interrupt for injected group */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+    
+  /* Stop potential conversion and disable ADC peripheral                     */
+  /* Conditioned to:                                                          */
+  /* - No conversion on the other group (regular group) is intended to        */
+  /*   continue (injected and regular groups stop conversion and ADC disable  */
+  /*   are common)                                                            */
+  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
+  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+  {
+    /* Stop potential conversion on going, on regular and injected groups */
+    /* Disable ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+    {
+      /* Disable ADC end of conversion interrupt for injected channels */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+      
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+    tmp_hal_status = HAL_ERROR;
+  }
   
-  /* Enable the Peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
   
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -433,8 +550,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   /* Check the parameters */
   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
   
-   /* Clear the ADCx's flag for injected end of conversion */
-   __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+  /* Clear injected group conversion flag to have similar behaviour as        */
+  /* regular group: reading data register also clears end of conversion flag. */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
   
   /* Return the selected ADC converted value */ 
   switch(InjectedRank)
@@ -488,35 +606,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Enable ADC overrun interrupt */
-  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-  
-  if (hadc->Init.DMAContinuousRequests != DISABLE)
-  {
-    /* Enable the selected ADC DMA request after last transfer */
-    ADC->CCR |= ADC_CCR_DDS;
-  }
-  else
-  {
-    /* Disable the selected ADC EOC rising on each regular channel conversion */
-    ADC->CCR &= ~ADC_CCR_DDS;
-  }
-  
-  /* Set the DMA transfer complete callback */
-  hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
-  
-  /* Set the DMA half transfer complete callback */
-  hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
-     
-  /* Set the DMA error callback */
-  hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_BUSY_REG;
-  
   /* Check if ADC peripheral is disabled in order to enable it and wait during 
      Tstab time the ADC's stabilization */
   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -533,16 +622,81 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     }
   }
   
-  /* if no external trigger present enable software conversion of regular channels */
-  if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    /* Enable the selected ADC software conversion for regular group */
-    hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Set the DMA transfer complete callback */
+    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+    
+    /* Set the DMA half transfer complete callback */
+    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+    
+    /* Set the DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+    
+    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+    /* start (in case of SW start):                                           */
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+    /* Enable ADC overrun interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+    
+    if (hadc->Init.DMAContinuousRequests != DISABLE)
+    {
+      /* Enable the selected ADC DMA request after last transfer */
+      ADC->CCR |= ADC_CCR_DDS;
+    }
+    else
+    {
+      /* Disable the selected ADC EOC rising on each regular channel conversion */
+      ADC->CCR &= ~ADC_CCR_DDS;
+    }
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+    
+    /* if no external trigger present enable software conversion of regular channels */
+    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+    {
+      /* Enable the selected ADC software conversion for regular group */
+      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
   }
   
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
   /* Return function status */
   return HAL_OK;
 }
@@ -555,29 +709,42 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
 {
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
   /* Process locked */
   __HAL_LOCK(hadc);
   
-  /* Enable the Peripheral */
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
   __HAL_ADC_DISABLE(hadc);
   
-  /* Disable ADC overrun interrupt */
-  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-  
-  /* Disable the selected ADC DMA request after last transfer */
-  ADC->CCR &= ~ADC_CCR_DDS;
-  
-  /* Disable the ADC DMA Stream */
-  HAL_DMA_Abort(hadc->DMA_Handle);
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_READY;
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Disable the selected ADC DMA mode for multimode */
+    ADC->CCR &= ~ADC_CCR_DDS;
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* DMA transfer is on going)                                              */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
   
   /* Process unlocked */
   __HAL_UNLOCK(hadc);
-    
+  
   /* Return function status */
-  return HAL_OK;
+  return tmp_hal_status;
 }
 
 /**
@@ -601,6 +768,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
   */
 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
    */
@@ -616,7 +785,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
 {
-
+  
 #ifdef USE_FULL_ASSERT  
   uint32_t tmp = 0;
 #endif /* USE_FULL_ASSERT  */
@@ -626,7 +795,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
   assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
   assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
@@ -636,6 +804,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
 #endif /* USE_FULL_ASSERT  */
 
+  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
+  {
+    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+  }
+
   /* Process locked */
   __HAL_LOCK(hadc);
   
@@ -669,13 +842,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   /* Set the SQx bits for the selected rank */
   hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
 
-  /* Select external trigger to start conversion */
-  hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
-  hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
-  
-  /* Select external trigger polarity */
-  hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
-  hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+  /* Enable external trigger if trigger selection is different of software  */
+  /* start.                                                                 */
+  /* Note: This configuration keeps the hardware feature of parameter       */
+  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+  /*       software start.                                                  */ 
+  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+  {  
+    /* Select external trigger to start conversion */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+    
+    /* Select external trigger polarity */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+  }
+  else
+  {
+    /* Reset the external trigger */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+  }
   
   if (sConfigInjected->AutoInjectedConv != DISABLE)
   {
@@ -793,21 +980,49 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   */
 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   
 {
-    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Check if an injected conversion is ready */
-  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+    {
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+    
+    /* Conversion complete callback */
+    HAL_ADC_ConvCpltCallback(hadc);
   }
   else
   {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_EOC_REG;
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
   }
-    
-    HAL_ADC_ConvCpltCallback(hadc); 
 }
 
 /**
@@ -832,7 +1047,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   
 {
     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    hadc->State= HAL_ADC_STATE_ERROR;
+    hadc->State= HAL_ADC_STATE_ERROR_DMA;
     /* Set ADC error code to DMA error */
     hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
     HAL_ADC_ErrorCallback(hadc); 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
index 82cb5e3b02..12f0ac5efe 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of ADC HAL module.
   ******************************************************************************
   * @attention
@@ -60,33 +60,78 @@
   */
    
 /** 
-  * @brief   ADC Configuration injected Channel structure definition
-  */ 
+  * @brief  ADC Configuration injected Channel structure definition
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
+  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
+  */
 typedef struct 
 {
-  uint32_t InjectedChannel;                /*!< Configure the ADC injected channel.
-                                                This parameter can be a value of @ref ADC_channels */ 
-  uint32_t InjectedRank;                   /*!< The rank in the injected group sequencer
-                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ 
-  uint32_t InjectedSamplingTime;           /*!< The sample time value to be set for the selected channel.
-                                                This parameter can be a value of @ref ADC_sampling_times */
-  uint32_t InjectedOffset;                 /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
-                                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t InjectedNbrOfConversion;        /*!< Specifies the number of ADC conversions that will be done using the sequencer for
-                                                injected channel group.
-                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
-  uint32_t AutoInjectedConv;               /*!< Enables or disables the selected ADC automatic injected group 
-                                                conversion after regular one */
-  uint32_t InjectedDiscontinuousConvMode;  /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
-                                                This parameter can be set to ENABLE or DISABLE. */
-  uint32_t ExternalTrigInjecConvEdge;      /*!< Select the external trigger edge and enable the trigger of an injected channels. 
-                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
-  uint32_t ExternalTrigInjecConv;          /*!< Select the external event used to trigger the start of conversion of a injected channels.
-                                                This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
-}ADC_InjectionConfTypeDef;
+  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
+                                               This parameter can be a value of @ref ADC_channels
+                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
+                                               This parameter must be a value of @ref ADCEx_injected_channel_selection
+                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
+                                               Unit: ADC clock cycles
+                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+                                               This parameter can be a value of @ref ADC_sampling_times
+                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+                                               Offset value must be a positive number.
+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+                                               This parameter can be set to ENABLE or DISABLE.      
+                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+                                               If set to external trigger source, triggering is on event rising edge.
+                                               This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
+                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef; 
+/**
+  * @}
+  */
 
 /** 
-  * @brief   ADC Configuration multi-mode structure definition  
+  * @brief ADC Configuration multi-mode structure definition  
   */ 
 typedef struct
 {
@@ -167,6 +212,7 @@ typedef struct
 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
 /**
   * @}
   */ 
@@ -185,7 +231,7 @@ typedef struct
 /** @defgroup ADCEx_channels  ADC Specific Channels
   * @{
   */
-#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)    
+#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | 0x10000000)    
 /**
   * @}
   */
@@ -217,11 +263,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-uint32_t          HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t          HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void       HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
 
 /* Peripheral Control functions *************************************************/
 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
@@ -286,7 +332,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO))
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
+											((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
 #define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
 #define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
index 22e8c93f88..54d73f5865 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   CAN HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Controller Area Network (CAN) peripheral:
@@ -490,6 +490,8 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
   */
 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_MspInit could be implemented in the user file
    */ 
@@ -503,6 +505,8 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
   */
 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_MspDeInit could be implemented in the user file
    */ 
@@ -1120,8 +1124,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
   {
     /* Set CAN error code to EWG error */
     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
-    /* Clear Error Warning Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
   }
   
   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
@@ -1132,8 +1134,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
   {
     /* Set CAN error code to EPV error */
     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-    /* Clear Error Passive Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
   }
   
   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
@@ -1144,8 +1144,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
   {
     /* Set CAN error code to BOF error */
     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
-    /* Clear Bus-Off Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
   }
   
   tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
@@ -1192,6 +1190,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
   /* Call the Error call Back in case of Errors */
   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
   {
+    /* Clear ERRI Flag */ 
+    hcan->Instance->MSR = CAN_MSR_ERRI; 
     /* Set the CAN state ready to be able to start again the process */
     hcan->State = HAL_CAN_STATE_READY;
     /* Call Error callback function */
@@ -1207,6 +1207,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
   */
 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_TxCpltCallback could be implemented in the user file
    */
@@ -1220,6 +1222,8 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
   */
 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_RxCpltCallback could be implemented in the user file
    */
@@ -1233,6 +1237,8 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
   */
 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_ErrorCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
index 598cb9c84c..9478ba84b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -412,9 +412,12 @@ typedef struct
 #define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
 
 /* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
+#define CAN_FLAG_INAK              ((uint32_t)0x00000100)  /*!<  Initialization acknowledge flag */
 #define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI              ((uint32_t)0x00000102)  /*!<  Error flag */
+#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
 #define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
+
 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
          In this case the SLAK bit can be polled.*/
 
@@ -559,17 +562,13 @@ typedef struct
   *            @arg CAN_FLAG_WKU: Wake up Flag
   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
 
 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
   * @param  __HANDLE__: CAN Handle
@@ -600,7 +599,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
 
 /**
   * @brief  Cancel a transmit request.
@@ -609,9 +608,9 @@ typedef struct
   * @retval None
   */
 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
 
 /**
   * @brief  Enable or disable the DBG Freeze for CAN.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
index 7d896a6706..94aab9c56c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   CEC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the High Definition Multimedia Interface 
@@ -246,6 +246,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
   */
  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_MspInit can be implemented in the user file
    */ 
@@ -258,6 +260,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
   */
  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_MspDeInit can be implemented in the user file
    */ 
@@ -877,6 +881,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
   */
  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_TxCpltCallback can be implemented in the user file
    */ 
@@ -889,6 +895,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
   */
 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_TxCpltCallback can be implemented in the user file
    */
@@ -901,6 +909,8 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
   */
  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_ErrorCallback can be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
index acd1ceb50e..13d796e6a8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
index 9a17168689..a3c6fd2422 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
index c83d3dc4e4..69d3b4159a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
@@ -266,29 +266,6 @@ typedef struct
 
 
 /* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/** @brief Configures the SysTick clock source.
-  * @param __CLKSRC__: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__)                             \
-                            do {                                               \
-                                 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK)   \
-                                  {                                            \
-                                    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;   \
-                                  }                                            \
-                                 else                                          \
-                                    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;  \
-                                } while(0)
-/**
-  * @}
-  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup CORTEX_Exported_Functions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
index d15792f1f2..48218bee34 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -92,8 +92,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   */
 
 /** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
+  *  @brief    Initialization and Configuration functions. 
+  *
 @verbatim    
  ===============================================================================
             ##### Initialization and de-initialization functions #####
@@ -110,8 +110,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   */
 
 /**
-  * @brief  Initializes the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and creates the associated handle.
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
   * @param  hcrc: CRC handle
   * @retval HAL status
   */
@@ -140,7 +140,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
   /* check whether or not non-default generating polynomial has been 
    * picked up by user */
   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); 
-  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+  if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
   {
     /* initialize IP with default generating polynomial */
     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);  
@@ -149,7 +149,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
   else
   {
     /* initialize CRC IP with generating polynomial defined by user */
-    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+    if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
     {
       return HAL_ERROR;
     }
@@ -158,7 +158,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
   /* check whether or not non-default CRC initial value has been 
    * picked up by user */
   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
-  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+  if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
   {
     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);  
   }
@@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
 }
 
 /**
-  * @brief  DeInitializes the CRC peripheral.
+  * @brief  DeInitialize the CRC peripheral.
   * @param  hcrc: CRC handle
   * @retval HAL status
   */
@@ -229,24 +229,30 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 }
 
 /**
-  * @brief  Initializes the CRC MSP.
+  * @brief  Initialize the CRC MSP.
   * @param  hcrc: CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CRC_MspInit can be implemented in the user file
    */
 }
 
 /**
-  * @brief  DeInitializes the CRC MSP.
+  * @brief  DeInitialize the CRC MSP.
   * @param  hcrc: CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CRC_MspDeInit can be implemented in the user file
    */
@@ -257,8 +263,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
   */
 
 /** @defgroup HAL_CRC_Group2 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
+  *  @brief   Peripheral Control functions 
+  *
 @verbatim  
  ==============================================================================
                       ##### Peripheral Control functions #####
@@ -282,7 +288,13 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
   * @param  hcrc: CRC handle
   * @param  pBuffer: pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat.  
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@@ -328,14 +340,19 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
   return temp;
 }
 
-
 /**                  
   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
   *         starting with hcrc->Instance->INIT as initialization value.
   * @param  hcrc: CRC handle
   * @param  pBuffer: pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat.   
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */  
 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@@ -387,8 +404,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
   return temp;
 }
 
-
-
 /**             
   * @brief  Enter 8-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
@@ -409,20 +424,20 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
      hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
    }
    /* last bytes specific handling */
-   if ((BufferLength%4) != 0)
+   if((BufferLength%4) != 0)
    {
-     if  (BufferLength%4 == 1)
+     if(BufferLength%4 == 1)
      {
        *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
      }
-     if  (BufferLength%4 == 2)
+     if(BufferLength%4 == 2)
      {
-       *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
+       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
      }
-     if  (BufferLength%4 == 3)
+     if(BufferLength%4 == 3)
      {
-       *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
-       *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       
+       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
+       *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       
      }
    }
   
@@ -430,8 +445,6 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
   return hcrc->Instance->DR;
 }
 
-
-
 /**             
   * @brief  Enter 16-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
@@ -451,9 +464,9 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   {
     hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
   }
-  if ((BufferLength%2) != 0)
+  if((BufferLength%2) != 0)
   {
-       *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; 
+     *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; 
   }
    
   /* Return the CRC computed value */ 
@@ -465,8 +478,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   */
 
 /** @defgroup HAL_CRC_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
+  *  @brief    Peripheral State functions. 
+  *
 @verbatim   
  ==============================================================================
                       ##### Peripheral State functions #####
@@ -480,7 +493,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   */
 
 /**
-  * @brief  Returns the CRC state.
+  * @brief  Return the CRC state.
   * @param  hcrc: CRC handle
   * @retval HAL state
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
index e007eaaa26..3f410f3397 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
index 321bff351c..6578394eea 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extended CRC HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
index 707648e10b..183dcf81e3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CRC HAL extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
index f64e8f66c6..ea580363a7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   CRYP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cryptography (CRYP) peripheral:
@@ -103,7 +103,7 @@
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */
-#if defined(STM32F756xx)
+#if defined (STM32F756xx)
 /** @defgroup CRYP CRYP
   * @brief CRYP HAL module driver.
   * @{
@@ -691,6 +691,9 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
   */
 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_MspInit could be implemented in the user file
    */
@@ -704,6 +707,9 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
   */
 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_MspDeInit could be implemented in the user file
    */
@@ -2285,13 +2291,13 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
   * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pPlainData: Pointer to the plaintext buffer
   * @param  Timeout: Specify Timeout value  
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
 {
   /* Process Locked */
   __HAL_LOCK(hcryp);
@@ -2306,7 +2312,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -2365,13 +2371,13 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
   * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pPlainData: Pointer to the plaintext buffer
   * @param  Timeout: Specify Timeout value  
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
 {
   /* Process Locked */
   __HAL_LOCK(hcryp);
@@ -2386,7 +2392,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -3638,6 +3644,9 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
   */
 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_InCpltCallback could be implemented in the user file
    */ 
@@ -3651,6 +3660,9 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
   */
 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_OutCpltCallback could be implemented in the user file
    */
@@ -3664,6 +3676,9 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
   */
  __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_ErrorCallback could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
index d997ec45a9..0519501439 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
@@ -43,7 +43,7 @@
  extern "C" {
 #endif
 
-#if defined(STM32F756xx)
+#if defined (STM32F756xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
@@ -388,9 +388,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
   */  
 /* DES encryption/decryption using polling  ***********************************/
 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
 
 /* DES encryption/decryption using interrupt  *********************************/
 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
index fa0f50c8b8..83a154c0f6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extended CRYP HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of CRYP extension peripheral:
@@ -102,7 +102,7 @@
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */
-#if defined(STM32F756xx)
+#if defined (STM32F756xx)
 /** @defgroup CRYPEx CRYPEx
   * @brief CRYP Extension HAL module driver.
   * @{
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
index ed6d45f539..1130a8473a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of CRYP HAL Extension module.
   ******************************************************************************
   * @attention
@@ -43,7 +43,7 @@
  extern "C" {
 #endif
 
-#if defined(STM32F756xx)
+#if defined (STM32F756xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f7xx_hal_def.h"
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
index 5f92022879..2da067bb03 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -302,6 +302,9 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_MspInit could be implemented in the user file
    */ 
@@ -315,6 +318,9 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_MspDeInit could be implemented in the user file
    */ 
@@ -682,6 +688,9 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_ConvCpltCallback could be implemented in the user file
    */
@@ -695,6 +704,9 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+   
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
    */
@@ -708,6 +720,9 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
    */
@@ -721,6 +736,9 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
   */
 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
index 9556ef1eda..7a3ac21b99 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
index 3586c8a175..cc8e05ed0c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extended DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of DAC extension peripheral:
@@ -269,6 +269,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
   */
 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
    */
@@ -282,6 +285,9 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
    */
@@ -295,6 +301,9 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
   */
 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
    */
@@ -308,6 +317,9 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
   */
 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
index ff4b6fa62a..22040be664 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
index 2bd407e6b2..353465702a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DCMI HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -247,6 +247,9 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
   */
 __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_MspInit could be implemented in the user file
    */ 
@@ -260,6 +263,9 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
   */
 __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_MspDeInit could be implemented in the user file
    */
@@ -539,6 +545,9 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
   */
 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_ErrorCallback could be implemented in the user file
    */
@@ -565,6 +574,9 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
   */
 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
    */
@@ -578,6 +590,9 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
   */
 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_FrameEventCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
index cc2eb820f7..5e988718cc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
index 7be8a52141..866718bf05 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DCMI Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of DCMI extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
index 16d49c5863..cbf4c73e69 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DCMI Extension HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
index a9b7fcea43..5e46652dd7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
@@ -103,7 +103,7 @@ typedef enum
 
 #if (USE_RTOS == 1)
   /* Reserved for future use */
-  #error “USE_RTOS should be 0 in the current HAL release”
+  #error "USE_RTOS should be 0 in the current HAL release"
 #else
   #define __HAL_LOCK(__HANDLE__)                                           \
                                 do{                                        \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
index a0a7cb78a0..65cd18f0f1 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DMA HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -73,8 +73,6 @@
       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
       (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
-      (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
-      (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
@@ -128,6 +126,13 @@
 #ifdef HAL_DMA_MODULE_ENABLED
 
 /* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @addtogroup DMA_Private_Constants
@@ -143,6 +148,8 @@
   * @{
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+
 /**
   * @brief  Sets the DMA Transfer parameter.
   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
@@ -291,6 +298,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   /* Write to DMA Stream FCR */
   hdma->Instance->FCR = tmp;
 
+  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+  DMA_CalcBaseAndBitshift(hdma);
+	
   /* Initialize the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 
@@ -308,6 +319,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   */
 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 {
+	DMA_Base_Registers *regs;
+	
   /* Check the DMA peripheral state */
   if(hdma == NULL)
   {
@@ -341,12 +354,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   /* Reset DMA Streamx FIFO control register */
   hdma->Instance->FCR  = (uint32_t)0x00000021;
 
-  /* Clear all flags */
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+  /* Get DMA steam Base Address */  
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags at correct offset within the register */
+  regs->IFCR = 0x3F << hdma->StreamIndex;
 
   /* Initialize the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -440,20 +452,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
   /* Configure the source, destination address and the data length */
   DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 
-  /* Enable the transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
-  /* Enable the Half transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);  
-
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
-  /* Enable the FIFO Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
-
-  /* Enable the direct mode Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
+  /* Enable all interrupts */
+  hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
+  hdma->Instance->FCR |= DMA_IT_FE;
 
    /* Enable the Peripheral */
   __HAL_DMA_ENABLE(hdma);
@@ -523,26 +524,31 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   uint32_t temp, tmp, tmp1, tmp2;
   uint32_t tickstart = 0; 
 
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs;
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+	
   /* Get the level transfer complete flag */
   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
   {
     /* Transfer Complete flag */
-    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+		temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
   }
   else
   {
     /* Half Transfer Complete flag */
-    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+		temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
   }
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+  while((regs->ISR & temp) == RESET)
   {
-    tmp  = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-    tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
-    tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    tmp  = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
+    tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
+    tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
     if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
     {
       if(tmp != RESET)
@@ -551,7 +557,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
 
         /* Clear the transfer error flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
       }
       if(tmp1 != RESET)
       {
@@ -559,7 +565,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
  
         /* Clear the FIFO error flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
       }
       if(tmp2 != RESET)
       {
@@ -567,7 +573,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
 
         /* Clear the Direct Mode error flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
       }
       /* Change the DMA state */
       hdma->State= HAL_DMA_STATE_ERROR;
@@ -598,14 +604,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
 
   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
   {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+		
     /* Multi_Buffering mode enabled */
     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
     {
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-      /* Clear the transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
       /* Current memory buffer used is Memory 0 */
       if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
       {
@@ -621,11 +625,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     }
     else
     {
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-      /* Clear the transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 
-
       /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
          are complete) */
       hdma->State = HAL_DMA_STATE_READY_MEM0;
@@ -634,13 +633,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     __HAL_UNLOCK(hdma);
   }
   else
-  { 
+  {
+    /* Clear the half transfer complete flag */
+    regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+		
     /* Multi_Buffering mode enabled */
     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
     {
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
       /* Current memory buffer used is Memory 0 */
       if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
       {
@@ -656,9 +655,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     }
     else
     {
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
       /* Change DMA peripheral state */
       hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
     }
@@ -674,8 +670,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   */
 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 {
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs;
+
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+	
   /* Transfer Error Interrupt management ***************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+  if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
     {
@@ -683,7 +684,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
 
       /* Clear the transfer error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
@@ -702,7 +703,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     }
   }
   /* FIFO Error Interrupt management ******************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
+  if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
     {
@@ -710,7 +711,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
 
       /* Clear the FIFO error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
@@ -729,7 +730,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     }
   }
   /* Direct Mode Error Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
+  if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
     {
@@ -737,7 +738,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
 
       /* Clear the direct mode error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
@@ -756,7 +757,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     }
   }
   /* Half Transfer Complete Interrupt management ******************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+  if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
     { 
@@ -764,7 +765,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
       {
         /* Clear the half transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
 
         /* Current memory buffer used is Memory 0 */
         if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -788,7 +789,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
         }
         /* Clear the half transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
 
         /* Change DMA peripheral state */
         hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
@@ -802,14 +803,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     }
   }
   /* Transfer Complete Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+  if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
     {
       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
       {
         /* Clear the transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
 
         /* Current memory buffer used is Memory 1 */
         if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -839,7 +840,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
         }
         /* Clear the transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
 
         /* Update error code */
         hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
@@ -860,6 +861,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @}
   */
@@ -905,6 +907,33 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
   * @}
   */
 
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
+  
+  /* lookup table for necessary bitshift of flags within status registers */
+  static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
+  hdma->StreamIndex = flagBitshiftOffset[stream_number];
+  
+  if (stream_number > 3)
+  {
+    /* return pointer to HISR and HIFCR */
+    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
+  }
+  else
+  {
+    /* return pointer to LISR and LIFCR */
+    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
+  }
+  
+  return hdma->StreamBaseAddress;
+}
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
index 6b45bb77c0..2169eafac3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
@@ -165,6 +165,11 @@ typedef struct __DMA_HandleTypeDef
   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 
  __IO uint32_t              ErrorCode;                                                    /*!< DMA Error code                          */
+
+ uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
+
+ uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
+ 
 }DMA_HandleTypeDef;
 
 /**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
index 904e76173b..b184973736 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DMA2D HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the DMA2D peripheral:
@@ -292,6 +292,9 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
   */
 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DMA2D_MspInit could be implemented in the user file
    */ 
@@ -305,6 +308,9 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
   */
 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DMA2D_MspDeInit could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
index 08f9528fe4..7ec4d72c40 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DMA2D HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
index e5d77521ab..a498113142 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
index 0fc88a196e..16516c3342 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
index 684fd39dad..3d3cfccc7a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   ETH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Ethernet (ETH) peripheral:
@@ -114,8 +114,9 @@
 /** @defgroup ETH_Private_Constants ETH Private Constants
   * @{
   */
-#define LINKED_STATE_TIMEOUT_VALUE          ((uint32_t)2000)  /* 2000 ms */
-#define AUTONEGO_COMPLETED_TIMEOUT_VALUE    ((uint32_t)1000)  /* 1000 ms */
+#define ETH_TIMEOUT_SWRESET                 ((uint32_t)500)  
+#define ETH_TIMEOUT_LINKED_STATE          ((uint32_t)5000)  
+#define ETH_TIMEOUT_AUTONEGO_COMPLETED    ((uint32_t)5000) 
 
 /**
   * @}
@@ -208,9 +209,25 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   /* After reset all the registers holds their respective reset values */
   (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
   
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
   /* Wait for software reset */
   while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
   {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
+    {     
+      heth->State= HAL_ETH_STATE_TIMEOUT;
+  
+      /* Process Unlocked */
+      __HAL_UNLOCK(heth);
+    
+      /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are  
+         not available, please check your external PHY or the IO configuration */
+               
+      return HAL_TIMEOUT;
+    }
   }
   
   /*-------------------------------- MAC Initialization ----------------------*/
@@ -243,7 +260,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
     /* CSR Clock Range between 100-150 MHz */ 
     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
   }
-  else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */
+  else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
   {
     /* CSR Clock Range between 150-216 MHz */ 
     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;    
@@ -283,7 +300,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
       
       /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
+      if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
       {
         /* In case of write timeout */
         err = ETH_ERROR;
@@ -326,7 +343,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
       
       /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
+      if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
       {
         /* In case of write timeout */
         err = ETH_ERROR;
@@ -589,6 +606,9 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
   */
 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_MspInit could be implemented in the user file
   */
@@ -602,6 +622,9 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
   */
 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_MspDeInit could be implemented in the user file
   */
@@ -981,6 +1004,9 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
   */
 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
   */ 
@@ -994,6 +1020,9 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
   */
 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
   */ 
@@ -1007,6 +1036,9 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
   */
 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
   */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
index 051dcb0dfe..7da1aede1c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of ETH HAL module.
   ******************************************************************************
   * @attention
@@ -66,10 +66,6 @@
                                   ((MODE) == ETH_MODE_HALFDUPLEX))
 #define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
                                  ((MODE) == ETH_RXINTERRUPT_MODE)) 
-#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
-                                 ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
-                                 ((MODE) == ETH_RXINTERRUPT_MODE))
 #define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
                                       ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
 #define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
index 129f174d1a..8ac63516bc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -415,8 +415,8 @@ void HAL_FLASH_IRQHandler(void)
         temp = pFlash.Address;
         break;
       }
-			default :
-				break;
+    default :
+      break;
     }
     /*Save the Error code*/
     FLASH_SetErrorCode();
@@ -455,9 +455,11 @@ void HAL_FLASH_IRQHandler(void)
   */
 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
+  the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+  */ 
 }
 
 /**
@@ -471,8 +473,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
   */
 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+  the HAL_FLASH_OperationErrorCallback could be implemented in the user file
    */ 
 }
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
index d93fc5b15b..2dce315d68 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
@@ -80,7 +80,7 @@ typedef struct
   
   __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */
   
-  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context    */
+  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */
   
   __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */
   
@@ -88,7 +88,7 @@ typedef struct
   
   HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */
 
-  __IO uint32_t               ErrorCode;          /* FLASH error code                    */
+  __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */
 
 }FLASH_ProcessTypeDef;
 
@@ -346,6 +346,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
   * @{
   */
 
+/** 
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
+  */ 
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
index 0d91b41d13..2cf7f3b4dc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
@@ -120,7 +120,7 @@ extern FLASH_ProcessTypeDef pFlash;
 static void               FLASH_MassErase(uint8_t VoltageRange);
 static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);
 static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);
-static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint32_t Level);
+static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
 static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
 static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
 static HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
@@ -281,7 +281,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 }
 
 /**
-  * @brief   Program option bytes
+  * @brief  Program option bytes
   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
   *         contains the configuration information for the programming.
   * 
@@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 {
   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
-	                      OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
 
   /*Get WRP*/
   pOBInit->WRPSector = FLASH_OB_GetWRP();
@@ -377,10 +377,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 
   /*Get BOR Level*/
   pOBInit->BORLevel = FLASH_OB_GetBOR();
-	
-	/*Get Boot Address when Boot pin = 0 */
+  
+  /*Get Boot Address when Boot pin = 0 */
   pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
-	
+  
   /*Get Boot Address when Boot pin = 1 */
   pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
 }
@@ -406,16 +406,13 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
   */
 static void FLASH_MassErase(uint8_t VoltageRange)
 {
-  uint32_t tmp_psize = 0;
-  
   /* Check the parameters */
   assert_param(IS_VOLTAGERANGE(VoltageRange));
 
   /* if the previous operation is completed, proceed to erase all sectors */
   FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= tmp_psize;
   FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT;
+  FLASH->CR |= FLASH_CR_STRT | (VoltageRange <<8);
   /* Data synchronous Barrier (DSB) Just after the write operation
      This will force the CPU to respect the sequence of instruction (no optimization).*/
   __DSB();
@@ -479,9 +476,8 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
   *
   * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash sector i if CortexM4  
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
+  *         it is not possible to program or erase the flash sector i if CortexM7  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1    
   * 
   * @param  WRPSector: specifies the sector(s) to be write protected.
   *          This parameter can be one of the following values:
@@ -543,9 +539,6 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
   return status;
 }
 
-
-
-
 /**
   * @brief  Set the read protection level.
   * @param  Level: specifies the read protection level.
@@ -558,7 +551,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
   *    
   * @retval HAL Status
   */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
 {
   HAL_StatusTypeDef status = HAL_OK;
   
@@ -570,7 +563,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
 
   if(status == HAL_OK)
   { 
-    MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);
+    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
   }
   
   return status;
@@ -604,7 +597,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
   *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY           
   * @retval HAL Status
   */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
 {
   uint32_t useroptionmask = 0x00;
   uint32_t useroptionvalue = 0x00;
@@ -687,17 +680,17 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_
     
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
+  
   if(status == HAL_OK)
   {
     if(BootOption == OPTIONBYTE_BOOTADDR_0)
     {			
       MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
-	  }
-		else
-		{
-			MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
-		}
+    }
+    else
+    {
+      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
+    }
   }
   
   return status;
@@ -736,11 +729,11 @@ static uint8_t FLASH_OB_GetRDP(void)
 {
   uint8_t readstatus = OB_RDP_LEVEL_0;
   
-  if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
+  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
   {
     readstatus = OB_RDP_LEVEL_0;
   }
-  else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
+  else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
   {
     readstatus = OB_RDP_LEVEL_2;
   }
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
index fa55ca57e7..3a2512150b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
@@ -89,7 +89,7 @@ typedef struct
   uint32_t WRPState;     /*!< Write protection activation or deactivation.
                               This parameter can be a value of @ref FLASHEx_WRP_State */
 
-  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
+  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
                               The value of this parameter depend on device used within the same series */
 
   uint32_t RDPLevel;     /*!< Set the read protection level.
@@ -212,7 +212,7 @@ typedef struct
   * @{
   */
 #define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
-#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */
+#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000) /*!< IWDG counter active in STOP mode */
 /**
   * @}
   */
@@ -248,7 +248,6 @@ typedef struct
 #define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000)  /*!< Boot from DTCM RAM (0x20000000)                 */
 #define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004)  /*!< Boot from SRAM1 (0x20010000)                    */
 #define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013)  /*!< Boot from SRAM2 (0x2004C000)                    */
-
 /**
   * @}
   */
@@ -313,8 +312,6 @@ typedef struct
 #define OB_WRP_SECTOR_7       ((uint32_t)0x00800000) /*!< Write protection of Sector7     */
 #define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
 
-
-
 /**
   * @}
   */
@@ -423,17 +420,17 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
                                    ((LATENCY) == FLASH_LATENCY_14) || \
                                    ((LATENCY) == FLASH_LATENCY_15))
 
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
+
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
 
-
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
-
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-
 #define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
+
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
index ffc7e08932..b400e1559c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -514,6 +514,9 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
   */
 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_GPIO_EXTI_Callback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
index 5ae5430556..f7db1cbb69 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
@@ -157,10 +157,10 @@ typedef enum
   * @brief GPIO Output Maximum frequency
   * @{
   */  
-#define  GPIO_SPEED_LOW         ((uint32_t)0x00000000)  /*!< Low speed     */
-#define  GPIO_SPEED_MEDIUM      ((uint32_t)0x00000001)  /*!< Medium speed  */
-#define  GPIO_SPEED_FAST        ((uint32_t)0x00000002)  /*!< Fast speed    */
-#define  GPIO_SPEED_HIGH        ((uint32_t)0x00000003)  /*!< High speed    */
+#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003)  /*!< High speed    */
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
index f4a25b224b..0486d4290b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
@@ -96,7 +96,6 @@
 #define GPIO_AF3_LPTIM1        ((uint8_t)0x03)  /* LPTIM1 Alternate Function mapping */
 #define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping */
 
-
 /** 
   * @brief   AF 4 selection  
   */ 
@@ -132,7 +131,6 @@
 #define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIF-RX Alternate Function mapping   */
 #define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping       */
 #define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping       */
-
 /** 
   * @brief   AF 8 selection  
   */ 
@@ -154,9 +152,9 @@
 #define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
 #define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
 #define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping */
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined(STM32F746xx) || defined(STM32F756xx)
 #define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 /** 
   * @brief   AF 10 selection  
   */ 
@@ -182,12 +180,12 @@
   */ 
 #define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
 
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined(STM32F746xx) || defined(STM32F756xx)
 /** 
   * @brief   AF 14 selection  
   */
 #define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 /** 
   * @brief   AF 15 selection  
   */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
index b75e961911..961f6ad3ec 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the HASH peripheral:
@@ -428,6 +428,9 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
   */
 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_HASH_MspInit could be implemented in the user file
    */
@@ -441,6 +444,9 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
   */
 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_HASH_MspDeInit could be implemented in the user file
    */
@@ -454,6 +460,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
   */
  __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_HASH_InCpltCallback could be implemented in the user file
    */ 
@@ -467,6 +476,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
   */
  __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_HASH_ErrorCallback could be implemented in the user file
    */ 
@@ -481,6 +493,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
   */
  __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_HASH_DgstCpltCallback could be implemented in the user file
    */ 
@@ -1836,7 +1851,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
   *         the configuration information for HASH module
   * @retval HAL state
   */
-HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
 {
   return hhash->State;
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
index 1b7be41300..2541b3ded7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention
@@ -90,7 +90,7 @@ typedef enum
   HAL_HASH_STATE_BUSY      = 0x02,  /*!< HASH internal process is ongoing     */
   HAL_HASH_STATE_TIMEOUT   = 0x03,  /*!< HASH timeout state                   */
   HAL_HASH_STATE_ERROR     = 0x04   /*!< HASH error state                     */
-}HAL_HASH_STATETypeDef;
+}HAL_HASH_StateTypeDef;
 
 /** 
   * @}
@@ -130,13 +130,13 @@ typedef struct
 
       HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
 
-      HAL_HASHPhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
+      HAL_HASH_PhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
 
       DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
 
       HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
 
-     __IO HAL_HASH_STATETypeDef  State;             /*!< HASH peripheral state          */
+     __IO HAL_HASH_StateTypeDef  State;             /*!< HASH peripheral state          */
 } HASH_HandleTypeDef;
 
 /** 
@@ -352,7 +352,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /** @addtogroup HASH_Exported_Functions_Group8
   * @{
   */
-HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
index 12f82fb31a..c8ad5b3258 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HASH HAL Extension module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of HASH peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
index e6ad9895cd..63c0887bcc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of HASH HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
index 99e408367d..d402cfa096 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -26,8 +26,9 @@
 
     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
         (##) Enable the HCD/USB Low Level interface clock using the following macros
-             (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
-             (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
+             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
            
         (##) Initialize the related GPIO clocks
         (##) Configure HCD pin-out
@@ -77,7 +78,8 @@
   * @{
   */
 
-/** @addtogroup HCD
+/** @defgroup HCD HCD 
+  * @brief HCD HAL module driver
   * @{
   */
 
@@ -88,7 +90,7 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function ----------------------------------------------------------*/
-/** @addtogroup HCD_Private_Functions
+/** @defgroup HCD_Private_Functions HCD Private Functions
   * @{
   */
 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
@@ -100,12 +102,12 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
   * @{
   */
 
-/** @addtogroup HCD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
  *
 @verbatim    
  ===============================================================================
@@ -118,7 +120,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
   */
 
 /**
-  * @brief  Initialize the host driver
+  * @brief  Initialize the host driver.
   * @param  hhcd: HCD handle
   * @retval HAL status
   */
@@ -156,7 +158,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Initialize a host channel
+  * @brief  Initialize a host channel.
   * @param  hhcd: HCD handle
   * @param  ch_num: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -212,7 +214,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
 }
 
 /**
-  * @brief  Halt a host channel
+  * @brief  Halt a host channel.
   * @param  hhcd: HCD handle
   * @param  ch_num: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -230,7 +232,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
 }
 
 /**
-  * @brief  DeInitialize the host driver
+  * @brief  DeInitialize the host driver.
   * @param  hhcd: HCD handle
   * @retval HAL status
   */
@@ -255,24 +257,30 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Initializes the HCD MSP.
+  * @brief  Initialize the HCD MSP.
   * @param  hhcd: HCD handle
   * @retval None
   */
 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_MspInit could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DeInitializes HCD MSP.
+  * @brief  DeInitialize the HCD MSP.
   * @param  hhcd: HCD handle
   * @retval None
   */
 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_MspDeInit could be implemented in the user file
    */
@@ -282,14 +290,14 @@ __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
   * @}
   */
 
-/** @addtogroup HCD_Exported_Functions_Group2
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
   *  @brief   HCD IO operation functions
   *
 @verbatim
  ===============================================================================
                       ##### IO operation functions #####
  ===============================================================================
-    This subsection provides a set of functions allowing to manage the USB Host Data 
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data 
     Transfer
        
 @endverbatim
@@ -297,7 +305,7 @@ __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
   */
   
 /**                                
-  * @brief  Submit a new URB for processing 
+  * @brief  Submit a new URB for processing. 
   * @param  hhcd: HCD handle
   * @param  ch_num: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -440,7 +448,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
 }
 
 /**
-  * @brief  This function handles HCD interrupt request.
+  * @brief  Handle HCD interrupt request.
   * @param  hhcd: HCD handle
   * @retval None
   */
@@ -549,30 +557,39 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
   */
 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_SOF_Callback could be implemented in the user file
    */
 }
 
 /**
-  * @brief Connexion Event callback.
+  * @brief Connection Event callback.
   * @param  hhcd: HCD handle
   * @retval None
   */
 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_Connect_Callback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Disconnexion Event callback.
+  * @brief  Disconnection Event callback.
   * @param  hhcd: HCD handle
   * @retval None
   */
 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_Disconnect_Callback could be implemented in the user file
    */
@@ -595,6 +612,9 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
   */
 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
    */
@@ -604,8 +624,8 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
   * @}
   */
 
-/** @addtogroup HCD_Exported_Functions_Group3
- *  @brief   Peripheral management functions 
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   Management functions 
  *
 @verbatim   
  ===============================================================================
@@ -620,7 +640,7 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
   */
 
 /**
-  * @brief  Start the host driver
+  * @brief  Start the host driver.
   * @param  hhcd: HCD handle
   * @retval HAL status
   */
@@ -634,7 +654,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Stop the host driver
+  * @brief  Stop the host driver.
   * @param  hhcd: HCD handle
   * @retval HAL status
   */
@@ -648,7 +668,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Reset the host port
+  * @brief  Reset the host port.
   * @param  hhcd: HCD handle
   * @retval HAL status
   */
@@ -661,7 +681,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
   * @}
   */
 
-/** @addtogroup HCD_Exported_Functions_Group4
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions 
  *  @brief   Peripheral State functions 
  *
 @verbatim   
@@ -677,7 +697,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
   */
 
 /**
-  * @brief  Return the HCD state
+  * @brief  Return the HCD handle state.
   * @param  hhcd: HCD handle
   * @retval HAL state
   */
@@ -687,7 +707,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Return  URB state for a channel
+  * @brief  Return  URB state for a channel.
   * @param  hhcd: HCD handle
   * @param  chnum: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -698,7 +718,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
   *            URB_NOTREADY/
   *            URB_NYET/ 
   *            URB_ERROR/  
-  *            URB_STALL/
+  *            URB_STALL
   */
 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
@@ -707,7 +727,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
 
 
 /**
-  * @brief  Return the last host transfer size
+  * @brief  Return the last host transfer size.
   * @param  hhcd: HCD handle
   * @param  chnum: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -719,12 +739,12 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 }
   
 /**
-  * @brief  Return the Host Channel state
+  * @brief  Return the Host Channel state.
   * @param  hhcd: HCD handle
   * @param  chnum: Channel number.
   *         This parameter can be a value from 1 to 15
   * @retval Host channel state
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            HC_IDLE/
   *            HC_XFRC/
   *            HC_HALTED/
@@ -733,7 +753,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
   *            HC_STALL/ 
   *            HC_XACTERR/  
   *            HC_BBLERR/  
-  *            HC_DATATGLERR/    
+  *            HC_DATATGLERR   
   */
 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
@@ -741,7 +761,7 @@ HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 }
 
 /**
-  * @brief  Return the current Host frame number
+  * @brief  Return the current Host frame number.
   * @param  hhcd: HCD handle
   * @retval Current Host frame number
   */
@@ -751,7 +771,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  Return the Host enumeration speed
+  * @brief  Return the Host enumeration speed.
   * @param  hhcd: HCD handle
   * @retval Enumeration speed
   */
@@ -759,6 +779,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
 {
   return (USB_GetHostSpeed(hhcd->Instance));
 }
+
 /**
   * @}
   */
@@ -771,7 +792,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
   * @{
   */
 /**
-  * @brief  This function handles Host Channel IN interrupt requests.
+  * @brief  Handle Host Channel IN interrupt requests.
   * @param  hhcd: HCD handle
   * @param  chnum: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -780,7 +801,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
 static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-    
+  uint32_t tmpreg = 0;
+  
   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
   {
     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
@@ -874,8 +896,10 @@ static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
       }
       
       /* re-activate the channel  */
-      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
-      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;      
+      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(chnum)->HCCHAR = tmpreg;    
     }
     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
@@ -896,22 +920,22 @@ static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
       __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
       USB_HC_Halt(hhcd->Instance, chnum);  
     }
-    
-    hhcd->hc[chnum].state = HC_NAK;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-     
-    if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+    else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
     {
       /* re-activate the channel  */
-      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
-      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(chnum)->HCCHAR = tmpreg;
     }
+    hhcd->hc[chnum].state = HC_NAK;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
   }
 }
 
 /**
-  * @brief  This function handles Host Channel OUT interrupt requests.
+  * @brief  Handle Host Channel OUT interrupt requests.
   * @param  hhcd: HCD handle
   * @param  chnum: Channel number.
   *         This parameter can be a value from 1 to 15
@@ -920,6 +944,7 @@ static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
 static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t tmpreg = 0;
   
   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
   {
@@ -1043,8 +1068,10 @@ static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
       }
       
       /* re-activate the channel  */
-      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
-      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;      
+      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(chnum)->HCCHAR = tmpreg;   
     }
     
     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
@@ -1053,7 +1080,7 @@ static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
 } 
 
 /**
-  * @brief  This function handles Rx Queue Level interrupt requests.
+  * @brief  Handle Rx Queue Level interrupt requests.
   * @param  hhcd: HCD handle
   * @retval none
   */
@@ -1064,6 +1091,7 @@ static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
   uint32_t                      pktsts;
   uint32_t                      pktcnt; 
   uint32_t                      temp = 0;
+  uint32_t tmpreg = 0;
   
   temp = hhcd->Instance->GRXSTSP ;
   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;  
@@ -1086,8 +1114,10 @@ static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
       {
         /* re-activate the channel when more packets are expected */
-        USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; 
-        USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+        tmpreg = USBx_HC(channelnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(channelnum)->HCCHAR = tmpreg;
         hhcd->hc[channelnum].toggle_in ^= 1;
       }
     }
@@ -1103,7 +1133,7 @@ static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
 }
 
 /**
-  * @brief  This function handles Host Port interrupt requests.
+  * @brief  Handle Host Port interrupt requests.
   * @param  hhcd: HCD handle
   * @retval None
   */
@@ -1187,6 +1217,10 @@ static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
   * @}
   */
 
+/**
+  * @}
+  */
+  
 #endif /* HAL_HCD_MODULE_ENABLED */
 /**
   * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
index 855b6f6112..db7cd6eddd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention
@@ -105,6 +105,7 @@ typedef struct
 /** @defgroup HCD_Exported_Constants HCD Exported Constants
   * @{
   */
+
 /** @defgroup HCD_Speed HCD Speed
   * @{
   */
@@ -150,7 +151,7 @@ typedef struct
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Functions HCD Exported Functions
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
   * @{
   */
 
@@ -174,7 +175,8 @@ void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
   * @}
   */
 
-/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
+/* I/O operation functions  ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
 HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
@@ -198,7 +200,8 @@ void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
   * @}
   */
 
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
 HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
@@ -208,7 +211,8 @@ HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
   * @}
   */
 
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+/* Peripheral State functions  ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
index 40142f8159..4f39b45d5a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -37,7 +37,7 @@
             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
 
-    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode,
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
 
     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 
@@ -66,16 +66,16 @@
     ===================================
     [..]
       (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
       (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
       (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
       (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_I2C_ErrorCallback
@@ -85,11 +85,11 @@
     [..]
       (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
           HAL_I2C_Mem_Write_IT()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
       (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
           HAL_I2C_Mem_Read_IT()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_I2C_ErrorCallback
@@ -99,19 +99,19 @@
     [..]
       (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
           HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
       (+) Receive in master mode an amount of data in non blocking mode (DMA) using
           HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
       (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
           HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
       (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
           HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_I2C_ErrorCallback
@@ -121,11 +121,11 @@
     [..]
       (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
           HAL_I2C_Mem_Write_DMA()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+      (+) At Memory end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
       (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
           HAL_I2C_Mem_Read_DMA()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+      (+) At Memory end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_I2C_ErrorCallback
@@ -138,7 +138,7 @@
 
       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+      (+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not
       (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
@@ -184,7 +184,7 @@
   * @{
   */
 
-/** @defgroup I2C I2C
+/** @defgroup I2C I2C HAL module driver
   * @brief I2C HAL module driver
   * @{
   */
@@ -197,15 +197,15 @@
   * @{
   */
 #define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR    ((uint32_t)10000)  /* 10 s  */
-#define I2C_TIMEOUT_BUSY    ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_DIR     ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_RXNE    ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_STOPF   ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_TC      ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_TCR     ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_TXIS    ((uint32_t)25)     /* 25 ms */
-#define I2C_TIMEOUT_FLAG    ((uint32_t)25)     /* 25 ms */
+#define I2C_TIMEOUT_ADDR    ((uint32_t)10000)       /* 10 s  */
+#define I2C_TIMEOUT_BUSY    ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_DIR     ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_RXNE    ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_STOPF   ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_TC      ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_TCR     ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_TXIS    ((uint32_t)25)          /* 25 ms */
+#define I2C_TIMEOUT_FLAG    ((uint32_t)25)          /* 25 ms */
 /**
   * @}
   */ 
@@ -406,6 +406,9 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_MspInit could be implemented in the user file
    */ 
@@ -419,6 +422,9 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_MspDeInit could be implemented in the user file
    */ 
@@ -500,7 +506,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t sizetmp = 0;
-
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {    
     if((pData == NULL ) || (Size == 0)) 
@@ -512,7 +518,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -532,7 +538,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
       I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
       sizetmp = Size;
     }
-      
+    
     do
     {
       /* Wait until TXIS flag is set */
@@ -551,10 +557,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
       hi2c->Instance->TXDR = (*pData++);
       sizetmp--;
       Size--;
-
+      
       if((sizetmp == 0)&&(Size!=0))
       {
-        /* Wait until TXE flag is set */
+        /* Wait until TCR flag is set */
         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)      
         {
           return HAL_TIMEOUT;
@@ -571,7 +577,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
           sizetmp = Size;
         }
       }
-
+      
     }while(Size > 0);
     
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
@@ -593,12 +599,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
+    
     hi2c->State = HAL_I2C_STATE_READY; 	  
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
+    
     return HAL_OK;
   }
   else
@@ -620,7 +626,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t sizetmp = 0;
-
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {    
     if((pData == NULL ) || (Size == 0)) 
@@ -632,7 +638,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -656,16 +662,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
     do
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)      
+      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)      
       {
-        return HAL_TIMEOUT;
-      }
-     
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          return HAL_ERROR;
+        }
+        else
+        {
+          return HAL_TIMEOUT;
+        }
+	  }
+      
       /* Write data to RXDR */
       (*pData++) =hi2c->Instance->RXDR;
       sizetmp--;
       Size--;
-
+      
       if((sizetmp == 0)&&(Size!=0))
       {
         /* Wait until TCR flag is set */
@@ -685,7 +698,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
           sizetmp = Size;
         }
       }
-
+      
     }while(Size > 0);
     
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
@@ -747,7 +760,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     /* Wait until ADDR flag is set */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)      
     {
@@ -758,7 +771,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
+    
     /* If 10bit addressing mode is selected */
     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
@@ -769,11 +782,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
         return HAL_TIMEOUT;
       }
-    
+      
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
     }
-
+    
     /* Wait until DIR flag is set Transmitter mode */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)      
     {
@@ -781,7 +794,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     do
     {
       /* Wait until TXIS flag is set */
@@ -789,7 +802,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+        
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
           return HAL_ERROR;
@@ -810,12 +823,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+      
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
-	/* Normal use case for Transmitter mode */
-	/* A NACK is generated to confirm the end of transfer */
-	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
       }
       else
       {
@@ -836,7 +849,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     
     /* Disable Address Acknowledge */
     hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+    
     hi2c->State = HAL_I2C_STATE_READY;
     
     /* Process Unlocked */
@@ -876,7 +889,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     /* Wait until ADDR flag is set */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)      
     {
@@ -884,7 +897,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
     
@@ -895,7 +908,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     while(Size > 0)
     {
       /* Wait until RXNE flag is set */
@@ -903,6 +916,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        
+        /* Store Last receive data if any */
+        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          (*pData++) = hi2c->Instance->RXDR;
+        }
+        
         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
         {
           return HAL_TIMEOUT;
@@ -923,7 +944,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+      
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
@@ -933,7 +954,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Clear STOP flag */
     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
     
@@ -944,13 +965,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     
     /* Disable Address Acknowledge */
     hi2c->Instance->CR2 |= I2C_CR2_NACK;
     
     hi2c->State = HAL_I2C_STATE_READY;
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
     
@@ -984,7 +1005,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1015,17 +1036,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    
+    
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
-        
+    
     return HAL_OK;
   }
   else
@@ -1056,7 +1077,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1087,10 +1108,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
     
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
@@ -1130,17 +1151,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     hi2c->pBuffPtr = pData;
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
     
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
@@ -1180,17 +1201,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     hi2c->pBuffPtr = pData;
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
     
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
@@ -1222,12 +1243,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
     {
       return  HAL_ERROR;                                    
     }     
-
+    
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1264,13 +1285,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
     {
       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
     }  
-
+    
     /* Wait until TXIS flag is set */
     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+      
+      /* Abort DMA */
+      HAL_DMA_Abort(hi2c->hdmatx);
+      
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
@@ -1280,7 +1304,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
         return HAL_TIMEOUT;
       }
     }
-
     
     /* Enable DMA Request */
     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;   
@@ -1313,12 +1336,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
     {
       return  HAL_ERROR;                                    
     }  
-
+    
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1355,13 +1378,22 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
     {
       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
     }
-
+    
     /* Wait until RXNE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)      
+    if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)      
     {
-      return HAL_TIMEOUT;
-    }
-
+      /* Abort DMA */
+      HAL_DMA_Abort(hi2c->hdmarx);
+      
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+	}
     
     /* Enable DMA Request */
     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;   
@@ -1414,7 +1446,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     /* Wait until ADDR flag is set */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)      
     {
@@ -1422,7 +1454,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
     
@@ -1436,7 +1468,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
         return HAL_TIMEOUT;
       }
-
+      
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
     }
@@ -1448,7 +1480,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-      
+    
     /* Enable DMA Request */
     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 
     
@@ -1500,7 +1532,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     
     /* Enable Address Acknowledge */
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
+    
     /* Wait until ADDR flag is set */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)      
     {
@@ -1508,7 +1540,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
-
+    
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
     
@@ -1519,7 +1551,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
- 
+    
     /* Enable DMA Request */
     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;  
     
@@ -1548,7 +1580,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t Sizetmp = 0;
-
+  
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
   
@@ -1558,12 +1590,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
     {
       return  HAL_ERROR;                                    
     }
-
+    
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1586,7 +1618,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Set NBYTES to write and reload if size > 255 */
     /* Size > 255, need to set RELOAD bit */
     if(Size > 255)
@@ -1614,12 +1646,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
           return HAL_TIMEOUT;
         }
       }
-     
+      
       /* Write data to DR */
       hi2c->Instance->TXDR = (*pData++);
       Sizetmp--;
       Size--;
-
+      
       if((Sizetmp == 0)&&(Size!=0))
       {
         /* Wait until TCR flag is set */
@@ -1627,7 +1659,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
         {
           return HAL_TIMEOUT;
         }
-
+        
         
         if(Size > 255)
         {
@@ -1662,7 +1694,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
+    
     hi2c->State = HAL_I2C_STATE_READY; 	  
     
     /* Process Unlocked */
@@ -1691,7 +1723,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t Sizetmp = 0;
-
+  
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
   
@@ -1701,12 +1733,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
     {
       return  HAL_ERROR;                                    
     }
-
+    
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1729,7 +1761,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Send Slave Address */
     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
     /* Size > 255, need to set RELOAD bit */
@@ -1751,14 +1783,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
       {
         return HAL_TIMEOUT;
       }
-          
+      
       /* Read data from RXDR */
       (*pData++) = hi2c->Instance->RXDR;
-
+      
       /* Decrement the Size counter */
       Sizetmp--;
       Size--;   
-
+      
       if((Sizetmp == 0)&&(Size!=0))
       {
         /* Wait until TCR flag is set */
@@ -1778,9 +1810,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
           Sizetmp = Size;
         }
       }
-
+      
     }while(Size > 0);
-
+    
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is reset */ 
     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
@@ -1794,7 +1826,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
   	
@@ -1840,7 +1872,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1874,7 +1906,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Set NBYTES to write and reload if size > 255 */
     /* Size > 255, need to set RELOAD bit */
     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
@@ -1885,13 +1917,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     {
       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
     }  
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
     
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
@@ -1933,7 +1965,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -1966,7 +1998,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
         return HAL_TIMEOUT;
       }
     }
-      
+    
     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
     /* Size > 255, need to set RELOAD bit */
     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
@@ -1977,13 +2009,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     {
       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
     }
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c); 
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
     
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
@@ -2024,7 +2056,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -2091,7 +2123,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Enable DMA Request */
     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;  
     
@@ -2128,12 +2160,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     {
       return  HAL_ERROR;                                    
     }
-
+    
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -2149,7 +2181,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     {
       hi2c->XferSize = Size;
     }
-
+    
     /* Set the I2C DMA transfer complete callback */
     hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
     
@@ -2185,7 +2217,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     {
       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
     }
-
+    
     /* Wait until RXNE flag is set */
     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)      
     {
@@ -2221,14 +2253,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
   uint32_t tickstart = 0;
   
   __IO uint32_t I2C_Trials = 0;
- 
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
-
+    
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
@@ -2269,7 +2301,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+        
         /* Device is ready */
         hi2c->State = HAL_I2C_STATE_READY;
         
@@ -2285,10 +2317,10 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         {
           return HAL_TIMEOUT;
         }
-
+        
         /* Clear NACK Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+        
         /* Clear STOP Flag, auto generated with autoend*/
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
       }
@@ -2309,12 +2341,12 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
       }      
     }while(I2C_Trials < Trials);
-
+    
     hi2c->State = HAL_I2C_STATE_READY;
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-        
+    
     return HAL_TIMEOUT;
   }
   else
@@ -2347,7 +2379,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
       I2C_SlaveTransmit_ISR(hi2c);
     }
   }
-    
+  
   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))
   {     
     /* Master mode selected */
@@ -2356,7 +2388,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
       I2C_MasterTransmit_ISR(hi2c);
     }
   }
-
+  
   /* I2C in mode Receiver ----------------------------------------------------*/
   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))
   {
@@ -2388,7 +2420,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
   { 
     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-   
+    
     /* Clear BERR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
   }
@@ -2397,20 +2429,20 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
   { 
     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
+    
     /* Clear OVR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
   }
-
+  
   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
   { 
     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
+    
     /* Clear ARLO flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
   }
-
+  
   /* Call the Error Callback in case of Error detected */
   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
   {
@@ -2428,6 +2460,9 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */ 
@@ -2441,6 +2476,9 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   */
 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */
@@ -2453,6 +2491,9 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */ 
@@ -2466,6 +2507,9 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
   */
 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */
@@ -2479,6 +2523,9 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+    
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */ 
@@ -2492,6 +2539,9 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
   */
 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_TxCpltCallback could be implemented in the user file
    */
@@ -2505,6 +2555,9 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
   */
  __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2C_ErrorCallback could be implemented in the user file
    */ 
@@ -2629,34 +2682,66 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
   }
   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
   {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    {
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+    
     /* Disable ERR, TC, STOP, NACK, TXI interrupt */
     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
-
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+    
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+    
+    /* Flush TX register if not empty */
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
     {
-      HAL_I2C_MemTxCpltCallback(hi2c);
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+    }
+    
+    /* Call the correct callback to inform upper layer */
+    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      
+      HAL_I2C_ErrorCallback(hi2c);
     }
     else
     {
-      HAL_I2C_MasterTxCpltCallback(hi2c);
+      if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+      {
+        hi2c->State = HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        HAL_I2C_MemTxCpltCallback(hi2c);
+      }
+      else
+      {
+        hi2c->State = HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+      }
     }
   }
   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
     
@@ -2679,7 +2764,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
 static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) 
 {
   uint16_t DevAddress;
-
+  
   /* Process Locked */
   __HAL_LOCK(hi2c);
   
@@ -2736,46 +2821,72 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
   }
   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
   {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    {
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+    
     /* Disable ERR, TC, STOP, NACK, TXI interrupt */
     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
-      
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      
+    
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
     
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-    
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+    /* Call the correct callback to inform upper layer */
+    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
-      HAL_I2C_MemRxCpltCallback(hi2c);
+      hi2c->State = HAL_I2C_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      
+      HAL_I2C_ErrorCallback(hi2c);
     }
     else
     {
-      HAL_I2C_MasterRxCpltCallback(hi2c);
+      if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+      {
+        hi2c->State = HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        HAL_I2C_MemRxCpltCallback(hi2c);
+      }
+      else
+      {
+        hi2c->State = HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+      }
     }
   }
   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
     
     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
     HAL_I2C_ErrorCallback(hi2c);
   }
-    
+  
   /* Process Unlocked */
   __HAL_UNLOCK(hi2c); 
   
   return HAL_OK; 
-
+  
 }  
 
 /**
@@ -2799,7 +2910,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
     {
       /* Clear NACK Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
     }
@@ -2808,13 +2919,13 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
       /* Clear NACK Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+      
       /* Set ErrorCode corresponding to a Non-Acknowledge */
       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
-    
+      
       /* Call the Error callback to prevent upper layer */
       HAL_I2C_ErrorCallback(hi2c);
     }
@@ -2835,15 +2946,15 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
     
     /* Disable Address Acknowledge */
     hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+    
     hi2c->State = HAL_I2C_STATE_READY;
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
+    
     HAL_I2C_SlaveTxCpltCallback(hi2c);
   }
   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
@@ -2857,7 +2968,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
       hi2c->XferCount--;
     }
   }
-
+  
   /* Process Unlocked */
   __HAL_UNLOCK(hi2c);
   
@@ -2879,7 +2990,7 @@ static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
     
@@ -2905,18 +3016,18 @@ static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
     
     /* Disable Address Acknowledge */
     hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+    
     hi2c->State = HAL_I2C_STATE_READY;
     
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
+    
     HAL_I2C_SlaveRxCpltCallback(hi2c);
   }
-
+  
   /* Process Unlocked */
   __HAL_UNLOCK(hi2c);
   
@@ -2936,7 +3047,7 @@ static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)   
 {
   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
+  
   /* Wait until TXIS flag is set */
   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
   {
@@ -2949,7 +3060,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
       return HAL_TIMEOUT;
     }
   }
-
+  
   /* If Memory address size is 8Bit */
   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
   {
@@ -2984,8 +3095,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
   {
     return HAL_TIMEOUT;
   }
-
-return HAL_OK;
+  
+  return HAL_OK;
 }
 
 /**
@@ -3072,7 +3183,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     }
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
     
@@ -3092,15 +3203,15 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         }
       }
-    
+      
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-          
+      
       /* Clear Configuration Register 2 */
       I2C_RESET_CR2(hi2c);
-
+      
       hi2c->XferCount = 0;
-    
+      
       hi2c->State = HAL_I2C_STATE_READY;
       HAL_I2C_ErrorCallback(hi2c);
     }
@@ -3116,9 +3227,9 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
       {
         hi2c->XferSize = hi2c->XferCount;
       }
-
+      
       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-              
+      
       /* Enable the DMA channel */
       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
       
@@ -3132,7 +3243,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
       {
         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
       }  
-
+      
       /* Wait until TXIS flag is set */
       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
       {
@@ -3149,15 +3260,15 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           }
         }
-      
+        
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-            
+        
         /* Clear Configuration Register 2 */
         I2C_RESET_CR2(hi2c);
-
+        
         hi2c->XferCount = 0;
-      
+        
         hi2c->State = HAL_I2C_STATE_READY;
         HAL_I2C_ErrorCallback(hi2c);
       }
@@ -3183,21 +3294,21 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       }
     }
-  
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
-  
+    
     hi2c->XferCount = 0;
-  
+    
     hi2c->State = HAL_I2C_STATE_READY;
-
-   /* Check if Errors has been detected during transfer */
+    
+    /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
       HAL_I2C_ErrorCallback(hi2c);
@@ -3248,7 +3359,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
   hi2c->XferCount = 0;
   
   hi2c->State = HAL_I2C_STATE_READY;
-
+  
   /* Check if Errors has been detected during transfer */
   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
   {
@@ -3279,10 +3390,10 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     }
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-
+    
     /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
@@ -3299,15 +3410,15 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         }
       }
-    
+      
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-          
+      
       /* Clear Configuration Register 2 */
       I2C_RESET_CR2(hi2c);
-    
+      
       hi2c->XferCount = 0;
-    
+      
       hi2c->State = HAL_I2C_STATE_READY;
       HAL_I2C_ErrorCallback(hi2c);
     }
@@ -3323,9 +3434,9 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
       {
         hi2c->XferSize = hi2c->XferCount;
       }
-
+      
       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-              
+      
       /* Enable the DMA channel */
       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
       
@@ -3339,7 +3450,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
       {
         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
       }  
-
+      
       /* Wait until RXNE flag is set */
       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)      
       {
@@ -3362,17 +3473,17 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           }
         }
-      
+        
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-            
+        
         /* Clear Configuration Register 2 */
         I2C_RESET_CR2(hi2c);
-      
+        
         hi2c->XferCount = 0;
-      
+        
         hi2c->State = HAL_I2C_STATE_READY;
-      
+        
         HAL_I2C_ErrorCallback(hi2c);
       }
       else
@@ -3397,20 +3508,20 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       }
     }
-  
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-  
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-  
+    
     hi2c->XferCount = 0;
-  
+    
     hi2c->State = HAL_I2C_STATE_READY;
-
+    
     /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
@@ -3459,11 +3570,11 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable Address Acknowledge */
   hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
+  
   hi2c->XferCount = 0;
   
   hi2c->State = HAL_I2C_STATE_READY;
-
+  
   /* Check if Errors has been detected during transfer */
   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
   {
@@ -3494,7 +3605,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     }
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
     
@@ -3514,15 +3625,15 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         }
       }
-    
+      
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-          
+      
       /* Clear Configuration Register 2 */
       I2C_RESET_CR2(hi2c);
-
+      
       hi2c->XferCount = 0;
-    
+      
       hi2c->State = HAL_I2C_STATE_READY;
       HAL_I2C_ErrorCallback(hi2c);
     }
@@ -3538,9 +3649,9 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
       {
         hi2c->XferSize = hi2c->XferCount;
       }
-
+      
       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-              
+      
       /* Enable the DMA channel */
       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
       
@@ -3554,7 +3665,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
       {
         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
       }  
-
+      
       /* Wait until TXIS flag is set */
       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
       {
@@ -3571,15 +3682,15 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           }
         }
-      
+        
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-            
+        
         /* Clear Configuration Register 2 */
         I2C_RESET_CR2(hi2c);
-
+        
         hi2c->XferCount = 0;
-      
+        
         hi2c->State = HAL_I2C_STATE_READY;
         HAL_I2C_ErrorCallback(hi2c);
       }
@@ -3605,20 +3716,20 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       }
     }
-  
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
-  
+    
     hi2c->XferCount = 0;
-  
+    
     hi2c->State = HAL_I2C_STATE_READY;
-
+    
     /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
@@ -3650,10 +3761,10 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     }
-
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-
+    
     /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
@@ -3670,15 +3781,15 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         }
       }
-    
+      
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-          
+      
       /* Clear Configuration Register 2 */
       I2C_RESET_CR2(hi2c);
-    
+      
       hi2c->XferCount = 0;
-    
+      
       hi2c->State = HAL_I2C_STATE_READY;
       HAL_I2C_ErrorCallback(hi2c);
     }
@@ -3694,9 +3805,9 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
       {
         hi2c->XferSize = hi2c->XferCount;
       }
-
+      
       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-              
+      
       /* Enable the DMA channel */
       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
       
@@ -3710,7 +3821,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
       {
         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
       }  
-
+      
       /* Wait until RXNE flag is set */
       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)      
       {
@@ -3733,15 +3844,15 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
           }
         }
-      
+        
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-            
+        
         /* Clear Configuration Register 2 */
         I2C_RESET_CR2(hi2c);
-      
+        
         hi2c->XferCount = 0;
-      
+        
         hi2c->State = HAL_I2C_STATE_READY;
         HAL_I2C_ErrorCallback(hi2c);
       }
@@ -3767,20 +3878,20 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       }
     }
-  
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
   	
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-  
+    
     /* Disable DMA Request */
     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-  
+    
     hi2c->XferCount = 0;
-  
+    
     hi2c->State = HAL_I2C_STATE_READY;
-
+    
     /* Check if Errors has been detected during transfer */
     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
@@ -3826,7 +3937,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
 {  
   uint32_t tickstart = HAL_GetTick();
-     
+  
   /* Wait until flag is set */
   if(Status == RESET)
   {    
@@ -3883,7 +3994,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     {
       return HAL_ERROR;
     }
-		
+    
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
@@ -3891,10 +4002,10 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->State= HAL_I2C_STATE_READY;
-
+        
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-
+        
         return HAL_TIMEOUT;
       }
     }
@@ -3921,16 +4032,16 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     {
       return HAL_ERROR;
     }
-		
+    
     /* Check for the Timeout */
     if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       hi2c->State= HAL_I2C_STATE_READY;
-
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
-
+      
       return HAL_TIMEOUT;
     }
   }
@@ -3951,33 +4062,39 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   
   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
   {
+    /* Check if a NACK is detected */
+    if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    
     /* Check if a STOPF is detected */
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
     {
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+      
       /* Clear Configuration Register 2 */
       I2C_RESET_CR2(hi2c);
-
+      
       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
       hi2c->State= HAL_I2C_STATE_READY;
-
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
-
+      
       return HAL_ERROR;
     }
-		
+    
     /* Check for the Timeout */
     if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       hi2c->State= HAL_I2C_STATE_READY;
-
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
-
+      
       return HAL_TIMEOUT;
     }
   }
@@ -3995,22 +4112,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
 {
   uint32_t tickstart = 0x00;
   tickstart = HAL_GetTick();
-
+  
   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
   {
-    /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */
-    if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
-       || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
-    {
-      /* No need to generate the STOP condition if AUTOEND mode is enabled */
-      /* Generate the STOP condition only in case of SOFTEND mode is enabled */
-      if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;
-      }
-    }
-		
     /* Wait until STOP Flag is reset */
     /* AutoEnd should be initiate after AF */
     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
@@ -4018,7 +4122,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
       {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
         {
           hi2c->State= HAL_I2C_STATE_READY;
           /* Process Unlocked */
@@ -4027,22 +4131,28 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
         }
       }
     }
-
+    
     /* Clear NACKF Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+    
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+    
+    /* Flush TX register if not empty */
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+    {
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+    }
+    
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
-
+    
     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
     hi2c->State= HAL_I2C_STATE_READY;
-
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
+    
     return HAL_ERROR;
   }
   return HAL_OK;
@@ -4075,7 +4185,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, ui
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_TRANSFER_MODE(Mode));
   assert_param(IS_TRANSFER_REQUEST(Request));
-    
+  
   /* Get the CR2 register value */
   tmpreg = hi2c->Instance->CR2;
   
@@ -4084,7 +4194,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, ui
   
   /* update tmpreg */
   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
-            (uint32_t)Mode | (uint32_t)Request);
+    (uint32_t)Mode | (uint32_t)Request);
   
   /* update CR2 register */
   hi2c->Instance->CR2 = tmpreg;  
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
index 3fdfaa61c7..0de3a38d6f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
index 0fcfb5f5f6..7fd7fa8612 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   I2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2C Extended peripheral:
@@ -90,7 +90,7 @@
                       ##### Extended features functions #####
  ===============================================================================  
     [..] This section provides functions allowing to:
-      (+) Configure Noise Filters 
+      (+) Configure Noise Filters
 
 @endverbatim
   * @{
@@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
   tmpreg = hi2c->Instance->CR1;
   
   /* Reset I2Cx DNF bits [11:8] */
-  tmpreg &= ~(I2C_CR1_DFN);
+  tmpreg &= ~(I2C_CR1_DNF);
   
   /* Set I2Cx DNF coefficient */
   tmpreg |= DigitalFilter << 8;
@@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
   __HAL_UNLOCK(hi2c);
 
   return HAL_OK; 
-}  
+}
 
 /**
   * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
index e856ce2eb6..ff2191e722 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of I2C HAL Extension module.
   ******************************************************************************
   * @attention
@@ -70,6 +70,7 @@
   * @}
   */
 
+ 
 /**
   * @}
   */ 
@@ -80,7 +81,6 @@
 /* Peripheral Control methods  ************************************************/
 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup I2C_Private_Constants I2C Private Constants
   * @{
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
index f89f23a4e6..457d78a1bb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -379,6 +379,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
   */
  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_MspInit could be implemented in the user file
    */ 
@@ -392,6 +395,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
   */
  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_MspDeInit could be implemented in the user file
    */ 
@@ -526,7 +532,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
     {
       /* Wait until Busy flag is reset */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) 
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) 
       {
         /* Set the error code and execute error callback*/
         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
@@ -1202,6 +1208,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
   */
  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
    */ 
@@ -1215,6 +1224,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
   */
  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_TxCpltCallback could be implemented in the user file
    */ 
@@ -1228,6 +1240,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
   */
 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_RxCpltCallback could be implemented in the user file
    */
@@ -1241,6 +1256,9 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
   */
 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_RxCpltCallback could be implemented in the user file
    */
@@ -1254,6 +1272,9 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
   */
  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_ErrorCallback could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
index f3d34bc0f7..bfb8ac3c09 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
@@ -334,7 +334,7 @@ typedef struct
   */
 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
   do{                                           \
-    __IO uint32_t tmpreg;                       \
+  __IO uint32_t tmpreg = 0x00;                       \
     tmpreg = (__HANDLE__)->Instance->DR;        \
     tmpreg = (__HANDLE__)->Instance->SR;        \
     UNUSED(tmpreg);                             \
@@ -346,7 +346,7 @@ typedef struct
   */
 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
   do{                                             \
-  __IO uint32_t tmpreg;                         \
+__IO uint32_t tmpreg = 0x00;                         \
   tmpreg = (__HANDLE__)->Instance->SR;          \
   UNUSED(tmpreg);                               \
   } while(0)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
index 32716ba6bf..c639a5dfd9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -297,6 +297,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
   */
  __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+      
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_IRDA_MspInit could be implemented in the user file
    */ 
@@ -310,6 +313,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
   */
  __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_IRDA_MspDeInit could be implemented in the user file
    */ 
@@ -967,6 +973,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
   */
  __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
    */ 
@@ -980,6 +989,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
   */
  __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IRDA_TxCpltCallback can be implemented in the user file
    */ 
@@ -993,6 +1005,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
   */
 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
    */
@@ -1006,6 +1021,9 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
   */
 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IRDA_RxCpltCallback can be implemented in the user file
    */
@@ -1019,6 +1037,9 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
   */
  __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+    
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IRDA_ErrorCallback can be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
index 69c1c8896a..976387cb18 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
index cba21cd82d..90cf20d626 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of IRDA HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
index ca63f0f9d9..2db141a9cc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   IWDG HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -207,7 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
   hiwdg->State = HAL_IWDG_STATE_BUSY;
 
   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
-  /* by writing 0x5555 in KR */
+  /* by writing 0x00005555 in KR */
   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
 
   /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
@@ -249,6 +249,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
   */
 __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hiwdg);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_IWDG_MspInit could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
index 4b579cce35..4c3f6b836f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
index 9c05928648..232ac277b3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   LPTIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Low Power Timer (LPTIM) peripheral:
@@ -352,6 +352,9 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_MspInit could be implemented in the user file
    */
@@ -364,6 +367,9 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_MspDeInit could be implemented in the user file
    */
@@ -1526,6 +1532,9 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
    */  
@@ -1538,6 +1547,9 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
    */  
@@ -1550,6 +1562,9 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_TriggerCallback could be implemented in the user file
    */  
@@ -1562,6 +1577,9 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
    */  
@@ -1574,6 +1592,9 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
    */  
@@ -1586,6 +1607,9 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
    */  
@@ -1598,6 +1622,9 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
   */
 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
    */  
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
index 783e2c012f..f0508c36db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of LPTIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
index e05240bbc5..09925fbb87 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   LTDC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the LTDC peripheral:
@@ -102,7 +102,7 @@
 /** @addtogroup STM32F7xx_HAL_Driver
   * @{
   */
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 
 /** @defgroup LTDC LTDC
   * @brief LTDC HAL module driver
@@ -263,6 +263,9 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
   */
 __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LTDC_MspInit could be implemented in the user file
    */ 
@@ -276,6 +279,9 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
   */
 __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LTDC_MspDeInit could be implemented in the user file
    */
@@ -385,6 +391,9 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
   */
 __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LTDC_ErrorCallback could be implemented in the user file
    */
@@ -398,6 +407,9 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
   */
 __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LTDC_LineEvenCallback could be implemented in the user file
    */
@@ -1184,7 +1196,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
 /**
   * @}
   */
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 
 /**
   * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
index 4cacf080eb..547fa5da65 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of LTDC HAL module.
   ******************************************************************************
   * @attention
@@ -467,7 +467,6 @@ typedef struct
 /**
   * @}
   */
-
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup LTDC_Exported_Functions
   * @{
@@ -616,7 +615,7 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
 /**
   * @}
   */ 
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
index fa42247714..61a20c3fda 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nand.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   NAND HAL module driver.
   *          This file provides a generic firmware to drive NAND memories mounted 
   *          as external device.
@@ -196,6 +196,9 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
   */
 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_MspInit could be implemented in the user file
    */ 
@@ -209,6 +212,9 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
   */
 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_MspDeInit could be implemented in the user file
    */ 
@@ -273,6 +279,9 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
   */
 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_ITCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
index 3aff116f07..9dd35ba380 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
index f7d0d9adbb..d540025d3f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.
@@ -231,6 +231,9 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
   */
 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspInit could be implemented in the user file
    */ 
@@ -244,6 +247,9 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
   */
 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspDeInit could be implemented in the user file
    */ 
@@ -258,6 +264,10 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
   */
 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  UNUSED(Timeout);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspWait could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
index b07c75fcd4..617bcd402d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
index ca106b7220..493a70779e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -24,12 +24,12 @@
         
      (#) Fill parameters of Init structure in HCD handle
   
-     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) 
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) 
 
      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
          (##) Enable the PCD/USB Low Level interface clock using 
-              (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
-              (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
            
          (##) Initialize the related GPIO clocks
          (##) Configure PCD pin-out
@@ -38,7 +38,7 @@
      (#)Associate the Upper USB device stack to the HAL PCD Driver:
          (##) hpcd.pData = pdev;
 
-     (#)Enable HCD transmission and reception:
+     (#)Enable PCD transmission and reception:
          (##) HAL_PCD_Start();
 
   @endverbatim
@@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  DeInitializes the PCD peripheral 
+  * @brief  DeInitializes the PCD peripheral. 
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -235,6 +235,9 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
   */
 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_MspInit could be implemented in the user file
    */
@@ -247,6 +250,9 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
   */
 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_MspDeInit could be implemented in the user file
    */
@@ -256,7 +262,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
   * @}
   */
 
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions 
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
  *  @brief   Data transfers functions 
  *
 @verbatim   
@@ -301,7 +307,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  This function handles PCD interrupt request.
+  * @brief  Handle PCD interrupt request.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -372,6 +378,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
           {
             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
           }
+          /* Clear Status Phase Received interrupt */
+          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
         }
         epnum++;
         ep_intr >>= 1;
@@ -462,7 +473,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
     /* Handle Suspend Interrupt */
     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
     {
-
       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
       {
         
@@ -508,7 +518,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
       }
       else
       {
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
         USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
       }
       
@@ -612,136 +622,168 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  Data out stage callbacks
+  * @brief  Data OUT stage callback.
   * @param  hpcd: PCD handle
   * @param  epnum: endpoint number  
   * @retval None
   */
  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_DataOutStageCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Data IN stage callbacks
+  * @brief  Data IN stage callback.
   * @param  hpcd: PCD handle
   * @param  epnum: endpoint number  
   * @retval None
   */
  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum); 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_DataInStageCallback could be implemented in the user file
    */ 
 }
 /**
-  * @brief  Setup stage callback
+  * @brief  Setup stage callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_SetupStageCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  USB Start Of Frame callbacks
+  * @brief  USB Start Of Frame callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_SOFCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  USB Reset callbacks
+  * @brief  USB Reset callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_ResetCallback could be implemented in the user file
    */ 
 }
 
-
 /**
-  * @brief  Suspend event callbacks
+  * @brief  Suspend event callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_SuspendCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Resume event callbacks
+  * @brief  Resume event callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_ResumeCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Incomplete ISO OUT callbacks
+  * @brief  Incomplete ISO OUT callback.
   * @param  hpcd: PCD handle
   * @param  epnum: endpoint number
   * @retval None
   */
  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Incomplete ISO IN  callbacks
+  * @brief  Incomplete ISO IN  callback.
   * @param  hpcd: PCD handle
   * @param  epnum: endpoint number  
   * @retval None
   */
  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Connection event callbacks
+  * @brief  Connection event callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_ConnectCallback could be implemented in the user file
    */ 
 }
 
 /**
-  * @brief  Disconnection event callbacks
+  * @brief  Disconnection event callback.
   * @param  hpcd: PCD handle
   * @retval None
   */
  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCD_DisconnectCallback could be implemented in the user file
    */ 
@@ -767,7 +809,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
   */
 
 /**
-  * @brief  Connect the USB device
+  * @brief  Connect the USB device.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -780,7 +822,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  Disconnect the USB device
+  * @brief  Disconnect the USB device.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -793,7 +835,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  Set the USB Device address 
+  * @brief  Set the USB Device address. 
   * @param  hpcd: PCD handle
   * @param  address: new device address
   * @retval HAL status
@@ -806,7 +848,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
   return HAL_OK;
 }
 /**
-  * @brief  Open and configure an endpoint
+  * @brief  Open and configure an endpoint.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @param  ep_mps: endpoint max packet size
@@ -850,7 +892,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
 
 
 /**
-  * @brief  Deactivate an endpoint
+  * @brief  Deactivate an endpoint.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @retval HAL status
@@ -879,7 +921,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 
 
 /**
-  * @brief  Receive an amount of data  
+  * @brief  Receive an amount of data.  
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @param  pBuf: pointer to the reception buffer   
@@ -920,7 +962,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
 }
 
 /**
-  * @brief  Get Received Data Size
+  * @brief  Get Received Data Size.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @retval Data Size
@@ -930,7 +972,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
   return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
 }
 /**
-  * @brief  Send an amount of data  
+  * @brief  Send an amount of data.  
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @param  pBuf: pointer to the transmission buffer   
@@ -972,7 +1014,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
 }
 
 /**
-  * @brief  Set a STALL condition over an endpoint
+  * @brief  Set a STALL condition over an endpoint.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @retval HAL status
@@ -1007,7 +1049,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 }
 
 /**
-  * @brief  Clear a STALL condition over in an endpoint
+  * @brief  Clear a STALL condition over in an endpoint.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @retval HAL status
@@ -1037,7 +1079,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 }
 
 /**
-  * @brief  Flush an endpoint
+  * @brief  Flush an endpoint.
   * @param  hpcd: PCD handle
   * @param  ep_addr: endpoint address
   * @retval HAL status
@@ -1061,7 +1103,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 }
 
 /**
-  * @brief  HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
+  * @brief  Activate remote wakeup signalling.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -1071,14 +1113,14 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
     
   if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
   {
-    /* Activate Remote wake-up signaling */
+    /* Activate Remote wakeup signaling */
     USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
   }
   return HAL_OK;  
 }
 
 /**
-  * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
+  * @brief  De-activate remote wakeup signalling.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -1086,7 +1128,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
 {
   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
   
-  /* De-activate Remote wake-up signaling */
+  /* De-activate Remote wakeup signaling */
    USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
   return HAL_OK;  
 }
@@ -1110,7 +1152,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
   */
 
 /**
-  * @brief  Return the PCD state
+  * @brief  Return the PCD handle state.
   * @param  hpcd: PCD handle
   * @retval HAL state
   */
@@ -1132,8 +1174,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
   */
 
 /**
-  * @brief  DCD_WriteEmptyTxFifo
-  *         check FIFO for the next packet to be loaded
+  * @brief  Check FIFO for the next packet to be loaded.
   * @param  hpcd: PCD handle
   * @param  epnum : endpoint number   
   * @retval HAL status
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
index 8335584225..e87542c426 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
@@ -219,6 +219,9 @@ typedef struct
                                                                    EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE 
                                                          
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                     
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
@@ -239,7 +242,7 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
 
 /* I/O operation functions  ***************************************************/
 /* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
@@ -295,6 +298,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
   * @}
   */ 
 
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
 /** @defgroup PCD_Instance_definition PCD Instance definition
   * @{
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
index 0dc553c216..92d08f0ad4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -59,7 +59,7 @@
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
   * @{
   */
 
@@ -103,7 +103,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
   
   if(fifo == 0)
   {
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
   }
   else
   {
@@ -114,8 +114,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
     }
     
     /* Multiply Tx_Size by 2 to get higher performance */
-    hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
-    
+    hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
   }
   
   return HAL_OK;
@@ -135,7 +134,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
 }
 
 /**
-  * @brief  HAL_PCDEx_ActivateLPM : active LPM Feature
+  * @brief  Activate LPM Feature
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -152,7 +151,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  HAL_PCDEx_DeActivateLPM : de-active LPM feature
+  * @brief  DeActivate LPM feature.
   * @param  hpcd: PCD handle
   * @retval HAL status
   */
@@ -168,13 +167,20 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
 }
 
 /**
-  * @brief  HAL_PCDEx_LPM_Callback : Send LPM message to user layer
+  * @brief  Send LPM message to user layer callback.
   * @param  hpcd: PCD handle
   * @param  msg: LPM message
   * @retval HAL status
   */
 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+  
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */	
 }
 
 /**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
index d6d43c06d9..93a6c18a1d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
@@ -63,7 +63,7 @@ typedef enum
 /* Exported constants --------------------------------------------------------*/
 /* Exported macros -----------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
   * @{
   */
 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
index bd881ac8f4..92d901ebb0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Power Controller (PWR) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
index 63ef22cbba..b210d51b96 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
@@ -181,7 +181,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg;                               \
+                                                          __IO uint32_t tmpreg = 0x00;                               \
                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
                                                             /* Delay after an RCC peripheral clock enabling */  \
                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
index a3182693b7..a4cf3ca054 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of PWR extension peripheral:           
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
index fa77f76a1e..0984b18b1f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
index 00ef8a41af..312936d218 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_qspi.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   QSPI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the QuadSPI interface (QSPI).
@@ -349,6 +349,9 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
   */
  __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_QSPI_MspInit can be implemented in the user file
    */ 
@@ -361,6 +364,9 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
   */
  __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_QSPI_MspDeInit can be implemented in the user file
    */ 
@@ -1168,28 +1174,28 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
   {
-  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
   }
-
+  
   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
   {
     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
   }
-
+  
   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
   {
     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
   }
-
+  
   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+  
   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+  
   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
@@ -1199,49 +1205,49 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
   
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
-  
-  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
-  /* Update state */
-  hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
-  /* Wait till BUSY flag reset */
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
-  
-  if (status == HAL_OK)
-  {
-    /* Configure QSPI: PSMAR register with the status match value */
-    WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
-    /* Configure QSPI: PSMKR register with the status mask value */
-    WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
     
-    /* Configure QSPI: PIR register with the interval value */
-    WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
     
-    /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
-       (otherwise there will be an infinite loop in blocking mode) */
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
-               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
-    /* Call the configuration function */
-    cmd->NbData = cfg->StatusBytesSize;
-    QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
-    /* Wait until SM flag is set to go back in idle state */
-    if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
-    { 
-      status = HAL_TIMEOUT;
-    }
-    else
+    if (status == HAL_OK)
     {
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_READY;
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+      
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+      
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+      
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
+      (otherwise there will be an infinite loop in blocking mode) */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
+                 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+      
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+      
+      /* Wait until SM flag is set to go back in idle state */
+      if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
+      { 
+        status = HAL_TIMEOUT;
+      }
+      else
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
     }
   }
-  }
   else
   {
     status = HAL_BUSY;   
@@ -1254,13 +1260,13 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
 }
 
 /**
-  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode. 
-  * @param  hqspi: QSPI handle
-  * @param  cmd: structure that contains the command configuration information.
-  * @param  cfg: structure that contains the polling configuration information.
-  * @note   This function is used only in Automatic Polling Mode
-  * @retval HAL status
-  */
+* @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode. 
+* @param  hqspi: QSPI handle
+* @param  cmd: structure that contains the command configuration information.
+* @param  cfg: structure that contains the polling configuration information.
+* @note   This function is used only in Automatic Polling Mode
+* @retval HAL status
+*/
 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
@@ -1271,26 +1277,26 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
   {
     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
   }
-
+  
   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
   {
     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
   }
-
+  
   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
   {
     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
   }
-
+  
   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+  
   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+  
   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
@@ -1299,7 +1305,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
   /* Process locked */
   __HAL_LOCK(hqspi);
   
-if(hqspi->State == HAL_QSPI_STATE_READY)
+  if(hqspi->State == HAL_QSPI_STATE_READY)
   {
     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
@@ -1309,34 +1315,37 @@ if(hqspi->State == HAL_QSPI_STATE_READY)
     /* Wait till BUSY flag reset */
     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
     
-  if (status == HAL_OK)
-  {
-    /* Configure QSPI: PSMAR register with the status match value */
-    WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-    
-    /* Configure QSPI: PSMKR register with the status mask value */
-    WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-    
-    /* Configure QSPI: PIR register with the interval value */
-    WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-    
-    /* Configure QSPI: CR register with Match mode and Automatic stop mode */
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
-               (cfg->MatchMode | cfg->AutomaticStop));
-
-    /* Call the configuration function */
-    cmd->NbData = cfg->StatusBytesSize;
-    QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
-    /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
-    __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));
-        }
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+      
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+      
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+      
+      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
+                 (cfg->MatchMode | cfg->AutomaticStop));
+      
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+      
+      /* Enable the QSPI Transfer Error and status match Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+      
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+    }
   }
   else
   {
     status = HAL_BUSY; 
   }
-
+  
   /* Process unlocked */
   __HAL_UNLOCK(hqspi);
   
@@ -1438,6 +1447,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
   */
 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_ErrorCallback could be implemented in the user file
    */
@@ -1450,6 +1462,9 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
    */
@@ -1462,6 +1477,9 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_RxCpltCallback could be implemented in the user file
    */
@@ -1474,6 +1492,9 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
   */
  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_TxCpltCallback could be implemented in the user file
    */ 
@@ -1486,6 +1507,9 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
    */
@@ -1498,6 +1522,9 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
   */
  __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
    */ 
@@ -1510,6 +1537,9 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
    */
@@ -1522,6 +1552,9 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+    
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
    */
@@ -1534,6 +1567,9 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
   */
 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_TimeOutCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
index d8835f9866..6833b7f6c3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_qspi.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of QSPI HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
index 3ec90947c7..2d1087ef43 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
index 2ae5f2cffe..532d7efa5e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
@@ -75,7 +75,7 @@ typedef struct
                             This parameter must be a number between Min_Data = 2 and Max_Data = 63    */        
 
   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+                            This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
 
   uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
@@ -442,7 +442,7 @@ typedef struct
   * @{
   */
 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
@@ -450,7 +450,7 @@ typedef struct
                                       } while(0)
 									  
 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
@@ -472,7 +472,7 @@ typedef struct
   * @{
   */
 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
@@ -480,7 +480,7 @@ typedef struct
                                       } while(0)
 									  
 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
@@ -501,7 +501,7 @@ typedef struct
   * @{
   */
 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
@@ -907,9 +907,9 @@ typedef struct
   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
   *         of 2 MHz to limit PLL jitter.
   * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  *         This parameter must be a number between Min_Data = 100 and Max_Data = 432.
   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 192 and 432 MHz.
+  *         output frequency is between 100 and 432 MHz.
   * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
   *         This parameter must be a number in the range {2, 4, 6, or 8}.
   * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
@@ -963,8 +963,8 @@ typedef struct
   *                                       used as I2S clock source.
   */
 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
-                                          RCC->CFGR |= (__SOURCE__); \
-                                         }while(0)
+                                             RCC->CFGR |= (__SOURCE__);       \
+                                            }while(0)
 
 /** @brief Macros to enable or disable the PLLI2S. 
   * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
@@ -1024,7 +1024,52 @@ typedef struct
 /**
   * @}
   */
+  
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{   
+  */ 
+  
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
 
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+                
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source 
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
+
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
+/**
+  * @}
+  */
+  
 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
   * @brief macros to manage the specified RCC Flags and interrupts.
   * @{
@@ -1225,7 +1270,7 @@ void HAL_RCC_CSSCallback(void);
                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
 
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
 
 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
                                   ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
@@ -1276,9 +1321,9 @@ void HAL_RCC_CSSCallback(void);
 
 
 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \
-                                     ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
-                                     ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
-                                     ((DRIVE) == RCC_LSEDRIVE_HIGH))
+                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
+                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
index fd6fc1c90e..e4d439a0bf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Extension RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
@@ -200,27 +200,26 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*------------------------------------ RTC configuration --------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+      
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+      
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+      
+    /* Wait for Backup domain Write protection disable */
+    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }      
+    }
     /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
     {
-      /* Enable Power Clock*/
-      __HAL_RCC_PWR_CLK_ENABLE();
-      
-      /* Enable write access to Backup domain */
-      PWR->CR1 |= PWR_CR1_DBP;
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait for Backup domain Write protection disable */
-      while((PWR->CR1 & PWR_CR1_DBP) == RESET)
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }      
-      }
-
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       
@@ -423,7 +422,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
    }
   
-  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
   {
     /* Check the parameters */
@@ -512,7 +511,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
     {
       /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
@@ -564,7 +562,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
     
     /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/  
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
     {
       /* check for PLLSAIQ Parameter */
@@ -650,8 +648,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
   uint32_t tempreg = 0;
   
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1 |\
+  /* Set all possible values for the extended clock type parameter------------*/ 
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
@@ -660,8 +658,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
                                         RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
                                         RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
                                         RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
-                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1    |\
-                                        RCC_PERIPHCLK_CLK48;          
+                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+                                        RCC_PERIPHCLK_CLK48;
+
   
   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
@@ -764,16 +763,84 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
 {
   uint32_t tmpreg = 0;
-  /* This variable used to store the SAI clock frequency (value in Hz) */
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
   uint32_t frequency = 0;
-  /* This variable used to store the VCO Input (value in Hz) */
+  /* This variable is used to store the VCO Input (value in Hz) */
   uint32_t vcoinput = 0;
-  /* This variable used to store the SAI clock source */
+  /* This variable is used to store the SAI clock source */
   uint32_t saiclocksource = 0;
-  if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
+  
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
   {
     saiclocksource = RCC->DCKCFGR1;   
-    saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL);
+    saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+    switch (saiclocksource)
+    {
+    case 0: /* PLLSAI is the clock source for SAI1 */ 
+      {
+        /* Configure the PLLSAI division factor */
+        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */ 
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }   
+        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+        
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+        frequency = frequency/(tmpreg); 
+        break;       
+      }
+    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
+      {  
+        /* Configure the PLLI2S division factor */
+        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */ 
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }
+        
+        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+        
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); 
+        frequency = frequency/(tmpreg);
+        break;
+      }
+    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;       
+      }
+    default :
+      {
+        break;
+      }
+    }
+  }
+  
+  if (PeriphClk == RCC_PERIPHCLK_SAI2)
+  {
+    saiclocksource = RCC->DCKCFGR1;   
+    saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
     switch (saiclocksource)
     {
     case 0: /* PLLSAI is the clock source for SAI*/ 
@@ -800,8 +867,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
         frequency = frequency/(tmpreg); 
         break;       
       }
-    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/
-    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/
+    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
       {  
         /* Configure the PLLI2S division factor */
         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */ 
@@ -826,8 +892,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
         frequency = frequency/(tmpreg);
         break;
       }
-    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/
-    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/
+    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
       {
         frequency = EXTERNAL_CLOCK_VALUE;
         break;       
@@ -838,9 +903,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
       }
     }
   }
+  
   return frequency;
 }
-
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
index 03d389174b..7714414b3c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
@@ -1,9 +1,9 @@
 /**
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @author  MCD Application Team                                                                                                     
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
@@ -65,7 +65,7 @@
 typedef struct
 {
   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 49 and Max_Data = 432.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
 
   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
@@ -77,8 +77,8 @@ typedef struct
                             This parameter will be used only when PLLI2S is selected as Clock Source SAI */
 
   uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.
-                            This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */
+                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
 }RCC_PLLI2SInitTypeDef;
 
 /** 
@@ -87,7 +87,7 @@ typedef struct
 typedef struct
 {
   uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 49 and Max_Data = 432.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
                                  
   uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
@@ -99,7 +99,7 @@ typedef struct
                             This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
 
   uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.
-                            This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
                             This parameter will be used only when PLLSAI is disabled */
 }RCC_PLLSAIInitTypeDef;
 
@@ -190,7 +190,6 @@ typedef struct
   
   uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source      
                                         This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
-
 }RCC_PeriphCLKInitTypeDef;
 /**
   * @}
@@ -205,9 +204,9 @@ typedef struct
   * @{
   */
 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined(STM32F746xx) || defined(STM32F756xx)
 #define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008)
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010)
 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020)
 #define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040)
@@ -231,7 +230,17 @@ typedef struct
 #define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000)
 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000)
 
+/**
+  * @}
+  */
 
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
+  * @{
+  */
+#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000)
+#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001)
+#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002)
+#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003)
 /**
   * @}
   */
@@ -290,15 +299,6 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
-  * @{
-  */
-#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000)
-#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL
-/**
-  * @}
-  */
-
 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
   * @{
   */
@@ -437,7 +437,6 @@ typedef struct
   * @}
   */
 
-
 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
   * @{
   */
@@ -464,8 +463,15 @@ typedef struct
   */
 #define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000)
 #define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE
+/**
+  * @}
+  */
 
-
+/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
+  * @{
+  */
+#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000)
+#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL
 /**
   * @}
   */
@@ -492,7 +498,7 @@ typedef struct
   *         using it.
   */
 #define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
@@ -500,7 +506,7 @@ typedef struct
                                       } while(0)
 									  
 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
@@ -508,7 +514,7 @@ typedef struct
                                       } while(0)
 									  
 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
@@ -516,7 +522,7 @@ typedef struct
                                       } while(0)  
 
 #define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
@@ -524,7 +530,7 @@ typedef struct
                                       } while(0) 
 
 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
@@ -532,7 +538,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
@@ -540,7 +546,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
@@ -548,7 +554,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
@@ -556,7 +562,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
@@ -564,7 +570,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
@@ -572,7 +578,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
@@ -580,7 +586,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
@@ -588,7 +594,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
@@ -596,7 +602,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
@@ -604,7 +610,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
@@ -612,7 +618,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
@@ -620,7 +626,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
@@ -648,7 +654,7 @@ typedef struct
   * @brief  Enable ETHERNET clock.
   */
 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
@@ -656,7 +662,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
@@ -664,7 +670,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
@@ -672,7 +678,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
@@ -703,7 +709,7 @@ typedef struct
   *         using it.
   */
 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
@@ -711,7 +717,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_RNG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
@@ -719,23 +725,21 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
                                         UNUSED(tmpreg); \
-										__HAL_RCC_SYSCFG_CLK_ENABLE();\
+					__HAL_RCC_SYSCFG_CLK_ENABLE();\
                                       } while(0) 
 									  
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))                                        
 #define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))                                        
 
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
-                                         __HAL_RCC_SYSCFG_CLK_DISABLE();\
-                                    }while(0)
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
 #if defined(STM32F756xx)
 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@@ -743,7 +747,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -753,13 +757,14 @@ typedef struct
 #define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
 #define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 
 #endif /* STM32F756x */
+                                        
 /** @brief  Enables or disables the AHB3 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it. 
   */
 #define __HAL_RCC_FMC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
@@ -767,7 +772,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
@@ -783,7 +788,7 @@ typedef struct
   *         using it. 
   */
 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
@@ -791,7 +796,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
@@ -799,7 +804,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
@@ -807,7 +812,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
@@ -815,7 +820,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
@@ -823,7 +828,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
@@ -831,7 +836,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
@@ -839,7 +844,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
@@ -847,7 +852,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
@@ -855,7 +860,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
@@ -863,7 +868,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
@@ -871,7 +876,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
@@ -879,7 +884,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
@@ -887,7 +892,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
@@ -895,7 +900,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
@@ -903,7 +908,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
@@ -911,7 +916,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
@@ -919,7 +924,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
@@ -927,7 +932,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
@@ -935,7 +940,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
@@ -943,7 +948,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
@@ -951,7 +956,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
@@ -959,7 +964,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
@@ -967,7 +972,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
@@ -975,7 +980,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
@@ -983,7 +988,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_UART7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
@@ -991,7 +996,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_UART8_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
@@ -1032,7 +1037,7 @@ typedef struct
   *         using it.
   */
 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
@@ -1040,7 +1045,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
@@ -1048,7 +1053,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
@@ -1056,7 +1061,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
@@ -1064,7 +1069,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
@@ -1072,7 +1077,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
@@ -1080,7 +1085,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
@@ -1088,7 +1093,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
@@ -1096,7 +1101,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
@@ -1104,7 +1109,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
@@ -1112,7 +1117,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
@@ -1120,7 +1125,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
@@ -1128,7 +1133,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
@@ -1136,7 +1141,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
@@ -1144,7 +1149,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
@@ -1152,7 +1157,7 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
@@ -1160,23 +1165,23 @@ typedef struct
                                       } while(0)
 
 #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                         UNUSED(tmpreg); \
                                       } while(0)
 
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
                                         UNUSED(tmpreg); \
                                       } while(0)
-#endif /* STM32F756xx || STM32F746xx */
-
+#endif /* STM32F746xx || STM32F756xx */
+                                        
 #define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
@@ -1184,7 +1189,7 @@ typedef struct
 #define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SDMMC1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 #define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
@@ -1194,9 +1199,9 @@ typedef struct
 #define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
 #define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
 #define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 /**
   * @}
   */
@@ -1280,8 +1285,7 @@ typedef struct
 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-
-                                    
+                                   
 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)                                        
 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
@@ -1291,7 +1295,7 @@ typedef struct
 #define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
 #define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
 #define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 
-#endif /* STM32F756x */
+#endif /* STM32F756xx */
 
 /** @brief  Get the enable or disable status of the AHB3 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
@@ -1387,9 +1391,9 @@ typedef struct
 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
@@ -1407,9 +1411,9 @@ typedef struct
 #define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
 #define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)  
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 /**
   * @}
   */  
@@ -1457,7 +1461,6 @@ typedef struct
   */
 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFF) 
 #define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-
 #define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
 
@@ -1558,9 +1561,9 @@ typedef struct
 #define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
 #define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
 #define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 
 #define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
 #define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
@@ -1577,9 +1580,10 @@ typedef struct
 #define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
 #define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
 #define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
+
 /**
   * @}
   */ 
@@ -1655,7 +1659,7 @@ typedef struct
   */
 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-                                         
+
 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
 
@@ -1741,8 +1745,8 @@ typedef struct
 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
 
 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -1767,9 +1771,9 @@ typedef struct
 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 
 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
@@ -1788,9 +1792,10 @@ typedef struct
 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
+
 /**
   * @}
   */
@@ -1870,7 +1875,7 @@ typedef struct
   */
 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
-                                         
+
 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
 
@@ -1982,9 +1987,9 @@ typedef struct
 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
 
 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
@@ -2003,13 +2008,14 @@ typedef struct
 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined (STM32F746xx) || defined (STM32F756xx)
 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx */
+
 /**
   * @}
   */
-  
+
 /*---------------------------------------------------------------------------------------------*/
 
 /** @brief  Macro to configure the Timers clocks prescalers 
@@ -2025,8 +2031,8 @@ typedef struct
   *                 to division by 8 or more.
   */     
 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
-                                             RCC->DCKCFGR1 |= (__PRESC__);\
-                                             }while(0)
+                                                 RCC->DCKCFGR1 |= (__PRESC__);           \
+                                                }while(0)
 
 /** @brief Macros to Enable or Disable the PLLISAI. 
   * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
@@ -2039,36 +2045,44 @@ typedef struct
   * @note   PLLSAI clock source is common with the main PLL (configured in 
   *         RCC_PLLConfig function )
   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 49 and Max_Data = 432.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 49 and Max_Data = 432 MHz.
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
+  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.                                                  
   * @param  __PLLSAIQ__: specifies the division factor for SAI clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @param  __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
-  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider .
   */   
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)                        \
+                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
+                               ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP))                    |\
+                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                    |\
+                               ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
 
-/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.
   * @note   This macro must be used only when the PLLI2S is disabled.
   * @note   PLLI2S clock source is common with the main PLL (configured in 
   *         HAL_RCC_ClockConfig() API)             
   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
-  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
+  *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.                                 
   * @param  __PLLI2SQ__: specifies the division factor for SAI clock.
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
   * @param  __PLLI2SR__: specifies the division factor for I2S clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  * @param  __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
-  *         This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8 
+  *         on the I2S clock frequency. 
   */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16)  | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)                        \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+                               ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP))                    |\
+                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))                    |\
+                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
     
 /** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
   * @note   This function must be called before enabling the PLLI2S.          
@@ -2090,7 +2104,7 @@ typedef struct
   * 
   * @note   This function must be called before enabling the PLLSAI. 
   * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
-  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+  *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
   *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
   */   
 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
@@ -2450,7 +2464,7 @@ typedef struct
   * @param  __CEC_CLKSOURCE__: specifies the CEC clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
   */
 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
@@ -2467,7 +2481,7 @@ typedef struct
   * @param  __CLK48_SOURCE__: specifies the CLK48 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
-  *            @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source
+  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
   */
 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
@@ -2475,7 +2489,7 @@ typedef struct
 /** @brief  macro to get the CLK48 source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
-  *            @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source
+  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
   */
 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
 
@@ -2499,7 +2513,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup RCCEx_Exported_Functions_Group1
   * @{
@@ -2520,7 +2534,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
   */
 #if defined(STM32F756xx) || defined(STM32F746xx)
 #define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)      || \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
                 (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
                 (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
                 (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
@@ -2540,12 +2554,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
                 (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
                 (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
                 (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
                 (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
 #elif defined(STM32F745xx)
 #define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)      || \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
                 (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
                 (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
                 (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
@@ -2564,17 +2578,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
                 (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
                 (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
                 (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
                 (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
-#endif /* STM32F756xx || STM32F746xx */
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
+#endif /* STM32F746xx || STM32F756xx */
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV8))                 
 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
 
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV8))
 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
 
@@ -2583,20 +2603,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
 
 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\
                                          ((VALUE) == RCC_PLLSAIDIVR_16))
 #define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
-                                          ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
-#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
-                                      ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
-                                      ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
-#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
-                                      ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
-                                      ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
+                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
 
-#define IS_RCC_SDMMC1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
-                                      ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
+#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
+                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
 
 #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
                                       ((SOURCE) == RCC_CECCLKSOURCE_LSE))
@@ -2674,6 +2688,16 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 #define IS_RCC_TIMPRES(VALUE)  \
                (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
                 ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
+#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
+#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx */
+                 
 /**
   * @}
   */ 
@@ -2689,6 +2713,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 /**
   * @}
   */  
+  
 #ifdef __cplusplus
 }
 #endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
index 8848718c5f..622adac2de 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rng.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   RNG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Random Number Generator (RNG) peripheral:
@@ -187,6 +187,9 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
   */
 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_MspInit must be implemented in the user file.
    */
@@ -200,6 +203,9 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
   */
 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_MspDeInit must be implemented in the user file.
    */
@@ -441,6 +447,9 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
   */
 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
    */
@@ -454,6 +463,9 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32
   */
 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_ErrorCallback must be implemented in the user file.
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
index 0f0a48bb69..5d7a16a088 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rng.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
index a52dd008fb..95720bbac3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) peripheral:
@@ -384,6 +384,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_MspInit could be implemented in the user file
    */ 
@@ -397,6 +400,9 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
   */
 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_MspDeInit could be implemented in the user file
    */ 
@@ -1345,6 +1351,9 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
   */
 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
index 52dabe13e8..2055807830 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
index 2ff39477d7..d7ed7099ab 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -728,6 +728,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_TimeStampEventCallback could be implemented in the user file
   */
@@ -741,6 +744,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_Tamper1EventCallback could be implemented in the user file
    */
@@ -754,6 +760,9 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_Tamper2EventCallback could be implemented in the user file
    */
@@ -766,6 +775,9 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
    */
@@ -1193,6 +1205,9 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
   */
 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
    */
@@ -1753,6 +1768,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
   */
 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_AlarmBEventCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
index e80c37beb1..1007c3f90c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
index cab0a701b9..53e69b7ec4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SAI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -185,6 +185,7 @@ typedef enum {
   */
 #define SAI_FIFO_SIZE       8
 #define SAI_DEFAULT_TIMEOUT 4
+#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
 /**
   * @}
   */
@@ -312,6 +313,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
   /* This variable used to store the SAI_CK_x (value in Hz) */
   uint32_t freq = 0;
   
+  uint32_t syncen_bits = 0;
+  
   /* Check the SAI handle allocation */
   if(hsai == NULL)
   {
@@ -384,25 +387,43 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
       hsai->Init.Mckdiv+= 1;
     }
   }
-
+  
   /* SAI Block Configuration ------------------------------------------------------------*/
+  switch(hsai->Init.Synchro)
+  {
+    case SAI_ASYNCHRONOUS :
+      {
+        syncen_bits = 0;
+      }
+      break;
+    case SAI_SYNCHRONOUS :
+      {
+        syncen_bits = SAI_xCR1_SYNCEN_0;
+      }
+      break;
+    case SAI_SYNCHRONOUS_EXT_SAI1 :
+    case SAI_SYNCHRONOUS_EXT_SAI2 :  
+      {
+        syncen_bits = SAI_xCR1_SYNCEN_1;
+      }
+      break;
+  }  
   /* SAI CR1 Configuration */
   hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
                          SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
                          SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
                          SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
-  
+
   hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
                         hsai->Init.DataSize | hsai->Init.FirstBit  |           \
-                        hsai->Init.ClockStrobing | hsai->Init.Synchro |        \
+                        hsai->Init.ClockStrobing | syncen_bits |        \
                         hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
-                        hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | hsai->Init.CompandingMode);  
+                        hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));  
   
   /* SAI CR2 Configuration */
-  hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP);
+  hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
   hsai->Instance->CR2|=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
 
-
   /* SAI Frame Configuration -----------------------------------------*/
   hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
                            SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF));
@@ -418,9 +439,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
   
   hsai->Instance->SLOTR|=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize
-                          | hsai->SlotInit.SlotActive | ((hsai->SlotInit.SlotNumber - 1) <<  8);           
+                          | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);           
   
-  /* Initialise the error code */
+  /* Initialize the error code */
   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
   
   /* Initialize the SAI state */
@@ -481,7 +502,10 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
   */
 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_MspInit could be implemented in the user file
    */ 
 }
@@ -494,7 +518,10 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
   */
 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_MspDeInit could be implemented in the user file
    */ 
 }
@@ -559,7 +586,7 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
   */
 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = HAL_GetTick();
   
   if((pData == NULL ) || (Size == 0)) 
   {
@@ -571,14 +598,14 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
     /* Process Locked */
     __HAL_LOCK(hsai);
     
-    hsai->State = HAL_SAI_STATE_BUSY_TX;
-    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
     hsai->XferSize = Size;
     hsai->XferCount = Size;
     hsai->pBuffPtr = pData;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
     
     /* Check if the SAI is already enabled */ 
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* fill the fifo with data before to enabled the SAI */
       SAI_FillFifo(hsai);      
@@ -609,25 +636,16 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
       }
       else
       {
-        /* Get tick */
-        tickstart = HAL_GetTick();      
         /* Check for the Timeout */
-        if(Timeout != HAL_MAX_DELAY)
+        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
         {
-          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-          {
-            /* Update error code */
-            hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-            
-            /* Process Unlocked */
-            __HAL_UNLOCK(hsai);
-            
-            /* Change the SAI state */
-            hsai->State = HAL_SAI_STATE_TIMEOUT;
-            
-            return HAL_TIMEOUT;
-          }
-        } 
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_TIMEOUT;
+          
+          return HAL_TIMEOUT;
+        }
       }
     }      
     
@@ -655,7 +673,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
   */
 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = HAL_GetTick();
   
   if((pData == NULL ) || (Size == 0)) 
   {
@@ -667,14 +685,14 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
     /* Process Locked */
     __HAL_LOCK(hsai);
     
-    hsai->State = HAL_SAI_STATE_BUSY_RX;
-    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
     hsai->pBuffPtr = pData;
     hsai->XferSize = Size;
     hsai->XferCount = Size;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
     
     /* Check if the SAI is already enabled */ 
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */    
       __HAL_SAI_ENABLE(hsai);
@@ -682,8 +700,7 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
     
     /* Receive data */
     while(hsai->XferCount > 0)
-    {
-      
+    {      
       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
       {
         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
@@ -704,24 +721,15 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
       }
       else
       {
-        /* Get tick */
-        tickstart = HAL_GetTick();
         /* Check for the Timeout */
-        if(Timeout != HAL_MAX_DELAY)
+        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
         {
-          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-          {
-            /* Update error code */
-            hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-            
-            /* Process Unlocked */
-            __HAL_UNLOCK(hsai);
-            
-            /* Change the SAI state */
-            hsai->State = HAL_SAI_STATE_TIMEOUT;
-            
-            return HAL_TIMEOUT;
-          }
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_TIMEOUT;
+          
+          return HAL_TIMEOUT;
         }
       }
     }      
@@ -748,21 +756,21 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
-{  
-  if(hsai->State == HAL_SAI_STATE_READY)
-  {
+{
     if((pData == NULL) || (Size == 0)) 
     {
       return  HAL_ERROR;
     }
     
-    hsai->pBuffPtr = pData;
-    hsai->XferSize = Size;
-    hsai->XferCount = Size;
-    
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {    
     /* Process Locked */
     __HAL_LOCK(hsai);
     
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;    
     hsai->State = HAL_SAI_STATE_BUSY_TX;
     
     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
@@ -778,15 +786,15 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u
       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
     }
     
+    /* Fill the fifo before starting the communication */
+    SAI_FillFifo(hsai);
+    
     /* Enable FRQ and OVRUDR interrupts */
     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
     
     /* Check if the SAI is already enabled */ 
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
-    {
-      /* Fill the fifo before starting the communication */
-      SAI_FillFifo(hsai);
-      
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {      
       /* Enable SAI peripheral */    
       __HAL_SAI_ENABLE(hsai);
     }
@@ -811,21 +819,20 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u
   */
 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
 {
-  
-  if(hsai->State == HAL_SAI_STATE_READY)
-  {
     if((pData == NULL) || (Size == 0)) 
     {
       return  HAL_ERROR;
     }
     
-    hsai->pBuffPtr = pData;
-    hsai->XferSize = Size;
-    hsai->XferCount = Size;
-    
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {   
     /* Process Locked */
     __HAL_LOCK(hsai);
     
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;    
     hsai->State = HAL_SAI_STATE_BUSY_RX;
     
     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
@@ -839,12 +846,13 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui
     else
     {
       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
-    }    
+    }
+    
     /* Enable TXE and OVRUDR interrupts */
     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
     
     /* Check if the SAI is already enabled */ 
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */    
       __HAL_SAI_ENABLE(hsai);
@@ -874,7 +882,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
   
   /* Pause the audio file playing by disabling the SAI DMA requests */
   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hsai);
   
@@ -894,14 +902,14 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
   
   /* Enable the SAI DMA requests */
   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-  
+
   /* If the SAI peripheral is still not enabled, enable it */
   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
   {
     /* Enable SAI peripheral */    
     __HAL_SAI_ENABLE(hsai);
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hsai);
   
@@ -925,14 +933,20 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
   /* Abort the SAI DMA Tx Stream */
   if(hsai->hdmatx != NULL)
   {
-    HAL_DMA_Abort(hsai->hdmatx);
+    if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
   /* Abort the SAI DMA Rx Stream */
   if(hsai->hdmarx != NULL)
   {  
-    HAL_DMA_Abort(hsai->hdmarx);
+    if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
-
+  
   /* Disable SAI peripheral */
   SAI_Disable(hsai);
   
@@ -958,12 +972,18 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
   /* Abort the SAI DMA Tx Stream */
   if(hsai->hdmatx != NULL)
   {
-    HAL_DMA_Abort(hsai->hdmatx);
+    if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
   /* Abort the SAI DMA Rx Stream */
   if(hsai->hdmarx != NULL)
   {  
-    HAL_DMA_Abort(hsai->hdmarx);
+    if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
 
   /* Disabled All interrupt and clear all the flag */
@@ -1003,13 +1023,13 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData,
   
   if(hsai->State == HAL_SAI_STATE_READY)
   {  
-    hsai->pBuffPtr = pData;
-    hsai->XferSize = Size;
-    hsai->XferCount = Size;
-    
     /* Process Locked */
     __HAL_LOCK(hsai);
     
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
     hsai->State = HAL_SAI_STATE_BUSY_TX;
     
     /* Set the SAI Tx DMA Half transfer complete callback */
@@ -1026,7 +1046,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData,
     HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
     
     /* Check if the SAI is already enabled */ 
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */
       __HAL_SAI_ENABLE(hsai);
@@ -1067,14 +1087,14 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
   } 
   
   if(hsai->State == HAL_SAI_STATE_READY)
-  {    
-    hsai->pBuffPtr = pData;
-    hsai->XferSize = Size;
-    hsai->XferCount = Size;
-    
+  {   
     /* Process Locked */
     __HAL_LOCK(hsai);
     
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;    
     hsai->State = HAL_SAI_STATE_BUSY_RX;
     
     /* Set the SAI Rx DMA Half transfer complete callback */
@@ -1091,7 +1111,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
     HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
     
     /* Check if the SAI is already enabled */
-    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */
       __HAL_SAI_ENABLE(hsai);
@@ -1166,7 +1186,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback
   {
     /* set the mute counter */
     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
-    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << 6));
+    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
     hsai->mutecallback = callback;
     /* enable the IT interrupt */
     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
@@ -1265,6 +1285,16 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
         HAL_SAI_Abort(hsai);
         HAL_SAI_ErrorCallback(hsai);
       }
+      /* SAI CNRDY interrupt occurred ----------------------------------*/
+      if(((tmpFlag & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((tmpItSource & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+      {
+        /* Clear the SAI CNRDY flag */
+        __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+        /* Change the SAI error code */
+        hsai->ErrorCode = HAL_SAI_ERROR_CNREADY;
+        /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+        HAL_SAI_ErrorCallback(hsai);
+      }      
     }
   }
 }
@@ -1277,6 +1307,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
   */
  __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SAI_TxCpltCallback could be implemented in the user file
    */ 
@@ -1290,6 +1323,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
   */
  __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
    */ 
@@ -1303,6 +1339,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
   */
 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SAI_RxCpltCallback could be implemented in the user file
    */
@@ -1316,6 +1355,9 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
   */
 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SAI_RxCpltCallback could be implemented in the user file
    */
@@ -1329,6 +1371,9 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
   */
 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SAI_ErrorCallback could be implemented in the user file
    */ 
@@ -1410,7 +1455,7 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
   {
     return HAL_ERROR;
   }
-    
+  
   switch(protocol)
   {
   case SAI_I2S_STANDARD :
@@ -1425,9 +1470,8 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
   default :
     return HAL_ERROR;
   }
-   
+  
   /* Frame definition */
-  hsai->Init.DataSize = 0xFFFFFFFF;
   switch(datasize)
   {
   case SAI_PROTOCOL_DATASIZE_16BIT:
@@ -1437,41 +1481,37 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
     break; 
   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
-    if(hsai->Init.DataSize == 0xFFFFFFFF)
-    {
-      hsai->Init.DataSize = SAI_DATASIZE_16;
-    }
-    break; 
-  case SAI_PROTOCOL_DATASIZE_24BIT:
-    if(hsai->Init.DataSize == 0xFFFFFFFF)
-    {
-      hsai->Init.DataSize = SAI_DATASIZE_24;
-    }
-    break;
-  case SAI_PROTOCOL_DATASIZE_32BIT: 
-    if(hsai->Init.DataSize == 0xFFFFFFFF)
-    {
-      hsai->Init.DataSize = SAI_DATASIZE_32;
-    }
+    hsai->Init.DataSize = SAI_DATASIZE_16;
+    hsai->FrameInit.FrameLength = 64*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break; 
+  case SAI_PROTOCOL_DATASIZE_24BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_24;
+    hsai->FrameInit.FrameLength = 64*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_32BIT: 
+    hsai->Init.DataSize = SAI_DATASIZE_32;
     hsai->FrameInit.FrameLength = 64*(nbslot/2);
     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
-    if(protocol == SAI_I2S_LSBJUSTIFIED)
-    {
-      if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
-      {
-        hsai->SlotInit.FirstBitOffset = 16;
-      }
-      if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
-      {
-        hsai->SlotInit.FirstBitOffset = 8;
-      }
-    }
     break;
   default :
-    return HAL_ERROR;
+    return HAL_ERROR;  
+  }
+  if(protocol == SAI_I2S_LSBJUSTIFIED)
+  {
+    if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+    {
+      hsai->SlotInit.FirstBitOffset = 16;
+    }
+    if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+    {
+      hsai->SlotInit.FirstBitOffset = 8;
+    }
   }
- 
   return HAL_OK;
 }
 
@@ -1525,7 +1565,11 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol,
     hsai->FrameInit.FrameLength = 32 * nbslot;
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
     break;
-    
+  case SAI_PROTOCOL_DATASIZE_24BIT :
+    hsai->Init.DataSize = SAI_DATASIZE_24;
+    hsai->FrameInit.FrameLength = 32 * nbslot;
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;    
   case SAI_PROTOCOL_DATASIZE_32BIT: 
     hsai->Init.DataSize = SAI_DATASIZE_32;
     hsai->FrameInit.FrameLength = 32 * nbslot;
@@ -1547,7 +1591,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol,
 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
 {
   /* fill the fifo with data before to enabled the SAI */
-  while((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+  while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))   
   {
     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
     {
@@ -1582,6 +1626,12 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
   {
     tmpIT|= SAI_IT_FREQ;
   }
+
+  if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && 
+    ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+  {
+    tmpIT|= SAI_IT_CNRDY;
+  }
   
   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
   {
@@ -1615,10 +1665,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
       /* Update error code */
       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
       
-      status = HAL_TIMEOUT;
-      
-      /* Change the SAI state */
-      HAL_SAI_ErrorCallback(hsai);
+      return HAL_TIMEOUT;
     }
   }
   return status;
@@ -1632,18 +1679,20 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
   */
 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
 {
-  /* Write data on DR register */
-  hsai->Instance->DR = (*hsai->pBuffPtr++);
-  hsai->XferCount--;
-  
-  /* Handle the end of the transmission */
   if(hsai->XferCount == 0)
   {
+    /* Handle the end of the transmission */
     /* Disable FREQ and OVRUDR interrupts */
     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); 
     hsai->State = HAL_SAI_STATE_READY;
     HAL_SAI_TxCpltCallback(hsai);
   }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = (*hsai->pBuffPtr++);
+    hsai->XferCount--;
+  }  
 }
 
 /**
@@ -1654,19 +1703,21 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
   */
 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
 {
-  /* Write data on DR register */
-  hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
-  hsai->pBuffPtr+=2;
-  hsai->XferCount--;
-  
-  /* Handle the end of the transmission */
   if(hsai->XferCount == 0)
   {
+    /* Handle the end of the transmission */    
     /* Disable FREQ and OVRUDR interrupts */
     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); 
     hsai->State = HAL_SAI_STATE_READY;
     HAL_SAI_TxCpltCallback(hsai);
   }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr+=2;
+    hsai->XferCount--;
+  }  
 }
 
 /**
@@ -1677,19 +1728,21 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
   */
 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
 {
-  /* Write data on DR register */
-  hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
-  hsai->pBuffPtr+=4;
-  hsai->XferCount--;
-  
-  /* Handle the end of the transmission */
   if(hsai->XferCount == 0)
   {
+    /* Handle the end of the transmission */
     /* Disable FREQ and OVRUDR interrupts */
     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); 
     hsai->State = HAL_SAI_STATE_READY;
     HAL_SAI_TxCpltCallback(hsai);
   }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr+=4;
+    hsai->XferCount--;
+  }
 }
 
 /**
@@ -1779,8 +1832,6 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
   */
 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)   
 {
-  uint32_t tickstart = 0;
-  
   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
   
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
@@ -1789,25 +1840,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
     
     /* Disable SAI Tx DMA Request */  
     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    /* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */
-    /* Wait until FIFO is empty */    
-    while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
-      {         
-        /* Update error code */
-        hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-        
-        /* Change the SAI state */
-        HAL_SAI_ErrorCallback(hsai);
-      }
-    } 
-    
+
     /* Stop the interrupts error handling */
     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
     
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
index ddb8508832..33331b5e8f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SAI HAL module.
   ******************************************************************************
   * @attention
@@ -254,9 +254,8 @@ typedef struct __SAI_HandleTypeDef
   * @{
   */
 #define SAI_SYNCEXT_DISABLE           ((uint32_t)0x00000000)
-#define SAI_SYNCEXT_IN_ENABLE         ((uint32_t)0x00000001)
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE  ((uint32_t)0x00000002)
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE  ((uint32_t)0x00000004)
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE  ((uint32_t)0x00000001)
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE  ((uint32_t)0x00000002)
 /**
   * @}
   */
@@ -373,10 +372,10 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
   * @{
   */
-#define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000)
-#define SAI_SYNCHRONOUS                   ((uint32_t)SAI_xCR1_SYNCEN_0)
-#define SAI_SYNCHRONOUS_EXT               ((uint32_t)SAI_xCR1_SYNCEN_1) 
-
+#define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000) /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   ((uint32_t)0x00000001) /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          ((uint32_t)0x00000002) /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2          ((uint32_t)0x00000003) /*!< Synchronous with other SAI, SAI2 */
 /**
   * @}
   */ 
@@ -447,23 +446,23 @@ typedef struct __SAI_HandleTypeDef
   * @{
   */
 #define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000)
-#define SAI_SLOTACTIVE_0             ((uint32_t)0x00010000)
-#define SAI_SLOTACTIVE_1             ((uint32_t)0x00020000)
-#define SAI_SLOTACTIVE_2             ((uint32_t)0x00040000)
-#define SAI_SLOTACTIVE_3             ((uint32_t)0x00080000)
-#define SAI_SLOTACTIVE_4             ((uint32_t)0x00100000)
-#define SAI_SLOTACTIVE_5             ((uint32_t)0x00200000)
-#define SAI_SLOTACTIVE_6             ((uint32_t)0x00400000)
-#define SAI_SLOTACTIVE_7             ((uint32_t)0x00800000)
-#define SAI_SLOTACTIVE_8             ((uint32_t)0x01000000)
-#define SAI_SLOTACTIVE_9             ((uint32_t)0x02000000)
-#define SAI_SLOTACTIVE_10            ((uint32_t)0x04000000)
-#define SAI_SLOTACTIVE_11            ((uint32_t)0x08000000)
-#define SAI_SLOTACTIVE_12            ((uint32_t)0x10000000)
-#define SAI_SLOTACTIVE_13            ((uint32_t)0x20000000)
-#define SAI_SLOTACTIVE_14            ((uint32_t)0x40000000)
-#define SAI_SLOTACTIVE_15            ((uint32_t)0x80000000)
-#define SAI_SLOTACTIVE_ALL           ((uint32_t)0xFFFF0000)
+#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001)
+#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002)
+#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004)
+#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008)
+#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010)
+#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020)
+#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040)
+#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080)
+#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100)
+#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200)
+#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400)
+#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800)
+#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000)
+#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000)
+#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000)
+#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000)
+#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFF)
 
 /**
   * @}
@@ -762,7 +761,6 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
   * @{
   */
 #define IS_SAI_BLOCK_SYNCEXT(STATE)   (((STATE) == SAI_SYNCEXT_DISABLE)           ||\
-                                       ((STATE) == SAI_SYNCEXT_IN_ENABLE)         ||\
                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE)  ||\
                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
 
@@ -811,7 +809,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 
 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
                                        ((SYNCHRO) == SAI_SYNCHRONOUS)  || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT))
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
 
 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
@@ -849,7 +848,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
                                        ((MODE) == SAI_STEREOMODE)) 
 
-#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((((ACTIVE) >> 16 )  > 0) && (((ACTIVE) >> 16 )  <= (SAI_SLOTACTIVE_ALL >> 16)))
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
 
 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))  
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
index 942ebc0cb3..ede3db4149 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SAI Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of SAI extension peripheral:
@@ -111,20 +111,23 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
   /* This setting must be done with both audio block (A & B) disabled     */
   switch(hsai->Init.SynchroExt)
   {
-  case SAI_SYNCEXT_DISABLE :
+    case SAI_SYNCEXT_DISABLE :
+      tmpregisterGCR = 0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+      break;
+  default:
     tmpregisterGCR = 0;
     break;
-  case SAI_SYNCEXT_IN_ENABLE :
-    tmpregisterGCR = SAI_GCR_SYNCIN_0;
-    break;
-  case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
-    tmpregisterGCR = SAI_GCR_SYNCOUT_0;
-    break;
-  case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
-    tmpregisterGCR = SAI_GCR_SYNCOUT_1;
-    break;
-  default :
-    break;
+  }
+    
+  if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
+  {
+        tmpregisterGCR |= SAI_GCR_SYNCIN_0;
   }
   
   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
index a3d506bfdb..4b5878ac69 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SAI Extension HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
index 8ae5553ad7..fe7866ae12 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sd.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SD card HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Secure Digital (SD) peripheral:
@@ -413,6 +413,9 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
   */
 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_MspInit could be implemented in the user file
    */
@@ -425,6 +428,9 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
   */
 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_MspDeInit could be implemented in the user file
    */
@@ -1371,6 +1377,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
   */
 __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_XferCpltCallback could be implemented in the user file
    */ 
@@ -1383,6 +1392,9 @@ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
   */
 __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_XferErrorCallback could be implemented in the user file
    */ 
@@ -1396,6 +1408,9 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
   */
 __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
    */ 
@@ -1409,6 +1424,9 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
    */ 
@@ -1422,6 +1440,9 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
    */ 
@@ -1435,6 +1456,9 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
    */ 
@@ -1557,8 +1581,8 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
     /* Byte 10 */
     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
     
-    pCardInfo->CardCapacity  = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
-    pCardInfo->CardBlockSize = 512;    
+    pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);
+    pCardInfo->CardBlockSize = 512;
   }
   else
   {
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
index 77b0d024e7..785007900c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sd.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
index 8aba81f8af..9f67fed016 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sdram.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SDRAM HAL module driver.
   *          This file provides a generic firmware to drive SDRAM memories mounted 
   *          as external device.
@@ -197,6 +197,9 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
   */
 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_SDRAM_MspInit could be implemented in the user file
    */ 
@@ -210,6 +213,9 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
   */
 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_SDRAM_MspDeInit could be implemented in the user file
    */ 
@@ -242,6 +248,9 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
   */
 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
    */ 
@@ -255,6 +264,9 @@ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
   */
 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
    */ 
@@ -267,6 +279,9 @@ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
index 8978716c58..9eed428e20 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sdram.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SDRAM HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
index 9d42679a28..2e929705db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SMARTCARD HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the SMARTCARD peripheral:
@@ -274,6 +274,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
   */
  __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_MspInit could be implemented in the user file
    */
@@ -286,6 +289,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
   */
  __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_MspDeInit could be implemented in the user file
    */
@@ -792,6 +798,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
   */
  __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
    */ 
@@ -804,6 +813,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
   */
 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
    */
@@ -816,6 +828,9 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
   */
  __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
index bbe2895e7a..9e0107eccf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
index 137d022353..a1deeb6748 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SMARTCARD HAL module driver.
   *
   *          This file provides extended firmware functions to manage the following 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
index e0555b1ea9..6490714987 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
index c14a10a84a..55aca7575f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spdifrx.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the SPDIFRX audio interface:
   *           + Initialization and Configuration
@@ -304,6 +304,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
 {
+   /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_MspInit could be implemented in the user file
   */ 
@@ -316,6 +319,9 @@ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_MspDeInit could be implemented in the user file
   */ 
@@ -891,6 +897,9 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
   */
@@ -903,6 +912,9 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
   */
@@ -915,6 +927,9 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
   */
@@ -927,6 +942,9 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
   */
@@ -939,6 +957,9 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   */
 __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
   */ 
@@ -997,10 +1018,12 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
   
   /* Disable Rx DMA Request */
-  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
-  hspdif->RxXferCount = 0;
-  
-  hspdif->State = HAL_SPDIFRX_STATE_READY; 
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  {
+    hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+    hspdif->RxXferCount = 0;
+    hspdif->State = HAL_SPDIFRX_STATE_READY; 
+  }
   HAL_SPDIFRX_RxCpltCallback(hspdif); 
 }
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
index 612afa4f20..a96e73213f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spdifrx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SPDIFRX HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
index 79e80e8d66..add07bc7d0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SPI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -334,6 +334,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
   */
  __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
  {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
    /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_MspInit should be implemented in the user file
    */
@@ -347,6 +350,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
   */
  __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_MspDeInit should be implemented in the user file
    */
@@ -1723,6 +1729,9 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_TxCpltCallback should be implemented in the user file
    */
@@ -1736,6 +1745,9 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+   
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_RxCpltCallback should be implemented in the user file
    */
@@ -1749,6 +1761,9 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
    */
@@ -1762,6 +1777,9 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
    */
@@ -1775,6 +1793,9 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
    */
@@ -1788,6 +1809,9 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   */
 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
    */
@@ -1801,6 +1825,9 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   */
  __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SPI_ErrorCallback should be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
index fdfb1202a6..feb222959d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
@@ -470,7 +470,7 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
    do{                                              \
-     __IO uint32_t tmpreg;                          \
+   __IO uint32_t tmpreg = 0x00;                          \
      tmpreg = (__HANDLE__)->Instance->SR;           \
      (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
      UNUSED(tmpreg);                                \
@@ -484,7 +484,7 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
    do{                                              \
-     __IO uint32_t tmpreg;                          \
+   __IO uint32_t tmpreg = 0x00;                          \
      tmpreg = (__HANDLE__)->Instance->DR;           \
      tmpreg = (__HANDLE__)->Instance->SR;           \
      UNUSED(tmpreg);                                \
@@ -498,7 +498,7 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
    do{                                              \
-     __IO uint32_t tmpreg;                          \
+   __IO uint32_t tmpreg = 0x00;                          \
      tmpreg = (__HANDLE__)->Instance->SR;           \
      UNUSED(tmpreg);                                \
    } while(0)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
index 22466a150a..e7fb8ff6e5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sram.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SRAM HAL module driver.
   *          This file provides a generic firmware to drive SRAM memories  
   *          mounted as external device.
@@ -197,6 +197,9 @@ HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
   */
 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_MspInit could be implemented in the user file
    */ 
@@ -210,6 +213,9 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
   */
 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_MspDeInit could be implemented in the user file
    */ 
@@ -223,6 +229,9 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
   */
 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
    */ 
@@ -236,6 +245,9 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
index 578efb21d7..ee3b310c9a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sram.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
index 2176bf097e..9c28ebe92f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer (TIM) peripheral:
@@ -265,6 +265,9 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_Base_MspInit could be implemented in the user file
    */
@@ -278,6 +281,9 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_Base_MspDeInit could be implemented in the user file
    */
@@ -544,6 +550,9 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_OC_MspInit could be implemented in the user file
    */
@@ -557,6 +566,9 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_OC_MspDeInit could be implemented in the user file
    */
@@ -1053,6 +1065,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_PWM_MspInit could be implemented in the user file
    */
@@ -1066,6 +1081,9 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
    */
@@ -1565,6 +1583,9 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_IC_MspInit could be implemented in the user file
    */
@@ -1578,6 +1599,9 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+   
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_IC_MspDeInit could be implemented in the user file
    */
@@ -2050,6 +2074,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
    */
@@ -2063,6 +2090,9 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
    */
@@ -2366,6 +2396,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_Encoder_MspInit could be implemented in the user file
    */
@@ -2379,6 +2412,9 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
    */
@@ -2948,9 +2984,6 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
   assert_param(IS_TIM_CHANNELS(Channel)); 
   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
-  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
-  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
   
   /* Check input state */
   __HAL_LOCK(htim); 
@@ -3120,9 +3153,6 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
   assert_param(IS_TIM_CHANNELS(Channel)); 
   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
-  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
-  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); 
   
   htim->State = HAL_TIM_STATE_BUSY;
@@ -3938,9 +3968,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
   
   /* Check the parameters */
   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-  assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-  assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-  assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
   
   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
   tmpsmcr = htim->Instance->SMCR;
@@ -3961,6 +3988,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_ETRMODE1:
     {
       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
       /* Configure the ETR Clock source */
       TIM_ETR_SetConfig(htim->Instance, 
                         sClockSourceConfig->ClockPrescaler, 
@@ -3980,6 +4010,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_ETRMODE2:
     {
       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+      
       /* Configure the ETR Clock source */
       TIM_ETR_SetConfig(htim->Instance, 
                         sClockSourceConfig->ClockPrescaler, 
@@ -3993,6 +4027,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_TI1:
     {
       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+  
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
       TIM_TI1_ConfigInputStage(htim->Instance, 
                         sClockSourceConfig->ClockPolarity, 
                         sClockSourceConfig->ClockFilter);
@@ -4002,6 +4041,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_TI2:
     {
       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+      
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
       TIM_TI2_ConfigInputStage(htim->Instance, 
                         sClockSourceConfig->ClockPolarity, 
                         sClockSourceConfig->ClockFilter);
@@ -4011,6 +4055,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_TI1ED:
     {
       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+  
       TIM_TI1_ConfigInputStage(htim->Instance, 
                         sClockSourceConfig->ClockPolarity,
                         sClockSourceConfig->ClockFilter);
@@ -4374,6 +4422,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
    */
@@ -4387,6 +4438,9 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
    */
@@ -4399,6 +4453,9 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
    */
@@ -4412,6 +4469,9 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
    */
@@ -4425,6 +4485,9 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_TriggerCallback could be implemented in the user file
    */
@@ -4438,6 +4501,9 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIM_ErrorCallback could be implemented in the user file
    */
@@ -4793,8 +4859,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
   {
     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
     
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC2NP;
@@ -4861,8 +4925,6 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
   {
     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
     
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC3NP;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
index 54b04bd298..f537e8e18c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
index 754b3b1dfa..e870df8488 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer extension peripheral:
@@ -266,6 +266,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
    */
@@ -279,6 +282,9 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
    */
@@ -1643,9 +1649,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
   assert_param(IS_TIM_CHANNELS(Channel)); 
   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
-  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
-  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
   
   /* Check input state */
   __HAL_LOCK(htim); 
@@ -1749,10 +1752,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
   assert_param(IS_TIM_CHANNELS(Channel)); 
   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
-  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
   
   /* Check input state */
   __HAL_LOCK(htim);
@@ -2265,6 +2265,9 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe
   */
 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIMEx_CommutationCallback could be implemented in the user file
    */
@@ -2278,6 +2281,9 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
   */
 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+ 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_TIMEx_BreakCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
index f043937de6..290ccfc32f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of TIM HAL Extension module.
   ******************************************************************************
   * @attention
@@ -123,8 +123,7 @@ typedef struct
 
 /**
   * @}
-  */
-  
+  */  
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup TIMEx_Exported_Constants  TIMEx Exported Constants
   * @{
@@ -261,6 +260,7 @@ typedef struct
 /**
   * @}
   */
+
 /**
   * @}
   */
@@ -291,7 +291,7 @@ typedef struct
  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
 
 /**
   * @brief  Gets the TIM Capture Compare Register value on runtime
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
index a321b7d86d..d9a6444515 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   UART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -168,7 +168,6 @@
     
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define HAL_UART_TXDMA_TIMEOUTVALUE                      22000
 #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
 /* Private macro -------------------------------------------------------------*/
@@ -524,6 +523,9 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
   */
  __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_MspInit can be implemented in the user file
    */ 
@@ -536,6 +538,9 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
   */
  __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_MspDeInit can be implemented in the user file
    */ 
@@ -1364,6 +1369,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   */
  __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_TxCpltCallback can be implemented in the user file
    */ 
@@ -1376,6 +1384,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   */
  __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_TxHalfCpltCallback can be implemented in the user file
    */ 
@@ -1388,6 +1399,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   */
 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_RxCpltCallback can be implemented in the user file
    */
@@ -1400,6 +1414,9 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
   */
 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_RxHalfCpltCallback can be implemented in the user file
    */
@@ -1412,6 +1429,9 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
   */
  __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_ErrorCallback can be implemented in the user file
    */ 
@@ -1442,10 +1462,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
         huart->State = HAL_UART_STATE_BUSY_RX;
       }
       else
-      {
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-        
+      {      
         huart->State = HAL_UART_STATE_READY;
       }
       
@@ -1501,9 +1518,6 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
   }
   else
   {
-    /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
     huart->State = HAL_UART_STATE_READY;
   }
 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
index 076aed8fc3..3fc66b3c50 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
@@ -102,7 +102,7 @@ typedef struct
 }UART_InitTypeDef;
 
 /**
-  * @brief  UART Advanced Features initalization structure definition
+  * @brief  UART Advanced Features initialization structure definition
   */
 typedef struct
 {
@@ -653,7 +653,7 @@ typedef struct
   *            @arg UART_CLEAR_CMF: Character Match Clear Flag
   * @retval None
   */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
 
 /** @brief  Clear the UART PE pending flag.
   * @param  __HANDLE__: specifies the UART Handle.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
index bff4b06894..6d6d656eda 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of UART HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
index 2bfa1160d5..a56cebf320 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   USART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
@@ -100,8 +100,6 @@
   */
 #define DUMMY_DATA                             ((uint16_t) 0xFFFF)
 #define TEACK_REACK_TIMEOUT                    ((uint32_t) 1000)
-#define USART_TXDMA_TIMEOUTVALUE            22000
-#define USART_TIMEOUT_VALUE                 22000
 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                      USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))
 #define USART_CR2_FIELDS       ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
@@ -269,6 +267,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   */
  __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_MspInit can be implemented in the user file
    */
@@ -281,6 +282,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   */
  __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_MspDeInit can be implemented in the user file
    */
@@ -1149,6 +1153,9 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
   */
 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_TxCpltCallback can be implemented in the user file
    */ 
@@ -1161,6 +1168,9 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
   */
  __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_TxHalfCpltCallback can be implemented in the user file
    */
@@ -1173,6 +1183,9 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
   */
 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_RxCpltCallback can be implemented in the user file
    */
@@ -1185,6 +1198,9 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
   */
 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
    */
@@ -1197,6 +1213,9 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
   */
 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_TxRxCpltCallback can be implemented in the user file
    */
@@ -1209,6 +1228,9 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
   */
 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+ 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_USART_ErrorCallback can be implemented in the user file
    */ 
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
index 03be547c20..578ff91d78 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
index ad6aa19c8e..b53b85afab 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart_ex.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of USART HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
index 724653ed52..e5e6ee1952 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   WWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Window Watchdog (WWDG) peripheral:
@@ -16,7 +16,7 @@
   ==============================================================================
   [..] 
     Once enabled the WWDG generates a system reset on expiry of a programmed
-    time period, unless the program refreshes the counter (downcounter) 
+    time period, unless the program refreshes the counter (down-counter) 
     before reaching 0x3F value (i.e. a reset is generated when the counter
     value rolls over from 0x40 to 0x3F). 
        
@@ -234,6 +234,9 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
   */
 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_WWDG_MspInit could be implemented in the user file
    */
@@ -247,6 +250,9 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
   */
 __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_WWDG_MspDeInit could be implemented in the user file
    */
@@ -399,6 +405,9 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
   */
 __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+ 
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_WWDG_WakeupCallback could be implemented in the user file
    */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
index a889bf8664..29eb602dbc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
@@ -131,8 +131,8 @@ typedef struct
   * @{
   */ 
 #define WWDG_PRESCALER_1                 ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
 /**
   * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
index 38adbcae50..212cd411b3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_fmc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   FMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -1025,8 +1025,6 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com
         return HAL_TIMEOUT;
       }
     }     
-    
-    return HAL_ERROR;
   }
   
   return HAL_OK;  
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
index 019ec0643b..85dcec696c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_fmc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of FMC HAL module.
   ******************************************************************************
   * @attention
@@ -385,6 +385,7 @@
 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
                                    ((__SIZE__) == FMC_PAGE_SIZE_128) || \
                                    ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \
                                    ((__SIZE__) == FMC_PAGE_SIZE_1024))
 
 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
@@ -793,6 +794,7 @@ typedef struct
 #define FMC_PAGE_SIZE_NONE           ((uint32_t)0x00000000)
 #define FMC_PAGE_SIZE_128            ((uint32_t)FMC_BCR1_CPSIZE_0)
 #define FMC_PAGE_SIZE_256            ((uint32_t)FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_512            ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
 #define FMC_PAGE_SIZE_1024           ((uint32_t)FMC_BCR1_CPSIZE_2)
 /**
   * @}
@@ -819,8 +821,8 @@ typedef struct
 /** @defgroup FMC_Write_FIFO FMC Write FIFO 
   * @{
   */
-#define FMC_WRITE_FIFO_DISABLE           ((uint32_t)0x00000000)
-#define FMC_WRITE_FIFO_ENABLE            ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_DISABLE           ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_ENABLE            ((uint32_t)0x00000000)
 /**
   * @}
   */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
index 565a24271c..b99067f01d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_sdmmc.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   SDMMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -485,7 +485,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM
   assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
   
   /* Set SDMMC read wait mode */
-  SDMMCx->DCTRL |= SDMMC_ReadWaitMode;
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
   
   return HAL_OK;  
 }
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
index 454ceffe4b..374156a7fa 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
index 2e9d772332..acabf79eff 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_usb.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   USB Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -72,7 +72,8 @@
 /* Private functions ---------------------------------------------------------*/
 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
 
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
   * @{
   */
 
@@ -117,7 +118,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   }
   else /* FS interface (embedded Phy) */
   {
-    
     /* Select FS Embedded PHY */
     USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
     
@@ -166,7 +166,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
   * @brief  USB_SetCurrentMode : Set functional mode
   * @param  USBx : Selected device
   * @param  mode :  current core mode
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
   *            @arg USB_OTG_HOST_MODE: Host mode
   *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
@@ -206,7 +206,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   
   if (cfg.vbus_sensing_enable == 0)
   {
-    /*Desactivate VBUS Sensing B */
+    /* Deactivate VBUS Sensing B */
     USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
     
     /* B-peripheral session valid override enable*/ 
@@ -242,7 +242,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   /* Flush the FIFOs */
   USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
   USB_FlushRxFifo(USBx);
-
   
   /* Clear all pending Device Interrupts */
   USBx_DEVICE->DIEPMSK = 0;
@@ -378,7 +377,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
   *         depending the PHY type and the enumeration speed of the device.
   * @param  USBx : Selected device
   * @param  speed : device speed
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
@@ -395,7 +394,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
   * @brief  USB_GetDevSpeed :Return the  Dev Speed 
   * @param  USBx : Selected device
   * @retval speed : device speed
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
   *            @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -512,7 +511,6 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
   }
   else
   {
-
      USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
      USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     
      USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
@@ -547,7 +545,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
   * @param  USBx : Selected device
   * @param  ep: pointer to endpoint structure
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @retval HAL status
@@ -669,7 +667,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
   * @param  USBx : Selected device
   * @param  ep: pointer to endpoint structure
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @retval HAL status
@@ -758,7 +756,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
   * @param  ch_ep_num : endpoint or host channel number
   * @param  len : Number of bytes to write
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @retval HAL status
@@ -786,7 +784,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
   * @param  ch_ep_num : endpoint or host channel number
   * @param  len : Number of bytes to read
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @retval pointer to destination buffer
@@ -1017,7 +1015,7 @@ void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
   * @brief  Returns USB core mode
   * @param  USBx : Selected device
   * @retval return core mode : Host or Device
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : Host 
   *           1 : Device
   */
@@ -1051,7 +1049,7 @@ HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
   * @brief  Prepare the EP0 to start the first control setup
   * @param  USBx : Selected device
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @param  psetup : pointer to setup packet
@@ -1161,7 +1159,6 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
   
   /* Clear any pending interrupts */
   USBx->GINTSTS = 0xFFFFFFFF;
-
   
   if(USBx == USB_OTG_FS)
   {
@@ -1169,9 +1166,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
     USBx->GRXFSIZ  = (uint32_t )0x80; 
     USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
     USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-
   }
-
   else
   {
     /* set Rx FIFO size */
@@ -1199,7 +1194,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
   *         HCFG register on the PHY type and set the right frame interval
   * @param  USBx : Selected device
   * @param  freq : clock frequency
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
   *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
   * @retval HAL status
@@ -1245,7 +1240,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
 /**
   * @brief  USB_DriveVbus : activate or de-activate vbus
   * @param  state : VBUS state
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : VBUS Active 
   *           1 : VBUS Inactive
   * @retval HAL status
@@ -1273,7 +1268,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
   * @brief  Return Host Core speed
   * @param  USBx : Selected device
   * @retval speed : Host speed
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
   *            @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -1306,12 +1301,12 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
   * @param  dev_address : Current device address
   *          This parameter can be a value from 0 to 255
   * @param  speed : Current device speed
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
   *            @arg USB_OTG_SPEED_LOW: Low speed mode
   * @param  ep_type : Endpoint Type
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *            @arg EP_TYPE_CTRL: Control type
   *            @arg EP_TYPE_ISOC: Isochronous type
   *            @arg EP_TYPE_BULK: Bulk type
@@ -1357,6 +1352,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
       }
     }
     break;
+    
   case EP_TYPE_INTR:
     
     USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
@@ -1414,7 +1410,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
   * @param  USBx : Selected device
   * @param  hc : pointer to host channel structure
   * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of the these values:
+  *          This parameter can be one of these values:
   *           0 : DMA feature not used 
   *           1 : DMA feature used  
   * @retval HAL state
@@ -1466,8 +1462,6 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
     hc->xfer_len = num_packets * hc->max_packet;
   }
   
-  
-  
   /* Initialize the HCTSIZn register */
   USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
     ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
@@ -1658,8 +1652,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
   
   /* Halt all channels to put them into a known state. */  
   for (i = 0; i <= 15; i++)
-  {   
-
+  {
     value = USBx_HC(i)->HCCHAR ;
     
     value |= USB_OTG_HCCHAR_CHDIS;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
index 7b0b0acc68..568d8fa682 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_usb.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   Header file of USB Core HAL module.
   ******************************************************************************
   * @attention

From 49338852ad3050f6d4cccd9bc89690e72ac5ab8e Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 4 Mar 2016 14:32:00 +0100
Subject: [PATCH 74/78] [STM32F7_DISCO_F746NG] Update target files with latest
 STM32F7Cube_FW version

---
 .../TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S |  10 +-
 .../TOOLCHAIN_ARM_MICRO/stm32f746ng.sct       |   2 +-
 .../TOOLCHAIN_ARM_STD/startup_stm32f746ng.S   |  10 +-
 .../TOOLCHAIN_ARM_STD/stm32f746ng.sct         |   2 +-
 .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S   |   4 +-
 .../TOOLCHAIN_IAR/startup_stm32f746xx.S       |   6 +-
 .../TARGET_DISCO_F746NG/cmsis.h               |   2 +-
 .../TARGET_DISCO_F746NG/cmsis_nvic.c          |   4 +-
 .../TARGET_DISCO_F746NG/cmsis_nvic.h          |   2 +-
 .../TARGET_DISCO_F746NG/hal_tick.c            |   2 +-
 .../TARGET_DISCO_F746NG/hal_tick.h            |   2 +-
 .../TARGET_DISCO_F746NG/stm32f746xx.h         | 122 ++++++++-----
 .../TARGET_DISCO_F746NG/stm32f7xx.h           |   6 +-
 .../TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h  |   6 +-
 .../TARGET_DISCO_F746NG/system_stm32f7xx.c    | 168 ++++++++++++++++--
 .../TARGET_DISCO_F746NG/system_stm32f7xx.h    |   6 +-
 16 files changed, 265 insertions(+), 89 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S
index ab302a5d11..b2326dcd07 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S
@@ -1,8 +1,8 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -350,12 +350,12 @@ Default_Handler PROC
                 EXPORT  DMA2D_IRQHandler                  [WEAK]
                 EXPORT  SAI2_IRQHandler                   [WEAK]   
                 EXPORT  QUADSPI_IRQHandler                [WEAK]
-				EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
                 EXPORT  CEC_IRQHandler                    [WEAK]   
                 EXPORT  I2C4_EV_IRQHandler                [WEAK]
-				EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
                 EXPORT  SPDIF_RX_IRQHandler               [WEAK]
-				
+
 WWDG_IRQHandler                                                       
 PVD_IRQHandler                                      
 TAMP_STAMP_IRQHandler                  
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct
index aabd424957..cb52146d47 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct
@@ -1,6 +1,6 @@
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
+; Copyright (c) 2016, STMicroelectronics
 ; All rights reserved.
 ;
 ; Redistribution and use in source and binary forms, with or without
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S
index 76cd68372a..4e25bfa2a8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S
@@ -1,8 +1,8 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -323,12 +323,12 @@ Default_Handler PROC
                 EXPORT  DMA2D_IRQHandler                  [WEAK]
                 EXPORT  SAI2_IRQHandler                   [WEAK]   
                 EXPORT  QUADSPI_IRQHandler                [WEAK]
-				EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
                 EXPORT  CEC_IRQHandler                    [WEAK]   
                 EXPORT  I2C4_EV_IRQHandler                [WEAK]
-				EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
                 EXPORT  SPDIF_RX_IRQHandler               [WEAK]
-				
+
 WWDG_IRQHandler                                                       
 PVD_IRQHandler                                      
 TAMP_STAMP_IRQHandler                  
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct
index aabd424957..cb52146d47 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct
@@ -1,6 +1,6 @@
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
+; Copyright (c) 2016, STMicroelectronics
 ; All rights reserved.
 ;
 ; Redistribution and use in source and binary forms, with or without
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
index 1fcde5f2bd..b14a8455b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f746xx.s
   * @author    MCD Application Team
-  * Version    V1.0.0
-  * Date       28-April-2015
+  * @Version    V1.0.2
+  * @Date       21-September-2015
   * @brief     STM32F746xx Devices vector table for GCC based toolchain. 
   *            This module performs:
   *                - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S
index 50788a47c1..42431f529c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h
index 1341e459a1..ee3ba9007b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h
@@ -1,7 +1,7 @@
 /* mbed Microcontroller Library
  * A generic CMSIS include header
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2016, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c
index 9263c748e7..69a0fa5832 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c
@@ -1,7 +1,7 @@
 /* mbed Microcontroller Library
  * CMSIS-style functionality to support dynamic vectors
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2016, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,7 +27,7 @@
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
- */ 
+ */
 #include "cmsis_nvic.h"
 
 #define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h
index b37c70e1a1..0a26d73682 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h
@@ -1,7 +1,7 @@
 /* mbed Microcontroller Library
  * CMSIS-style functionality to support dynamic vectors
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2016, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c
index a1b76f9b61..e21ca156ae 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c
@@ -6,7 +6,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h
index 168d313950..6501819b5d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h
@@ -6,7 +6,7 @@
   ******************************************************************************  
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h
index a510fb023c..b84b4cf36e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f746xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS STM32F746xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -14,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -64,7 +64,7 @@
  * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
  *        in @ref Library_configuration_section 
  */
-typedef enum IRQn
+typedef enum
 {
 /******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
@@ -125,7 +125,7 @@ typedef enum IRQn
   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                             */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
@@ -182,14 +182,14 @@ typedef enum IRQn
 /**
  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
  */
-#define __CM7_REV                 0x0000   /*!< Cortex-M7 revision r0p1                       */
+#define __CM7_REV                 0x0001  /*!< Cortex-M7 revision r0p1                       */
 #define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
 #define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
 #define __FPU_PRESENT             1       /*!< FPU present                                   */
 #define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
 #define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals      */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
   
   
 #include "system_stm32f7xx.h"
@@ -353,6 +353,7 @@ typedef struct
   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
 } DAC_TypeDef;
 
+
 /** 
   * @brief Debug MCU
   */
@@ -697,11 +698,10 @@ typedef struct
   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
   uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                              Address offset: 0x144 */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
 
 } LTDC_Layer_TypeDef;
 
-
 /** 
   * @brief Power Control
   */
@@ -967,7 +967,6 @@ typedef struct
   __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
   __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;       /*!< LPTIM Option register,                              Address offset: 0x20 */
 } LPTIM_TypeDef;
 
 
@@ -1002,6 +1001,7 @@ typedef struct
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 
+
 /** 
   * @brief RNG
   */
@@ -1140,7 +1140,8 @@ typedef struct
   * @}
   */
 
-  
+
+
 /** @addtogroup Peripheral_memory_map
   * @{
   */
@@ -1148,13 +1149,13 @@ typedef struct
 #define FLASHITCM_BASE         ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory  accessible over ITCM               */                       
 #define FLASHAXI_BASE          ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */                       
 #define RAMDTCM_BASE           ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
-#define SRAM1_BASE             ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
 #define PERIPH_BASE            ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals                                                   */
 #define BKPSRAM_BASE           ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB)                                                     */
 #define QSPI_BASE              ((uint32_t)0x90000000) /*!< Base address of : QSPI memories  accessible over AXI                                    */
 #define FMC_R_BASE             ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers                                                 */
 #define QSPI_R_BASE            ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control  registers                                               */
+#define SRAM1_BASE             ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
 #define FLASH_END              ((uint32_t)0x080FFFFF) /*!< FLASH end address */
 
 /* Legacy define */
@@ -1226,7 +1227,7 @@ typedef struct
 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104)
 /*!< AHB1 peripherals */
 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
@@ -3125,6 +3126,7 @@ typedef struct
 /*******************  Bit definition for CRC_POL register  ********************/
 #define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF)     /*!< Coefficients of the polynomial */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                      Digital to Analog Converter                           */
@@ -3216,6 +3218,7 @@ typedef struct
 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                                 Debug MCU                                  */
@@ -3291,7 +3294,7 @@ typedef struct
 #define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
 #define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
 #define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000)
 #define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
 #define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
 #define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
@@ -3841,8 +3844,6 @@ typedef struct
 #define FLASH_OPTCR1_BOOT_ADD0              ((uint32_t)0x0000FFFF)
 #define FLASH_OPTCR1_BOOT_ADD1              ((uint32_t)0xFFFF0000)
 
-
-
 /******************************************************************************/
 /*                                                                            */
 /*                          Flexible Memory Controller                        */
@@ -4877,6 +4878,7 @@ typedef struct
 #define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
 #define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                      Inter-integrated Circuit Interface (I2C)              */
@@ -4891,7 +4893,7 @@ typedef struct
 #define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable     */
 #define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable  */
 #define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
+#define  I2C_CR1_DNF                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
 #define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF             */
 #define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset                      */
 #define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable    */
@@ -4905,6 +4907,9 @@ typedef struct
 #define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable                  */
 #define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable                          */
 
+/* Legacy define */
+#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
+
 /******************  Bit definition for I2C_CR2 register  ********************/
 #define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode)                             */
 #define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode)                        */
@@ -5163,7 +5168,6 @@ typedef struct
 #define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value    */
 #define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                             Power Control                                  */
@@ -5453,6 +5457,7 @@ typedef struct
 #define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
 #define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
 
+
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
@@ -6496,7 +6501,7 @@ typedef struct
 #define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
 #define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000)        /*!< Complement Bit             */
 
 #define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
 #define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
@@ -6907,13 +6912,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_BOOT          ((uint32_t)0x00000001) /*!< Boot information after Reset */
+#define SYSCFG_MEMRMP_MEM_BOOT         ((uint32_t)0x00000001) /*!< Boot information after Reset */
+
 
 #define SYSCFG_MEMRMP_SWP_FMC          ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
 #define SYSCFG_MEMRMP_SWP_FMC_0        ((uint32_t)0x00000400) 
 #define SYSCFG_MEMRMP_SWP_FMC_1        ((uint32_t)0x00000800) 
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
+
 #define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
 #define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
 #define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
@@ -7540,6 +7547,7 @@ typedef struct
 /*******************  Bit definition for TIM_CCR6 register  *******************/
 #define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 6 Value */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                         Low Power Timer (LPTIM)                            */
@@ -7705,6 +7713,7 @@ typedef struct
 #define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
 #define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
 
+
 /******************  Bit definition for USART_BRR register  *******************/
 #define  USART_BRR_DIV_FRACTION              ((uint32_t)0x000F)                /*!< Fraction of USARTDIV */
 #define  USART_BRR_DIV_MANTISSA              ((uint32_t)0xFFF0)                /*!< Mantissa of USARTDIV */
@@ -7775,35 +7784,57 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                            ((uint32_t)0x7F)                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                          ((uint32_t)0x01)                 /*!<Bit 0 */
+#define  WWDG_CR_T_1                          ((uint32_t)0x02)                 /*!<Bit 1 */
+#define  WWDG_CR_T_2                          ((uint32_t)0x04)                 /*!<Bit 2 */
+#define  WWDG_CR_T_3                          ((uint32_t)0x08)                 /*!<Bit 3 */
+#define  WWDG_CR_T_4                          ((uint32_t)0x10)                 /*!<Bit 4 */
+#define  WWDG_CR_T_5                          ((uint32_t)0x20)                 /*!<Bit 5 */
+#define  WWDG_CR_T_6                          ((uint32_t)0x40)                 /*!<Bit 6 */
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+/* Legacy defines */
+#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
+#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
+#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
+#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
+#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
+#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
+#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint32_t)0x80)                  /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          ((uint32_t)0x007F)                /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        ((uint32_t)0x0001)                /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        ((uint32_t)0x0002)                /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        ((uint32_t)0x0004)                /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        ((uint32_t)0x0008)                /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        ((uint32_t)0x0010)                /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        ((uint32_t)0x0020)                /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        ((uint32_t)0x0040)                /*!<Bit 6 */
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)                /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    ((uint32_t)0x0080)                /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    ((uint32_t)0x0100)                /*!<Bit 1 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)               /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        ((uint32_t)0x01)                  /*!<Early Wakeup Interrupt Flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -8476,6 +8507,7 @@ typedef struct
 #define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask               */
 #define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask                          */
 #define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                ((uint32_t)0x00000020)            /*!< Status Phase Received mask                     */
 #define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask       */
 #define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask                          */
 #define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask                             */
@@ -8943,6 +8975,7 @@ typedef struct
 #define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
 #define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
 #define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 ((uint32_t)0x00000020)            /*!< Status Phase Received For Control Write */
 #define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
 #define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
 
@@ -8989,6 +9022,7 @@ typedef struct
 /******************************* DCMI Instances *******************************/
 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
 
+
 /******************************* DMA2D Instances *******************************/
 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
 
@@ -9059,6 +9093,7 @@ typedef struct
 /****************************** LTDC Instances ********************************/
 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
 
+
 /******************************* RNG Instances ********************************/
 #define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
 
@@ -9075,7 +9110,6 @@ typedef struct
 /******************************** SDMMC Instances *******************************/
 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
 
-
 /****************************** SPDIFRX Instances *********************************/
 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
                                      
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h
index 5ec8dd9f13..1602f517b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h
index 8c67585b9b..d0339d3055 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h
@@ -2,15 +2,15 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f7xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c
index 9c3676eb68..9672a56d78 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -39,7 +39,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -109,14 +109,13 @@ HAL_StatusTypeDef HAL_Init(void);
 
 /************************* Miscellaneous Configuration ************************/
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on EVAL board as data memory  */
+     on STMicroelectronics EVAL/Discovery boards as data memory  */
+/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
+     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
+     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
 /* #define DATA_IN_ExtSRAM */ 
 /* #define DATA_IN_ExtSDRAM */
 
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " 
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
-
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
@@ -218,7 +217,7 @@ void SystemInit(void)
 
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
@@ -336,7 +335,151 @@ void SystemCoreClockUpdate(void)
 void SystemInit_ExtMemCtl(void)
 {
   __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM)
+#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;  
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;  
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xFF800FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC00000CC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80220AAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80320FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40110555;
+
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;   
+
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
+  
+#elif defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
   register uint32_t index;
 
@@ -473,9 +616,8 @@ void SystemInit_ExtMemCtl(void)
   /* Disable write protection */
   tmpreg = FMC_Bank5_6->SDCR[0]; 
   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif /* DATA_IN_ExtSDRAM */
-
-#if defined(DATA_IN_ExtSRAM)
+  
+#elif defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
   RCC->AHB1ENR   |= 0x00000078;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h
index 529cb4a24d..146e57a589 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

From c97e05f4962c3ee5768a3f1af07abf5ca785d2f9 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Fri, 4 Mar 2016 14:32:17 +0100
Subject: [PATCH 75/78] [STM32F7_NUCLEO_F746ZG] Update target files with latest
 STM32F7Cube_FW version

---
 .../TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S |   4 +-
 .../TOOLCHAIN_ARM_STD/startup_stm32f746zg.S   |   4 +-
 .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S   |   4 +-
 .../TOOLCHAIN_IAR/startup_stm32f746xx.S       |   4 +-
 .../TARGET_NUCLEO_F746ZG/stm32f746xx.h        | 122 ++++--
 .../TARGET_NUCLEO_F746ZG/stm32f7xx.h          |   6 +-
 .../TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h |   6 +-
 .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.c   | 392 +++++++++++++++++-
 .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.h   |   6 +-
 9 files changed, 483 insertions(+), 65 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
index 71ee787e89..b2326dcd07 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
@@ -1,8 +1,8 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
index 92857c9fda..4e25bfa2a8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
@@ -1,8 +1,8 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
index 1fcde5f2bd..b14a8455b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f746xx.s
   * @author    MCD Application Team
-  * Version    V1.0.0
-  * Date       28-April-2015
+  * @Version    V1.0.2
+  * @Date       21-September-2015
   * @brief     STM32F746xx Devices vector table for GCC based toolchain. 
   *            This module performs:
   *                - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
index 70dad9c77c..42431f529c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
@@ -1,8 +1,8 @@
 ;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
 ;* File Name          : startup_stm32f746xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 28-April-2015
+;* Version            : V1.0.2
+;* Date               : 21-September-2015
 ;* Description        : STM32F746xx devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
index a510fb023c..b84b4cf36e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f746xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS STM32F746xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -14,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -64,7 +64,7 @@
  * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
  *        in @ref Library_configuration_section 
  */
-typedef enum IRQn
+typedef enum
 {
 /******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
@@ -125,7 +125,7 @@ typedef enum IRQn
   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                             */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
@@ -182,14 +182,14 @@ typedef enum IRQn
 /**
  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
  */
-#define __CM7_REV                 0x0000   /*!< Cortex-M7 revision r0p1                       */
+#define __CM7_REV                 0x0001  /*!< Cortex-M7 revision r0p1                       */
 #define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
 #define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
 #define __FPU_PRESENT             1       /*!< FPU present                                   */
 #define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
 #define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals      */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
   
   
 #include "system_stm32f7xx.h"
@@ -353,6 +353,7 @@ typedef struct
   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
 } DAC_TypeDef;
 
+
 /** 
   * @brief Debug MCU
   */
@@ -697,11 +698,10 @@ typedef struct
   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
   uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                              Address offset: 0x144 */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
 
 } LTDC_Layer_TypeDef;
 
-
 /** 
   * @brief Power Control
   */
@@ -967,7 +967,6 @@ typedef struct
   __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
   __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;       /*!< LPTIM Option register,                              Address offset: 0x20 */
 } LPTIM_TypeDef;
 
 
@@ -1002,6 +1001,7 @@ typedef struct
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 
+
 /** 
   * @brief RNG
   */
@@ -1140,7 +1140,8 @@ typedef struct
   * @}
   */
 
-  
+
+
 /** @addtogroup Peripheral_memory_map
   * @{
   */
@@ -1148,13 +1149,13 @@ typedef struct
 #define FLASHITCM_BASE         ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory  accessible over ITCM               */                       
 #define FLASHAXI_BASE          ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */                       
 #define RAMDTCM_BASE           ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
-#define SRAM1_BASE             ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
 #define PERIPH_BASE            ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals                                                   */
 #define BKPSRAM_BASE           ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB)                                                     */
 #define QSPI_BASE              ((uint32_t)0x90000000) /*!< Base address of : QSPI memories  accessible over AXI                                    */
 #define FMC_R_BASE             ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers                                                 */
 #define QSPI_R_BASE            ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control  registers                                               */
+#define SRAM1_BASE             ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
 #define FLASH_END              ((uint32_t)0x080FFFFF) /*!< FLASH end address */
 
 /* Legacy define */
@@ -1226,7 +1227,7 @@ typedef struct
 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104)
 /*!< AHB1 peripherals */
 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
@@ -3125,6 +3126,7 @@ typedef struct
 /*******************  Bit definition for CRC_POL register  ********************/
 #define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF)     /*!< Coefficients of the polynomial */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                      Digital to Analog Converter                           */
@@ -3216,6 +3218,7 @@ typedef struct
 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                                 Debug MCU                                  */
@@ -3291,7 +3294,7 @@ typedef struct
 #define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
 #define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
 #define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000)
 #define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
 #define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
 #define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
@@ -3841,8 +3844,6 @@ typedef struct
 #define FLASH_OPTCR1_BOOT_ADD0              ((uint32_t)0x0000FFFF)
 #define FLASH_OPTCR1_BOOT_ADD1              ((uint32_t)0xFFFF0000)
 
-
-
 /******************************************************************************/
 /*                                                                            */
 /*                          Flexible Memory Controller                        */
@@ -4877,6 +4878,7 @@ typedef struct
 #define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
 #define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                      Inter-integrated Circuit Interface (I2C)              */
@@ -4891,7 +4893,7 @@ typedef struct
 #define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable     */
 #define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable  */
 #define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
+#define  I2C_CR1_DNF                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
 #define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF             */
 #define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset                      */
 #define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable    */
@@ -4905,6 +4907,9 @@ typedef struct
 #define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable                  */
 #define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable                          */
 
+/* Legacy define */
+#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
+
 /******************  Bit definition for I2C_CR2 register  ********************/
 #define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode)                             */
 #define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode)                        */
@@ -5163,7 +5168,6 @@ typedef struct
 #define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value    */
 #define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                             Power Control                                  */
@@ -5453,6 +5457,7 @@ typedef struct
 #define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
 #define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
 
+
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
@@ -6496,7 +6501,7 @@ typedef struct
 #define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
 #define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000)        /*!< Complement Bit             */
 
 #define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
 #define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
@@ -6907,13 +6912,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_BOOT          ((uint32_t)0x00000001) /*!< Boot information after Reset */
+#define SYSCFG_MEMRMP_MEM_BOOT         ((uint32_t)0x00000001) /*!< Boot information after Reset */
+
 
 #define SYSCFG_MEMRMP_SWP_FMC          ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
 #define SYSCFG_MEMRMP_SWP_FMC_0        ((uint32_t)0x00000400) 
 #define SYSCFG_MEMRMP_SWP_FMC_1        ((uint32_t)0x00000800) 
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
+
 #define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
 #define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
 #define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
@@ -7540,6 +7547,7 @@ typedef struct
 /*******************  Bit definition for TIM_CCR6 register  *******************/
 #define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 6 Value */
 
+
 /******************************************************************************/
 /*                                                                            */
 /*                         Low Power Timer (LPTIM)                            */
@@ -7705,6 +7713,7 @@ typedef struct
 #define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
 #define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
 
+
 /******************  Bit definition for USART_BRR register  *******************/
 #define  USART_BRR_DIV_FRACTION              ((uint32_t)0x000F)                /*!< Fraction of USARTDIV */
 #define  USART_BRR_DIV_MANTISSA              ((uint32_t)0xFFF0)                /*!< Mantissa of USARTDIV */
@@ -7775,35 +7784,57 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                            ((uint32_t)0x7F)                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                          ((uint32_t)0x01)                 /*!<Bit 0 */
+#define  WWDG_CR_T_1                          ((uint32_t)0x02)                 /*!<Bit 1 */
+#define  WWDG_CR_T_2                          ((uint32_t)0x04)                 /*!<Bit 2 */
+#define  WWDG_CR_T_3                          ((uint32_t)0x08)                 /*!<Bit 3 */
+#define  WWDG_CR_T_4                          ((uint32_t)0x10)                 /*!<Bit 4 */
+#define  WWDG_CR_T_5                          ((uint32_t)0x20)                 /*!<Bit 5 */
+#define  WWDG_CR_T_6                          ((uint32_t)0x40)                 /*!<Bit 6 */
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+/* Legacy defines */
+#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
+#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
+#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
+#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
+#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
+#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
+#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint32_t)0x80)                  /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          ((uint32_t)0x007F)                /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        ((uint32_t)0x0001)                /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        ((uint32_t)0x0002)                /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        ((uint32_t)0x0004)                /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        ((uint32_t)0x0008)                /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        ((uint32_t)0x0010)                /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        ((uint32_t)0x0020)                /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        ((uint32_t)0x0040)                /*!<Bit 6 */
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)                /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    ((uint32_t)0x0080)                /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    ((uint32_t)0x0100)                /*!<Bit 1 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)               /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        ((uint32_t)0x01)                  /*!<Early Wakeup Interrupt Flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -8476,6 +8507,7 @@ typedef struct
 #define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask               */
 #define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask                          */
 #define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                ((uint32_t)0x00000020)            /*!< Status Phase Received mask                     */
 #define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask       */
 #define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask                          */
 #define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask                             */
@@ -8943,6 +8975,7 @@ typedef struct
 #define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
 #define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
 #define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 ((uint32_t)0x00000020)            /*!< Status Phase Received For Control Write */
 #define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
 #define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
 
@@ -8989,6 +9022,7 @@ typedef struct
 /******************************* DCMI Instances *******************************/
 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
 
+
 /******************************* DMA2D Instances *******************************/
 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
 
@@ -9059,6 +9093,7 @@ typedef struct
 /****************************** LTDC Instances ********************************/
 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
 
+
 /******************************* RNG Instances ********************************/
 #define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
 
@@ -9075,7 +9110,6 @@ typedef struct
 /******************************** SDMMC Instances *******************************/
 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
 
-
 /****************************** SPDIFRX Instances *********************************/
 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
                                      
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
index 5ec8dd9f13..1602f517b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
index 313fa4355e..f290a155c9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
@@ -2,15 +2,15 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.4
+  * @date    09-December-2015
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f7xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
index 9a9ffb49e3..f2fc22dbfb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -39,7 +39,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -108,6 +108,14 @@ HAL_StatusTypeDef HAL_Init(void);
   */
 
 /************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+     on STMicroelectronics EVAL/Discovery boards as data memory  */
+/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
+     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
+     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
+/* #define DATA_IN_ExtSRAM */ 
+/* #define DATA_IN_ExtSDRAM */
+
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
@@ -153,6 +161,10 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
   * @{
   */
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 #endif
@@ -199,9 +211,13 @@ void SystemInit(void)
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
 
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
@@ -307,6 +323,374 @@ void SystemCoreClockUpdate(void)
   SystemCoreClock >>= tmp;
 }
 
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f7xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0;
+#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;  
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;  
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xFF800FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC00000CC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80220AAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80320FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40110555;
+
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;   
+
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
+  
+#elif defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x50150005;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554005;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC000000C;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80020A0A;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80020A0A;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40010505;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+  
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+  
+#elif defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  
+    /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55000555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00100555;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
+
+#endif /* DATA_IN_ExtSRAM */
+
+  (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
 /**
   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
   *               AHB/APBx prescalers and Flash settings
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
index 529cb4a24d..146e57a589 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    system_stm32f7xx.h
   * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
+  * @version V1.0.2
+  * @date    21-September-2015
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

From b3e2763784bc2936917e4bfaa293f0ecfdcd9ee0 Mon Sep 17 00:00:00 2001
From: neilt6 <neilt66@icloud.com>
Date: Fri, 4 Mar 2016 09:23:23 -0700
Subject: [PATCH 76/78] [LPC11U68, LPC1549] Improved PwmOut Documentation

Improved commenting in pwmout_write(), pwmout_period_us(), and
pwmout_pulsewidth_us().
---
 .../hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c     | 13 ++++++++++++-
 .../hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c      | 13 ++++++++++++-
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
index a8263f7090..942e950ade 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c
@@ -137,11 +137,14 @@ void pwmout_write(pwmout_t* obj, float value) {
     uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
     if (t_on > 0) {
         pwm->MATCHREL1 = t_on - 1;
+        
+        // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
     }
@@ -174,15 +177,20 @@ void pwmout_period_us(pwmout_t* obj, int us) {
     pwm->MATCHREL0 = period_ticks - 1;
     if (pulsewidth_ticks > 0) {
         pwm->MATCHREL1 = pulsewidth_ticks - 1;
+        
+        // Un-halt the timer and ensure the new period & pulse-width take immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH0 = pwm->MATCHREL0;
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
-        pwm->MATCH0 = pwm->MATCHREL0;
         pwm->OUTPUT = 0x00000000;
+        
+        // Ensure the new period will take immediate effect when the timer is un-halted
+        pwm->MATCH0 = pwm->MATCHREL0;
     }
 }
 
@@ -198,11 +206,14 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     if (us > 0) {
         pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
+        
+        // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
     }
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
index a8f0c06659..150823a609 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
@@ -118,11 +118,14 @@ void pwmout_write(pwmout_t* obj, float value) {
     uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
     if (t_on > 0) {
         pwm->MATCHREL1 = t_on - 1;
+        
+        // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
     }
@@ -155,15 +158,20 @@ void pwmout_period_us(pwmout_t* obj, int us) {
     pwm->MATCHREL0 = period_ticks - 1;
     if (pulsewidth_ticks > 0) {
         pwm->MATCHREL1 = pulsewidth_ticks - 1;
+        
+        // Un-halt the timer and ensure the new period & pulse-width take immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH0 = pwm->MATCHREL0;
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
-        pwm->MATCH0 = pwm->MATCHREL0;
         pwm->OUTPUT = 0x00000000;
+        
+        // Ensure the new period will take immediate effect when the timer is un-halted
+        pwm->MATCH0 = pwm->MATCHREL0;
     }
 }
 
@@ -179,11 +187,14 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
     LPC_SCT0_Type* pwm = obj->pwm;
     if (us > 0) {
         pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
+        
+        // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
         if (pwm->CTRL & (1 << 2)) {
             pwm->MATCH1 = pwm->MATCHREL1;
             pwm->CTRL &= ~(1 << 2);
         }
     } else {
+        // Halt the timer and force the output low
         pwm->CTRL |= (1 << 2) | (1 << 3);
         pwm->OUTPUT = 0x00000000;
     }

From a4c27c1f40dd80839a330e2e47099138ffcaba18 Mon Sep 17 00:00:00 2001
From: tomoyuki yamanaka <tomoyuki.yamanaka.xd@renesas.com>
Date: Mon, 7 Mar 2016 13:14:06 +0900
Subject: [PATCH 77/78] Bug fix the export function to the IAR.

We added the IAR tool chain to release build.
---
 workspace_tools/build_release.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py
index 372a27bef2..87948c2d43 100644
--- a/workspace_tools/build_release.py
+++ b/workspace_tools/build_release.py
@@ -125,7 +125,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
     ('ARM_MPS2_M7'   ,     ('ARM',)),
     ('ARM_MPS2_BEID' ,     ('ARM',)),
 
-    ('RZ_A1H'   ,     ('ARM', 'GCC_ARM')),
+    ('RZ_A1H'   ,     ('ARM', 'GCC_ARM', 'IAR')),
 
     ('EFM32ZG_STK3200',     ('GCC_ARM', 'uARM')),
     ('EFM32HG_STK3400',     ('GCC_ARM', 'uARM')),

From 58e1c63013bd8b0f4d855cb6ace43370e4e04015 Mon Sep 17 00:00:00 2001
From: bcostm <bco.stm@gmail.com>
Date: Mon, 7 Mar 2016 13:17:37 +0100
Subject: [PATCH 78/78] [NUCLEO_L073RZ] Add SW4STM32 exporter

---
 workspace_tools/export/sw4stm32.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/workspace_tools/export/sw4stm32.py b/workspace_tools/export/sw4stm32.py
index 8b91ca3e4e..c062e12577 100644
--- a/workspace_tools/export/sw4stm32.py
+++ b/workspace_tools/export/sw4stm32.py
@@ -47,6 +47,7 @@ class Sw4STM32(Exporter):
         'NUCLEO_F411RE':    {'name': 'NUCLEO-F411RE',           'mcuId': 'STM32F411RETx'},
         'NUCLEO_F446RE':    {'name': 'NUCLEO-F446RE',           'mcuId': 'STM32F446RETx'},
         'NUCLEO_L053R8':    {'name': 'NUCLEO-L053R8',           'mcuId': 'STM32L053R8Tx'},
+        'NUCLEO_L073RZ':    {'name': 'NUCLEO-L073RZ',           'mcuId': 'STM32L073RZTx'},
         'NUCLEO_L152RE':    {'name': 'NUCLEO-L152RE',           'mcuId': 'STM32L152RETx'},
         'NUCLEO_L476RG':    {'name': 'NUCLEO-L476RG',           'mcuId': 'STM32L476RGTx'},
         'NUCLEO_F031K6':    {'name': 'NUCLEO-F031K6',           'mcuId': 'STM32F031K6Tx'},