mirror of https://github.com/ARMmbed/mbed-os.git
				
				
				
			serial_api: Fix the interrupt registration for Nordic Serial Device
Using the nrfx_get_irq_number only works with the handle. Since we know the IRQ numbers for UART0, RTC2 and EGU0, use them directly.pull/10652/head
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			@ -860,8 +860,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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                             NRF_RTC_INT_COMPARE1_MASK);
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        /* Enable RTC2 IRQ. Priority is set to highest so that the UARTE ISR can't interrupt it. */
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        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void const*)RTC2_IRQn), APP_IRQ_PRIORITY_HIGHEST);
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        NRFX_IRQ_ENABLE(nrfx_get_irq_number((void const*)RTC2_IRQn));
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        NRFX_IRQ_PRIORITY_SET(RTC2_IRQn, APP_IRQ_PRIORITY_HIGHEST);
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        NRFX_IRQ_ENABLE(RTC2_IRQn);
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        /* Start RTC2. According to the datasheet the added power consumption is neglible so
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			@ -871,8 +871,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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        /* Enable interrupts for SWI. */
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        NVIC_SetVector(SWI0_EGU0_IRQn, (uint32_t) nordic_nrf5_uart_swi0);
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        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void const*)SWI0_EGU0_IRQn), APP_IRQ_PRIORITY_LOWEST);
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        NRFX_IRQ_ENABLE(nrfx_get_irq_number((void const*)SWI0_EGU0_IRQn));
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        NRFX_IRQ_PRIORITY_SET(SWI0_EGU0_IRQn, APP_IRQ_PRIORITY_LOWEST);
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        NRFX_IRQ_ENABLE(SWI0_EGU0_IRQn);
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        /* Initialize FIFO buffer for UARTE0. */
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        NRF_ATFIFO_INIT(nordic_nrf5_uart_fifo_0);
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			@ -892,8 +892,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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        nrf_uarte_int_disable(nordic_nrf5_uart_register[0], 0xFFFFFFFF);
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        NVIC_SetVector(UARTE0_UART0_IRQn, (uint32_t) nordic_nrf5_uart0_handler);
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        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void const*)UARTE0_UART0_IRQn), APP_IRQ_PRIORITY_HIGHEST);
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        NRFX_IRQ_ENABLE(nrfx_get_irq_number((void const*)UARTE0_UART0_IRQn));
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        NRFX_IRQ_PRIORITY_SET(UARTE0_UART0_IRQn, APP_IRQ_PRIORITY_HIGHEST);
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        NRFX_IRQ_ENABLE(UARTE0_UART0_IRQn);
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#if UART1_ENABLED
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        /* Initialize FIFO buffer for UARTE1. */
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