mirror of https://github.com/ARMmbed/mbed-os.git
Core(A): Updated __FPU_Enable function (VFP register count detection)
Robert Rostohar
adbridge
parent
6852fffd49
commit
80521c8369
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@ -134,6 +134,7 @@
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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@ -141,6 +142,7 @@
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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@ -153,12 +155,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
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#endif
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/**
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\brief Reverse byte order in signed short value
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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@ -351,14 +354,16 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
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/** \brief Get Mode
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\return Processor Mode
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*/
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__STATIC_INLINE uint32_t __get_mode(void) {
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__STATIC_INLINE uint32_t __get_mode(void)
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{
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return (__get_CPSR() & 0x1FU);
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}
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/** \brief Set Mode
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\param [in] mode Mode value to set
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*/
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__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
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__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
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{
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MOV r1, lr
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MSR CPSR_C, r0
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BX r1
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@ -443,15 +448,30 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
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* Include common core functions to access Coprocessor 15 registers
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*/
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); Rt = tmp; } while(0)
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = Rt; } while(0)
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
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#define __get_CP64(cp, op1, Rt, CRm) \
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do { \
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uint32_t ltmp, htmp; \
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__ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
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(Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
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} while(0)
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#define __set_CP64(cp, op1, Rt, CRm) \
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do { \
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const uint64_t tmp = (Rt); \
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const uint32_t ltmp = (uint32_t)(tmp); \
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const uint32_t htmp = (uint32_t)(tmp >> 32U); \
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__ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
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} while(0)
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#include "cmsis_cp15.h"
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/** \brief Clean and Invalidate the entire data or unified cache
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* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
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*/
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__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
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__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
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{
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ARM
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PUSH {R4-R11}
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@ -510,7 +530,8 @@ Finished
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Critical section, called from undef handler, so systick is disabled
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*/
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__STATIC_INLINE __ASM void __FPU_Enable(void) {
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__STATIC_INLINE __ASM void __FPU_Enable(void)
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{
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ARM
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//Permit access to VFP/NEON, registers by modifying CPACR
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@ -528,7 +549,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) {
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//Initialise VFP/NEON registers to 0
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MOV R2,#0
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IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
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//Initialise D16 registers to 0
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VMOV D0, R2,R2
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VMOV D1, R2,R2
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@ -546,7 +567,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) {
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VMOV D13,R2,R2
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VMOV D14,R2,R2
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VMOV D15,R2,R2
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ENDIF
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IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
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//Initialise D32 registers to 0
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VMOV D16,R2,R2
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@ -25,6 +25,8 @@
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#ifndef __CMSIS_ARMCLANG_H
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#define __CMSIS_ARMCLANG_H
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#pragma clang system_header /* treat file as system include file */
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#ifndef __ARM_COMPAT_H
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#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
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#endif
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@ -148,38 +150,29 @@
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV __builtin_bswap32
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#define __REV(value) __builtin_bswap32(value)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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{
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uint32_t result;
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__ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
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return result;
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}
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#endif
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#define __REV16(value) __ROR(__REV(value), 16)
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/**
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\brief Reverse byte order in signed short value
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
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{
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int32_t result;
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__ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
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return result;
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}
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#endif
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#define __REVSH(value) (int16_t)__builtin_bswap16(value)
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/**
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\brief Rotate Right in unsigned value (32 bit)
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@ -188,11 +181,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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op2 %= 32U;
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if (op2 == 0U)
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{
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return op1;
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}
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return (op1 >> op2) | (op1 << (32U - op2));
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}
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/**
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\brief Breakpoint
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\param [in] value is ignored by the processor.
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@ -212,7 +211,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ __builtin_clz
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#define __CLZ (uint8_t)__builtin_clz
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/**
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\brief LDR Exclusive (8 bit)
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@ -313,7 +312,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
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/** \brief Get CPSR Register
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\return CPSR Register value
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void)
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__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
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{
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uint32_t result;
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__ASM volatile("MRS %0, cpsr" : "=r" (result) );
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/** \brief Set CPSR Register
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\param [in] cpsr CPSR value to set
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*/
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__attribute__((always_inline)) __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
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__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
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{
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__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
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}
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@ -331,7 +330,7 @@ __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
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/** \brief Get Mode
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\return Processor Mode
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void)
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__STATIC_FORCEINLINE uint32_t __get_mode(void)
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{
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return (__get_CPSR() & 0x1FU);
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}
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@ -339,7 +338,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void)
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/** \brief Set Mode
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\param [in] mode Mode value to set
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*/
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__attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode)
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__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
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{
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__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
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}
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@ -347,7 +346,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode)
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/** \brief Get Stack Pointer
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\return Stack Pointer value
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP()
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__STATIC_FORCEINLINE uint32_t __get_SP()
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{
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uint32_t result;
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__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
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@ -357,7 +356,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP()
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/** \brief Set Stack Pointer
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\param [in] stack Stack Pointer value to set
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*/
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__attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack)
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__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
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{
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__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
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}
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@ -365,7 +364,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack)
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/** \brief Get USR/SYS Stack Pointer
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\return USR/SYS Stack Pointer value
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr()
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__STATIC_FORCEINLINE uint32_t __get_SP_usr()
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{
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uint32_t cpsr;
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uint32_t result;
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@ -382,7 +381,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr()
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/** \brief Set USR/SYS Stack Pointer
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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__attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack)
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__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
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{
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uint32_t cpsr;
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__ASM volatile(
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@ -397,7 +396,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfP
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/** \brief Get FPEXC
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\return Floating Point Exception Control register value
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*/
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void)
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__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
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{
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#if (__FPU_PRESENT == 1)
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uint32_t result;
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@ -411,7 +410,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void)
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/** \brief Set FPEXC
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\param [in] fpexc Floating Point Exception Control value to set
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*/
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__attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
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__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
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{
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#if (__FPU_PRESENT == 1)
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__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
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@ -424,6 +423,8 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
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#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
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#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
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#include "cmsis_cp15.h"
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@ -510,7 +511,6 @@ __STATIC_INLINE void __FPU_Enable(void)
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//Initialise VFP/NEON registers to 0
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" MOV R2,#0 \n"
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#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
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//Initialise D16 registers to 0
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" VMOV D0, R2,R2 \n"
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" VMOV D1, R2,R2 \n"
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@ -528,9 +528,8 @@ __STATIC_INLINE void __FPU_Enable(void)
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" VMOV D13,R2,R2 \n"
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" VMOV D14,R2,R2 \n"
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" VMOV D15,R2,R2 \n"
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#endif
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#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
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#if __ARM_NEON == 1
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//Initialise D32 registers to 0
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" VMOV D16,R2,R2 \n"
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" VMOV D17,R2,R2 \n"
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@ -548,8 +547,8 @@ __STATIC_INLINE void __FPU_Enable(void)
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" VMOV D29,R2,R2 \n"
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" VMOV D30,R2,R2 \n"
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" VMOV D31,R2,R2 \n"
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".endif \n"
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#endif
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//Initialise FPSCR to a known state
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" VMRS R2,FPSCR \n"
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" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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@ -157,7 +157,7 @@ __STATIC_FORCEINLINE void __DMB(void)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in integer value.
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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@ -169,12 +169,13 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
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uint32_t result;
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__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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return result;
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#endif
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}
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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@ -188,20 +189,20 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_
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#endif
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/**
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\brief Reverse byte order in signed short value
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\details Reverses the byte order in a signed short value with sign extension to integer.
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__STATIC_FORCEINLINE int32_t __REVSH(int32_t value)
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__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
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{
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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return (short)__builtin_bswap16(value);
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return (int16_t)__builtin_bswap16(value);
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#else
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int32_t result;
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int16_t result;
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__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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return result;
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#endif
|
||||
}
|
||||
|
||||
|
|
@ -214,9 +215,14 @@ __STATIC_FORCEINLINE int32_t __REVSH(int32_t value)
|
|||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U) {
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\param [in] value is ignored by the processor.
|
||||
|
|
@ -239,7 +245,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
|||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
#else
|
||||
int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
|
||||
int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
|
|
@ -250,7 +256,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
|||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
#endif
|
||||
return(result);
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -496,14 +502,16 @@ __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
|
|||
/** \brief Get Mode
|
||||
\return Processor Mode
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_mode(void) {
|
||||
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
||||
{
|
||||
return (__get_CPSR() & 0x1FU);
|
||||
}
|
||||
|
||||
/** \brief Set Mode
|
||||
\param [in] mode Mode value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_mode(uint32_t mode) {
|
||||
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
||||
{
|
||||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
|
|
@ -585,6 +593,8 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
|||
|
||||
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
|
|
@ -621,8 +631,10 @@ __STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
|
|||
log2_linesize = (ccsidr & 0x00000007) + 2 + 2;
|
||||
log2_num_ways = log2_up(num_ways);
|
||||
shift_way = 32 - log2_num_ways;
|
||||
for(int way = num_ways-1; way >= 0; way--) {
|
||||
for(int set = num_sets-1; set >= 0; set--) {
|
||||
for(int way = num_ways-1; way >= 0; way--)
|
||||
{
|
||||
for(int set = num_sets-1; set >= 0; set--)
|
||||
{
|
||||
Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);
|
||||
switch (maint)
|
||||
{
|
||||
|
|
@ -648,7 +660,8 @@ __STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
|
|||
|
||||
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
|
||||
*/
|
||||
__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
|
||||
__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
|
||||
{
|
||||
register volatile uint32_t clidr;
|
||||
uint32_t cache_type;
|
||||
clidr = __get_CLIDR();
|
||||
|
|
@ -667,7 +680,8 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
|
|||
|
||||
Critical section, called from undef handler, so systick is disabled
|
||||
*/
|
||||
__STATIC_INLINE void __FPU_Enable(void) {
|
||||
__STATIC_INLINE void __FPU_Enable(void)
|
||||
{
|
||||
__ASM volatile(
|
||||
//Permit access to VFP/NEON, registers by modifying CPACR
|
||||
" MRC p15,0,R1,c1,c0,2 \n"
|
||||
|
|
@ -685,7 +699,6 @@ __STATIC_INLINE void __FPU_Enable(void) {
|
|||
//Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
|
||||
//Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
|
|
@ -703,9 +716,8 @@ __STATIC_INLINE void __FPU_Enable(void) {
|
|||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
#endif
|
||||
|
||||
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
|
||||
#if __ARM_NEON == 1
|
||||
//Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
|
|
@ -724,6 +736,7 @@ __STATIC_INLINE void __FPU_Enable(void) {
|
|||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
#endif
|
||||
|
||||
//Initialise FPSCR to a known state
|
||||
" VMRS R2,FPSCR \n"
|
||||
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
|
|
|
|||
|
|
@ -123,7 +123,8 @@
|
|||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr) {
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
|
|
@ -134,7 +135,8 @@
|
|||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
|
|
@ -144,7 +146,8 @@
|
|||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr) {
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
|
|
@ -154,7 +157,8 @@
|
|||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
|
|
@ -238,19 +242,22 @@
|
|||
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
|
||||
|
||||
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
|
||||
(RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
|
||||
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
|
||||
|
||||
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
|
||||
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, RT))
|
||||
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
|
||||
|
||||
#define __get_CP64(cp, op1, RT, CRm) \
|
||||
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRm))
|
||||
|
||||
#define __set_CP64(cp, op1, RT, CRm) \
|
||||
(__arm_wsr("p" # cp ":" # op1 ":c" # CRm, (RT)))
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
__IAR_FT uint8_t __CLZ(uint32_t val) {
|
||||
return __iar_builtin_CLZ(val);
|
||||
}
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
|
|
@ -265,8 +272,9 @@
|
|||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int32_t __REVSH(int32_t val) {
|
||||
return __iar_builtin_REVSH((int16_t)val);
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
|
|
@ -354,6 +362,10 @@
|
|||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if !__FPU_PRESENT
|
||||
|
|
@ -376,23 +388,27 @@
|
|||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) {
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) {
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value) {
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) {
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
|
|
@ -419,6 +435,10 @@
|
|||
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
|
||||
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
|
|
@ -533,7 +553,6 @@ void __FPU_Enable(void)
|
|||
//Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
|
||||
//Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
|
|
@ -551,9 +570,8 @@ void __FPU_Enable(void)
|
|||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
#endif
|
||||
|
||||
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
|
||||
#ifdef __ARM_ADVANCED_SIMD__
|
||||
//Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
|
|
@ -571,8 +589,8 @@ void __FPU_Enable(void)
|
|||
" VMOV D29,R2,R2 \n"
|
||||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
".endif \n"
|
||||
#endif
|
||||
|
||||
//Initialise FPSCR to a known state
|
||||
" VMRS R2,FPSCR \n"
|
||||
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
|
|
|
|||
Loading…
Reference in New Issue