mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F091RC] Move files in STM32F0 folder
bcostm
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a6d6f5c645
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;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f091xc.s
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;* Author : MCD Application Team
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;* Version : V2.1.0
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;* Date : 03-Oct-2014
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;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM0 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20008000 ; Top of RAM (32KB)
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit EQU (__initial_sp - Stack_Size)
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
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DCD RTC_IRQHandler ; RTC through EXTI Line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_CRS_IRQHandler ; RCC and CRS
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DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
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DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
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DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
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DCD TSC_IRQHandler ; TS
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DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
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DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
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DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
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DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
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DCD TIM7_IRQHandler ; TIM7
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DCD TIM14_IRQHandler ; TIM14
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DCD TIM15_IRQHandler ; TIM15
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DCD TIM16_IRQHandler ; TIM16
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DCD TIM17_IRQHandler ; TIM17
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DCD I2C1_IRQHandler ; I2C1
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DCD I2C2_IRQHandler ; I2C2
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
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DCD CEC_CAN_IRQHandler ; CEC and CAN
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler routine
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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IMPORT SystemInit
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_VDDIO2_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_CRS_IRQHandler [WEAK]
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EXPORT EXTI0_1_IRQHandler [WEAK]
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EXPORT EXTI2_3_IRQHandler [WEAK]
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EXPORT EXTI4_15_IRQHandler [WEAK]
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EXPORT TSC_IRQHandler [WEAK]
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EXPORT DMA1_Ch1_IRQHandler [WEAK]
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EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
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EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
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EXPORT ADC1_COMP_IRQHandler [WEAK]
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EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM6_DAC_IRQHandler [WEAK]
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EXPORT TIM7_IRQHandler [WEAK]
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EXPORT TIM14_IRQHandler [WEAK]
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EXPORT TIM15_IRQHandler [WEAK]
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EXPORT TIM16_IRQHandler [WEAK]
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EXPORT TIM17_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_8_IRQHandler [WEAK]
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EXPORT CEC_CAN_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_VDDIO2_IRQHandler
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RTC_IRQHandler
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FLASH_IRQHandler
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RCC_CRS_IRQHandler
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EXTI0_1_IRQHandler
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EXTI2_3_IRQHandler
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EXTI4_15_IRQHandler
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TSC_IRQHandler
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DMA1_Ch1_IRQHandler
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DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
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ADC1_COMP_IRQHandler
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TIM1_BRK_UP_TRG_COM_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM6_DAC_IRQHandler
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TIM7_IRQHandler
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TIM14_IRQHandler
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TIM15_IRQHandler
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TIM16_IRQHandler
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TIM17_IRQHandler
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I2C1_IRQHandler
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I2C2_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_8_IRQHandler
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CEC_CAN_IRQHandler
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B .
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ENDP
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ALIGN
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END
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@ -0,0 +1,45 @@
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; Scatter-Loading Description File
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2014, STMicroelectronics
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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; 3. Neither the name of STMicroelectronics nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; STM32F091RC: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
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LR_IROM1 0x08000000 0x40000 { ; load region size_region
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ER_IROM1 0x08000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
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RW_IRAM1 (0x20000000+0xC0) (0x8000-0xC0) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,56 @@
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/* mbed Microcontroller Library - stackheap
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*******************************************************************************
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* Copyright (c) 2014, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,217 @@
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;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f091xc.s
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;* Author : MCD Application Team
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;* Version : V2.1.0
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;* Date : 03-Oct-2014
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;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM0 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM (32KB)
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||||
|
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||||
|
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||||
|
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||||
|
DCD TSC_IRQHandler ; TS
|
||||||
|
DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
|
||||||
|
DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
|
||||||
|
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||||
|
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD TIM14_IRQHandler ; TIM14
|
||||||
|
DCD TIM15_IRQHandler ; TIM15
|
||||||
|
DCD TIM16_IRQHandler ; TIM16
|
||||||
|
DCD TIM17_IRQHandler ; TIM17
|
||||||
|
DCD I2C1_IRQHandler ; I2C1
|
||||||
|
DCD I2C2_IRQHandler ; I2C2
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
|
||||||
|
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler routine
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_15_IRQHandler [WEAK]
|
||||||
|
EXPORT TSC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Ch1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_COMP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_8_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_CAN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_VDDIO2_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_CRS_IRQHandler
|
||||||
|
EXTI0_1_IRQHandler
|
||||||
|
EXTI2_3_IRQHandler
|
||||||
|
EXTI4_15_IRQHandler
|
||||||
|
TSC_IRQHandler
|
||||||
|
DMA1_Ch1_IRQHandler
|
||||||
|
DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
|
||||||
|
DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
|
||||||
|
ADC1_COMP_IRQHandler
|
||||||
|
TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
TIM14_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
I2C1_IRQHandler
|
||||||
|
I2C2_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_8_IRQHandler
|
||||||
|
CEC_CAN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
; Scatter-Loading Description File
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
; Copyright (c) 2014, STMicroelectronics
|
||||||
|
; All rights reserved.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software
|
||||||
|
; without specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
|
||||||
|
; STM32F091RC: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
|
||||||
|
RW_IRAM1 (0x20000000+0xC0) (0x8000-0xC0) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* A generic CMSIS include header
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_H
|
||||||
|
#define MBED_CMSIS_H
|
||||||
|
|
||||||
|
#include "stm32f0xx.h"
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||||
|
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
||||||
|
|
||||||
|
static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
|
||||||
|
|
||||||
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||||
|
int i;
|
||||||
|
// Space for dynamic vectors, initialised to allocate in R/W
|
||||||
|
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
|
|
||||||
|
// Copy and switch to dynamic vectors if first time called
|
||||||
|
if (vtor_remap == 0) {
|
||||||
|
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
|
||||||
|
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
||||||
|
vectors[i] = old_vectors[i];
|
||||||
|
}
|
||||||
|
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
|
||||||
|
vtor_remap = 1; // The vectors remap is done
|
||||||
|
}
|
||||||
|
|
||||||
|
// Set the vector
|
||||||
|
vectors[IRQn + 16] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||||
|
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
|
// Return the vector
|
||||||
|
return vectors[IRQn + 16];
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
|
// STM32F091RC
|
||||||
|
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||||
|
// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
|
||||||
|
// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
|
||||||
|
#define NVIC_NUM_VECTORS 48
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||||
|
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,228 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f0xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 03-Oct-2014
|
||||||
|
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
|
||||||
|
*
|
||||||
|
* The file is the unique include file that the application programmer
|
||||||
|
* is using in the C source code, usually in main.c. This file contains:
|
||||||
|
* - Configuration section that allows to select:
|
||||||
|
* - The STM32F0xx device used in the target application
|
||||||
|
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||||
|
* code will be based on direct access to peripheral’s registers
|
||||||
|
* rather than drivers API), this option is controlled by
|
||||||
|
* "#define USE_HAL_DRIVER"
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f0xx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __STM32F0xx_H
|
||||||
|
#define __STM32F0xx_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/** @addtogroup Library_configuration_section
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Uncomment the line below according to the target STM32 device used in your
|
||||||
|
application
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
|
||||||
|
!defined (STM32F031x6) && !defined (STM32F038xx) && \
|
||||||
|
!defined (STM32F042x6) && !defined (STM32F048xx) && \
|
||||||
|
!defined (STM32F051x8) && !defined (STM32F058xx) && \
|
||||||
|
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
|
||||||
|
!defined (STM32F091xC) && !defined (STM32F098xx)
|
||||||
|
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||||
|
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||||
|
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||||
|
/* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
|
||||||
|
/* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||||
|
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
|
||||||
|
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
|
||||||
|
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||||
|
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||||
|
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||||
|
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
|
||||||
|
#define STM32F091xC /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||||
|
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
|
*/
|
||||||
|
#if !defined (USE_HAL_DRIVER)
|
||||||
|
/**
|
||||||
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
|
In this case, these drivers will not be included and the application code will
|
||||||
|
be based on direct access to peripherals registers
|
||||||
|
*/
|
||||||
|
#define USE_HAL_DRIVER
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CMSIS Device version number V2.1.0
|
||||||
|
*/
|
||||||
|
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||||
|
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||||
|
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||||
|
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
|
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||||
|
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||||
|
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||||
|
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Device_Included
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32F030x6)
|
||||||
|
#include "stm32f030x6.h"
|
||||||
|
#elif defined(STM32F030x8)
|
||||||
|
#include "stm32f030x8.h"
|
||||||
|
#elif defined(STM32F031x6)
|
||||||
|
#include "stm32f031x6.h"
|
||||||
|
#elif defined(STM32F038xx)
|
||||||
|
#include "stm32f038xx.h"
|
||||||
|
#elif defined(STM32F042x6)
|
||||||
|
#include "stm32f042x6.h"
|
||||||
|
#elif defined(STM32F048xx)
|
||||||
|
#include "stm32f048xx.h"
|
||||||
|
#elif defined(STM32F051x8)
|
||||||
|
#include "stm32f051x8.h"
|
||||||
|
#elif defined(STM32F058xx)
|
||||||
|
#include "stm32f058xx.h"
|
||||||
|
#elif defined(STM32F071xB)
|
||||||
|
#include "stm32f071xb.h"
|
||||||
|
#elif defined(STM32F072xB)
|
||||||
|
#include "stm32f072xb.h"
|
||||||
|
#elif defined(STM32F078xx)
|
||||||
|
#include "stm32f078xx.h"
|
||||||
|
#elif defined(STM32F091xC)
|
||||||
|
#include "stm32f091xc.h"
|
||||||
|
#elif defined(STM32F098xx)
|
||||||
|
#include "stm32f098xx.h"
|
||||||
|
#else
|
||||||
|
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RESET = 0,
|
||||||
|
SET = !RESET
|
||||||
|
} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DISABLE = 0,
|
||||||
|
ENABLE = !DISABLE
|
||||||
|
} FunctionalState;
|
||||||
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
ERROR = 0,
|
||||||
|
SUCCESS = !ERROR
|
||||||
|
} ErrorStatus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Exported_macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||||
|
|
||||||
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||||
|
|
||||||
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||||
|
|
||||||
|
#define READ_REG(REG) ((REG))
|
||||||
|
|
||||||
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USE_HAL_DRIVER)
|
||||||
|
#include "stm32f0xx_hal.h"
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* __STM32F0xx_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,443 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32f0xx.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 03-Oct-2014
|
||||||
|
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
|
||||||
|
*
|
||||||
|
* 1. This file provides two functions and one global variable to be called from
|
||||||
|
* user application:
|
||||||
|
* - SystemInit(): This function is called at startup just after reset and
|
||||||
|
* before branch to main program. This call is made inside
|
||||||
|
* the "startup_stm32f0xx.s" file.
|
||||||
|
*
|
||||||
|
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||||
|
* by the user application to setup the SysTick
|
||||||
|
* timer or configure other parameters.
|
||||||
|
*
|
||||||
|
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||||
|
* be called whenever the core clock is changed
|
||||||
|
* during program execution.
|
||||||
|
*
|
||||||
|
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||||
|
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
|
||||||
|
* configure the system clock before to branch to main program.
|
||||||
|
*
|
||||||
|
* 3. This file configures the system clock as follows:
|
||||||
|
*=============================================================================
|
||||||
|
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
|
||||||
|
* | (external 8 MHz clock) | (internal 48 MHz)
|
||||||
|
* | 2- PLL_HSE_XTAL |
|
||||||
|
* | (external 8 MHz xtal) |
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* SYSCLK(MHz) | 48 | 48
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* AHBCLK (MHz) | 48 | 48
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* APB1CLK (MHz) | 48 | 48
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* USB capable (48 MHz precise clock) | YES | YES
|
||||||
|
*=============================================================================
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f0xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32f0xx.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
|
||||||
|
This value can be provided and adapted by the user application. */
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
|
||||||
|
This value can be provided and adapted by the user application. */
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||||
|
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||||
|
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock there is no need to
|
||||||
|
call the 2 first functions listed above, since SystemCoreClock variable is
|
||||||
|
updated automatically.
|
||||||
|
*/
|
||||||
|
uint32_t SystemCoreClock = 48000000;
|
||||||
|
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
|
/* Set HSION bit */
|
||||||
|
RCC->CR |= (uint32_t)0x00000001;
|
||||||
|
|
||||||
|
#if defined (STM32F051x8) || defined (STM32F058x8)
|
||||||
|
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
|
||||||
|
RCC->CFGR &= (uint32_t)0xF8FFB80C;
|
||||||
|
#else
|
||||||
|
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
|
||||||
|
RCC->CFGR &= (uint32_t)0x08FFB80C;
|
||||||
|
#endif /* STM32F051x8 or STM32F058x8 */
|
||||||
|
|
||||||
|
/* Reset HSEON, CSSON and PLLON bits */
|
||||||
|
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||||
|
|
||||||
|
/* Reset HSEBYP bit */
|
||||||
|
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||||
|
|
||||||
|
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
|
||||||
|
RCC->CFGR &= (uint32_t)0xFFC0FFFF;
|
||||||
|
|
||||||
|
/* Reset PREDIV[3:0] bits */
|
||||||
|
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||||
|
|
||||||
|
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
|
||||||
|
/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||||
|
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
|
||||||
|
#elif defined (STM32F091xC) || defined (STM32F098xx)
|
||||||
|
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
|
||||||
|
RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
|
||||||
|
#else
|
||||||
|
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||||
|
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Reset HSI14 bit */
|
||||||
|
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
RCC->CIR = 0x00000000;
|
||||||
|
|
||||||
|
/* Configure the Cube driver */
|
||||||
|
HAL_Init();
|
||||||
|
|
||||||
|
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||||
|
AHB/APBx prescalers and Flash settings */
|
||||||
|
SetSysClock();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||||
|
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||||
|
* be used by the user application to setup the SysTick timer or configure
|
||||||
|
* other parameters.
|
||||||
|
*
|
||||||
|
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||||
|
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||||
|
* based on this variable will be incorrect.
|
||||||
|
*
|
||||||
|
* @note - The system frequency computed by this function is not the real
|
||||||
|
* frequency in the chip. It is calculated based on the predefined
|
||||||
|
* constant and the selected clock source:
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||||
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||||
|
*
|
||||||
|
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
|
||||||
|
* 8 MHz) but the real value may vary depending on the variations
|
||||||
|
* in voltage and temperature.
|
||||||
|
*
|
||||||
|
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
|
||||||
|
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||||
|
* frequency of the crystal used. Otherwise, this function may
|
||||||
|
* have wrong result.
|
||||||
|
*
|
||||||
|
* - The result of this function could be not correct when using fractional
|
||||||
|
* value for HSE crystal.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate (void)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
|
||||||
|
|
||||||
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||||||
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||||
|
|
||||||
|
switch (tmp)
|
||||||
|
{
|
||||||
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
|
||||||
|
SystemCoreClock = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
|
||||||
|
SystemCoreClock = HSE_VALUE;
|
||||||
|
break;
|
||||||
|
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
|
||||||
|
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||||
|
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||||
|
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||||
|
pllmull = ( pllmull >> 18) + 2;
|
||||||
|
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
|
||||||
|
|
||||||
|
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
||||||
|
{
|
||||||
|
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
|
||||||
|
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
|
||||||
|
}
|
||||||
|
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
|
||||||
|
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
||||||
|
{
|
||||||
|
/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
|
||||||
|
SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
|
||||||
|
}
|
||||||
|
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
|
||||||
|
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
|
||||||
|
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
|
||||||
|
#else
|
||||||
|
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
|
||||||
|
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||||
|
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default: /* HSI used as system clock */
|
||||||
|
SystemCoreClock = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* Compute HCLK clock frequency ----------------*/
|
||||||
|
/* Get HCLK prescaler */
|
||||||
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||||
|
/* HCLK clock frequency */
|
||||||
|
SystemCoreClock >>= tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||||
|
* AHB/APBx prescalers and Flash settings
|
||||||
|
* @note This function should be called only once the RCC clock configuration
|
||||||
|
* is reset to the default reset state (done in SystemInit() function).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SetSysClock(void)
|
||||||
|
{
|
||||||
|
/* 1- Try to start with HSE and external clock */
|
||||||
|
#if USE_PLL_HSE_EXTC != 0
|
||||||
|
if (SetSysClock_PLL_HSE(1) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
/* 2- If fail try to start with HSE and external xtal */
|
||||||
|
#if USE_PLL_HSE_XTAL != 0
|
||||||
|
if (SetSysClock_PLL_HSE(0) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
/* 3- If fail start with HSI clock */
|
||||||
|
if (SetSysClock_PLL_HSI() == 0)
|
||||||
|
{
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
// [TODO] Put something here to tell the user that a problem occured...
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Output clock on MCO pin(PA8) for debugging purpose
|
||||||
|
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSE) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
|
||||||
|
// Select HSE oscillator as PLL source
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
|
||||||
|
if (bypass == 0) {
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||||
|
} else {
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
|
||||||
|
}
|
||||||
|
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||||
|
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
|
||||||
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Output clock on MCO pin(PA8) for debugging purpose
|
||||||
|
//if (bypass == 0)
|
||||||
|
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
|
||||||
|
//else
|
||||||
|
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSI) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
|
||||||
|
// Select HSI48 oscillator as PLL source
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
|
||||||
|
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
|
||||||
|
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
|
||||||
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||||
|
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Used for the different timeouts in the HAL */
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
HAL_IncTick();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,123 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32f0xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 03-Oct-2014
|
||||||
|
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f0xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion
|
||||||
|
*/
|
||||||
|
#ifndef __SYSTEM_STM32F0XX_H
|
||||||
|
#define __SYSTEM_STM32F0XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
3) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||||
|
3) by calling HAL API function HAL_RCC_ClockConfig()
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F0xx_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
extern void SetSysClock(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32F0XX_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
Loading…
Reference in New Issue