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TARGET_STM32F7 astyle

pull/7375/head
jeromecoutant 2018-06-27 14:42:56 +02:00 committed by adbridge
parent b6cbec8a30
commit 7fa433d75d
18 changed files with 403 additions and 401 deletions
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100
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h
View File

@ -47,27 +47,27 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0|ALT0,
PA_0_ALT1 = PA_0|ALT1,
PA_0_ALT0 = PA_0 | ALT0,
PA_0_ALT1 = PA_0 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT1 = PA_3|ALT1,
PA_3_ALT0 = PA_3 | ALT0,
PA_3_ALT1 = PA_3 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_5_ALT0 = PA_5|ALT0,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -76,68 +76,68 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT0 = PB_8 | ALT0,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT0 = PB_9 | ALT0,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT1 = PC_0|ALT1,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT1 = PC_2|ALT1,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT1 = PC_3|ALT1,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -332,7 +332,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -358,7 +358,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PH_3,
ETH_COL_ALT0 = PA_3,
ETH_CRS = PH_2,
@ -390,13 +390,13 @@ typedef enum {
ETH_TX_EN = PG_11,
ETH_TX_EN_ALT0 = PB_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c
View File

@ -63,7 +63,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -123,7 +123,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

100
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h
View File

@ -47,27 +47,27 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0|ALT0,
PA_0_ALT1 = PA_0|ALT1,
PA_0_ALT0 = PA_0 | ALT0,
PA_0_ALT1 = PA_0 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT1 = PA_3|ALT1,
PA_3_ALT0 = PA_3 | ALT0,
PA_3_ALT1 = PA_3 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_5_ALT0 = PA_5|ALT0,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -76,66 +76,66 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT1 = PC_0|ALT1,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT1 = PC_2|ALT1,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT1 = PC_3|ALT1,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -275,7 +275,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -299,7 +299,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PA_3,
ETH_CRS = PA_0,
ETH_CRS_DV = PA_7,
@ -326,13 +326,13 @@ typedef enum {
ETH_TX_EN = PB_11,
ETH_TX_EN_ALT0 = PG_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c
View File

@ -64,7 +64,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -124,7 +124,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

100
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h
View File

@ -47,27 +47,27 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0|ALT0,
PA_0_ALT1 = PA_0|ALT1,
PA_0_ALT0 = PA_0 | ALT0,
PA_0_ALT1 = PA_0 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT1 = PA_3|ALT1,
PA_3_ALT0 = PA_3 | ALT0,
PA_3_ALT1 = PA_3 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_5_ALT0 = PA_5|ALT0,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -76,66 +76,66 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT1 = PC_0|ALT1,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT1 = PC_2|ALT1,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT1 = PC_3|ALT1,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -275,7 +275,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -299,7 +299,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PA_3,
ETH_CRS = PA_0,
ETH_CRS_DV = PA_7,
@ -326,13 +326,13 @@ typedef enum {
ETH_TX_EN = PB_11,
ETH_TX_EN_ALT0 = PG_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c
View File

@ -63,7 +63,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -123,7 +123,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

110
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h
View File

@ -47,28 +47,28 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0|ALT0,
PA_0_ALT1 = PA_0|ALT1,
PA_0_ALT0 = PA_0 | ALT0,
PA_0_ALT1 = PA_0 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT1 = PA_3|ALT1,
PA_3_ALT0 = PA_3 | ALT0,
PA_3_ALT1 = PA_3 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT1 = PA_4|ALT1,
PA_4_ALT0 = PA_4 | ALT0,
PA_4_ALT1 = PA_4 | ALT1,
PA_5 = 0x05,
PA_5_ALT0 = PA_5|ALT0,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -77,70 +77,70 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT1 = PA_15|ALT1,
PA_15_ALT0 = PA_15 | ALT0,
PA_15_ALT1 = PA_15 | ALT1,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT1 = PB_3|ALT1,
PB_3_ALT0 = PB_3 | ALT0,
PB_3_ALT1 = PB_3 | ALT1,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT0 = PB_6 | ALT0,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT0 = PB_7 | ALT0,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT1 = PC_0|ALT1,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT1 = PC_2|ALT1,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT1 = PC_3|ALT1,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -280,7 +280,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -304,7 +304,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PA_3,
ETH_CRS = PA_0,
ETH_CRS_DV = PA_7,
@ -331,13 +331,13 @@ typedef enum {
ETH_TX_EN = PB_11,
ETH_TX_EN_ALT0 = PG_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c
View File

@ -64,7 +64,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -124,7 +124,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

114
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h
View File

@ -47,28 +47,28 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = PA_0|ALT0,
PA_0_ALT1 = PA_0|ALT1,
PA_0_ALT0 = PA_0 | ALT0,
PA_0_ALT1 = PA_0 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT1 = PA_3|ALT1,
PA_3_ALT0 = PA_3 | ALT0,
PA_3_ALT1 = PA_3 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT1 = PA_4|ALT1,
PA_4_ALT0 = PA_4 | ALT0,
PA_4_ALT1 = PA_4 | ALT1,
PA_5 = 0x05,
PA_5_ALT0 = PA_5|ALT0,
PA_5_ALT0 = PA_5 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -77,74 +77,74 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT1 = PA_15|ALT1,
PA_15_ALT0 = PA_15 | ALT0,
PA_15_ALT1 = PA_15 | ALT1,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT1 = PB_3|ALT1,
PB_3_ALT0 = PB_3 | ALT0,
PB_3_ALT1 = PB_3 | ALT1,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT0 = PB_6 | ALT0,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT0 = PB_7 | ALT0,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT1 = PC_0|ALT1,
PC_0_ALT0 = PC_0 | ALT0,
PC_0_ALT1 = PC_0 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT1 = PC_2|ALT1,
PC_2_ALT0 = PC_2 | ALT0,
PC_2_ALT1 = PC_2 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT1 = PC_3|ALT1,
PC_3_ALT0 = PC_3 | ALT0,
PC_3_ALT1 = PC_3 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -339,7 +339,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -365,7 +365,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PH_3,
ETH_COL_ALT0 = PA_3,
ETH_CRS = PH_2,
@ -397,13 +397,13 @@ typedef enum {
ETH_TX_EN = PG_11,
ETH_TX_EN_ALT0 = PB_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

6
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c
View File

@ -63,7 +63,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -123,7 +123,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}
@ -180,7 +180,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
RCC_PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
RCC_PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
if(HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}

8
targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "stm32f7xx_hal.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -73,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) {
obj->handle.Instance = DAC;
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
}

2
targets/TARGET_STM/TARGET_STM32F7/common_objects.h
View File

@ -80,7 +80,7 @@ struct serial_s {
PinName pin_rts;
PinName pin_cts;
#endif
};
};
struct i2c_s {
/* The 1st 2 members I2CName i2c

19
targets/TARGET_STM/TARGET_STM32F7/flash_api.c
View File

@ -49,14 +49,12 @@ int32_t flash_init(flash_t *obj)
/* Allow Access to option bytes sector */
HAL_FLASH_OB_Lock();
#if MBED_CONF_TARGET_FLASH_DUAL_BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be enabled (box unchecked)\n");
return -1;
}
#else // SINGLE BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be disabled (box checked)\n");
return -1;
}
@ -128,7 +126,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
EraseInitStruct.Sector = SectorId;
EraseInitStruct.NbSectors = 1;
if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) {
status = -1;
}
@ -219,8 +217,7 @@ static uint32_t GetSector(uint32_t address)
sector += 12 + (tmp >> 14);
} else if (address < ADDR_FLASH_SECTOR_17) { // Sector 16
sector += FLASH_SECTOR_16;
}
else { // Sectors 17 to 23
} else { // Sectors 17 to 23
tmp = address - ADDR_FLASH_SECTOR_12;
sector += 16 + (tmp >> 17);
}
@ -245,9 +242,9 @@ static uint32_t GetSectorSize(uint32_t Sector)
{
uint32_t sectorsize = 0x00;
#if (MBED_CONF_TARGET_FLASH_DUAL_BANK) && defined(FLASH_OPTCR_nDBANK)
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) ||\
(Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3) ||\
(Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || \
(Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3) || \
(Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \
(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
sectorsize = 16 * 1024;
} else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
@ -256,7 +253,7 @@ static uint32_t GetSectorSize(uint32_t Sector)
sectorsize = 128 * 1024;
}
#else // SINGLE BANK
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) ||\
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || \
(Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3)) {
sectorsize = 32 * 1024;
} else if (Sector == FLASH_SECTOR_4) {

7
targets/TARGET_STM/TARGET_STM32F7/pin_device.h
View File

@ -127,14 +127,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

28
targets/TARGET_STM/TARGET_STM32F7/serial_device.c
View File

@ -50,7 +50,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
@ -413,11 +413,11 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
@ -439,7 +439,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
@ -467,7 +467,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
@ -489,7 +489,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -524,13 +524,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
}
@ -557,14 +559,14 @@ int serial_irq_handler_asynch(serial_t *obj)
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
@ -643,7 +645,7 @@ void serial_tx_abort_asynch(serial_t *obj)
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -676,7 +678,7 @@ void serial_rx_abort_asynch(serial_t *obj)
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -706,7 +708,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}

7
targets/TARGET_STM/TARGET_STM32F7/spi_api.c
View File

@ -39,16 +39,17 @@
#include "mbed_error.h"
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;