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TARGET_STM32F7 astyle

pull/7375/head
jeromecoutant 2018-06-27 14:42:56 +02:00 committed by adbridge
parent b6cbec8a30
commit 7fa433d75d
18 changed files with 403 additions and 401 deletions
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6
targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "stm32f7xx_hal.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
}

9
targets/TARGET_STM/TARGET_STM32F7/flash_api.c
View File

@ -49,14 +49,12 @@ int32_t flash_init(flash_t *obj)
/* Allow Access to option bytes sector */
HAL_FLASH_OB_Lock();
#if MBED_CONF_TARGET_FLASH_DUAL_BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be enabled (box unchecked)\n");
return -1;
}
#else // SINGLE BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be disabled (box checked)\n");
return -1;
}
@ -219,8 +217,7 @@ static uint32_t GetSector(uint32_t address)
sector += 12 + (tmp >> 14);
} else if (address < ADDR_FLASH_SECTOR_17) { // Sector 16
sector += FLASH_SECTOR_16;
}
else { // Sectors 17 to 23
} else { // Sectors 17 to 23
tmp = address - ADDR_FLASH_SECTOR_12;
sector += 16 + (tmp >> 17);
}

5
targets/TARGET_STM/TARGET_STM32F7/pin_device.h
View File

@ -131,10 +131,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F7/serial_device.c
View File

@ -524,13 +524,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
}

3
targets/TARGET_STM/TARGET_STM32F7/spi_api.c
View File

@ -48,7 +48,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;