From 7de6aba0ee1758d7cc130fb02d58db8f8362e579 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <0xc0170@gmail.com>
Date: Tue, 5 Dec 2017 11:38:47 +0000
Subject: [PATCH] QSPI STM32: add QSPI_x support to pinnames

---
 .../TARGET_DISCO_F469NI/PeripheralNames.h            |  4 ++++
 .../TARGET_DISCO_F469NI/PeripheralPins.c             | 12 ++++++------
 targets/TARGET_STM/qspi_api.c                        | 12 +++++++++++-
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h
index 210319584f..49467559f7 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h
@@ -92,6 +92,10 @@ typedef enum {
     CAN_2 = (int)CAN2_BASE
 } CANName;
 
+typedef enum {
+    QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c
index 941872a16f..ef1fe29fc1 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c
@@ -347,21 +347,21 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
 
 
 const PinMap PinMap_QSPI_DATA[] = {
-    {PF_6,  0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
-    {PF_7,  0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
-    {PF_8, 0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
-    {PF_9,  0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
+    {PF_6,  QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
+    {PF_7,  QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
+    {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
+    {PF_9,  QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
 
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_QSPI_SCLK[] = {
-    {PF_10,  0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
+    {PF_10,  QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_QSPI_SSEL[] = {
-    {PB_6,  0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
+    {PB_6,  QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
     {NC,    NC,    0}
 };
 
diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c
index af82283f73..76f1221824 100644
--- a/targets/TARGET_STM/qspi_api.c
+++ b/targets/TARGET_STM/qspi_api.c
@@ -137,7 +137,17 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN
 
     obj->handle.Init.ClockMode = mode == 0 ? QSPI_CLOCK_MODE_0 : QSPI_CLOCK_MODE_3;
 
-    obj->handle.Instance = QUADSPI;
+    QSPIName qspi_data_first = (SPIName)pinmap_merge(io0, io1);
+    QSPIName qspi_data_second = (SPIName)pinmap_merge(io1, io2);
+    QSPIName qspi_data_third = (SPIName)pinmap_merge(io2, io3);
+
+    if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
+        qspi_data_first != qspi_data_third) {
+        return QSPI_STATUS_INVALID_PARAMETER;
+    }
+
+    // tested all combinations, take first
+    obj->handle.Instance = (QUADSPI_TypeDef *)qspi_data_first;
 
     // TODO pinmap here for pins (enable clock)
     pinmap_pinout(io0, PinMap_QSPI_DATA);