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K64F SPI driver: Add the delay between CS assertion and first sclk edge 

FPGA test shield requires at lease half slck period delay between CS assertion and first sclk edge.
pull/10989/head
Przemyslaw Stekiel 2019-07-08 13:00:03 +02:00
parent 17d5e6d00a
commit 7d7c1416af
1 changed files with 1 additions and 1 deletions
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2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c
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@ -109,7 +109,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance]));
}