mirror of https://github.com/ARMmbed/mbed-os.git
[LPC1347] Added support for the ARM toolchain.
Bogdan Marinescu
parent
4bbd13b957
commit
7d5e9dac70
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@ -0,0 +1,19 @@
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LR_IROM1 0x00000000 0x10000 { ; load region size_region
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ER_IROM1 0x00000000 0x10000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20000000 0x800 { ; RW data
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.ANY (AHBSRAM0)
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}
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RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (AHBSRAM1)
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}
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}
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@ -0,0 +1,231 @@
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;/*****************************************************************************
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; * @file: startup_LPC13xx.s
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC13xx Device Series
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; * @version: V1.02, modified for mbed
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; * @date: 27. July 2009, modified 3rd Aug 2009
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC1347
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PIN_INT0_Handler ; All GPIO pin can be routed to PIN_INTx
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DCD PIN_INT1_Handler
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DCD PIN_INT2_Handler
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DCD PIN_INT3_Handler
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DCD PIN_INT4_Handler
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DCD PIN_INT5_Handler
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DCD PIN_INT6_Handler
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DCD PIN_INT7_Handler
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DCD GINT0_Handler
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DCD GINT1_Handler ; PIO0 (0:7)
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DCD 0
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DCD 0
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DCD OSTIMER_Handler
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DCD 0
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DCD SSP1_Handler ; SSP1
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DCD I2C_Handler ; I2C
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DCD CT16B0_Handler ; 16-bit Timer0
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DCD CT16B1_Handler ; 16-bit Timer1
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DCD CT32B0_Handler ; 32-bit Timer0
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DCD CT32B1_Handler ; 32-bit Timer1
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DCD SSP0_Handler ; SSP0
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DCD USART_Handler ; USART
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DCD USB_Handler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_Handler ; A/D Converter
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DCD WDT_Handler ; Watchdog timer
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DCD BOD_Handler ; Brown Out Detect
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DCD FMC_Handler ; IP2111 Flash Memory Controller
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DCD OSCFAIL_Handler ; OSC FAIL
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DCD PVTCIRCUIT_Handler ; PVT CIRCUIT
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DCD USBWakeup_Handler ; USB wake up
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DCD 0
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PIN_INT0_Handler [WEAK]
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EXPORT PIN_INT1_Handler [WEAK]
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EXPORT PIN_INT2_Handler [WEAK]
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EXPORT PIN_INT3_Handler [WEAK]
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EXPORT PIN_INT4_Handler [WEAK]
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EXPORT PIN_INT5_Handler [WEAK]
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EXPORT PIN_INT6_Handler [WEAK]
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EXPORT PIN_INT7_Handler [WEAK]
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EXPORT GINT0_Handler [WEAK]
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EXPORT GINT1_Handler [WEAK]
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EXPORT OSTIMER_Handler [WEAK]
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EXPORT SSP1_Handler [WEAK]
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EXPORT I2C_Handler [WEAK]
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EXPORT CT16B0_Handler [WEAK]
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EXPORT CT16B1_Handler [WEAK]
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EXPORT CT32B0_Handler [WEAK]
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EXPORT CT32B1_Handler [WEAK]
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EXPORT SSP0_Handler [WEAK]
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EXPORT USART_Handler [WEAK]
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EXPORT USB_Handler [WEAK]
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EXPORT USB_FIQHandler [WEAK]
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EXPORT ADC_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT BOD_Handler [WEAK]
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EXPORT FMC_Handler [WEAK]
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EXPORT OSCFAIL_Handler [WEAK]
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EXPORT PVTCIRCUIT_Handler [WEAK]
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EXPORT USBWakeup_Handler [WEAK]
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PIN_INT0_Handler
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PIN_INT1_Handler
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PIN_INT2_Handler
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PIN_INT3_Handler
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PIN_INT4_Handler
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PIN_INT5_Handler
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PIN_INT6_Handler
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PIN_INT7_Handler
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GINT0_Handler
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GINT1_Handler
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OSTIMER_Handler
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SSP1_Handler
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I2C_Handler
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CT16B0_Handler
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CT16B1_Handler
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CT32B0_Handler
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CT32B1_Handler
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SSP0_Handler
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USART_Handler
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USB_Handler
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USB_FIQHandler
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ADC_Handler
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WDT_Handler
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BOD_Handler
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FMC_Handler
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OSCFAIL_Handler
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PVTCIRCUIT_Handler
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USBWakeup_Handler
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B .
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ENDP
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ALIGN
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END
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@ -0,0 +1,31 @@
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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,19 @@
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LR_IROM1 0x00000000 0x10000 { ; load region size_region
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ER_IROM1 0x00000000 0x10000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20000000 0x800 { ; RW data
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.ANY (AHBSRAM0)
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}
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RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (AHBSRAM1)
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}
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}
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@ -0,0 +1,215 @@
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;/*****************************************************************************
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; * @file: startup_LPC13xx.s
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC13xx Device Series
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; * @version: V1.02, modified for mbed
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; * @date: 27. July 2009, modified 3rd Aug 2009
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC1347
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PIN_INT0_Handler ; All GPIO pin can be routed to PIN_INTx
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DCD PIN_INT1_Handler
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DCD PIN_INT2_Handler
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DCD PIN_INT3_Handler
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DCD PIN_INT4_Handler
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DCD PIN_INT5_Handler
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DCD PIN_INT6_Handler
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DCD PIN_INT7_Handler
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DCD GINT0_Handler
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DCD GINT1_Handler ; PIO0 (0:7)
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DCD 0
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DCD 0
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DCD OSTIMER_Handler
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DCD 0
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DCD SSP1_Handler ; SSP1
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DCD I2C_Handler ; I2C
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DCD CT16B0_Handler ; 16-bit Timer0
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DCD CT16B1_Handler ; 16-bit Timer1
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DCD CT32B0_Handler ; 32-bit Timer0
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DCD CT32B1_Handler ; 32-bit Timer1
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DCD SSP0_Handler ; SSP0
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DCD USART_Handler ; USART
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DCD USB_Handler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_Handler ; A/D Converter
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DCD WDT_Handler ; Watchdog timer
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DCD BOD_Handler ; Brown Out Detect
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DCD FMC_Handler ; IP2111 Flash Memory Controller
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DCD OSCFAIL_Handler ; OSC FAIL
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DCD PVTCIRCUIT_Handler ; PVT CIRCUIT
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DCD USBWakeup_Handler ; USB wake up
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DCD 0
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PIN_INT0_Handler [WEAK]
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EXPORT PIN_INT1_Handler [WEAK]
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EXPORT PIN_INT2_Handler [WEAK]
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EXPORT PIN_INT3_Handler [WEAK]
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EXPORT PIN_INT4_Handler [WEAK]
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EXPORT PIN_INT5_Handler [WEAK]
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EXPORT PIN_INT6_Handler [WEAK]
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EXPORT PIN_INT7_Handler [WEAK]
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EXPORT GINT0_Handler [WEAK]
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EXPORT GINT1_Handler [WEAK]
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EXPORT OSTIMER_Handler [WEAK]
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EXPORT SSP1_Handler [WEAK]
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EXPORT I2C_Handler [WEAK]
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EXPORT CT16B0_Handler [WEAK]
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EXPORT CT16B1_Handler [WEAK]
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EXPORT CT32B0_Handler [WEAK]
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EXPORT CT32B1_Handler [WEAK]
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EXPORT SSP0_Handler [WEAK]
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EXPORT USART_Handler [WEAK]
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EXPORT USB_Handler [WEAK]
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EXPORT USB_FIQHandler [WEAK]
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EXPORT ADC_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT BOD_Handler [WEAK]
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EXPORT FMC_Handler [WEAK]
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EXPORT OSCFAIL_Handler [WEAK]
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EXPORT PVTCIRCUIT_Handler [WEAK]
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EXPORT USBWakeup_Handler [WEAK]
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PIN_INT0_Handler
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PIN_INT1_Handler
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PIN_INT2_Handler
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PIN_INT3_Handler
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PIN_INT4_Handler
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PIN_INT5_Handler
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PIN_INT6_Handler
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PIN_INT7_Handler
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GINT0_Handler
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GINT1_Handler
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OSTIMER_Handler
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SSP1_Handler
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I2C_Handler
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CT16B0_Handler
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CT16B1_Handler
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CT32B0_Handler
|
||||
CT32B1_Handler
|
||||
SSP0_Handler
|
||||
USART_Handler
|
||||
USB_Handler
|
||||
USB_FIQHandler
|
||||
ADC_Handler
|
||||
WDT_Handler
|
||||
BOD_Handler
|
||||
FMC_Handler
|
||||
OSCFAIL_Handler
|
||||
PVTCIRCUIT_Handler
|
||||
USBWakeup_Handler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue