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* added files for KEIL IDE Support for SAML21 

* updated Startup files for KEIL IDE Support
pull/1410/head^2
akhilpanayam 2015-10-30 17:03:01 +05:30 committed by Parthasarathy.S
parent 1623bc6a0c
commit 7ca0d74564
9 changed files with 512 additions and 13 deletions
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19
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct Normal file
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@ -0,0 +1,19 @@
;SAML21J18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
;SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
.ANY (+RW +ZI)
}
}

193
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/startup_SAML21.s Normal file
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@ -0,0 +1,193 @@
;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
__initial_sp EQU 0x20008000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD SYSTEM_Handler ; 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ; 1 Watchdog Timer
DCD RTC_Handler ; 2 Real-Time Counter
DCD EIC_Handler ; 3 External Interrupt Controller
DCD NVMCTRL_Handler ; 4 Non-Volatile Memory Controller
DCD DMAC_Handler ; 5 Direct Memory Access Controller
DCD USB_Handler ; 6 Universal Serial Bus
DCD EVSYS_Handler ; 7 Event System Interface
DCD SERCOM0_Handler ; 8 Serial Communication Interface 0
DCD SERCOM1_Handler ; 9 Serial Communication Interface 1
DCD SERCOM2_Handler ; 10 Serial Communication Interface 2
DCD SERCOM3_Handler ; 11 Serial Communication Interface 3
DCD SERCOM4_Handler ; 12 Serial Communication Interface 4
DCD SERCOM5_Handler ; 13 Serial Communication Interface 5
DCD TCC0_Handler ; 14 Timer Counter Control 0
DCD TCC1_Handler ; 15 Timer Counter Control 1
DCD TCC2_Handler ; 16 Timer Counter Control 2
DCD TC0_Handler ; 17 Basic Timer Counter 0
DCD TC1_Handler ; 18 Basic Timer Counter 1
DCD TC2_Handler ; 19 Basic Timer Counter 2
DCD TC3_Handler ; 20 Basic Timer Counter 3
DCD TC4_Handler ; 21 Basic Timer Counter 4
DCD ADC_Handler ; 22 Analog Digital Converter
DCD AC_Handler ; 23 Analog Comparators
DCD DAC_Handler ; 24 Digital-to-Analog Converter
DCD PTC_Handler ; 25 Peripheral Touch Controller
DCD AES_Handler ; 26 Advanced Encryption Standard
DCD TRNG_Handler ; 27 True Random Generator
DCD PICOP_Handler ; 28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

41
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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@ -0,0 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

19
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/SAML21J18A.sct Normal file
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@ -0,0 +1,19 @@
;SAML21J18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
;SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
.ANY (+RW +ZI)
}
}

193
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/startup_SAML21.s Normal file
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@ -0,0 +1,193 @@
;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
__initial_sp EQU 0x20008000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD SYSTEM_Handler ; 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ; 1 Watchdog Timer
DCD RTC_Handler ; 2 Real-Time Counter
DCD EIC_Handler ; 3 External Interrupt Controller
DCD NVMCTRL_Handler ; 4 Non-Volatile Memory Controller
DCD DMAC_Handler ; 5 Direct Memory Access Controller
DCD USB_Handler ; 6 Universal Serial Bus
DCD EVSYS_Handler ; 7 Event System Interface
DCD SERCOM0_Handler ; 8 Serial Communication Interface 0
DCD SERCOM1_Handler ; 9 Serial Communication Interface 1
DCD SERCOM2_Handler ; 10 Serial Communication Interface 2
DCD SERCOM3_Handler ; 11 Serial Communication Interface 3
DCD SERCOM4_Handler ; 12 Serial Communication Interface 4
DCD SERCOM5_Handler ; 13 Serial Communication Interface 5
DCD TCC0_Handler ; 14 Timer Counter Control 0
DCD TCC1_Handler ; 15 Timer Counter Control 1
DCD TCC2_Handler ; 16 Timer Counter Control 2
DCD TC0_Handler ; 17 Basic Timer Counter 0
DCD TC1_Handler ; 18 Basic Timer Counter 1
DCD TC2_Handler ; 19 Basic Timer Counter 2
DCD TC3_Handler ; 20 Basic Timer Counter 3
DCD TC4_Handler ; 21 Basic Timer Counter 4
DCD ADC_Handler ; 22 Analog Digital Converter
DCD AC_Handler ; 23 Analog Comparators
DCD DAC_Handler ; 24 Digital-to-Analog Converter
DCD PTC_Handler ; 25 Peripheral Touch Controller
DCD AES_Handler ; 26 Advanced Encryption Standard
DCD TRNG_Handler ; 27 True Random Generator
DCD PICOP_Handler ; 28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

41
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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@ -0,0 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

9
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/saml21j18a.ld
View File

@ -5,7 +5,7 @@ SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
@ -73,13 +73,6 @@ MEMORY {
. = ALIGN(4);
_etext = .;
.dvectors (NOLOAD) :
{
_sdvectors = .;
. = . + 0xB4;
_edvectors = .;
} > ram
.relocate :
AT (_etext)
{

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_IAR/startup_saml21.c
View File

@ -130,7 +130,7 @@ void Dummy_Handler(void);
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) Reset_Handler,
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAML21/cmsis_nvic.c
View File

@ -30,8 +30,8 @@
*/
#include "cmsis_nvic.h"
//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
extern uint32_t _sdvectors;
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
//extern uint32_t _sdvectors;
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)&_sdvectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)&_sdvectors;
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}