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Merge pull request #7729 from davidsaada/david_fix_arm_linker_script_renesas_realtek 

Rename text region in ARM linker file for Renesas & Realtek boards
pull/7749/head
Cruz Monrreal 2018-08-09 15:57:29 -05:00 committed by GitHub
parent e923bbdbfb 84412d6493
commit 7bcbb78661
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 5 additions and 5 deletions
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2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct
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@ -23,7 +23,7 @@ LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{ } ; Level-1 Translation Table for MMU
}
SFLASH MBED_APP_START MBED_APP_SIZE ; load region size_region
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
{
#if (MBED_APP_START == 0x18000000)
BOOT_LOADER_BEGIN MBED_APP_START FIXED

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct
View File

@ -23,7 +23,7 @@ LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{ } ; Level-1 Translation Table for MMU
}
SFLASH MBED_APP_START MBED_APP_SIZE ; load region size_region
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
{
#if (MBED_APP_START == 0x18000000)
BOOT_LOADER_BEGIN MBED_APP_START FIXED

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct
View File

@ -16,7 +16,7 @@ LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{ } ; Level-1 Translation Table for MMU
}
SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
LR_IROM1 __ROM_BASE __ROM_SIZE ; load region size_region
{
VECTORS __VECTOR_BASE FIXED
{

4
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct
View File

@ -17,7 +17,7 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) {
*rtl8195a_init*.o(.image2.validate.rodata*)
}
ER_IRAM +0 FIXED {
LR_IROM1 +0 FIXED {
*(.ARM.exidx)
*(.init_array)
*rtl8195a_crypto*.o (+RO)
@ -55,7 +55,7 @@ LR_TCM 0x1FFF0000 0x10000 {
}
}
LR_DRAM 0x30000000 0x200000 {
LR_IROM1 0x30000000 0x200000 {
ER_DRAM +0 FIXED {
.ANY (+RO)