mirror of https://github.com/ARMmbed/mbed-os.git
[XDOT_L151] add IAR support
Mike Fiore
parent
1b8cb3ca76
commit
7b2942157a
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@ -1184,7 +1184,7 @@
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"core": "Cortex-M3",
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"default_toolchain": "ARM",
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"extra_labels": ["STM", "STM32L1", "STM32L151CC"],
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"supported_toolchains": ["ARM", "GCC_ARM"],
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"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
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"progen": {"target": "xdot-l151cc"},
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"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
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"default_lib": "std",
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@ -0,0 +1,536 @@
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;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
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;* File Name : startup_stm32l152xc.s
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;* Author : MCD Application Team
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;* Version : V2.2.0
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;* Date : 01-July-2016
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;* Description : STM32L152XC Devices vector for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == __iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Configure the system clock
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M3 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;*******************************************************************************
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_IRQHandler ; PVD through EXTI Line detect
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DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line 0
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DCD EXTI1_IRQHandler ; EXTI Line 1
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DCD EXTI2_IRQHandler ; EXTI Line 2
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DCD EXTI3_IRQHandler ; EXTI Line 3
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DCD EXTI4_IRQHandler ; EXTI Line 4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_IRQHandler ; ADC1
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DCD USB_HP_IRQHandler ; USB High Priority
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DCD USB_LP_IRQHandler ; USB Low Priority
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DCD DAC_IRQHandler ; DAC
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DCD COMP_IRQHandler ; COMP through EXTI Line
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DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
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DCD LCD_IRQHandler ; LCD
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DCD TIM9_IRQHandler ; TIM9
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DCD TIM10_IRQHandler ; TIM10
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DCD TIM11_IRQHandler ; TIM11
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
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DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
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DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
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DCD TIM6_IRQHandler ; TIM6
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DCD TIM7_IRQHandler ; TIM7
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DCD 0 ; Reserved
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
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DCD 0 ; Reserved
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DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PVD_IRQHandler
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B PVD_IRQHandler
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PUBWEAK TAMPER_STAMP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TAMPER_STAMP_IRQHandler
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B TAMPER_STAMP_IRQHandler
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PUBWEAK RTC_WKUP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RTC_WKUP_IRQHandler
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B RTC_WKUP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI0_IRQHandler
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B EXTI0_IRQHandler
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PUBWEAK EXTI1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI1_IRQHandler
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B EXTI1_IRQHandler
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PUBWEAK EXTI2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI2_IRQHandler
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B EXTI2_IRQHandler
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PUBWEAK EXTI3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI3_IRQHandler
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B EXTI3_IRQHandler
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PUBWEAK EXTI4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI4_IRQHandler
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B EXTI4_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel2_IRQHandler
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B DMA1_Channel2_IRQHandler
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PUBWEAK DMA1_Channel3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel3_IRQHandler
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B DMA1_Channel3_IRQHandler
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PUBWEAK DMA1_Channel4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel4_IRQHandler
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B DMA1_Channel4_IRQHandler
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PUBWEAK DMA1_Channel5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel5_IRQHandler
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B DMA1_Channel5_IRQHandler
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PUBWEAK DMA1_Channel6_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel6_IRQHandler
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B DMA1_Channel6_IRQHandler
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PUBWEAK DMA1_Channel7_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Channel7_IRQHandler
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B DMA1_Channel7_IRQHandler
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PUBWEAK ADC1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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ADC1_IRQHandler
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B ADC1_IRQHandler
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PUBWEAK USB_HP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USB_HP_IRQHandler
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B USB_HP_IRQHandler
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PUBWEAK USB_LP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USB_LP_IRQHandler
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B USB_LP_IRQHandler
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PUBWEAK DAC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DAC_IRQHandler
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B DAC_IRQHandler
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PUBWEAK COMP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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COMP_IRQHandler
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B COMP_IRQHandler
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PUBWEAK EXTI9_5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI9_5_IRQHandler
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B EXTI9_5_IRQHandler
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PUBWEAK LCD_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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LCD_IRQHandler
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B LCD_IRQHandler
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PUBWEAK TIM9_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM9_IRQHandler
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B TIM9_IRQHandler
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PUBWEAK TIM10_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM10_IRQHandler
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B TIM10_IRQHandler
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PUBWEAK TIM11_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM11_IRQHandler
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B TIM11_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM4_IRQHandler
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B TIM4_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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PUBWEAK I2C2_EV_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C2_EV_IRQHandler
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B I2C2_EV_IRQHandler
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PUBWEAK I2C2_ER_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C2_ER_IRQHandler
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B I2C2_ER_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK SPI2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI2_IRQHandler
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B SPI2_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK USART2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USART2_IRQHandler
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B USART2_IRQHandler
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PUBWEAK USART3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USART3_IRQHandler
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B USART3_IRQHandler
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PUBWEAK EXTI15_10_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI15_10_IRQHandler
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B EXTI15_10_IRQHandler
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PUBWEAK RTC_Alarm_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RTC_Alarm_IRQHandler
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B RTC_Alarm_IRQHandler
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PUBWEAK USB_FS_WKUP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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USB_FS_WKUP_IRQHandler
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B USB_FS_WKUP_IRQHandler
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PUBWEAK TIM6_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM6_IRQHandler
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B TIM6_IRQHandler
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PUBWEAK TIM7_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM7_IRQHandler
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B TIM7_IRQHandler
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PUBWEAK TIM5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK COMP_ACQ_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_ACQ_IRQHandler
|
||||
B COMP_ACQ_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* [ROM = 256kb = 0x40000] */
|
||||
define symbol __intvec_start__ = 0x08000000;
|
||||
define symbol __region_ROM_start__ = 0x08000000;
|
||||
define symbol __region_ROM_end__ = 0x0803FFFF;
|
||||
|
||||
/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */
|
||||
define symbol __region_RAM_start__ = 0x20000128;
|
||||
define symbol __region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = 0x800;
|
||||
define symbol __size_heap__ = 0x800;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
Loading…
Reference in New Issue