Merge pull request #13375 from RyoheiHagimoto/add_gr-mango

Add GR_MANGO as a new target

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.cpp

@@ -16,7 +16,7 @@
 #include "cmsis_os.h"
 #include "rtos/ThisThread.h"
 #include "netsocket/nsapi_types.h"
-#include "events/mbed_shared_queues.h"
+#include "mbed_shared_queues.h"
 #include "rza1_eth.h"
 #include "rza1_eth_ext.h"
 #include "rza1_emac.h"
@@ -24,17 +24,19 @@
 #define RZ_A1_ETH_IF_NAME    "en"
 
 // Weak so a module can override
-MBED_WEAK EMAC &EMAC::get_default_instance() {
+MBED_WEAK EMAC &EMAC::get_default_instance()
+{
     return RZ_A1_EMAC::get_instance();
 }
 
-RZ_A1_EMAC &RZ_A1_EMAC::get_instance() {
+RZ_A1_EMAC &RZ_A1_EMAC::get_instance()
+{
     static RZ_A1_EMAC emac;
     return emac;
 }
 
 RZ_A1_EMAC::RZ_A1_EMAC() : hwaddr(), hwaddr_set(false), power_on(false), connect_sts(false),
-     link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896)
+    link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896)
 {
 }
 
@@ -168,15 +170,18 @@ void RZ_A1_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
 }
 
 
-void RZ_A1_EMAC::_recv_callback(void) {
+void RZ_A1_EMAC::_recv_callback(void)
+{
     get_instance().recv_callback();
 }
 
-void RZ_A1_EMAC::recv_callback(void) {
+void RZ_A1_EMAC::recv_callback(void)
+{
     recvThread.flags_set(1);
 }
 
-void RZ_A1_EMAC::recv_task(void) {
+void RZ_A1_EMAC::recv_task(void)
+{
     uint16_t       recv_size;
     emac_mem_buf_t *buf;
     int            cnt;

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.c

@@ -80,13 +80,13 @@
 #define LOOP_100us              (6700)     /* Loop counter for software wait  6666=100us/((1/400MHz)*6cyc) */
 
 #define EDMAC_EESIPR_INI_RECV   (0x0205001F)    /* 0x02000000 : Detect reception suspended */
-                                                /* 0x00040000 : Detect frame reception */
+/* 0x00040000 : Detect frame reception */
-                                                /* 0x00010000 : Receive FIFO overflow */
+/* 0x00010000 : Receive FIFO overflow */
-                                                /* 0x00000010 : Residual bit frame reception */
+/* 0x00000010 : Residual bit frame reception */
-                                                /* 0x00000008 : Long frame reception */
+/* 0x00000008 : Long frame reception */
-                                                /* 0x00000004 : Short frame reception */
+/* 0x00000004 : Short frame reception */
-                                                /* 0x00000002 : PHY-LSI reception error */
+/* 0x00000002 : PHY-LSI reception error */
-                                                /* 0x00000001 : Receive frame CRC error */
+/* 0x00000001 : Receive frame CRC error */
 #define EDMAC_EESIPR_INI_EtherC (0x00400000)    /* 0x00400000 : E-MAC status register */
 
 void rza1_ethernet_address(char *);
@@ -115,16 +115,16 @@ typedef struct tag_edmac_recv_desc {
 #if defined(__ICCARM__)
 #pragma data_alignment=16
 static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
-                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                                                  (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
-                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                                                  (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
-                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]  //16 bytes aligned!
+                                                                  (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]  //16 bytes aligned!
-                                 @ ".mirrorram";
+@ ".mirrorram";
 #else
 static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
-                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                                                  (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
-                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                                                  (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
-                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
+                                                                  (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
-                                 __attribute((section("NC_BSS"),aligned(16)));  //16 bytes aligned!
+__attribute((section("NC_BSS"), aligned(16))); //16 bytes aligned!
 #endif
 static int32_t            rx_read_offset;   /* read offset */
 static int32_t            tx_wite_offset;   /* write offset */
@@ -140,10 +140,10 @@ static uint32_t           phy_id            = 0;
 static uint32_t           start_stop        = 1;  /* 0:stop  1:start */
 static uint32_t           tsu_ten_tmp       = 0;
 
-volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
+volatile struct st_ether_from_tsu_adrh0  *ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
-    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
-    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
+        ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
-    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
 
 /* function */
 static void lan_reg_reset(void);
@@ -162,7 +162,8 @@ static void set_ether_pir(uint32_t set_data);
 static void wait_100us(int32_t wait_cnt);
 
 
-int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) {
+int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg)
+{
     int32_t  i;
     uint16_t val;
 
@@ -224,7 +225,7 @@ int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) {
     }
 
     phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
-           |  (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
+             | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
 
     Interrupt_priority = p_ethcfg->int_priority;
     p_recv_cb_fnc      = p_ethcfg->recv_cb;
@@ -239,7 +240,8 @@ int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) {
     return 0;
 }
 
-void ethernetext_start_stop(int32_t mode) {
+void ethernetext_start_stop(int32_t mode)
+{
     if (mode == 1) {
         /* start */
         ETHEREDTRR0 |= EDTRR0_TR;
@@ -253,7 +255,8 @@ void ethernetext_start_stop(int32_t mode) {
     }
 }
 
-int ethernetext_chk_link_mode(void) {
+int ethernetext_chk_link_mode(void)
+{
     int32_t  link;
     uint16_t data;
 
@@ -283,13 +286,15 @@ int ethernetext_chk_link_mode(void) {
     return link;
 }
 
-void ethernetext_set_link_mode(int32_t link) {
+void ethernetext_set_link_mode(int32_t link)
+{
     lan_reg_reset();            /* Resets the E-MAC,E-DMAC */
     lan_desc_create();          /* Initialize of buffer memory */
     lan_reg_set(link);          /* E-DMAC, E-MAC initialization */
 }
 
-void ethernetext_add_multicast_group(const uint8_t *addr) {
+void ethernetext_add_multicast_group(const uint8_t *addr)
+{
     uint32_t cnt;
     uint32_t tmp_data_h;
     uint32_t tmp_data_l;
@@ -320,7 +325,8 @@ void ethernetext_add_multicast_group(const uint8_t *addr) {
     }
 }
 
-void ethernetext_remove_multicast_group(const uint8_t *addr) {
+void ethernetext_remove_multicast_group(const uint8_t *addr)
+{
     uint32_t cnt;
     uint32_t tmp_data_h;
     uint32_t tmp_data_l;
@@ -328,9 +334,9 @@ void ethernetext_remove_multicast_group(const uint8_t *addr) {
     tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
     tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
 
-    for (cnt = 0; cnt< 32; cnt++) {
+    for (cnt = 0; cnt < 32; cnt++) {
-        if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0  == tmp_data_h) && 
+        if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0  == tmp_data_h) &&
-            (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0  == tmp_data_l)) {
+                (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0  == tmp_data_l)) {
             while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
                 ;
             }
@@ -347,7 +353,8 @@ void ethernetext_remove_multicast_group(const uint8_t *addr) {
     }
 }
 
-void ethernetext_set_all_multicast(int all) {
+void ethernetext_set_all_multicast(int all)
+{
     if (all != 0) {
         ETHERECMR0 &= ~(0x00002000);
         ETHERTSU_TEN = 0x00000000;
@@ -358,7 +365,8 @@ void ethernetext_set_all_multicast(int all) {
 }
 
 
-int rza1_ethernet_init() {
+int rza1_ethernet_init()
+{
     rza1_ethernet_cfg_t ethcfg;
 
     ethcfg.int_priority = 5;
@@ -370,17 +378,19 @@ int rza1_ethernet_init() {
     return 0;
 }
 
-void rza1_ethernet_free() {
+void rza1_ethernet_free()
+{
     ETHERARSTR |= 0x00000001;            /* ETHER software reset */
     CPGSTBCR7  |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
 }
 
-int rza1_ethernet_write(const char *data, int slen) {
+int rza1_ethernet_write(const char *data, int slen)
+{
     edmac_send_desc_t *p_send_desc;
     int32_t           copy_size;
 
     if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
-     || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
+            || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
         copy_size = 0;
     } else {
         p_send_desc = &p_eth_desc_dsend[send_top_index];   /* Current descriptor */
@@ -399,7 +409,8 @@ int rza1_ethernet_write(const char *data, int slen) {
     return copy_size;
 }
 
-int rza1_ethernet_send() {
+int rza1_ethernet_send()
+{
     edmac_send_desc_t *p_send_desc;
     int32_t           ret;
 
@@ -431,7 +442,8 @@ int rza1_ethernet_send() {
     return ret;
 }
 
-int rza1_ethernet_receive() {
+int rza1_ethernet_receive()
+{
     edmac_recv_desc_t *p_recv_desc;
     int32_t           receive_size = 0;
 
@@ -475,7 +487,8 @@ int rza1_ethernet_receive() {
     return receive_size;
 }
 
-int rza1_ethernet_read(char *data, int dlen) {
+int rza1_ethernet_read(char *data, int dlen)
+{
     edmac_recv_desc_t *p_recv_desc = p_recv_end_desc;                   /* Read top descriptor */
     int32_t           copy_size;
 
@@ -493,13 +506,15 @@ int rza1_ethernet_read(char *data, int dlen) {
     return copy_size;
 }
 
-void rza1_ethernet_address(char *mac) {
+void rza1_ethernet_address(char *mac)
+{
     if (mac != NULL) {
         mbed_mac_address(mac); /* Get MAC Address */
     }
 }
 
-int rza1_ethernet_link(void) {
+int rza1_ethernet_link(void)
+{
     int32_t  ret;
     uint16_t data;
 
@@ -513,7 +528,8 @@ int rza1_ethernet_link(void) {
     return ret;
 }
 
-void rza1_ethernet_set_link(int speed, int duplex) {
+void rza1_ethernet_set_link(int speed, int duplex)
+{
     uint16_t data;
     int32_t  i;
     int32_t  link;
@@ -538,7 +554,8 @@ void rza1_ethernet_set_link(int speed, int duplex) {
     ethernetext_set_link_mode(link);
 }
 
-void INT_Ether(void) {
+void INT_Ether(void)
+{
     uint32_t stat_edmac;
     uint32_t stat_etherc;
 
@@ -559,7 +576,8 @@ void INT_Ether(void) {
     }
 }
 
-static void lan_reg_reset(void) {
+static void lan_reg_reset(void)
+{
     volatile int32_t j = 400;    /* Wait for B dia 256 cycles  ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
 
     ETHERARSTR      |= 0x00000001;      /* ETHER software reset */
@@ -576,7 +594,8 @@ static void lan_reg_reset(void) {
     }
 }
 
-static void lan_desc_create(void) {
+static void lan_desc_create(void)
+{
     int32_t i;
     uint8_t *p_memory_top;
 
@@ -615,14 +634,15 @@ static void lan_desc_create(void) {
     p_recv_end_desc = NULL;
 }
 
-static void lan_reg_set(int32_t link) {
+static void lan_reg_set(int32_t link)
+{
     /* MAC address setting */
     ETHERMAHR0      = ((uint8_t)mac_addr[0] << 24)
-                    | ((uint8_t)mac_addr[1] << 16)
+                      | ((uint8_t)mac_addr[1] << 16)
-                    | ((uint8_t)mac_addr[2] << 8)
+                      | ((uint8_t)mac_addr[2] << 8)
-                    |  (uint8_t)mac_addr[3];
+                      | (uint8_t)mac_addr[3];
     ETHERMALR0      = ((uint8_t)mac_addr[4] << 8)
-                    |  (uint8_t)mac_addr[5];
+                      | (uint8_t)mac_addr[5];
 
     /* E-DMAC */
     ETHERTDLAR0     = (uint32_t)&p_eth_desc_dsend[0];
@@ -676,7 +696,8 @@ static void lan_reg_set(int32_t link) {
     }
 }
 
-static uint16_t phy_reg_read(uint16_t reg_addr) {
+static uint16_t phy_reg_read(uint16_t reg_addr)
+{
     uint16_t data;
 
     mii_preamble();
@@ -688,7 +709,8 @@ static uint16_t phy_reg_read(uint16_t reg_addr) {
     return data;
 }
 
-static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
+static void phy_reg_write(uint16_t reg_addr, uint16_t data)
+{
     mii_preamble();
     mii_cmd(reg_addr, PHY_WRITE);
     mii_write_1();
@@ -697,7 +719,8 @@ static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
     mii_z();
 }
 
-static void mii_preamble(void) {
+static void mii_preamble(void)
+{
     int32_t i = 32;
 
     for (i = 32; i > 0; i--) {
@@ -706,7 +729,8 @@ static void mii_preamble(void) {
     }
 }
 
-static void mii_cmd(uint16_t reg_addr, uint32_t option) {
+static void mii_cmd(uint16_t reg_addr, uint32_t option)
+{
     int32_t  i;
     uint16_t data = 0;
 
@@ -724,7 +748,8 @@ static void mii_cmd(uint16_t reg_addr, uint32_t option) {
     }
 }
 
-static void mii_reg_read(uint16_t *data) {
+static void mii_reg_read(uint16_t *data)
+{
     int32_t  i;
     uint16_t reg_data = 0;
 
@@ -740,7 +765,8 @@ static void mii_reg_read(uint16_t *data) {
     *data = reg_data;
 }
 
-static void mii_reg_write(uint16_t data) {
+static void mii_reg_write(uint16_t data)
+{
     int32_t i;
 
     /* Data are written one bit at a time */
@@ -754,28 +780,32 @@ static void mii_reg_write(uint16_t data) {
     }
 }
 
-static void mii_z(void) {
+static void mii_z(void)
+{
     set_ether_pir(PIR0_MDC_LOW);
     set_ether_pir(PIR0_MDC_HIGH);
     set_ether_pir(PIR0_MDC_HIGH);
     set_ether_pir(PIR0_MDC_LOW);
 }
 
-static void mii_write_1(void) {
+static void mii_write_1(void)
+{
     set_ether_pir(PIR0_MDO | PIR0_MMD);
     set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
     set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
     set_ether_pir(PIR0_MDO | PIR0_MMD);
 }
 
-static void mii_write_0(void) {
+static void mii_write_0(void)
+{
     set_ether_pir(PIR0_MMD);
     set_ether_pir(PIR0_MMD | PIR0_MDC);
     set_ether_pir(PIR0_MMD | PIR0_MDC);
     set_ether_pir(PIR0_MMD);
 }
 
-static void set_ether_pir(uint32_t set_data) {
+static void set_ether_pir(uint32_t set_data)
+{
     int32_t i;
 
     for (i = MDC_WAIT; i > 0; i--) {
@@ -783,7 +813,8 @@ static void set_ether_pir(uint32_t set_data) {
     }
 }
 
-static void wait_100us(int32_t wait_cnt) {
+static void wait_100us(int32_t wait_cnt)
+{
     volatile int32_t j = LOOP_100us * wait_cnt;
 
     while (--j) {

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/mbed_lib.json

@@ -0,0 +1,3 @@
+{
+    "name": "rza2-emac"
+}

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/r_ether_rza2_if.h

@@ -0,0 +1,190 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+ * File Name    : r_ether_rza2_if.h
+ * Version      : 1.00
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_RZA2_IF_H
+#define R_ETHER_RZA2_IF_H
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include <stdint.h>
+
+#include "r_ether_rza2_config.h"
+#include "src/phy/phy.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* Version Number of API. */
+#define ETHER_RZA2_VERSION_MAJOR  (1)
+#define ETHER_RZA2_VERSION_MINOR  (0)
+
+/* When using the Read functions, ETHER_NO_DATA is the return value that indicates that no received data. */
+#define ETHER_NO_DATA             (0)
+
+/* The value of flag which indicates that the interrupt of Ethernet occur. */
+#define ETHER_FLAG_OFF            (0)
+#define ETHER_FLAG_ON             (1)
+#define ETHER_FLAG_ON_LINK_ON     (3)
+#define ETHER_FLAG_ON_LINK_OFF    (2)
+
+/* Channel definition of Ethernet */
+#define ETHER_CHANNEL_0           (0)
+#define ETHER_CHANNEL_1           (1)
+
+#define ETHER_CHANNEL_MAX         (ETHER_CH0_EN + ETHER_CH1_EN)
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+/* ETHER API error codes */
+typedef enum {
+    ETHER_SUCCESS = 0,            /* Processing completed successfully */
+    ETHER_ERR_INVALID_PTR = -1,   /* Value of the pointer is NULL */
+    ETHER_ERR_INVALID_DATA = -2,  /* Value of the argument is out of range */
+    ETHER_ERR_INVALID_CHAN = -3,  /* Nonexistent channel number */
+    ETHER_ERR_INVALID_ARG = -4,   /* Invalid argument */
+    ETHER_ERR_LINK = -5,          /* Auto-negotiation is not completed, and transmission/reception is not enabled. */
+    ETHER_ERR_MPDE = -6,          /* As a Magic Packet is being detected, and transmission/reception is not enabled. */
+    ETHER_ERR_TACT = -7,          /* Transmit buffer is not empty. */
+    ETHER_ERR_CHAN_OPEN = -8,     /* Indicates the Ethernet cannot be opened because it is being used by another application */
+    ETHER_ERR_MC_FRAME = -9,      /* Detect multicast frame when multicast frame filtering enable */
+    ETHER_ERR_RECV_ENABLE = -10,  /* Enable receive function in ETHERC */
+    ETHER_ERR_OTHER = -11         /* Other error */
+} ether_return_t;
+
+/* Event code of callback function */
+typedef enum {
+    ETHER_CB_EVENT_ID_WAKEON_LAN, /* Magic packet detection */
+    ETHER_CB_EVENT_ID_LINK_ON,    /* Link up detection */
+    ETHER_CB_EVENT_ID_LINK_OFF,   /* Link down detection */
+} ether_cb_event_t;
+
+/* Structure of the callback function pointer */
+typedef struct {
+    void (*pcb_func)(void *);     /* Callback function pointer */
+    void (*pcb_int_hnd)(void *);  /* Interrupt handler function pointer */
+} ether_cb_t;
+
+/* Structure to be used when decoding the argument of the callback function */
+typedef struct {
+    uint32_t         channel;     /* ETHERC channel */
+    ether_cb_event_t event_id;    /* Event code for callback function */
+    uint32_t         status_ecsr; /* ETHERC status register for interrupt handler */
+    uint32_t         status_eesr; /* ETHERC/EDMAC status register for interrupt handler */
+} ether_cb_arg_t;
+
+/* Parameters of the control function (1st argument) */
+typedef enum {
+    CONTROL_SET_CALLBACK,         /* Callback function registration */
+    CONTROL_SET_PROMISCUOUS_MODE, /* Promiscuous mode setting */
+    CONTROL_SET_INT_HANDLER,      /* Interrupt handler function registration */
+    CONTROL_POWER_ON,             /* Cancel ETHERC/EDMAC module stop */
+    CONTROL_POWER_OFF,            /* Transition to ETHERC/EDMAC module stop */
+    CONTROL_MULTICASTFRAME_FILTER,/* Multicast frame filter setting*/
+    CONTROL_BROADCASTFRAME_FILTER /* Broadcast frame filter setting*/
+} ether_cmd_t;
+
+typedef enum {
+    ETHER_PROMISCUOUS_OFF,        /* ETHERC operates in standard mode */
+    ETHER_PROMISCUOUS_ON          /* ETHERC operates in promiscuous mode */
+} ether_promiscuous_bit_t;
+
+typedef enum {
+    ETHER_MC_FILTER_OFF,          /* Multicast frame filter disable */
+    ETHER_MC_FILTER_ON            /* Multicast frame filter enable */
+} ether_mc_filter_t;
+
+typedef struct {
+    uint32_t                channel; /* ETHERC channel */
+    ether_promiscuous_bit_t bit;     /* Promiscuous mode */
+} ether_promiscuous_t;
+
+typedef struct {
+    uint32_t          channel;    /* ETHERC channel */
+    ether_mc_filter_t flag;       /* Multicast frame filter */
+} ether_multicast_t;
+
+typedef struct {
+    uint32_t channel;             /* ETHERC channel */
+    uint32_t counter;             /* Continuous reception number of Broadcast frame */
+} ether_broadcast_t;
+
+/* Parameters of the control function (2nd argument) */
+typedef union {
+    ether_cb_t          ether_callback;        /* Callback function pointer */
+    ether_promiscuous_t *p_ether_promiscuous;  /* Promiscuous mode setting */
+    ether_cb_t          ether_int_hnd;         /* Interrupt handler function pointer */
+    uint32_t            channel;               /* ETHERC channel number */
+    ether_multicast_t    *p_ether_multicast;   /* Multicast frame filter setting */
+    ether_broadcast_t    *p_ether_broadcast;   /* Broadcast frame filter setting */
+} ether_param_t;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+extern void R_ETHER_Initial(void);
+extern ether_return_t R_ETHER_Open_ZC2(uint32_t channel, const uint8_t mac_addr[], uint8_t pause);
+extern ether_return_t R_ETHER_Close_ZC2(uint32_t channel);
+extern int32_t R_ETHER_Read(uint32_t channel, void *pbuf);
+extern int32_t R_ETHER_Read_ZC2(uint32_t channel, void **pbuf);
+extern int32_t R_ETHER_Read_ZC2_BufRelease(uint32_t channel);
+extern ether_return_t R_ETHER_Write(uint32_t channel, void *pbuf, uint32_t len);
+extern ether_return_t R_ETHER_Write_ZC2_GetBuf(uint32_t channel, void **pbuf, uint16_t *pbuf_size);
+extern ether_return_t R_ETHER_Write_ZC2_SetBuf(uint32_t channel, const uint32_t len);
+extern ether_return_t R_ETHER_CheckLink_ZC(uint32_t channel);
+extern void R_ETHER_LinkProcess(uint32_t channel);
+extern ether_return_t R_ETHER_WakeOnLAN(uint32_t channel);
+extern ether_return_t R_ETHER_CheckWrite(uint32_t channel);
+extern ether_return_t R_ETHER_Control(ether_cmd_t const cmd, ether_param_t const control);
+extern uint32_t R_ETHER_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* R_ETHER_RZA2_IF_H*/

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.c

@@ -0,0 +1,731 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+ * File Name    : phy.c
+ * Version      : 1.00
+ * Description  : Ethernet PHY device driver
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+
+/* Access to peripherals and board defines. */
+
+#include "r_ether_rza2_config.h"
+#include "src/r_ether_rza2_private.h"
+#include "src/phy/phy.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* Media Independent Interface */
+#define PHY_MII_ST                      (1)
+#define PHY_MII_READ                    (2)
+#define PHY_MII_WRITE                   (1)
+
+/* Standard PHY Registers */
+#define PHY_REG_CONTROL                 (0)
+#define PHY_REG_STATUS                  (1)
+#define PHY_REG_IDENTIFIER1             (2)
+#define PHY_REG_IDENTIFIER2             (3)
+#define PHY_REG_AN_ADVERTISEMENT        (4)
+#define PHY_REG_AN_LINK_PARTNER         (5)
+#define PHY_REG_AN_EXPANSION            (6)
+
+/* Vendor Specific PHY Registers */
+#ifdef ETHER_CFG_USE_PHY_KSZ8041NL
+#define PHY_REG_PHY_CONTROL_1           (0x1E)
+#endif /* MICREL_KSZ8041NL */
+
+/* Basic Mode Control Register Bit Definitions */
+#define PHY_CONTROL_RESET               (1 << 15)
+#define PHY_CONTROL_LOOPBACK            (1 << 14)
+#define PHY_CONTROL_100_MBPS            (1 << 13)
+#define PHY_CONTROL_AN_ENABLE           (1 << 12)
+#define PHY_CONTROL_POWER_DOWN          (1 << 11)
+#define PHY_CONTROL_ISOLATE             (1 << 10)
+#define PHY_CONTROL_AN_RESTART          (1 << 9)
+#define PHY_CONTROL_FULL_DUPLEX         (1 << 8)
+#define PHY_CONTROL_COLLISION           (1 << 7)
+
+/* Basic Mode Status Register Bit Definitions */
+#define PHY_STATUS_100_T4               (1 << 15)
+#define PHY_STATUS_100F                 (1 << 14)
+#define PHY_STATUS_100H                 (1 << 13)
+#define PHY_STATUS_10F                  (1 << 12)
+#define PHY_STATUS_10H                  (1 << 11)
+#define PHY_STATUS_AN_COMPLETE          (1 << 5)
+#define PHY_STATUS_RM_FAULT             (1 << 4)
+#define PHY_STATUS_AN_ABILITY           (1 << 3)
+#define PHY_STATUS_LINK_UP              (1 << 2)
+#define PHY_STATUS_JABBER               (1 << 1)
+#define PHY_STATUS_EX_CAPABILITY        (1 << 0)
+
+/* Auto Negotiation Advertisement Bit Definitions */
+#define PHY_AN_ADVERTISEMENT_NEXT_PAGE  (1 << 15)
+#define PHY_AN_ADVERTISEMENT_RM_FAULT   (1 << 13)
+#define PHY_AN_ADVERTISEMENT_ASM_DIR    (1 << 11)
+#define PHY_AN_ADVERTISEMENT_PAUSE      (1 << 10)
+#define PHY_AN_ADVERTISEMENT_100_T4     (1 << 9)
+#define PHY_AN_ADVERTISEMENT_100F       (1 << 8)
+#define PHY_AN_ADVERTISEMENT_100H       (1 << 7)
+#define PHY_AN_ADVERTISEMENT_10F        (1 << 6)
+#define PHY_AN_ADVERTISEMENT_10H        (1 << 5)
+#define PHY_AN_ADVERTISEMENT_SELECTOR   (1 << 0)
+
+/* Auto Negotiate Link Partner Ability Bit Definitions */
+#define PHY_AN_LINK_PARTNER_NEXT_PAGE   (1 << 15)
+#define PHY_AN_LINK_PARTNER_ACK         (1 << 14)
+#define PHY_AN_LINK_PARTNER_RM_FAULT    (1 << 13)
+#define PHY_AN_LINK_PARTNER_ASM_DIR     (1 << 11)
+#define PHY_AN_LINK_PARTNER_PAUSE       (1 << 10)
+#define PHY_AN_LINK_PARTNER_100_T4      (1 << 9)
+#define PHY_AN_LINK_PARTNER_100F        (1 << 8)
+#define PHY_AN_LINK_PARTNER_100H        (1 << 7)
+#define PHY_AN_LINK_PARTNER_10F         (1 << 6)
+#define PHY_AN_LINK_PARTNER_10H         (1 << 5)
+#define PHY_AN_LINK_PARTNER_SELECTOR    (1 << 0)
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Private global variables and functions
+ ***********************************************************************************************************************/
+static uint16_t phy_read(uint32_t ether_channel, uint16_t reg_addr);
+static void phy_write(uint32_t ether_channel, uint16_t reg_addr, uint16_t data);
+static void phy_preamble(uint32_t ether_channel);
+static void phy_reg_set(uint32_t ether_channel, uint16_t reg_addr, int32_t option);
+static void phy_reg_read(uint32_t ether_channel, uint16_t *pdata);
+static void phy_reg_write(uint32_t ether_channel, uint16_t data);
+static void phy_trans_zto0(uint32_t ether_channel);
+static void phy_trans_1to0(uint32_t ether_channel);
+static void phy_mii_write1(uint32_t ether_channel);
+static void phy_mii_write0(uint32_t ether_channel);
+static int16_t phy_get_pir_address(uint32_t ether_channel, volatile uint32_t **pppir_addr);
+static uint32_t phy_get_ctrl_tbl_idx(uint32_t ether_channel);
+
+static uint16_t local_advertise[ETHER_CHANNEL_MAX]; /* the capabilities of the local link as PHY data */
+
+/**
+ * Public functions
+ */
+
+/***********************************************************************************************************************
+ * Function Name: phy_init
+ * Description  : Resets Ethernet PHY device
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : R_PHY_OK -
+ *
+ *                R_PHY_ERROR -
+ *
+ ***********************************************************************************************************************/
+int16_t phy_init(uint32_t ether_channel)
+{
+    uint16_t reg;
+    uint32_t count;
+
+    /* Reset PHY */
+    phy_write(ether_channel, PHY_REG_CONTROL, PHY_CONTROL_RESET);
+
+    count = 0;
+
+    /* Reset completion waiting */
+    do {
+        reg = phy_read(ether_channel, PHY_REG_CONTROL);
+        count++;
+    } while ((reg & PHY_CONTROL_RESET) && (count < ETHER_CFG_PHY_DELAY_RESET));
+
+    if (count < ETHER_CFG_PHY_DELAY_RESET) {
+        /*
+         * When KSZ8041NL of the Micrel, Inc. is used,
+         * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default.
+         * The setting of the pin is changed so that only the state of LINK is output.
+         */
+#if ETHER_CFG_USE_PHY_KSZ8041NL != 0
+        reg = phy_read(ether_channel, PHY_REG_PHY_CONTROL_1);
+        reg &= ~0x8000;
+        reg |= 0x4000;
+        phy_write(ether_channel, PHY_REG_PHY_CONTROL_1, reg);
+#endif /* ETHER_CFG_USE_PHY_KSZ8041NL != 0 */
+
+        return R_PHY_OK;
+    }
+    return R_PHY_ERROR;
+} /* End of function phy_init() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_start_autonegotiate
+ * Description  : Starts auto-negotiate
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pause -
+ *                    Using state of pause frames
+ * Return Value : none
+ ***********************************************************************************************************************/
+void phy_start_autonegotiate(uint32_t ether_channel, uint8_t pause)
+{
+    volatile uint16_t reg = 0;
+    uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel);
+
+    /* Set local ability */
+    /* When pause frame is not used */
+    if (ETHER_FLAG_OFF == pause) {
+        local_advertise[ether_channel_index] = ((((PHY_AN_ADVERTISEMENT_100F |
+                                                   PHY_AN_ADVERTISEMENT_100H) |
+                                                  PHY_AN_ADVERTISEMENT_10F) |
+                                                 PHY_AN_ADVERTISEMENT_10H) |
+                                                PHY_AN_ADVERTISEMENT_SELECTOR);
+
+    }
+
+    /* When pause frame is used */
+    else {
+        local_advertise[ether_channel_index] = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR |
+                                                     PHY_AN_ADVERTISEMENT_PAUSE) |
+                                                    PHY_AN_ADVERTISEMENT_100F) |
+                                                   PHY_AN_ADVERTISEMENT_100H) |
+                                                  PHY_AN_ADVERTISEMENT_10F) |
+                                                 PHY_AN_ADVERTISEMENT_10H) |
+                                                PHY_AN_ADVERTISEMENT_SELECTOR);
+    }
+
+    /* Configure what the PHY and the Ethernet controller on this board supports */
+    phy_write(ether_channel, PHY_REG_AN_ADVERTISEMENT, local_advertise[ether_channel_index]);
+    phy_write(ether_channel, PHY_REG_CONTROL, (PHY_CONTROL_AN_ENABLE |
+                                               PHY_CONTROL_AN_RESTART));
+
+    reg = phy_read(ether_channel, PHY_REG_AN_ADVERTISEMENT);
+    (void)reg;
+
+} /* End of function phy_start_autonegotiate() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_set_autonegotiate
+ * Description  : reports the other side's physical capability
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *              : *pline_speed_duplex -
+ *                    a pointer to the location of both the line speed and the duplex
+ *                *plocal_pause -
+ *                    a pointer to the location to store the local pause bits.
+ *                *ppartner_pause -
+ *                    a pointer to the location to store the partner pause bits.
+ * Return Value : R_PHY_OK -
+ *
+ *                R_PHY_ERROR -
+ *
+ * Note         : The value returned to local_pause and patner_pause is used
+ *                as it is as an argument of ether_pause_resolution function.
+ ***********************************************************************************************************************/
+int16_t phy_set_autonegotiate(uint32_t ether_channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause,
+                              uint16_t *ppartner_pause)
+{
+    uint16_t reg;
+    uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel);
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+
+    /* When the link isn't up, return error */
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP)) {
+        return R_PHY_ERROR;
+    }
+
+    /* Establish local pause capability */
+    if (PHY_AN_ADVERTISEMENT_PAUSE == (local_advertise[ether_channel_index] & PHY_AN_ADVERTISEMENT_PAUSE)) {
+        (*plocal_pause) |= (1 << 1);
+    }
+
+    if (PHY_AN_ADVERTISEMENT_ASM_DIR == (local_advertise[ether_channel_index] & PHY_AN_ADVERTISEMENT_ASM_DIR)) {
+        (*plocal_pause) |= 1;
+    }
+
+    /* When the auto-negotiation isn't completed, return error */
+    if (PHY_STATUS_AN_COMPLETE != (reg & PHY_STATUS_AN_COMPLETE)) {
+        return R_PHY_ERROR;
+    }
+
+    /* Get the link partner response */
+    reg = phy_read(ether_channel, PHY_REG_AN_LINK_PARTNER);
+
+    /* Establish partner pause capability */
+    if (PHY_AN_LINK_PARTNER_PAUSE == (reg & PHY_AN_LINK_PARTNER_PAUSE)) {
+        (*ppartner_pause) = (1 << 1);
+    }
+
+    if (PHY_AN_LINK_PARTNER_ASM_DIR == (reg & PHY_AN_LINK_PARTNER_ASM_DIR)) {
+        (*ppartner_pause) |= 1;
+    }
+
+    /* Establish the line speed and the duplex */
+    if (PHY_AN_LINK_PARTNER_10H == (reg & PHY_AN_LINK_PARTNER_10H)) {
+        (*pline_speed_duplex) = PHY_LINK_10H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_10F == (reg & PHY_AN_LINK_PARTNER_10F)) {
+        (*pline_speed_duplex) = PHY_LINK_10F;
+    }
+
+    if (PHY_AN_LINK_PARTNER_100H == (reg & PHY_AN_LINK_PARTNER_100H)) {
+        (*pline_speed_duplex) = PHY_LINK_100H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_100F == (reg & PHY_AN_LINK_PARTNER_100F)) {
+        (*pline_speed_duplex) = PHY_LINK_100F;
+    }
+
+    return R_PHY_OK;
+} /* End of function phy_set_autonegotiate() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_get_link_status
+ * Description  : Returns the status of the physical link
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : -1 if links is down, 0 otherwise
+ ***********************************************************************************************************************/
+int16_t phy_get_link_status(uint32_t ether_channel)
+{
+    uint16_t reg;
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+
+
+    /* When the link isn't up, return error */
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP)) {
+        /* Link is down */
+        return R_PHY_ERROR;
+    }
+
+    /* Link is up */
+    return R_PHY_OK;
+} /* End of function phy_get_link_status() */
+
+/**
+ * Private functions
+ */
+
+/***********************************************************************************************************************
+ * Function Name: phy_read
+ * Description  : Reads a PHY register
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ * Return Value : read value
+ ***********************************************************************************************************************/
+static uint16_t phy_read(uint32_t ether_channel, uint16_t reg_addr)
+{
+    uint16_t data;
+
+    /*
+     * The value is read from the PHY register by the frame format of MII Management Interface provided
+     * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2.
+     */
+    phy_preamble(ether_channel);
+    phy_reg_set(ether_channel, reg_addr, PHY_MII_READ);
+    phy_trans_zto0(ether_channel);
+    phy_reg_read(ether_channel, &data);
+    phy_trans_zto0(ether_channel);
+
+    return (data);
+} /* End of function phy_read() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_write
+ * Description  : Writes to a PHY register
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ *                data -
+ *                    value
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_write(uint32_t ether_channel, uint16_t reg_addr, uint16_t data)
+{
+    /*
+     * The value is read from the PHY register by the frame format of MII Management Interface provided
+     * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2.
+     */
+    phy_preamble(ether_channel);
+    phy_reg_set(ether_channel, reg_addr, PHY_MII_WRITE);
+    phy_trans_1to0(ether_channel);
+    phy_reg_write(ether_channel, data);
+    phy_trans_zto0(ether_channel);
+} /* End of function phy_write() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_preamble
+ * Description  : As preliminary preparation for access to the PHY module register,
+ *                "1" is output via the MII management interface.
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_preamble(uint32_t ether_channel)
+{
+    int16_t i;
+
+    /*
+     * The processing of PRE (preamble) about the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    i = 32;
+    while (i > 0) {
+        phy_mii_write1(ether_channel);
+        i--;
+    }
+} /* End of function phy_preamble() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_set
+ * Description  : Sets a PHY device to read or write mode
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ *                option -
+ *                    mode
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_set(uint32_t ether_channel, uint16_t reg_addr, int32_t option)
+{
+    int32_t i;
+    uint16_t data;
+    uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel);
+
+    /*
+     * The processing of ST (start of frame),OP (operation code), PHYAD (PHY Address), and
+     * REGAD (Register Address)  about the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    data = 0;
+    data = (PHY_MII_ST << 14); /* ST code    */
+
+    if (PHY_MII_READ == option) {
+        data |= (PHY_MII_READ << 12); /* OP code(RD)  */
+    } else {
+        data |= (PHY_MII_WRITE << 12); /* OP code(WT)  */
+    }
+
+    data |= (uint16_t)(g_eth_control_ch[ether_channel_index].phy_address << 7);  /* PHY Address  */
+
+    data |= (reg_addr << 2); /* Reg Address  */
+
+    i = 14;
+    while (i > 0) {
+        if (0 == (data & 0x8000)) {
+            phy_mii_write0(ether_channel);
+        } else {
+            phy_mii_write1(ether_channel);
+        }
+        data <<= 1;
+        i--;
+    }
+} /* End of function phy_reg_set() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_read
+ * Description  : Reads PHY register through MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pdata -
+ *                    pointer to store the data read
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_read(uint32_t ether_channel, uint16_t *pdata)
+{
+    int32_t i;
+    int32_t j;
+    uint16_t reg_data;
+    int16_t ret;
+    volatile uint32_t *petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if (R_PHY_ERROR == ret) {
+        return;
+    }
+
+    /*
+     * The processing of DATA (data) about reading of the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    reg_data = 0;
+    i = 16;
+    while (i > 0) {
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+            (*petherc_pir) = 0x00000000;
+        }
+
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+            (*petherc_pir) = 0x00000001;
+        }
+        reg_data <<= 1;
+
+        reg_data |= (uint16_t)(((*petherc_pir) & 0x00000008) >> 3);  /* MDI read  */
+
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+            (*petherc_pir) = 0x00000001;
+        }
+
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+            (*petherc_pir) = 0x00000000;
+        }
+
+        i--;
+    }
+    (*pdata) = reg_data;
+} /* End of function phy_reg_read() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_write
+ * Description  : Writes to PHY register through MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                data -
+ *                    value to write
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_write(uint32_t ether_channel, uint16_t data)
+{
+    int32_t i;
+
+    /*
+     * The processing of DATA (data) about writing of the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    i = 16;
+    while (i > 0) {
+        if (0 == (data & 0x8000)) {
+            phy_mii_write0(ether_channel);
+        } else {
+            phy_mii_write1(ether_channel);
+        }
+        i--;
+        data <<= 1;
+    }
+} /* End of function phy_reg_write() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_trans_zto0
+ * Description  : Performs bus release so that PHY can drive data
+ *              : for read operation
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_trans_zto0(uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t *petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if (R_PHY_ERROR == ret) {
+        return;
+    }
+
+    /*
+     * The processing of TA (turnaround) about reading of the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000000;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000001;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000001;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000000;
+    }
+
+} /* End of function phy_trans_zto0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_trans_1to0
+ * Description  : Switches data bus so MII interface can drive data
+ *              : for write operation
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_trans_1to0(uint32_t ether_channel)
+{
+    /*
+     * The processing of TA (turnaround) about writing of the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    phy_mii_write1(ether_channel);
+    phy_mii_write0(ether_channel);
+} /* End of function phy_trans_1to0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_mii_write1
+ * Description  : Outputs 1 to the MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_mii_write1(uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t *petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if (R_PHY_ERROR == ret) {
+        return;
+    }
+
+    /*
+     * The processing of one bit about frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     * The data that 1 is output.
+     */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000006;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000007;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000007;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000006;
+    }
+
+} /* End of function phy_mii_write1() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_mii_write0
+ * Description  : Outputs 0 to the MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_mii_write0(uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t *petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if (R_PHY_ERROR == ret) {
+        return;
+    }
+
+    /*
+     * The processing of one bit about frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     * The data that 0 is output.
+     */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000002;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000003;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000003;
+    }
+
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) {
+        (*petherc_pir) = 0x00000002;
+    }
+
+} /* End of function phy_mii_write0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_get_pir_address
+ * Description  : Get the address of the PHY interface register.
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pppir_addr -
+ *                    Pointer of the PHY interface register
+ * Return Value : none
+ ***********************************************************************************************************************/
+static int16_t phy_get_pir_address(uint32_t ether_channel, volatile uint32_t **pppir_addr)
+{
+    volatile uint32_t *petherc_pir;
+    uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel);
+
+    petherc_pir = g_eth_control_ch[ether_channel_index].preg_pir;
+
+    (*pppir_addr) = petherc_pir;
+
+    return R_PHY_OK;
+} /* End of function phy_get_pir_address() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_get_ctrl_tbl_idx
+ * Description  : get index of control table.
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : Index of control table
+ ***********************************************************************************************************************/
+static uint32_t phy_get_ctrl_tbl_idx(uint32_t ether_channel)
+{
+#if (ETHER_CHANNEL_MAX == 1)
+    return 0;
+#else
+    return ether_channel;
+#endif
+} /* End of function phy_get_ctrl_tbl_idx() */

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.h

@@ -0,0 +1,84 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+ * File Name    : phy.h
+ * Version      : 1.00
+ * Description  : Ethernet PHY device driver
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef PHY_H
+#define PHY_H
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* PHY return definitions */
+#define R_PHY_OK        (0)
+#define R_PHY_ERROR     (-1)
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+typedef enum LinkStatE {
+    PHY_NO_LINK = 0, PHY_LINK_10H, PHY_LINK_10F, PHY_LINK_100H, PHY_LINK_100F
+} linkstat_t;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+extern int16_t phy_init(uint32_t channel);
+extern void phy_start_autonegotiate(uint32_t channel, uint8_t pause);
+extern int16_t phy_set_autonegotiate(uint32_t channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause,
+                                     uint16_t *ppartner_pause);
+extern int16_t phy_get_link_status(uint32_t channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PHY_H */
+

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2_private.h

@@ -0,0 +1,275 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+ * File Name    : r_ether_rza2_private.h
+ * Version      : 1.00
+ * Device       : RZA2M
+ * H/W Platform :
+ * Description  : File that defines macro and structure seen only in "r_ether_rza2.c" file.
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_PRIVATE_H
+#define R_ETHER_PRIVATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include "r_ether_rza2_if.h"
+#include "r_ether_rza2_config.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+
+/* Check the setting values is valid. Please review the setting values in r_ether_rza2_config.h if error message is output */
+#if !((ETHER_CFG_MODE_SEL == 0) || (ETHER_CFG_MODE_SEL == 1))
+#error "ERROR- ETHER_CFG_MODE_SEL - Ethernet interface select is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_CH0_PHY_ADDRESS >= 0) && (ETHER_CFG_CH0_PHY_ADDRESS <= 31))
+#error "ERROR- ETHER_CFG_CH0_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_CH1_PHY_ADDRESS >= 0) && (ETHER_CFG_CH1_PHY_ADDRESS <= 31))
+#error "ERROR- ETHER_CFG_CH1_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !(ETHER_CFG_EMAC_RX_DESCRIPTORS >= 1)
+#error "ERROR- ETHER_CFG_EMAC_RX_DESCRIPTORS - Transmission descriptors is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !(ETHER_CFG_EMAC_TX_DESCRIPTORS >= 1)
+#error "ERROR- ETHER_CFG_EMAC_TX_DESCRIPTORS - Receive descriptors is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_BUFSIZE % 32) == 0)
+#error "ERROR- ETHER_CFG_BUFSIZE - transmission and receive buffers is not 32-byte aligned in r_ether_rza2_config.h."
+#endif
+
+#if !(ETHER_CFG_PHY_MII_WAIT >= 1)
+#error "ERROR- ETHER_CFG_PHY_MII_WAIT - PHY-LSI access timing is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_LINK_PRESENT == 0) || (ETHER_CFG_LINK_PRESENT == 1))
+#error "ERROR- ETHER_CFG_LINK_PRESENT - Link signal polarity of PHY-LSI is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_USE_LINKSTA == 0) || (ETHER_CFG_USE_LINKSTA == 1))
+#error "ERROR- ETHER_CFG_USE_LINKSTA - Use LINKSTA select is out of range defined in r_ether_rza2_config.h."
+#endif
+
+#if !((ETHER_CFG_USE_PHY_KSZ8041NL == 0) || (ETHER_CFG_USE_PHY_KSZ8041NL == 1))
+#error "ERROR- ETHER_CFG_USE_PHY_KSZ8041NL - use KSZ8041NL is out of range defined in r_ether_rza2_config.h."
+#endif
+
+/*
+ * The total number of EMAC buffers to allocate. The number of
+ * total buffers is simply the sum of the number of transmit and
+ * receive buffers.
+ */
+#define EMAC_NUM_BUFFERS            (ETHER_CFG_EMAC_RX_DESCRIPTORS + (ETHER_CFG_EMAC_TX_DESCRIPTORS))
+
+/* Definition of the maximum / minimum number of data that can be sent at one time in the Ethernet */
+#define ETHER_BUFSIZE_MAX           (1514)          /* Maximum number of transmitted data */
+#define ETHER_BUFSIZE_MIN           (60)            /* Minimum number of transmitted data */
+
+/* Bit definition of interrupt factor of Ethernet interrupt */
+#define EMAC_LCHNG_INT      (1UL << 2)
+#define EMAC_MPD_INT        (1UL << 1)
+
+#define EMAC_RFCOF_INT      (1UL << 24)
+#define EMAC_ECI_INT        (1UL << 22)
+#define EMAC_TC_INT         (1UL << 21)
+#define EMAC_FR_INT         (1UL << 18)
+#define EMAC_RDE_INT        (1UL << 17)
+#define EMAC_RFOF_INT       (1UL << 16)
+
+/* Bit definitions of status member of DescriptorS */
+#define  TACT               (0x80000000)
+#define  RACT               (0x80000000)
+#define  TDLE               (0x40000000)
+#define  RDLE               (0x40000000)
+#define  TFP1               (0x20000000)
+#define  RFP1               (0x20000000)
+#define  TFP0               (0x10000000)
+#define  RFP0               (0x10000000)
+#define  TFE                (0x08000000)
+#define  RFE                (0x08000000)
+
+#define  RFS9_RFOVER        (0x00000200)
+#define  RFS8_RAD           (0x00000100)
+#define  RFS7_RMAF          (0x00000080)
+#define  RFS4_RRF           (0x00000010)
+#define  RFS3_RTLF          (0x00000008)
+#define  RFS2_RTSF          (0x00000004)
+#define  RFS1_PRE           (0x00000002)
+#define  RFS0_CERF          (0x00000001)
+
+#define  TWBI               (0x04000000)
+#define  TFS8_TAD           (0x00000100)
+#define  TFS3_CND           (0x00000008)
+#define  TFS2_DLC           (0x00000004)
+#define  TFS1_CD            (0x00000002)
+#define  TFS0_TRO           (0x00000001)
+
+/* Number of entries in PAUSE resolution table */
+#define PAUSE_TABLE_ENTRIES (8)
+
+/* Local device and link partner PAUSE settings */
+#define XMIT_PAUSE_OFF      (0) /* The pause frame transmission is prohibited. */
+#define RECV_PAUSE_OFF      (0) /* The pause frame reception is prohibited.    */
+#define XMIT_PAUSE_ON       (1) /* The pause frame transmission is permitted.  */
+#define RECV_PAUSE_ON       (1) /* The pause frame reception is permitted.     */
+
+/* PAUSE link mask and shift values */
+/*
+ * The mask value and shift value which are for that shift the bits form a line and
+ * for comparing the bit information of PAUSE function which support the local device and
+ * Link partner with the assorted table(pause_resolution) which enable or disable the PAUSE frame.
+ */
+#define LINK_RES_ABILITY_MASK           (3)
+#define LINK_RES_LOCAL_ABILITY_BITSHIFT (2)
+
+/* Etherc mode */
+#define NO_USE_MAGIC_PACKET_DETECT  (0)
+#define USE_MAGIC_PACKET_DETECT     (1)
+
+/* Defines the port connection to be used in the Ether */
+#define PORT_CONNECT_ET0            (0x01)
+#define PORT_CONNECT_ET1            (0x02)
+
+/** Ethernet module usage status */
+#define ETEHR_MODULE_NOT_USE    (0) /* Ethernet module is not used */
+#define ETHER_MODULE_USE        (1) /* Ethernet module is used */
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+/*
+ * EDMAC descriptor as defined in the hardware manual. It is
+ * modified to support little endian CPU mode.
+ */
+typedef struct DescriptorS {
+    volatile uint32_t  status;
+    volatile uint16_t  size;
+    volatile uint16_t  bufsize;
+    volatile uint8_t   *buf_p;
+    struct DescriptorS *next;
+} descriptor_t;
+
+/*
+ * Ethernet buffer type definition.
+ */
+typedef struct EtherBufferS {
+    uint8_t buffer[EMAC_NUM_BUFFERS][ETHER_CFG_BUFSIZE];
+
+} etherbuffer_t;
+
+/*
+ * PauseMaskE, PauseValE and pause_resolutionS are use to create
+ * PAUSE resolution Table 28B-3 in IEEE 802.3-2008 standard.
+ */
+typedef enum PauseMaskE {
+    PAUSE_MASK0,
+    PAUSE_MASK1,
+    PAUSE_MASK2,
+    PAUSE_MASK3,
+    PAUSE_MASK4,
+    PAUSE_MASK5,
+    PAUSE_MASK6,
+    PAUSE_MASK7,
+    PAUSE_MASK8,
+    PAUSE_MASK9,
+    PAUSE_MASKA,
+    PAUSE_MASKB,
+    PAUSE_MASKC,
+    PAUSE_MASKD,
+    PAUSE_MASKE,
+    PAUSE_MASKF
+} pausemask_t;
+
+typedef enum PauseValE {
+    PAUSE_VAL0,
+    PAUSE_VAL1,
+    PAUSE_VAL2,
+    PAUSE_VAL3,
+    PAUSE_VAL4,
+    PAUSE_VAL5,
+    PAUSE_VAL6,
+    PAUSE_VAL7,
+    PAUSE_VAL8,
+    PAUSE_VAL9,
+    PAUSE_VALA,
+    PAUSE_VALB,
+    PAUSE_VALC,
+    PAUSE_VALD,
+    PAUSE_VALE,
+    PAUSE_VALF
+} pauseval_t;
+
+typedef struct pause_resolutionS {
+    pausemask_t mask;
+    pauseval_t  value;
+    uint8_t     transmit;
+    uint8_t     receive;
+} pauseresolution_t;
+
+typedef struct {
+    volatile struct st_etherc *petherc;  /* ETHERC module */
+    volatile struct st_edmac *pedmac;  /* EDMAC */
+    volatile uint32_t          *preg_pir;
+    uint32_t                  phy_address;
+    uint8_t                   port_connect;
+} ether_control_t;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+extern const ether_control_t g_eth_control_ch[];
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+extern void ether_set_phy_mode(uint8_t connect);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* R_ETHER_PRIVATE_H */

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_rza2_config.h

@@ -0,0 +1,118 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+ * File Name    : r_ether_rza2_config.h
+ * Version      : 1.00
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_RZA2_CONFIG_H
+#define R_ETHER_RZA2_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* Ethernet channel select.
+ 0 = disable
+ 1 = enable
+ If only one of them is enabled, the API argument "channel" value is not referenced.
+ */
+#define ETHER_CH0_EN                                (0)
+#define ETHER_CH1_EN                                (1)
+
+/* Ethernet interface select.
+ 0 = MII  (Media Independent Interface)
+ 1 = RMII (Reduced Media Independent Interface)
+ */
+#define ETHER_CFG_MODE_SEL                          (0)
+
+/* PHY-LSI address setting for ETHER0/1.
+ */
+#define ETHER_CFG_CH0_PHY_ADDRESS                   (0)     /* Please define the PHY-LSI address in the range of 0-31. */
+#define ETHER_CFG_CH1_PHY_ADDRESS                   (0)     /* Please define the PHY-LSI address in the range of 0-31. */
+
+/* The number of Rx descriptors. */
+#define ETHER_CFG_EMAC_RX_DESCRIPTORS               (8)
+
+/* The number of Tx descriptors. */
+#define ETHER_CFG_EMAC_TX_DESCRIPTORS               (8)
+
+/* Please define the size of the sending and receiving buffer in the value where one frame can surely be stored
+ because the driver is single-frame/single-buffer processing.  */
+#define ETHER_CFG_BUFSIZE                           (1536)  /* Must be 32-byte aligned */
+
+/* Define the access timing of MII/RMII register */
+#define ETHER_CFG_PHY_MII_WAIT                      (8)     /* Plese define the value of 1 or more */
+
+/* Define the waiting time for reset completion of PHY-LSI */
+#define ETHER_CFG_PHY_DELAY_RESET                   (0x00020000L)
+
+/**
+ * Link status read from LMON bit of ETHERC PSR register.  The state is hardware dependent.
+ */
+#define ETHER_CFG_LINK_PRESENT                      (0)
+
+/*  Use LINKSTA signal for detect link status changes
+ 0 = unused  (use PHY-LSI status register)
+ 1 = use     (use LINKSTA signal)
+ */
+#define ETHER_CFG_USE_LINKSTA                       (0)     /* This setting is reflected in all channels */
+
+/* Definition of whether or not to use KSZ8041NL of the Micrel Inc.
+ 0 = unused
+ 1 = use
+ */
+#define ETHER_CFG_USE_PHY_KSZ8041NL                 (0)
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* R_ETHER_RZA2_CONFIG_H */

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_setting_rza2m.c

@@ -0,0 +1,119 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/***********************************************************************************************************************
+* File Name    : r_ether_setting_rza2m.c
+* Version      : 1.00
+* Device       : RZA2M
+* Description  : Ethernet module device driver
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include "r_ether_rza2_if.h"
+#include "src/r_ether_rza2_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: ether_set_phy_mode
+* Description  :
+* Arguments    : connect -
+*                    Ethernet channel number
+* Return Value : none
+***********************************************************************************************************************/
+void ether_set_phy_mode(uint8_t connect)
+{
+#if (ETHER_CH0_EN == 1)
+#error "Not support in this board."
+#endif
+
+#if (ETHER_CH1_EN == 1)
+    if (PORT_CONNECT_ET1 == (connect & PORT_CONNECT_ET1)) {
+#if (ETHER_CFG_MODE_SEL == 0)
+        /* CH1 MII */
+        GPIO.PFENET.BIT.PHYMODE1 = 1;
+        pin_function(P3_3, 1); // ET1_MDC
+        pin_function(P3_4, 1); // ET1_MDIO
+        pin_function(PC_0, 3); // ET1_TXCLK
+        pin_function(PC_4, 3); // ET1_TXER
+        pin_function(PK_0, 1); // ET1_TXEN
+        pin_function(PK_1, 1); // ET1_TXD0
+        pin_function(PK_2, 1); // ET1_TXD1
+        pin_function(PC_1, 3); // ET1_TXD2
+        pin_function(PC_2, 3); // ET1_TXD3
+        pin_function(PK_3, 1); // ET1_RXCLK
+        pin_function(P3_1, 1); // ET1_RXER
+        pin_function(PC_5, 3); // ET1_RXDV
+        pin_function(PK_4, 1); // ET1_RXD0
+        pin_function(P3_5, 1); // ET1_RXD1
+        pin_function(PC_6, 3); // ET1_RXD2
+        pin_function(PC_7, 3); // ET1_RXD3
+        pin_function(P3_2, 1); // ET1_CRS
+        pin_function(PC_3, 3); // ET1_COL
+#elif (ETHER_CFG_MODE_SEL == 1)
+        /* CH1 RMII */
+        GPIO.PFENET.BIT.PHYMODE1 = 0;
+        GPIO.PMODEPFS.BIT.ET1_EXOUT_SEL = 0;
+#error "Not support in this board."
+#endif
+    }
+#endif
+
+} /* End of function ether_set_phy_mode() */
+
+/* End of File */

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.cpp

@@ -0,0 +1,290 @@
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <ctype.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "cmsis_os.h"
+
+#include "mbed_interface.h"
+#include "mbed_assert.h"
+#include "netsocket/nsapi_types.h"
+#include "mbed_shared_queues.h"
+
+#include "r_ether_rza2_if.h"
+#include "rza2_emac.h"
+#include "r_ether_rza2_config.h"
+
+#define RZ_A2_ETH_IF_NAME    "en"
+#define PHY_TASK_PERIOD      200ms
+
+using namespace std::chrono;
+
+// Weak so a module can override
+MBED_WEAK EMAC &EMAC::get_default_instance()
+{
+#if (ETHER_CH0_EN == 1)
+    return RZ_A2_EMAC::get_instance(ETHER_CHANNEL_0);
+#elif (ETHER_CH1_EN == 1)
+    return RZ_A2_EMAC::get_instance(ETHER_CHANNEL_1);
+#else
+#error "Set ETHER_CH0_EN or ETHER_CH1_EN to 1."
+#endif
+}
+
+RZ_A2_EMAC &RZ_A2_EMAC::get_instance(uint32_t channel)
+{
+#if (ETHER_CH0_EN == 1) && (ETHER_CH1_EN == 1)
+    static RZ_A2_EMAC emac_0(ETHER_CHANNEL_0);
+    static RZ_A2_EMAC emac_1(ETHER_CHANNEL_1);
+
+    if (channel == 0) {
+        return emac_0;
+    } else {
+        return emac_1;
+    }
+#else
+    static RZ_A2_EMAC emac(channel);
+    return emac;
+#endif
+}
+
+RZ_A2_EMAC::RZ_A2_EMAC(uint32_t channel) : _channel(channel), hwaddr(), hwaddr_set(false), power_on(false),
+    recvThread(osPriorityNormal, 896), sem_recv(0)
+{
+}
+
+uint32_t RZ_A2_EMAC::get_mtu_size() const
+{
+    return 1500;
+}
+
+uint32_t RZ_A2_EMAC::get_align_preference() const
+{
+    return 0;
+}
+
+void RZ_A2_EMAC::get_ifname(char *name, uint8_t size) const
+{
+    memcpy(name, RZ_A2_ETH_IF_NAME, (size < sizeof(RZ_A2_ETH_IF_NAME)) ? size : sizeof(RZ_A2_ETH_IF_NAME));
+}
+
+uint8_t RZ_A2_EMAC::get_hwaddr_size() const
+{
+    return 6;
+}
+
+bool RZ_A2_EMAC::get_hwaddr(uint8_t *addr) const
+{
+    return false;
+}
+
+void RZ_A2_EMAC::set_hwaddr(const uint8_t *addr)
+{
+    memcpy(hwaddr, addr, sizeof(hwaddr));
+    hwaddr_set = true;
+
+    /* Reconnect */
+    if (power_on != false) {
+        R_ETHER_Open_ZC2(_channel, hwaddr, ETHER_FLAG_OFF);
+    }
+}
+
+bool RZ_A2_EMAC::link_out(emac_mem_buf_t *buf)
+{
+    emac_mem_buf_t *copy_buf = buf;
+    uint32_t       retry_cnt = 0;
+    uint16_t       write_buf_size;
+    int            total_write_size = 0;
+    uint8_t       *pwrite_buffer_address;
+
+    while (1) {
+        if (R_ETHER_Write_ZC2_GetBuf(_channel, (void **) &pwrite_buffer_address, &write_buf_size) == ETHER_SUCCESS) {
+            break;
+        }
+        retry_cnt++;
+        if (retry_cnt > 200) {
+            memory_manager->free(buf);
+            return false;
+        }
+        osDelay(1);
+    }
+
+    while ((copy_buf != NULL) && (memory_manager->get_ptr(copy_buf) != NULL) && (memory_manager->get_len(copy_buf) != 0)) {
+        memcpy(&pwrite_buffer_address[total_write_size], memory_manager->get_ptr(copy_buf), memory_manager->get_len(copy_buf));
+        total_write_size +=  memory_manager->get_len(copy_buf);
+        copy_buf = memory_manager->get_next(copy_buf);
+    }
+    memory_manager->free(buf);
+
+    if (total_write_size > 0) {
+        if (total_write_size < 60) {
+            memset(&pwrite_buffer_address[total_write_size], 0, 60 - total_write_size);
+            total_write_size = 60;
+        }
+        if (R_ETHER_Write_ZC2_SetBuf(_channel, total_write_size) == ETHER_SUCCESS) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+bool RZ_A2_EMAC::power_up()
+{
+    ether_param_t param;
+
+    if (power_on != false) {
+        return true;
+    }
+
+    /* Initialize memory which ETHERC/EDMAC is used */
+    R_ETHER_Initial();
+
+    /* Set the callback function */
+    param.ether_callback.pcb_func    = &_callback_pcb;
+    R_ETHER_Control(CONTROL_SET_CALLBACK, param);
+
+    /* Set the callback function */
+    param.ether_callback.pcb_int_hnd    = &_callback_hnd;
+    R_ETHER_Control(CONTROL_SET_INT_HANDLER, param);
+
+    param.channel = _channel;
+    R_ETHER_Control(CONTROL_POWER_ON, param);
+
+    if (hwaddr_set != false) {
+        R_ETHER_Open_ZC2(_channel, hwaddr, ETHER_FLAG_OFF);
+    }
+
+    /* task */
+    recvThread.start(mbed::callback(this, &RZ_A2_EMAC::recv_task));
+    phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD, mbed::callback(this, &RZ_A2_EMAC::phy_task));
+
+    power_on = true;
+    return true;
+}
+
+void RZ_A2_EMAC::power_down()
+{
+    power_on = false;
+}
+
+void RZ_A2_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
+{
+    emac_link_input_cb = input_cb;
+}
+
+void RZ_A2_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
+{
+    emac_link_state_cb = state_cb;
+}
+
+void RZ_A2_EMAC::add_multicast_group(const uint8_t *addr)
+{
+    // Not supported
+}
+
+void RZ_A2_EMAC::remove_multicast_group(const uint8_t *addr)
+{
+    // Not supported
+}
+
+void RZ_A2_EMAC::set_all_multicast(bool all)
+{
+    // Not supported
+}
+
+void RZ_A2_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
+{
+    memory_manager = &mem_mngr;
+}
+
+void RZ_A2_EMAC::_callback_pcb(void *arg)
+{
+    ether_cb_arg_t *p_cb_arg = (ether_cb_arg_t *)arg;
+    get_instance(p_cb_arg->channel).callback_pcb(arg);
+}
+
+void RZ_A2_EMAC::_callback_hnd(void *arg)
+{
+    ether_cb_arg_t *p_cb_arg = (ether_cb_arg_t *)arg;
+    get_instance(p_cb_arg->channel).callback_hnd(arg);
+}
+
+void RZ_A2_EMAC::callback_pcb(void *arg)
+{
+    ether_cb_arg_t *p_cb_arg = (ether_cb_arg_t *)arg;
+
+    if (p_cb_arg->event_id == ETHER_CB_EVENT_ID_LINK_ON) {
+        emac_link_state_cb(true);
+    } else if (p_cb_arg->event_id == ETHER_CB_EVENT_ID_LINK_OFF) {
+        emac_link_state_cb(false);
+    } else {
+        // do nothing
+    }
+}
+
+void RZ_A2_EMAC::callback_hnd(void *arg)
+{
+    ether_cb_arg_t *p_cb_arg = (ether_cb_arg_t *)arg;
+
+    if (p_cb_arg->status_eesr & 0x00040000) {
+        sem_recv.release();
+    }
+}
+
+void RZ_A2_EMAC::recv_task(void)
+{
+    int32_t ret;
+    emac_mem_buf_t *buf;
+    uint8_t *pread_buffer_address;
+
+    while (1) {
+        sem_recv.acquire();
+        while (1) {
+            /* (1) Retrieve the receive buffer location controlled by the  descriptor. */
+            ret = R_ETHER_Read_ZC2(_channel, (void **)&pread_buffer_address);
+            if (ret <= ETHER_NO_DATA) {
+                break;
+            }
+
+            /* When there is data to receive */
+            while (1) {
+                buf = memory_manager->alloc_heap(ret, 0);
+                if (buf != NULL) {
+                    /* (2) Copy the data read from the receive buffer which is controlled by the descriptor to
+                     the buffer which is specified by the user (up to 1024 bytes). */
+                    memcpy(memory_manager->get_ptr(buf), pread_buffer_address, (uint32_t)memory_manager->get_len(buf));
+
+                    /* (3) Read the receive data from the receive buffer controlled by the descriptor,
+                     and then release the receive buffer. */
+                    R_ETHER_Read_ZC2_BufRelease(_channel);
+
+                    emac_link_input_cb(buf);
+                    break;
+                }
+                osDelay(5);
+            }
+        }
+    }
+}
+
+void RZ_A2_EMAC::phy_task(void)
+{
+    R_ETHER_LinkProcess(_channel);
+}
+

connectivity/drivers/emac/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.h

@@ -0,0 +1,172 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef RZ_A2_EMAC_H
+#define RZ_A2_EMAC_H
+
+#include "EMAC.h"
+#include "rtos/Thread.h"
+#include "rtos/Semaphore.h"
+
+class RZ_A2_EMAC : public EMAC {
+public:
+    RZ_A2_EMAC(uint32_t channel);
+
+    static RZ_A2_EMAC &get_instance(uint32_t channel);
+
+    /**
+     * Return maximum transmission unit
+     *
+     * @return     MTU in bytes
+     */
+    virtual uint32_t get_mtu_size() const;
+
+    /**
+     * Gets memory buffer alignment preference
+     *
+     * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not
+     * align link out memory buffer chains using the alignment.
+     *
+     * @return         Memory alignment requirement in bytes
+     */
+    virtual uint32_t get_align_preference() const;
+
+    /**
+     * Return interface name
+     *
+     * @param name Pointer to where the name should be written
+     * @param size Maximum number of character to copy
+     */
+    virtual void get_ifname(char *name, uint8_t size) const;
+
+    /**
+     * Returns size of the underlying interface HW address size.
+     *
+     * @return     HW address size in bytes
+     */
+    virtual uint8_t get_hwaddr_size() const;
+
+    /**
+     * Return interface-supplied HW address
+     *
+     * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size
+     *
+     * HW address need not be provided if this interface does not have its own HW
+     * address configuration; stack will choose address from central system
+     * configuration if the function returns false and does not write to addr.
+     *
+     * @param addr HW address for underlying interface
+     * @return     true if HW address is available
+     */
+    virtual bool get_hwaddr(uint8_t *addr) const;
+
+    /**
+     * Set HW address for interface
+     *
+     * Provided address has to be of correct size, see @a get_hwaddr_size
+     *
+     * Called to set the MAC address to actually use - if @a get_hwaddr is provided
+     * the stack would normally use that, but it could be overridden, eg for test
+     * purposes.
+     *
+     * @param addr Address to be set
+     */
+    virtual void set_hwaddr(const uint8_t *addr);
+
+    /**
+     * Sends the packet over the link
+     *
+     * That can not be called from an interrupt context.
+     *
+     * @param buf  Packet to be send
+     * @return     True if the packet was send successfully, False otherwise
+     */
+    virtual bool link_out(emac_mem_buf_t *buf);
+
+    /**
+     * Initializes the HW
+     *
+     * @return True on success, False in case of an error.
+     */
+    virtual bool power_up();
+
+    /**
+     * Deinitializes the HW
+     *
+     */
+    virtual void power_down();
+
+    /**
+     * Sets a callback that needs to be called for packets received for that interface
+     *
+     * @param input_cb Function to be register as a callback
+     */
+    virtual void set_link_input_cb(emac_link_input_cb_t input_cb);
+
+    /**
+     * Sets a callback that needs to be called on link status changes for given interface
+     *
+     * @param state_cb Function to be register as a callback
+     */
+    virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb);
+
+    /** Add device to a multicast group
+     *
+     * @param address  A multicast group hardware address
+     */
+    virtual void add_multicast_group(const uint8_t *address);
+
+    /** Remove device from a multicast group
+     *
+     * @param address  A multicast group hardware address
+     */
+    virtual void remove_multicast_group(const uint8_t *address);
+
+    /** Request reception of all multicast packets
+     *
+     * @param all True to receive all multicasts
+     *            False to receive only multicasts addressed to specified groups
+     */
+    virtual void set_all_multicast(bool all);
+
+    /** Sets memory manager that is used to handle memory buffers
+     *
+     * @param mem_mngr Pointer to memory manager
+     */
+    virtual void set_memory_manager(EMACMemoryManager &mem_mngr);
+
+private:
+    EMACMemoryManager *memory_manager; /**< Memory manager */
+    uint32_t _channel;
+    uint8_t hwaddr[6];
+    bool hwaddr_set;
+    bool power_on;
+    emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */
+    emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */
+    rtos::Thread recvThread;
+    int phy_task_handle; /**< Handle for phy task event */
+    rtos::Semaphore sem_recv;
+
+    static void _callback_pcb(void *);
+    static void _callback_hnd(void *);
+    void callback_pcb(void *);
+    void callback_hnd(void *);
+    void recv_task(void);
+    void phy_task(void);
+};
+
+#endif /* RZ_A2_EMAC_H */

connectivity/libraries/ppp/mbed_lib.json

@@ -33,7 +33,10 @@
         }
     },
     "target_overrides": {
-        "RZ_A1_EMAC": {
+        "RZ_A1XX": {
+            "thread-stacksize": 896
+        },
+        "RZ_A2XX": {
             "thread-stacksize": 896
         },
         "CY8CPROTO_062_4343W": {

connectivity/lwipstack/lwip/src/core/lwip_dns.c

@@ -491,7 +491,9 @@ dns_get_interface_server(u8_t numdns, const char *interface_name)
   if (numdns >= DNS_MAX_SERVERS) {
     return IP_ADDR_ANY;
   }
-
+  if (interface_name == NULL) {
+    return IP_ADDR_ANY;
+  }
   for (interface_server = multihoming_dns_servers; interface_server != NULL; interface_server = interface_server->next) {
     if (!strcmp(interface_name, interface_server->interface_name)) {
       return &interface_server->dns_servers[numdns];

connectivity/lwipstack/mbed_lib.json

@@ -174,7 +174,17 @@
         "EFM32GG11_STK3701": {
             "mem-size": 36560
         },
-        "RZ_A1_EMAC": {
+        "RZ_A1XX": {
+            "tcpip-thread-stacksize": 1328,
+            "default-thread-stacksize": 640,
+            "memp-num-tcp-seg": 32,
+            "tcp-mss": 1440,
+            "tcp-snd-buf": "(8 * TCP_MSS)",
+            "tcp-wnd": "(TCP_MSS * 8)",
+            "pbuf-pool-size": 16,
+            "mem-size": 51200
+        },
+        "RZ_A2XX": {
             "tcpip-thread-stacksize": 1328,
             "default-thread-stacksize": 640,
             "memp-num-tcp-seg": 32,

targets/TARGET_RENESAS/TARGET_RZ_A2XX/PeripheralPins.h

@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+typedef struct {
+    PinName pin;
+    int function;
+    int pm;
+} PinFunc;
+
+/************IRQ***************/
+extern const PinMap PinMap_IRQ[];
+
+/************PINMAP***************/
+extern const PinFunc PIPC_0_tbl[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************DAC***************/
+extern const PinMap PinMap_DAC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************CAN***************/
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralNames.h

@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART0,
+    UART1,
+    UART2,
+    UART3,
+    UART4,
+} UARTName;
+
+typedef enum {
+    PWM_GTIOC0A = 0,
+    PWM_GTIOC0B,
+    PWM_GTIOC1A,
+    PWM_GTIOC1B,
+    PWM_GTIOC2A,
+    PWM_GTIOC2B,
+    PWM_GTIOC3A,
+    PWM_GTIOC3B,
+    PWM_GTIOC4A,
+    PWM_GTIOC4B,
+    PWM_GTIOC5A,
+    PWM_GTIOC5B,
+    PWM_GTIOC6A,
+    PWM_GTIOC6B,
+    PWM_GTIOC7A,
+    PWM_GTIOC7B,
+
+    PWM_TIOC0A = 0x100,
+    PWM_TIOC0C,
+    PWM_TIOC1A,
+    PWM_TIOC2A,
+    PWM_TIOC3A,
+    PWM_TIOC3C,
+    PWM_TIOC4A,
+    PWM_TIOC4C,
+} PWMName;
+
+typedef enum {
+    AN0 = 0,
+    AN1 = 1,
+    AN2 = 2,
+    AN3 = 3,
+    AN4 = 4,
+    AN5 = 5,
+    AN6 = 6,
+    AN7 = 7,
+} ADCName;
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1,
+    SPI_2,
+    SPI_3,
+    SPI_4,
+} SPIName;
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1,
+    I2C_2,
+    I2C_3,
+} I2CName;
+
+typedef enum {
+    CAN_0 = 0,
+    CAN_1,
+    CAN_2,
+    CAN_3,
+    CAN_4,
+} CANName;
+
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART4
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralPins.c

@@ -0,0 +1,212 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+//#define ISEL_BIT    (0x40)  // use interrupt
+
+/************IRQ***************/
+enum {
+    IRQ0, IRQ1,
+    IRQ2, IRQ3,
+    IRQ4, IRQ5,
+    IRQ6, IRQ7,
+} IRQNo;
+
+const PinMap PinMap_IRQ[] = {
+    {P6_2,  IRQ0,   6}, {PL_4,  IRQ0,   5}, {PD_0,  IRQ0,   2},
+    {PJ_6,  IRQ0,   5}, {PJ_1,  IRQ0,   6}, {P5_4,  IRQ0,   2},
+    {P1_0,  IRQ0,   3}, {P4_0,  IRQ0,   6}, {PC_5,  IRQ0,   6},
+    {PF_4,  IRQ1,   6}, {PE_1,  IRQ1,   6}, {PD_1,  IRQ1,   2},
+    {PF_7,  IRQ1,   5}, {P1_1,  IRQ1,   3}, {PC_4,  IRQ1,   6},
+    {P5_5,  IRQ1,   2}, {P4_1,  IRQ1,   6}, {P8_2,  IRQ2,   5},
+    {PH_1,  IRQ2,   6}, {PD_2,  IRQ2,   2}, {PH_4,  IRQ2,   6},
+    {P1_2,  IRQ2,   3}, {P5_6,  IRQ2,   2}, {PC_0,  IRQ2,   5},
+    {P4_2,  IRQ2,   6},
+    {PH_0,  IRQ3,   6}, {PD_3,  IRQ3,   2}, {P8_1,  IRQ3,   5},
+    {PH_3,  IRQ3,   6}, {P4_3,  IRQ3,   6}, {P5_7,  IRQ3,   2},
+    {P3_0,  IRQ3,   5}, {P1_3,  IRQ3,   3},
+    {PL_0,  IRQ4,   5}, {PF_1,  IRQ4,   6}, {PD_4,  IRQ4,   2},
+    {PG_2,  IRQ4,   6}, {PH_6,  IRQ4,   5}, {PJ_5,  IRQ4,   6},
+    {P1_4,  IRQ4,   3}, {P5_0,  IRQ4,   2},
+    {PL_1,  IRQ5,   5}, {PA_5,  IRQ5,   6}, {PK_2,  IRQ5,   6},
+    {PD_5,  IRQ5,   2}, {PH_5,  IRQ5,   5}, {PG_6,  IRQ5,   6},
+    {P2_0,  IRQ5,   3}, {P5_1,  IRQ5,   2},
+    {PL_2,  IRQ6,   5}, {PA_1,  IRQ6,   6}, {PD_6,  IRQ6,   2},
+    {PK_4,  IRQ6,   6}, {P3_1,  IRQ6,   6}, {P5_2,  IRQ6,   2},
+    {PC_7,  IRQ6,   6}, {P2_1,  IRQ6,   3},
+    {PL_3,  IRQ7,   5}, {PD_7,  IRQ7,   2}, {P3_3,  IRQ7,   6},
+    {P2_2,  IRQ7,   3}, {PC_6,  IRQ7,   6}, {P5_3,  IRQ7,   2},
+    {NC,    NC,     0}
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P5_0,  AN0,    1},
+    {P5_1,  AN1,    1},
+    {P5_2,  AN2,    1},
+    {P5_3,  AN3,    1},
+    {P5_4,  AN4,    1},
+    {P5_5,  AN5,    1},
+    {P5_6,  AN6,    1},
+    {P5_7,  AN7,    1},
+    {NC,    NC,     0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {PD_1,  I2C_0,  1},
+    {PD_3,  I2C_1,  1},
+    {PD_5,  I2C_2,  1},
+    {PD_7,  I2C_3,  1},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PD_0,  I2C_0,  1},
+    {PD_2,  I2C_1,  1},
+    {PD_4,  I2C_2,  1},
+    {PD_6,  I2C_3,  1},
+    {NC,    NC,     0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P8_5,  UART0,  5},
+    {P4_2,  UART0,  1},
+    {P7_3,  UART1,  4},
+    {PJ_2,  UART1,  4},
+    {PF_5,  UART2,  1},
+    {PE_2,  UART2,  3},
+    {P6_3,  UART3,  3},
+    {PF_2,  UART3,  1},
+    {P9_0,  UART4,  4},
+    {P4_6,  UART4,  4},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P7_7,  UART0,  5},
+    {P4_1,  UART0,  1},
+    {P7_1,  UART1,  4},
+    {PJ_1,  UART1,  4},
+    {PF_4,  UART2,  1},
+    {PE_1,  UART2,  3},
+    {P6_2,  UART3,  3},
+    {PF_1,  UART3,  1},
+    {P9_1,  UART4,  4},
+    {P4_5,  UART4,  4},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PB_3,  UART0,  5},
+    {P4_4,  UART0,  1},
+    {P7_5,  UART1,  4},
+    {PJ_4,  UART1,  4},
+    {PH_2,  UART2,  1},
+    {PH_4,  UART2,  2},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PB_4,  UART0,  5},
+    {P4_3,  UART0,  1},
+    {P7_4,  UART1,  4},
+    {PJ_3,  UART1,  4},
+    {PF_6,  UART2,  1},
+    {PH_3,  UART2,  2},
+    {NC,    NC,     0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P8_7,  SPI_0,  4},
+    {PG_0,  SPI_0,  3},
+    {PK_2,  SPI_0,  5},
+    {PF_0,  SPI_1,  5},
+    {PG_4,  SPI_1,  3},
+    {P3_1,  SPI_2,  5},
+    {PC_0,  SPI_2,  4},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P8_6,  SPI_0,  4},
+    {PK_3,  SPI_0,  5},
+    {PG_1,  SPI_0,  3},
+    {PF_1,  SPI_1,  5},
+    {PG_5,  SPI_1,  3},
+    {P3_2,  SPI_2,  5},
+    {PC_1,  SPI_2,  4},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P8_5,  SPI_0,  4},
+    {PG_2,  SPI_0,  3},
+    {PK_4,  SPI_0,  5},
+    {PF_2,  SPI_1,  5},
+    {PG_6,  SPI_1,  3},
+    {PC_2,  SPI_2,  4},
+    {P3_3,  SPI_2,  5},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P8_4,  SPI_0,  4},
+    {PG_3,  SPI_0,  3},
+    {P3_5,  SPI_0,  5},
+    {PF_3,  SPI_1,  5},
+    {PG_7,  SPI_1,  3},
+    {P3_4,  SPI_2,  5},
+    {PC_3,  SPI_2,  4},
+    {NC,    NC,     0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {PG_2,  PWM_GTIOC0A, 5},
+    {PG_3,  PWM_GTIOC0B, 5},
+    {PG_4,  PWM_GTIOC1A, 5},
+    {PG_5,  PWM_GTIOC1B, 5},
+    {PG_6,  PWM_GTIOC2A, 5},
+    {PG_7,  PWM_GTIOC2B, 5},
+    {P8_3,  PWM_GTIOC3A, 5},
+    {P7_6,  PWM_GTIOC3A, 4},
+    {P7_7,  PWM_GTIOC3B, 4},
+    {P0_0,  PWM_GTIOC3B, 5},
+    {PH_0,  PWM_GTIOC4A, 3},
+    {P0_1,  PWM_GTIOC4A, 5},
+    {PH_1,  PWM_GTIOC4B, 3},
+    {P0_2,  PWM_GTIOC4B, 5},
+    {P8_2,  PWM_GTIOC5A, 4},
+    {P8_1,  PWM_GTIOC5B, 4},
+    {PH_3,  PWM_GTIOC6A, 3},
+    {P0_3,  PWM_GTIOC6A, 5},
+    {P2_0,  PWM_GTIOC6A, 2},
+    {PH_4,  PWM_GTIOC6B, 3},
+    {P0_4,  PWM_GTIOC6B, 5},
+    {P2_1,  PWM_GTIOC6B, 2},
+    {P0_5,  PWM_GTIOC7A, 5},
+    {P2_2,  PWM_GTIOC7A, 2},
+    {P0_6,  PWM_GTIOC7B, 5},
+    {P2_3,  PWM_GTIOC7B, 2},
+    {NC,    NC,     0}
+};
+

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PinNames.h

@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  4
+
+typedef enum {
+    P0_0 = 0x0000, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6,
+    P1_0 = 0x0010, P1_1, P1_2, P1_3, P1_4,
+    P2_0 = 0x0020, P2_1, P2_2, P2_3,
+    P3_0 = 0x0030, P3_1, P3_2, P3_3, P3_4, P3_5,
+    P4_0 = 0x0040, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
+    P5_0 = 0x0050, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7,
+    P6_0 = 0x0060, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7,
+    P7_0 = 0x0070, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7,
+    P8_0 = 0x0080, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7,
+    P9_0 = 0x0090, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7,
+    PA_0 = 0x00A0, PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7,
+    PB_0 = 0x00B0, PB_1, PB_2, PB_3, PB_4, PB_5,
+    PC_0 = 0x00C0, PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7,
+    PD_0 = 0x00D0, PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7,
+    PE_0 = 0x00E0, PE_1, PE_2, PE_3, PE_4, PE_5, PE_6,
+    PF_0 = 0x00F0, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7,
+    PG_0 = 0x0100, PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7,
+    PH_0 = 0x0110, PH_1, PH_2, PH_3, PH_4, PH_5, PH_6,
+    PJ_0 = 0x0120, PJ_1, PJ_2, PJ_3, PJ_4, PJ_5, PJ_6, PJ_7,
+    PK_0 = 0x0130, PK_1, PK_2, PK_3, PK_4, PK_5,
+    PL_0 = 0x0140, PL_1, PL_2, PL_3, PL_4,
+    JP0_0 = 0x0150, JP0_1,
+
+    NMI = 0x0700,
+
+    // mbed Pin Names
+    LED1 = P0_1,
+    LED2 = P0_3,
+    LED3 = P0_5,
+    LED4 = P8_2,
+
+    LED_GREEN  = LED1,
+    LED_YELLOW = LED2,
+    LED_ORANGE = LED3,
+    LED_RED    = LED4,
+
+    USBTX = P9_0,
+    USBRX = P9_1,
+
+    A0 = P5_0,
+    A1 = P5_1,
+    A2 = P5_2,
+    A3 = P5_3,
+    A4 = P5_4,
+    A5 = P5_5,
+    A6 = P5_6,
+    A7 = P5_7,
+
+    I2C_SCL = PD_2,
+    I2C_SDA = PD_3,
+
+    USER_BUTTON0 = PD_6,
+    USER_BUTTON1 = PD_7,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON0,
+
+    // Raspberry Pi Pin Names
+    SPI_MOSI = P8_6,
+    SPI_MISO = P8_5,
+    SPI_SCKL = P8_7,
+    SPI_SSL  = P8_4,
+
+    UART_TXD = P4_2,
+    UART_RXD = P4_1,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown = 3,
+    PullNone = 2,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0xff)
+#define PINNO(pin) ((pin)&0x0f)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PortNames.h

@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3,
+    Port4 = 4,
+    Port5 = 5,
+    Port6 = 6,
+    Port7 = 7,
+    Port8 = 8,
+    Port9 = 9,
+    PortA = 10,
+    PortB = 11,
+    PortC = 12,
+    PortD = 13,
+    PortE = 14,
+    PortF = 15,
+    PortG = 16,
+    PortH = 17,
+    PortJ = 18,
+    PortK = 19,
+    PortL = 20,
+    PortM = 21  /* PortM = JP0 */
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/TARGET_MBED_MBRZA2M/reserved_pins.h

@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef RESERVED_PINS_H
+#define RESERVED_PINS_H
+
+#define TARGET_RESERVED_PINS {}
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device.h

@@ -0,0 +1,44 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+#define TRANSACTION_QUEUE_SIZE_SPI 16
+
+
+
+
+
+#define DEVICE_ID_LENGTH            32
+#define DEVICE_MAC_OFFSET           20
+
+
+
+
+
+#include "objects.h"
+#include "dma_api.h"
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/MBRZA2M.h

@@ -0,0 +1,16 @@
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RZ_A2M.h"

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/RZ_A2_Init.c

@@ -0,0 +1,168 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2012-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**************************************************************************//**
+* @file         RZ_A2_Init.c
+* $Rev: 624 $
+* $Date:: 2013-04-24 13:37:48 +0900#$
+* @brief        RZ_A2 Initialize
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA2M.h"
+#include "RZ_A2_Init.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: RZ_A2_SetSramWriteEnable
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Set SRAM write enable
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A2_SetSramWriteEnable(void)
+{
+    /* Enable SRAM write access */
+    CPG.SYSCR3.BYTE = 0x0F;
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A2_InitClock
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Initialize Clock
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A2_InitClock(void)
+{
+    /* WARNING:                                                                */
+    /* The section area for the .data data or the .bss data is not initialized */
+    /* because this function is called by the Peripheral_BasicInit             */
+    /* function. Do not use the variables allocated to the section area        */
+    /* for the .data or the .bss data within this function and the user-       */
+    /* defined function called by this function.                               */
+
+    volatile uint32_t dummy_buf_32b;
+
+    /* standby_mode_en bit of Power Control Register setting */
+    pl310.REG15_POWER_CTRL.BIT.standby_mode_en = 1;
+    dummy_buf_32b = pl310.REG15_POWER_CTRL.LONG;
+    (void)dummy_buf_32b;
+
+    /* ==== CPG Settings ==== */
+    CPG.FRQCR.WORD  = 0x1012u;  /* PLL(x88), I:G:B:P1:P0 = 22:11:5.5:2.75:1.375 */
+    /* CKIO:Output at time usually,                 */
+    /* Output when bus right is opened,             */
+    /* output at standby"L"                         */
+    /* Clockin  = 24MHz,                            */
+    /* I  Clock = 528MHz,                           */
+    /* G  Clock = 264MHz                            */
+    /* B  Clock = 132MHz,                           */
+    /* P1 Clock = 66MHz,                            */
+    /* P0 Clock = 33MHz                             */
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A2_IsClockMode0
+* @brief         Query Clock Mode
+*
+*                Description:<br>
+*                Answer ClockMode0 or not
+* @param         none
+* @retval        true  : clock mode 0
+* @retval        false : clock mode 1
+******************************************************************************/
+int RZ_A2_IsClockMode0(void)
+{
+    /* ClockMode0 */
+    return true;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A2_InitBus
+* @brief         Initialize Bus
+*
+*                Description:<br>
+*                Initialize Pin Setting
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A2_InitBus(void)
+{
+    /*************************************************************************/
+    /* If need Pin Setting before run program, the setting will be wrote here*/
+    /*************************************************************************/
+
+    pin_function(P6_5, 4); // AUDIO_XOUT
+
+    return;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct

@@ -0,0 +1,139 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017-2020 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; Copyright (c) 2017-2020 Arm Lmimited.
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+
+#define __RAM_BASE       0x80000000
+#define __RAM_SIZE       0x00400000
+#define __NV_RAM_BASE    0x80000000
+#define __NV_RAM_SIZE    0x00020000
+#define __TTB_BASE       (__NV_RAM_BASE + __NV_RAM_SIZE)
+#define __TTB_SIZE       (0x4000 + 0x1000)
+#define __APP_RAM_START  (__TTB_BASE + __TTB_SIZE)
+
+#define __OCTARAM_BASE   0x60000000
+#define __OCTARAM_SIZE   0x00800000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE     (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x50000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x1000000
+#endif
+
+#if (MBED_APP_START == 0x50000000)
+  #define BOOT_LOADER_SIZE  (0x00004000)
+#else
+  #define BOOT_LOADER_SIZE  (0x00000000)
+#endif
+
+LOAD_TTB    __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+
+    TTB_L2  +0 EMPTY 0x1000            
+    { }                           ; Level-2 Translation Table for MMU
+}
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE       ; load region size_region
+{
+#if (BOOT_LOADER_SIZE != 0x00000000)
+  BOOT_LOADER_BEGIN MBED_APP_START FIXED
+  {
+    * (BOOT_LOADER)
+  }
+
+  VECTORS (MBED_APP_START + 0x4000) FIXED
+  {
+    * (RESET, +FIRST)         ; Vector table and other startup code
+    * (InRoot$$Sections)      ; All (library) code that must be in a root region
+    * (+RO-CODE)              ; Application RO code (.text)
+  }
+#else
+  VECTORS MBED_APP_START FIXED
+  {
+    * (RESET, +FIRST)         ; Vector table and other startup code
+    * (InRoot$$Sections)      ; All (library) code that must be in a root region
+    * (+RO-CODE)              ; Application RO code (.text)
+  }
+#endif
+
+  RO_DATA    +0
+  { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+  NV      __NV_RAM_BASE UNINIT __NV_RAM_SIZE   ; Page 0 of On-Chip Data Retention RAM
+  { * (.bss.NoInit) }           ; Application RW data Non volatile area
+
+  RAM_CODE   __APP_RAM_START
+  { * (RAM_CODE) }              ; Application RAM_CODE
+
+  RW_DATA     +0 ALIGN 0x8
+  { * (+RW) }                   ; Application RW data (.data)
+
+  RW_IRAM1    +0 ALIGN 0x10
+  { * (+ZI) }                   ; Application ZI data (.bss)
+
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; RAM-NC : Internal non-cached RAM region
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  RW_DATA_NC +0 ALIGN 0x1000
+  { * (NC_DATA) }              ; Application RW data Non cached area
+
+  ZI_DATA_NC +0
+  { * (NC_BSS) }               ; Application ZI data Non cached area
+
+  MEMORY_ADJUST +0 ALIGN 0x1000
+  { }
+
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; Heap and Stack
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  ARM_LIB_HEAP  +0 EMPTY (__RAM_SIZE - (ImageLimit(MEMORY_ADJUST) - __RAM_BASE) - __STACK_SIZE)
+  { }
+
+  ARM_LIB_STACK (__RAM_BASE + __RAM_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }
+
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; RAM-OCTA : OctaRAM region
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  RW_DATA_OCTA __OCTARAM_BASE __OCTARAM_SIZE
+  { * (OCTA_DATA) }              ; Application RW data OctaRAM
+
+  ZI_DATA_OCTA +0
+  { * (OCTA_BSS) }               ; Application ZI data OctaRAM
+
+}
+

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/startup_RZ_A2M.S

@@ -0,0 +1,151 @@
+;/******************************************************************************
+; * @file     startup_RZ_A1H.S
+; * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2020 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+__UND_STACK_SIZE   EQU      0x00000100
+__SVC_STACK_SIZE   EQU      0x00008000
+__ABT_STACK_SIZE   EQU      0x00000100
+__FIQ_STACK_SIZE   EQU      0x00000100
+__IRQ_STACK_SIZE   EQU      0x0000F000
+
+USR_MODE           EQU      0x10            ; User mode
+FIQ_MODE           EQU      0x11            ; Fast Interrupt Request mode
+IRQ_MODE           EQU      0x12            ; Interrupt Request mode
+SVC_MODE           EQU      0x13            ; Supervisor mode
+ABT_MODE           EQU      0x17            ; Abort mode
+UND_MODE           EQU      0x1B            ; Undefined Instruction mode
+SYS_MODE           EQU      0x1F            ; System mode
+
+
+                PRESERVE8
+                ARM
+
+                AREA    RESET, CODE, READONLY
+
+Vectors         PROC
+                EXPORT  Vectors
+                IMPORT  Undef_Handler
+                IMPORT  SVC_Handler
+                IMPORT  PAbt_Handler
+                IMPORT  DAbt_Handler
+                IMPORT  IRQ_Handler
+                IMPORT  FIQ_Handler
+
+                LDR    PC, =Reset_Handler
+                LDR    PC, =Undef_Handler
+                LDR    PC, =SVC_Handler
+                LDR    PC, =PAbt_Handler
+                LDR    PC, =DAbt_Handler
+                NOP
+                LDR    PC, =IRQ_Handler
+                LDR    PC, =FIQ_Handler
+
+                ENDP
+
+
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler
+                IMPORT  SystemInit
+                IMPORT  __main
+
+
+                ; Mask interrupts
+                CPSID   if                           
+
+                ; Put any cores other than 0 to sleep
+                MRC     p15, 0, R0, c0, c0, 5       ; Read MPIDR
+                ANDS    R0, R0, #3
+goToSleep
+                WFINE
+                BNE     goToSleep
+
+                ; Reset SCTLR Settings
+                MRC     p15, 0, R0, c1, c0, 0       ; Read CP15 System Control register
+                BIC     R0, R0, #(0x1 << 12)        ; Clear I bit 12 to disable I Cache
+                BIC     R0, R0, #(0x1 <<  2)        ; Clear C bit  2 to disable D Cache
+                BIC     R0, R0, #0x1                ; Clear M bit  0 to disable MMU
+                BIC     R0, R0, #(0x1 << 11)        ; Clear Z bit 11 to disable branch prediction
+                BIC     R0, R0, #(0x1 << 13)        ; Clear V bit 13 to disable hivecs
+                MCR     p15, 0, R0, c1, c0, 0       ; Write value back to CP15 System Control register
+                ISB
+
+                ; Configure ACTLR
+                MRC     p15, 0, r0, c1, c0, 1       ; Read CP15 Auxiliary Control Register
+                ORR     r0, r0, #(1 <<  1)          ; Enable L2 prefetch hint (UNK/WI since r4p1)
+                MCR     p15, 0, r0, c1, c0, 1       ; Write CP15 Auxiliary Control Register
+
+                ; Set Vector Base Address Register (VBAR) to point to this application's vector table
+                LDR    R0, =Vectors
+                MCR    p15, 0, R0, c12, c0, 0
+
+                ; Setup Stack for each exceptional mode
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+                LDR    R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+                ;Enter Undefined Instruction Mode and set its Stack Pointer 
+                CPS    #UND_MODE
+                MOV    SP, R0
+                SUB    R0, R0, #__UND_STACK_SIZE
+
+                ; Enter Abort Mode and set its Stack Pointer 
+                CPS    #ABT_MODE
+                MOV    SP, R0
+                SUB    R0, R0, #__ABT_STACK_SIZE
+
+                ; Enter FIQ Mode and set its Stack Pointer 
+                CPS    #FIQ_MODE
+                MOV    SP, R0
+                SUB    R0, R0, #__FIQ_STACK_SIZE
+
+                ; Enter IRQ Mode and set its Stack Pointer 
+                CPS    #IRQ_MODE
+                MOV    SP, R0
+                SUB    R0, R0, #__IRQ_STACK_SIZE
+
+                ; Enter Supervisor Mode and set its Stack Pointer 
+                CPS    #SVC_MODE
+                MOV    SP, R0
+                SUB    R0, R0, #__SVC_STACK_SIZE
+
+                ; Enter System Mode to complete initialization and enter kernel 
+                CPS    #SYS_MODE
+                MOV    SP, R0
+
+                ; Call SystemInit
+                IMPORT SystemInit
+                BL     SystemInit
+
+                ; Unmask interrupts
+                CPSIE  if
+
+                ; Call __main
+                IMPORT __main
+                BL     __main
+
+                ENDP
+
+                END

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/weak_handler.S

@@ -0,0 +1,91 @@
+;/*
+; * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-A Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+MODE_SVC        EQU      0x13
+
+                PRESERVE8
+                THUMB
+
+                AREA     |.text|, CODE, READONLY
+
+IRQ_Handler     PROC
+                EXPORT  IRQ_Handler [WEAK]
+
+                IMPORT  IRQ_GetActiveIRQ
+                IMPORT  IRQ_GetHandler
+                IMPORT  IRQ_EndOfInterrupt
+
+                SUB     LR, LR, #4                  ; Pre-adjust LR
+                SRSFD   SP!, #MODE_SVC              ; Save LR_irq and SPSR_irq on to the SVC stack
+                CPS     #MODE_SVC                   ; Change to SVC mode
+                PUSH    {R0-R3, R12, LR}            ; Save APCS corruptible registers
+
+                MOV     R3, SP                      ; Move SP into R3
+                AND     R3, R3, #4                  ; Get stack adjustment to ensure 8-byte alignment
+                SUB     SP, SP, R3                  ; Adjust stack
+                PUSH    {R3, R4}                    ; Store stack adjustment(R3) and user data(R4)
+
+                BLX     IRQ_GetActiveIRQ            ; Retrieve interrupt ID into R0
+                MOV     R4, R0                      ; Move interrupt ID to R4
+
+                BLX     IRQ_GetHandler              ; Retrieve interrupt handler address for current ID
+                CMP     R0, #0                      ; Check if handler address is 0
+                BEQ     IRQ_End                     ; If 0, end interrupt and return
+
+                CPSIE   i                           ; Re-enable interrupts
+                BLX     R0                          ; Call IRQ handler
+                CPSID   i                           ; Disable interrupts
+
+IRQ_End
+                MOV     R0, R4                      ; Move interrupt ID to R0
+                BLX     IRQ_EndOfInterrupt          ; Signal end of interrupt
+
+                POP     {R3, R4}                    ; Restore stack adjustment(R3) and user data(R4)
+                ADD     SP, SP, R3                  ; Unadjust stack
+
+                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers
+                RFEFD   SP!                         ; Return from IRQ handler
+
+                ENDP
+
+
+Default_Handler PROC
+                EXPORT  Undef_Handler             [WEAK]
+                EXPORT  SVC_Handler               [WEAK]
+                EXPORT  PAbt_Handler              [WEAK]
+                EXPORT  DAbt_Handler              [WEAK]
+                EXPORT  FIQ_Handler               [WEAK]
+
+Undef_Handler
+SVC_Handler
+PAbt_Handler
+DAbt_Handler
+FIQ_Handler
+
+                B       .
+
+                ENDP
+
+                END

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/RZA2M.ld

@@ -0,0 +1,283 @@
+/* Linker script for mbed RZ_A2M */
+
+/* Linker script to configure memory regions. */
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x50000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x1000000
+#endif
+
+#define BOOT_LOADER_ADDR    (MBED_APP_START)
+#if (MBED_APP_START == 0x50000000)
+  #define BOOT_LOADER_SIZE  (0x00004000)
+#else
+  #define BOOT_LOADER_SIZE  (0x00000000)
+#endif
+
+#define ROM_ADDR            (MBED_APP_START + BOOT_LOADER_SIZE)
+#define ROM_SIZE            (MBED_APP_SIZE - BOOT_LOADER_SIZE)
+
+MEMORY
+{
+  BOOT_LOADER (rx) : ORIGIN = BOOT_LOADER_ADDR, LENGTH = BOOT_LOADER_SIZE
+  ROM (rx)         : ORIGIN = ROM_ADDR,         LENGTH = ROM_SIZE
+  RAM_NV (rwx)     : ORIGIN = 0x80000000,       LENGTH = 0x00020000
+  L_TTB (rw)       : ORIGIN = 0x80020000,       LENGTH = 0x00005000
+  RAM (rwx)        : ORIGIN = 0x80025000,       LENGTH = 0x003DB000
+  RAM_OCTA (rwx)   : ORIGIN = 0x60000000,       LENGTH = 0x00800000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+#if (BOOT_LOADER_SIZE != 0x00000000)
+    .boot :
+    {
+        KEEP(*(.boot_loader)) 
+    } > BOOT_LOADER 
+#endif
+
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+
+        KEEP(*(.isr_vector))
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        Image$$VECTORS$$Limit = .;
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+
+        __etext = .;
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+    .copy.table :
+    {
+        . = ALIGN(8);
+        __copy_table_start__ = .;
+        LONG (LOADADDR(.data))
+        LONG (ADDR(.data))
+        LONG (SIZEOF(.data))
+        LONG (LOADADDR(.nc_data))
+        LONG (ADDR(.nc_data))
+        LONG (SIZEOF(.nc_data))
+        LONG (LOADADDR(.octa_data))
+        LONG (ADDR(.octa_data))
+        LONG (SIZEOF(.octa_data))
+        LONG (LOADADDR(.ram_code))
+        LONG (ADDR(.ram_code))
+        LONG (SIZEOF(.ram_code))
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(8);
+        __zero_table_start__ = .;
+        LONG (ADDR(.bss))
+        LONG (SIZEOF(.bss))
+        LONG (ADDR(.nc_bss))
+        LONG (SIZEOF(.nc_bss))
+        LONG (ADDR(.octa_bss))
+        LONG (SIZEOF(.octa_bss))
+        __zero_table_end__ = .;
+    } > ROM
+
+    .nv_data (NOLOAD) :
+    {
+        *(NV_DATA)
+    } > RAM_NV
+
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += 0x00004000;
+        Image$$TTB$$ZI$$Limit = .;
+        Image$$TTB_L2$$ZI$$Base = .;
+        . += 0x00001000;
+        Image$$TTB_L2$$ZI$$Limit = .;
+    } > L_TTB
+
+    .ram_code : ALIGN( 0x8 ) {
+        *(RAM_CODE)
+        *(RAM_CONST)
+        . = ALIGN( 0x8 );
+    } > RAM AT > ROM
+    Load$$SEC_RAM_CODE$$Base    = LOADADDR(.ram_code);
+    Image$$SEC_RAM_CODE$$Base   = ADDR(.ram_code);
+    Load$$SEC_RAM_CODE$$Length  = SIZEOF(.ram_code);
+
+    .data :
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(8);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(8);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+        . = ALIGN(8);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(8);
+        /* All data end */
+        __data_end__ = .;
+    } > RAM AT > ROM
+
+    .bss ALIGN(0x10):
+    {
+        Image$$RW_IRAM1$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$RW_IRAM1$$Limit = .;
+    } > RAM
+
+    .memory_adjust (NOLOAD):
+    {
+        . = ALIGN(0x1000);
+    } > RAM
+
+    .nc_data :
+    {
+        Image$$RW_DATA_NC$$Base = .;
+        *(NC_DATA)
+        Image$$RW_DATA_NC$$Limit = .;
+    } > RAM AT > ROM
+
+    .nc_bss (NOLOAD) :
+    {
+        Image$$ZI_DATA_NC$$Base = .;
+        *(NC_BSS)
+        Image$$ZI_DATA_NC$$Limit = .;
+    } > RAM
+
+    .heap ALIGN(0x1000):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    __HeapLimit = __StackLimit;
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+    /* OctaRAM */
+    .octa_data :
+    {
+        Image$$RW_DATA_OCTA$$Base = .;
+        *(OCTA_DATA)
+
+        . = ALIGN(8);
+        Image$$RW_DATA_OCTA$$Limit = .;
+    } > RAM_OCTA AT > ROM
+
+    .octa_bss (NOLOAD) :
+    {
+        Image$$ZI_DATA_OCTA$$Base = .;
+
+        *(OCTA_BSS)
+
+        . = ALIGN(8);
+        Image$$ZI_DATA_OCTA$$Limit = .;
+    } > RAM_OCTA
+
+}

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/startup_RZA2M.S

@@ -0,0 +1,240 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with 
+ *   GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ * 
+ * Copyright (C) 2011-2020 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+/* Copyright (c) 2011-2020 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */    .syntax unified
+    .extern _start
+ 
+@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+    .equ    Mode_USR        ,   0x10
+    .equ    Mode_FIQ        ,   0x11
+    .equ    Mode_IRQ        ,   0x12
+    .equ    Mode_SVC        ,   0x13
+    .equ    Mode_ABT        ,   0x17
+    .equ    Mode_UND        ,   0x1B
+    .equ    Mode_SYS        ,   0x1F
+
+    .equ    I_Bit           ,   0x80            @ when I bit is set, IRQ is disabled 
+    .equ    F_Bit           ,   0x40            @ when F bit is set, FIQ is disabled 
+    .equ    T_Bit           ,   0x20            @ when T bit is set, core is in Thumb state 
+ 
+@ Stack Configuration
+
+    .EQU    UND_Stack_Size  , 0x00000100
+    .EQU    SVC_Stack_Size  , 0x00008000
+    .EQU    ABT_Stack_Size  , 0x00000100
+    .EQU    FIQ_Stack_Size  , 0x00000100
+    .EQU    IRQ_Stack_Size  , 0x0000F000
+
+    .EQU    ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
+
+    .section .stack
+    .align 3
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    ISR_Stack_Size
+__initial_sp:
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+
+@ Heap Configuration
+
+    .EQU    Heap_Size       , 0x00080000
+
+    .section .heap
+    .align 3
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   0xe59ff018 /* 0x00 */
+    .long   0xe59ff018 /* 0x04 */
+    .long   0xe59ff018 /* 0x08 */
+    .long   0xe59ff018 /* 0x0c */
+    .long   0xe59ff018 /* 0x10 */
+    .long   0xe59ff018 /* 0x14 */
+    .long   0xe59ff018 /* 0x18 */
+    .long   0xe59ff018 /* 0x1c */
+
+    .long   Reset_Handler         /* 0x20 */
+    .long   Undef_Handler         /* 0x24 */
+    .long   SVC_Handler           /* 0x28 */
+    .long   PAbt_Handler          /* 0x2c */
+    .long   DAbt_Handler          /* 0x30 */
+    .long   0                     /* Reserved */
+    .long   IRQ_Handler           /* IRQ */
+    .long   FIQ_Handler           /* FIQ */
+
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .align 2
+    .globl         Reset_Handler
+    .type          Reset_Handler, %function
+Reset_Handler:
+    @ Mask interrupts
+    CPSID   if                           
+
+    @ Put any cores other than 0 to sleep
+    mrc     p15, 0, r0, c0, c0, 5   @ Read MPIDR
+    ands    r0, r0, #3
+goToSleep:
+    wfine
+    bne     goToSleep
+
+    @ Reset SCTLR Settings
+    mrc     p15, 0, r0, c1, c0, 0       @ Read CP15 System Control register 
+    bic     r0, r0, #(0x1 << 12)        @ Clear I bit 12 to disable I Cache 
+    bic     r0, r0, #(0x1 <<  2)        @ Clear C bit  2 to disable D Cache 
+    bic     r0, r0, #0x1                @ Clear M bit  0 to disable MMU 
+    bic     r0, r0, #(0x1 << 11)        @ Clear Z bit 11 to disable branch prediction 
+    bic     r0, r0, #(0x1 << 13)        @ Clear V bit 13 to disable hivecs 
+    mcr     p15, 0, r0, c1, c0, 0       @ Write value back to CP15 System Control register 
+    isb
+
+    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       @ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          @ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       @ Write CP15 Auxiliary Control Register
+
+    @ Set Vector Base Address Register (VBAR) to point to this application's vector table
+    ldr     r0, =__isr_vector
+    mcr     p15, 0, r0, c12, c0, 0
+ 
+@ Setup Stack for each exceptional mode 
+    ldr     r0, =__StackTop
+
+@ Enter Undefined Instruction Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_UND | I_Bit | F_Bit)
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+@ Enter Abort Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #ABT_Stack_Size
+
+@ Enter FIQ Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #FIQ_Stack_Size
+
+@ Enter IRQ Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #IRQ_Stack_Size
+
+@ Enter Supervisor Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
+    mov     sp, r0 
+
+@ Enter System Mode to complete initialization and enter kernel 
+    msr     cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
+    mov     sp, r0 
+
+@  USR/SYS stack pointer will be set during kernel init
+    ldr     r0, =SystemInit
+    blx     r0
+
+    @ Unmask interrupts
+    CPSIE  if
+
+@ data sections copy
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+
+@ bss sections clear
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+
+
+    ldr     r0, =_start
+    bx      r0
+
+    ldr     r0, sf_boot     @ dummy to keep boot loader area
+loop_here:
+    b       loop_here
+
+sf_boot: 
+    .word   boot_loader
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .end

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/weak_handler.S

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-A Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+                .file    "irq_weak.S"
+                .syntax  unified
+
+                .equ   MODE_SVC,        0x13
+
+                .arm
+                .section ".text"
+                .align   4
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+                .macro    def_default_handler    handler_name
+                .align 1
+                .thumb_func
+                .weak    \handler_name
+                .type    \handler_name, %function
+\handler_name :
+                b    .
+                .size    \handler_name, . - \handler_name
+                .endm
+
+                def_default_handler    Undef_Handler
+                def_default_handler    SVC_Handler
+                def_default_handler    PAbt_Handler
+                def_default_handler    DAbt_Handler
+                def_default_handler    FIQ_Handler
+
+
+                .weak    IRQ_Handler
+                .type    IRQ_Handler, %function
+                .global  IRQ_Handler
+                .fnstart
+                .cantunwind
+IRQ_Handler:
+
+                SUB     LR, LR, #4                  // Pre-adjust LR
+                SRSFD   SP!, #MODE_SVC              // Save LR_irq and SPSR_irq on to the SVC stack
+                CPS     #MODE_SVC                   // Change to SVC mode
+                PUSH    {R0-R3, R12, LR}            // Save APCS corruptible registers
+
+                MOV     R3, SP                      // Move SP into R3
+                AND     R3, R3, #4                  // Get stack adjustment to ensure 8-byte alignment
+                SUB     SP, SP, R3                  // Adjust stack
+                PUSH    {R3, R4}                    // Store stack adjustment(R3) and user data(R4)
+
+                BLX     IRQ_GetActiveIRQ            // Retrieve interrupt ID into R0
+                MOV     R4, R0                      // Move interrupt ID to R4
+
+                BLX     IRQ_GetHandler              // Retrieve interrupt handler address for current ID
+                CMP     R0, #0                      // Check if handler address is 0
+                BEQ     IRQ_End                     // If 0, end interrupt and return
+
+                CPSIE   i                           // Re-enable interrupts
+                BLX     R0                          // Call IRQ handler
+                CPSID   i                           // Disable interrupts
+
+IRQ_End:
+                MOV     R0, R4                      // Move interrupt ID to R0
+                BLX     IRQ_EndOfInterrupt          // Signal end of interrupt
+
+                POP     {R3, R4}                    // Restore stack adjustment(R3) and user data(R4)
+                ADD     SP, SP, R3                  // Unadjust stack
+
+                POP     {R0-R3, R12, LR}            // Restore stacked APCS registers
+                RFEFD   SP!                         // Return from IRQ handler
+
+                .fnend
+                .size    IRQ_Handler, .-IRQ_Handler
+
+                .end

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/MBRZA1H.icf

@@ -0,0 +1,81 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0x50000000;
+}
+if (MBED_APP_START == 0x50000000) {
+    /* No boot loader is used */
+    /* define symbol BOOT_LOADER_SIZE =  0x4000; */
+    define symbol BOOT_LOADER_SIZE =  0x0;
+} else {
+    define symbol BOOT_LOADER_SIZE =  0x0;
+}
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START + BOOT_LOADER_SIZE;
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0x1000000;
+}
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__     = MBED_APP_START + MBED_APP_SIZE - 1;
+
+define symbol __ICFEDIT_region_NvRAM_start__    = 0x80000000;
+define symbol __ICFEDIT_region_NvRAM_end__      = 0x8001FFFF;
+define symbol __ICFEDIT_region_TTB_start__      = 0x80020000;
+define symbol __ICFEDIT_region_TTB_end__        = 0x80023FFF;
+define symbol __ICFEDIT_region_TTB_L2_start__   = 0x80024000;
+define symbol __ICFEDIT_region_TTB_L2_end__     = 0x80024FFF;
+define symbol __ICFEDIT_region_RAM_start__      = 0x80025000;
+define symbol __ICFEDIT_region_RAM_end__        = 0x803DAFFF;
+define symbol __ICFEDIT_region_OctaRAM_start__  = 0x60000000;
+define symbol __ICFEDIT_region_OctaRAM_end__    = 0x607FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x00004000;
+define symbol __ICFEDIT_size_svcstack__ = 0x00008000;
+define symbol __ICFEDIT_size_irqstack__ = 0x00008000;
+define symbol __ICFEDIT_size_fiqstack__ = 0x00000100;
+define symbol __ICFEDIT_size_undstack__ = 0x00000100;
+define symbol __ICFEDIT_size_abtstack__ = 0x00000100;
+define symbol __ICFEDIT_size_heap__     = 0x00080000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+
+define region ROM_region          = mem:[from __ICFEDIT_region_ROM_start__          to __ICFEDIT_region_ROM_end__];
+define region NvRAM_region        = mem:[from __ICFEDIT_region_NvRAM_start__        to __ICFEDIT_region_NvRAM_end__];
+define region TTB_region          = mem:[from __ICFEDIT_region_TTB_start__          to __ICFEDIT_region_TTB_end__];
+define region TTB_L2_region       = mem:[from __ICFEDIT_region_TTB_L2_start__       to __ICFEDIT_region_TTB_L2_end__];
+define region RAM_region          = mem:[from __ICFEDIT_region_RAM_start__          to __ICFEDIT_region_RAM_end__];
+define region OctaRAM_region      = mem:[from __ICFEDIT_region_OctaRAM_start__      to __ICFEDIT_region_OctaRAM_end__];
+
+define block ROM_FIXED_ORDER with fixed order { ro code, ro data };
+define block NC_RAM    with fixed order, alignment = 4K { section NC_DATA, section .mirrorram, section NC_BSS };
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+define block C_RAM     with alignment = 4K { block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                                             block UND_STACK, block ABT_STACK, block HEAP };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { section NV_DATA };
+do not initialize  { section TTB };
+do not initialize  { section TTB_L2 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region      { readonly, block ROM_FIXED_ORDER };
+place in NvRAM_region    { section NV_DATA };
+place in TTB_region      { section TTB };
+place in TTB_L2_region   { section TTB_L2 };
+place in RAM_region      { readwrite,
+                           block NC_RAM,
+                           block C_RAM };
+place in OctaRAM_region  { section OCTA_DATA, section OCTA_BSS };

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/startup_RZA2M.S

@@ -0,0 +1,226 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007-2020 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION SVC_STACK:DATA:NOROOT(3)
+        SECTION IRQ_STACK:DATA:NOROOT(3)
+        SECTION ABT_STACK:DATA:NOROOT(3)
+        SECTION FIQ_STACK:DATA:NOROOT(3)
+        SECTION UND_STACK:DATA:NOROOT(3)
+        SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        PUBLIC  __vector_table
+        PUBLIC  __RST_Handler
+        EXTERN  Undef_Handler
+        EXTERN  SVC_Handler
+        EXTERN  PAbt_Handler
+        EXTERN  DAbt_Handler
+        EXTERN  IRQ_Handler
+        PUBLIC  FIQ_Handler
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+__vector_table:                 ; Make this a DATA label, so that stack usage
+                                ; analysis doesn't consider it an uncalled fun
+
+        ARM
+
+        ; All default exception handlers (except reset) are
+        ; defined as weak symbol definitions.
+        ; If a handler is defined by the application it will take precedence.
+        LDR     PC,Reset_Addr           ; Reset
+        LDR     PC,Undefined_Addr       ; Undefined instructions
+        LDR     PC,SWI_Addr             ; Software interrupt (SWI/SVC)
+        LDR     PC,Prefetch_Addr        ; Prefetch abort
+        LDR     PC,Abort_Addr           ; Data abort
+        DCD     0                       ; RESERVED
+        LDR     PC,IRQ_Addr             ; IRQ
+        LDR     PC,FIQ_Addr             ; FIQ
+
+        DATA
+
+Reset_Addr:     DCD   __RST_Handler
+Undefined_Addr: DCD   Undef_Handler
+SWI_Addr:       DCD   SVC_Handler
+Prefetch_Addr:  DCD   PAbt_Handler
+Abort_Addr:     DCD   DAbt_Handler
+IRQ_Addr:       DCD   IRQ_Handler
+FIQ_Addr:       DCD   FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+        SECTION .text:CODE:NOROOT(2)
+        EXTERN  SystemInit
+        EXTERN  __iar_program_start
+        REQUIRE __vector_table
+        EXTWEAK __iar_init_core
+        EXTWEAK __iar_init_vfp
+
+
+        ARM
+
+__RST_Handler:
+?cstartup:
+
+;;;    @ Mask interrupts
+    CPSID   if   
+
+;;;    @ Put any cores other than 0 to sleep
+    mrc     p15, 0, r0, c0, c0, 5   ;;; @ Read MPIDR
+    ands    r0, r0, #3
+
+goToSleep:
+    wfine
+    bne     goToSleep
+
+;;;    @ Reset SCTLR Settings
+    mrc     p15, 0, r0, c1, c0, 0       ;@ Read CP15 System Control register 
+    bic     r0, r0, #(0x1 << 12)        ;@ Clear I bit 12 to disable I Cache 
+    bic     r0, r0, #(0x1 <<  2)        ;@ Clear C bit  2 to disable D Cache 
+    bic     r0, r0, #0x1                ;@ Clear M bit  0 to disable MMU 
+    bic     r0, r0, #(0x1 << 11)        ;@ Clear Z bit 11 to disable branch prediction 
+    bic     r0, r0, #(0x1 << 13)        ;@ Clear V bit 13 to disable hivecs 
+    mcr     p15, 0, r0, c1, c0, 0       ;@ Write value back to CP15 System Control register 
+    isb
+
+;;;    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       ;@ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          ;@ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       ;@ Write CP15 Auxiliary Control Register
+
+;; Set Vector Base Address Register (VBAR) to point to this application's vector table
+    ldr     r0, =__vector_table
+    mcr     p15, 0, r0, c12, c0, 0
+    
+    
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F            ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10            ; User mode
+#define FIQ_MODE 0x11            ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12            ; Interrupt Request mode
+#define SVC_MODE 0x13            ; Supervisor mode
+#define ABT_MODE 0x17            ; Abort mode
+#define UND_MODE 0x1B            ; Undefined Instruction mode
+#define SYS_MODE 0x1F            ; System mode
+
+        MRS     r0, cpsr                ; Original PSR value
+
+        ;; Set up the SVC stack pointer.        
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #SVC_MODE       ; Set SVC mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(SVC_STACK)     ; End of SVC_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the fast interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #FIQ_MODE       ; Set FIR mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(FIQ_STACK)     ; End of FIQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+
+        ;; Set up the ABT stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #ABT_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(ABT_STACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+
+        ;; Set up the UDF stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #UND_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(UND_STACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+        
+        ;; Set up the normal stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #SYS_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(CSTACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+;;;
+;  USR/SYS stack pointer will be set during kernel init
+    ldr     r0, =SystemInit
+    blx     r0
+
+;;; Continue to __cmain for C-level initialization.
+
+          FUNCALL __RST_Handler, __iar_program_start
+        B       __iar_program_start
+
+
+    ldr     r0, sf_boot     ;@ dummy to keep boot loader area
+loop_here:
+    b       loop_here
+
+sf_boot: 
+    DC32   0x00000001
+
+FIQ_Handler:
+    B       .
+ 
+  END

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/weak_handler.S

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-A Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+                NAME     irq_weak.S
+
+MODE_SVC        EQU      0x13
+
+                PRESERVE8
+
+                SECTION .text:CODE:NOROOT(2)
+
+                PUBWEAK Undef_Handler
+Undef_Handler
+                B       .
+
+                PUBWEAK SVC_Handler
+SVC_Handler
+                B       .
+
+                PUBWEAK PAbt_Handler
+PAbt_Handler
+                B       .
+
+                PUBWEAK DAbt_Handler
+DAbt_Handler
+                B       .
+
+                PUBWEAK IRQ_Handler
+IRQ_Handler
+                IMPORT  IRQ_GetActiveIRQ
+                IMPORT  IRQ_GetHandler
+                IMPORT  IRQ_EndOfInterrupt
+
+                SUB     LR, LR, #4                  ; Pre-adjust LR
+                SRSFD   SP!, #MODE_SVC              ; Save LR_irq and SPSR_irq on to the SVC stack
+                CPS     #MODE_SVC                   ; Change to SVC mode
+                PUSH    {R0-R3, R12, LR}            ; Save APCS corruptible registers
+
+                MOV     R3, SP                      ; Move SP into R3
+                AND     R3, R3, #4                  ; Get stack adjustment to ensure 8-byte alignment
+                SUB     SP, SP, R3                  ; Adjust stack
+                PUSH    {R3, R4}                    ; Store stack adjustment(R3) and user data(R4)
+
+                BLX     IRQ_GetActiveIRQ            ; Retrieve interrupt ID into R0
+                MOV     R4, R0                      ; Move interrupt ID to R4
+
+                BLX     IRQ_GetHandler              ; Retrieve interrupt handler address for current ID
+                CMP     R0, #0                      ; Check if handler address is 0
+                BEQ     IRQ_End                     ; If 0, end interrupt and return
+
+                CPSIE   i                           ; Re-enable interrupts
+                BLX     R0                          ; Call IRQ handler
+                CPSID   i                           ; Disable interrupts
+
+IRQ_End
+                MOV     R0, R4                      ; Move interrupt ID to R0
+                BLX     IRQ_EndOfInterrupt          ; Signal end of interrupt
+
+                POP     {R3, R4}                    ; Restore stack adjustment(R3) and user data(R4)
+                ADD     SP, SP, R3                  ; Unadjust stack
+
+                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers
+                RFEFD   SP!                         ; Return from IRQ handler
+
+                END

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis.h

@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2020 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+/* Copyright (c) 2009-2020 ARM Limited.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MBRZA2M.h"
+#include "cmsis_nvic.h"
+#include "mbed_rtx.h"
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis_nvic.c

@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015-2020 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+/* Copyright (c) 2015-2020 ARM Limited.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "MBRZA2M.h"
+#include "irq_ctrl.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
+    return vectors;
+}

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/RZ_A2M.h

@@ -0,0 +1,844 @@
+/******************************************************************************
+ * @file     RZ_A2M.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version  V1.00
+ * @data     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RZ_A2M_H__
+#define __RZ_A2M_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn {
+    /******  SGI Interrupts Numbers                 ****************************************/
+    SGI0_IRQn            =  0,
+    SGI1_IRQn            =  1,
+    SGI2_IRQn            =  2,
+    SGI3_IRQn            =  3,
+    SGI4_IRQn            =  4,
+    SGI5_IRQn            =  5,
+    SGI6_IRQn            =  6,
+    SGI7_IRQn            =  7,
+    SGI8_IRQn            =  8,
+    SGI9_IRQn            =  9,
+    SGI10_IRQn           = 10,
+    SGI11_IRQn           = 11,
+    SGI12_IRQn           = 12,
+    SGI13_IRQn           = 13,
+    SGI14_IRQn           = 14,
+    SGI15_IRQn           = 15,
+
+    /* 16-31 Reserved */
+
+    /******  Cortex-A9 Processor Exceptions Numbers ****************************************/
+    /* 32 - ????? */
+    PMUIRQ0_IRQn         = 32,
+    COMMRX0_IRQn         = 33,
+    COMMTX0_IRQn         = 34,
+    CTIIRQ0_IRQn         = 35,
+
+    IRQ0_IRQn            = 36,
+    IRQ1_IRQn            = 37,
+    IRQ2_IRQn            = 38,
+    IRQ3_IRQn            = 39,
+    IRQ4_IRQn            = 40,
+    IRQ5_IRQn            = 41,
+    IRQ6_IRQn            = 42,
+    IRQ7_IRQn            = 43,
+
+    PL310ERR_IRQn        = 44,
+
+    DMAINT0_IRQn         = 45,        /*!< DMAC Interrupt         */
+    DMAINT1_IRQn         = 46,        /*!< DMAC Interrupt         */
+    DMAINT2_IRQn         = 47,        /*!< DMAC Interrupt         */
+    DMAINT3_IRQn         = 48,        /*!< DMAC Interrupt         */
+    DMAINT4_IRQn         = 49,        /*!< DMAC Interrupt         */
+    DMAINT5_IRQn         = 50,        /*!< DMAC Interrupt         */
+    DMAINT6_IRQn         = 51,        /*!< DMAC Interrupt         */
+    DMAINT7_IRQn         = 52,        /*!< DMAC Interrupt         */
+    DMAINT8_IRQn         = 53,        /*!< DMAC Interrupt         */
+    DMAINT9_IRQn         = 54,        /*!< DMAC Interrupt         */
+    DMAINT10_IRQn        = 55,        /*!< DMAC Interrupt         */
+    DMAINT11_IRQn        = 56,        /*!< DMAC Interrupt         */
+    DMAINT12_IRQn        = 57,        /*!< DMAC Interrupt         */
+    DMAINT13_IRQn        = 58,        /*!< DMAC Interrupt         */
+    DMAINT14_IRQn        = 59,        /*!< DMAC Interrupt         */
+    DMAINT15_IRQn        = 60,        /*!< DMAC Interrupt         */
+    DMAERR0_IRQn         = 61,        /*!< DMAC Interrupt         */
+    DMAERR1_IRQn         = 62,        /*!< DMAC Interrupt         */
+
+    USBHI0_IRQn          = 63,
+    USBFI0_IRQn          = 64,
+    USBFDMA00_IRQn       = 65,
+    USBFDMA01_IRQn       = 66,
+    USBFDMAERR0_IRQn     = 67,
+    USBHI1_IRQn          = 68,
+    USBFI1_IRQn          = 69,
+    USBFDMA10_IRQn       = 70,
+    USBFDMA11_IRQn       = 71,
+    USBFDMAERR1_IRQn     = 72,
+
+    S0_VI_VSYNC0_IRQn    = 73,
+    S0_LO_VSYNC0_IRQn    = 74,
+    S0_VSYNCERR0_IRQn    = 75,
+    GR3_VLINE0_IRQn      = 76,
+    S0_VFIELD0_IRQn      = 77,
+    IV1_VBUFERR0_IRQn    = 78,
+    IV3_VBUFERR0_IRQn    = 79,
+    IV5_VBUFERR0_IRQn    = 80,
+    IV6_VBUFERR0_IRQn    = 81,
+    S0_WLINE0_IRQn       = 82,
+
+    IMR2I0_IRQn          = 83,
+
+    JEDI_IRQn            = 84,
+    JDTI_IRQn            = 85,
+
+    DRWI_IRQn            = 86,
+
+    CSII_IRQn            = 87,
+
+    OSTMI0_IRQn          = 88,       /*!< OSTM Interrupt         */
+    OSTMI1_IRQn          = 89,       /*!< OSTM Interrupt         */
+    OSTMI2_IRQn          = 90,       /*!< OSTM Interrupt         */
+
+    CMI_IRQn             = 91,
+    WTOUT_IRQn           = 92,
+
+    ITI_IRQn             = 93,
+    CA9PEI_IRQn          = 94,
+
+    TGIA0_IRQn           = 95,
+    TGIB0_IRQn           = 96,
+    TGIC0_IRQn           = 97,
+    TGID0_IRQn           = 98,
+    TGIV0_IRQn           = 99,
+    TGIE0_IRQn           = 100,
+    TGIF0_IRQn           = 101,
+    TGIA1_IRQn           = 102,
+    TGIB1_IRQn           = 103,
+    TGIV1_IRQn           = 104,
+    TGIU1_IRQn           = 105,
+    TGIA2_IRQn           = 106,
+    TGIB2_IRQn           = 107,
+    TGIV2_IRQn           = 108,
+    TGIU2_IRQn           = 109,
+    TGIA3_IRQn           = 110,
+    TGIB3_IRQn           = 111,
+    TGIC3_IRQn           = 112,
+    TGID3_IRQn           = 113,
+    TGIV3_IRQn           = 114,
+    TGIA4_IRQn           = 115,
+    TGIB4_IRQn           = 116,
+    TGIC4_IRQn           = 117,
+    TGID4_IRQn           = 118,
+    TGIV4_IRQn           = 119,
+    TGIU5_IRQn           = 120,
+    TGIV5_IRQn           = 121,
+    TGIW5_IRQn           = 122,
+    TGIA6_IRQn           = 123,
+    TGIB6_IRQn           = 124,
+    TGIC6_IRQn           = 125,
+    TGID6_IRQn           = 126,
+    TGIV6_IRQn           = 127,
+    TGIA7_IRQn           = 128,
+    TGIB7_IRQn           = 129,
+    TGIC7_IRQn           = 130,
+    TGID7_IRQn           = 131,
+    TGIV7_IRQn           = 132,
+    TGIA8_IRQn           = 133,
+    TGIB8_IRQn           = 134,
+    TGIC8_IRQn           = 135,
+    TGID8_IRQn           = 136,
+    TGIV8_IRQn           = 137,
+
+    /* 138 Reserved */
+
+    CCMPA0_IRQn          = 139,
+    CCMPB0_IRQn          = 140,
+    CMPC0_IRQn           = 141,
+    CMPD0_IRQn           = 142,
+    /* 143-145 Reserved */
+    CMPE0_IRQn           = 146,
+    CMPF0_IRQn           = 147,
+    ADTRGA0_IRQn         = 148,
+    ADTRGB0_IRQn         = 149,
+    OVF0_IRQn            = 150,
+    UNF0_IRQn            = 151,
+    CCMPA1_IRQn          = 152,
+    CCMPB1_IRQn          = 153,
+    CMPC1_IRQn           = 154,
+    CMPD1_IRQn           = 155,
+    /* 156-158 Reserved */
+    CMPE1_IRQn           = 159,
+    CMPF1_IRQn           = 160,
+    ADTRGA1_IRQn         = 161,
+    ADTRGB1_IRQn         = 162,
+    OVF1_IRQn            = 163,
+    UNF1_IRQn            = 164,
+    CCMPA2_IRQn          = 165,
+    CCMPB2_IRQn          = 166,
+    CMPC2_IRQn           = 167,
+    CMPD2_IRQn           = 168,
+    /* 169-171 Reserved */
+    CMPE2_IRQn           = 172,
+    CMPF2_IRQn           = 173,
+    ADTRGA2_IRQn         = 174,
+    ADTRGB2_IRQn         = 175,
+    OVF2_IRQn            = 176,
+    UNF2_IRQn            = 177,
+    CCMPA3_IRQn          = 178,
+    CCMPB3_IRQn          = 179,
+    CMPC3_IRQn           = 180,
+    CMPD3_IRQn           = 181,
+    /* 182-184 Reserved */
+    CMPE3_IRQn           = 185,
+    CMPF3_IRQn           = 186,
+    ADTRGA3_IRQn         = 187,
+    ADTRGB3_IRQn         = 188,
+    OVF3_IRQn            = 189,
+    UNF3_IRQn            = 190,
+    CCMPA4_IRQn          = 191,
+    CCMPB4_IRQn          = 192,
+    CMPC4_IRQn           = 193,
+    CMPD4_IRQn           = 194,
+    /* 195-197 Reserved */
+    CMPE4_IRQn           = 198,
+    CMPF4_IRQn           = 199,
+    ADTRGA4_IRQn         = 200,
+    ADTRGB4_IRQn         = 201,
+    OVF4_IRQn            = 202,
+    UNF4_IRQn            = 203,
+    CCMPA5_IRQn          = 204,
+    CCMPB5_IRQn          = 205,
+    CMPC5_IRQn           = 206,
+    CMPD5_IRQn           = 207,
+    /* 208-210 Reserved */
+    CMPE5_IRQn           = 211,
+    CMPF5_IRQn           = 212,
+    ADTRGA5_IRQn         = 213,
+    ADTRGB5_IRQn         = 214,
+    OVF5_IRQn            = 215,
+    UNF5_IRQn            = 216,
+    CCMPA6_IRQn          = 217,
+    CCMPB6_IRQn          = 218,
+    CMPC6_IRQn           = 219,
+    CMPD6_IRQn           = 220,
+    /* 221-223 Reserved */
+    CMPE6_IRQn           = 224,
+    CMPF6_IRQn           = 225,
+    ADTRGA6_IRQn         = 226,
+    ADTRGB6_IRQn         = 227,
+    OVF6_IRQn            = 228,
+    UNF6_IRQn            = 229,
+    CCMPA7_IRQn          = 230,
+    CCMPB7_IRQn          = 231,
+    CMPC7_IRQn           = 232,
+    CMPD7_IRQn           = 233,
+    /* 234-236 Reserved */
+    CMPE7_IRQn           = 237,
+    CMPF7_IRQn           = 238,
+    ADTRGA7_IRQn         = 239,
+    ADTRGB7_IRQn         = 240,
+    OVF7_IRQn            = 241,
+    UNF7_IRQn            = 242,
+
+    OEI1_IRQn            = 243,
+    OEI2_IRQn            = 244,
+    OEI3_IRQn            = 245,
+    OEI4_IRQn            = 246,
+
+    S12ADI0_IRQn         = 247,
+    S12GBADI0_IRQn       = 248,
+    S12GCADI0_IRQn       = 249,
+    S12ADCMPAI0_IRQn     = 250,
+    S12ADCMPBI0_IRQn     = 251,
+
+    INT_SSIF_INT_REQ_0_IRQn = 252,
+    INT_SSIF_DMA_RX_0_IRQn  = 253,
+    INT_SSIF_DMA_TX_0_IRQn  = 254,
+    INT_SSIF_INT_REQ_1_IRQn = 255,
+    INT_SSIF_DMA_RX_1_IRQn  = 256,
+    INT_SSIF_DMA_TX_1_IRQn  = 257,
+    INT_SSIF_INT_REQ_2_IRQn = 258,
+    INT_SSIF_DMA_RT_2_IRQn  = 259,
+    INT_SSIF_INT_REQ_3_IRQn = 260,
+    INT_SSIF_DMA_RX_3_IRQn  = 261,
+    INT_SSIF_DMA_TX_3_IRQn = 262,
+
+    SPDIFI_IRQn          = 263,
+
+    INTRIICTEI0_IRQn     = 264,
+    INTRIICRI0_IRQn      = 265,
+    INTRIICTI0_IRQn      = 266,
+    INTRIICSPI0_IRQn     = 267,
+    INTRIICSTI0_IRQn     = 268,
+    INTRIICNAKI0_IRQn    = 269,
+    INTRIICALI0_IRQn     = 270,
+    INTRIICTMOI0_IRQn    = 271,
+    INTRIICTEI1_IRQn     = 272,
+    INTRIICRI1_IRQn      = 273,
+    INTRIICTI1_IRQn      = 274,
+    INTRIICSPI1_IRQn     = 275,
+    INTRIICSTI1_IRQn     = 276,
+    INTRIICNAKI1_IRQn    = 277,
+    INTRIICALI1_IRQn     = 278,
+    INTRIICTMOI1_IRQn    = 279,
+    INTRIICTEI2_IRQn     = 280,
+    INTRIICRI2_IRQn      = 281,
+    INTRIICTI2_IRQn      = 282,
+    INTRIICSPI2_IRQn     = 283,
+    INTRIICSTI2_IRQn     = 284,
+    INTRIICNAKI2_IRQn    = 285,
+    INTRIICALI2_IRQn     = 286,
+    INTRIICTMOI2_IRQn    = 287,
+    INTRIICTEI3_IRQn     = 288,
+    INTRIICRI3_IRQn      = 289,
+    INTRIICTI3_IRQn      = 290,
+    INTRIICSPI3_IRQn     = 291,
+    INTRIICSTI3_IRQn     = 292,
+    INTRIICNAKI3_IRQn    = 293,
+    INTRIICALI3_IRQn     = 294,
+    INTRIICTMOI3_IRQn    = 295,
+
+    /* 296 Reserved */
+
+    ERI0_IRQn            = 297,
+    RXI0_IRQn            = 298,
+    TXI0_IRQn            = 299,
+    TEI0_IRQn            = 300,
+    /* 301-302 Reserved */
+    ERI1_IRQn            = 303,
+    RXI1_IRQn            = 304,
+    TXI1_IRQn            = 305,
+    TEI1_IRQn            = 306,
+    /* 307-308 Reserved */
+    ERI2_IRQn            = 309,
+    RXI2_IRQn            = 310,
+    TXI2_IRQn            = 311,
+    TEI2_IRQn            = 312,
+    /* 313-314 Reserved */
+    ERI3_IRQn            = 315,
+    RXI3_IRQn            = 316,
+    TXI3_IRQn            = 317,
+    TEI3_IRQn            = 318,
+    /* 319-320 Reserved */
+    ERI4_IRQn            = 321,
+    RXI4_IRQn            = 322,
+    TXI4_IRQn            = 323,
+    TEI4_IRQn            = 324,
+
+    /* 325 Reserved */
+
+    GERI_IRQn            = 326,
+    RFI_IRQn             = 327,
+    CFRXI0_IRQn          = 328,
+    CERI0_IRQn           = 329,
+    CTXI0_IRQn           = 330,
+    CFRXI1_IRQn          = 331,
+    CERI1_IRQn           = 332,
+    CTXI1_IRQn           = 333,
+
+    DMA31INT0_IRQn       = 334,
+    DMA31INT1_IRQn       = 335,
+    DMA31INT2_IRQn       = 336,
+    DMA31INT3_IRQn       = 337,
+    DMA31INT4_IRQn       = 338,
+    DMA31INT5_IRQn       = 339,
+    DMA31INT6_IRQn       = 340,
+    DMA31INT7_IRQn       = 341,
+    DMA31INT8_IRQn       = 342,
+    DMA31INT9_IRQn       = 343,
+
+    SPEI0_IRQn           = 344,
+    SPRI0_IRQn           = 345,
+    SPTI0_IRQn           = 346,
+    SPEI1_IRQn           = 347,
+    SPRI1_IRQn           = 348,
+    SPTI1_IRQn           = 349,
+    SPEI2_IRQn           = 350,
+    SPRI2_IRQn           = 351,
+    SPTI2_IRQn           = 352,
+
+    NAND_IRQn            = 353,
+
+    SDHI0_0_IRQn         = 354,
+    /* 355 Reserved */
+    SDHI1_0_IRQn         = 356,
+
+    /* 357 Reserved */
+
+    NET_HYPER_IENON_IRQn = 358,
+
+    ARM_IRQn             = 359,
+    PRD_IRQn             = 360,
+    CUP_IRQn             = 361,
+    ARM_S_IRQn           = 362,
+    PRD_S_IRQn           = 363,
+    CUP_S_IRQn           = 364,
+
+    SCIM_ERI0_IRQn       = 365,
+    SCIM_RXI0_IRQn       = 366,
+    SCIM_TXI0_IRQn       = 367,
+    SCIM_TEI0_IRQn       = 368,
+    SCIM_ERI1_IRQn       = 369,
+    SCIM_RXI1_IRQn       = 370,
+    SCIM_TXI1_IRQn       = 371,
+    SCIM_TEI1_IRQn       = 372,
+
+    EINT0_IRQn           = 373,
+    EINT1_IRQn           = 374,
+    PINT_IRQn            = 375,
+    MINT_IRQn            = 376,
+    IPLS_IRQn            = 377,
+
+    CEUI_IRQn            = 378,
+
+    H2USB00_ERRINT_IRQn  = 379,
+    H2USB01_ERRINT_IRQn  = 380,
+    H2USB10_ERRINT_IRQn  = 381,
+    H2USB11_ERRINT_IRQn  = 382,
+    H2ETH_ERRINT_IRQn    = 383,
+    X2PERI12_ERRINT_IRQn = 384,
+    X2PERI34_ERRINT_IRQn = 385,
+    X2PERI5_ERRINT_IRQn  = 386,
+    X2PERI67_ERRINT_IRQn = 387,
+    H2IC4_ERRINT_IRQn    = 388,
+    X2DBGR_ERRINT_IRQn   = 389,
+
+    DMA31INT10_IRQn      = 390,
+    DMA31INT11_IRQn      = 391,
+    DMA31INT12_IRQn      = 392,
+    DMA31INT13_IRQn      = 393,
+    DMA31INT14_IRQn      = 394,
+    DMA31INT15_IRQn      = 395,
+
+    H2XDAV0_ERRINT_IRQn  = 396,
+    H2XDAV1_ERRINT_IRQn  = 397,
+
+    ECC0E10_IRQn         = 398,
+    ECC0E20_IRQn         = 399,
+    ECC0OVF0_IRQn        = 400,
+    ECC0E11_IRQn         = 401,
+    ECC0E21_IRQn         = 402,
+    ECC0OVF1_IRQn        = 403,
+    ECC0E12_IRQn         = 404,
+    ECC0E22_IRQn         = 405,
+    ECC0OVF2_IRQn        = 406,
+    ECC0E13_IRQn         = 407,
+    ECC0E23_IRQn         = 408,
+    ECC0OVF3_IRQn        = 409,
+    ECC1E10_IRQn         = 410,
+    ECC1E20_IRQn         = 411,
+    ECC1OVF0_IRQn        = 412,
+    ECC1E11_IRQn         = 413,
+    ECC1E21_IRQn         = 414,
+    ECC1OVF1_IRQn        = 415,
+    ECC1E12_IRQn         = 416,
+    ECC1E22_IRQn         = 417,
+    ECC1OVF2_IRQn        = 418,
+    ECC1E13_IRQn         = 419,
+    ECC1E23_IRQn         = 420,
+    ECC1OVF3_IRQn        = 421,
+    ECC2E10_IRQn         = 422,
+    ECC2E20_IRQn         = 423,
+    ECC2OVF0_IRQn        = 424,
+    ECC2E11_IRQn         = 425,
+    ECC2E21_IRQn         = 426,
+    ECC2OVF1_IRQn        = 427,
+    ECC2E12_IRQn         = 428,
+    ECC2E22_IRQn         = 429,
+    ECC2OVF2_IRQn        = 430,
+    ECC2E13_IRQn         = 431,
+    ECC2E23_IRQn         = 432,
+    ECC2OVF3_IRQn        = 433,
+
+    /* 434-445 Reserved */
+
+    ERRINT_IRQn          = 446,
+    NMLINT_IRQn          = 447,
+    PAE5_IRQn            = 448,
+    PAF5_IRQn            = 449,
+    INTB5_IRQn           = 450,
+    INTA5_IRQn           = 451,
+    PAE4_IRQn            = 452,
+    PAF4_IRQn            = 453,
+    INTB4_IRQn           = 454,
+    INTA4_IRQn           = 455,
+    PAE3_IRQn            = 456,
+    PAF3_IRQn            = 457,
+    INTB3_IRQn           = 458,
+    INTA3_IRQn           = 459,
+    PAE2_IRQn            = 460,
+    PAF2_IRQn            = 461,
+    INTB2_IRQn           = 462,
+    INTA2_IRQn           = 463,
+    PAE1_IRQn            = 464,
+    PAF1_IRQn            = 465,
+    INTB1_IRQn           = 466,
+    INTA1_IRQn           = 467,
+    PAE0_IRQn            = 468,
+    PAF0_IRQn            = 469,
+    INTB0_IRQn           = 470,
+    INTA0_IRQn           = 471,
+
+    VINI_IRQn            = 472,
+
+    GROUP0_IRQn          = 473,
+    GROUP1_IRQn          = 474,
+    GROUP2_IRQn          = 475,
+    GROUP3_IRQn          = 476,
+    SPIHF_IRQn           = 477,
+
+    /* 478-479 Reserved */
+
+    TINT0_IRQn           = 480,
+    TINT1_IRQn           = 481,
+    TINT2_IRQn           = 482,
+    TINT3_IRQn           = 483,
+    TINT4_IRQn           = 484,
+    TINT5_IRQn           = 485,
+    TINT6_IRQn           = 486,
+    TINT7_IRQn           = 487,
+    TINT8_IRQn           = 488,
+    TINT9_IRQn           = 489,
+    TINT10_IRQn          = 490,
+    TINT11_IRQn          = 491,
+    TINT12_IRQn          = 492,
+    TINT13_IRQn          = 493,
+    TINT14_IRQn          = 494,
+    TINT15_IRQn          = 495,
+    TINT16_IRQn          = 496,
+    TINT17_IRQn          = 497,
+    TINT18_IRQn          = 498,
+    TINT19_IRQn          = 499,
+    TINT20_IRQn          = 500,
+    TINT21_IRQn          = 501,
+    TINT22_IRQn          = 502,
+    TINT23_IRQn          = 503,
+    TINT24_IRQn          = 504,
+    TINT25_IRQn          = 505,
+    TINT26_IRQn          = 506,
+    TINT27_IRQn          = 507,
+    TINT28_IRQn          = 508,
+    TINT29_IRQn          = 509,
+    TINT30_IRQn          = 510,
+    TINT31_IRQn          = 511
+} IRQn_Type;
+
+#define RZ_A2_IRQ_MAX  TINT31_IRQn
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define RZ_A2_SDRAM                        (0x0C000000uL)                        /*!< SDRAM(CS3) area (Cacheable) */
+#define RZ_A2_SPI_IO                       (0x20000000uL)                        /*!< SPI multi I/O bus area (Cacheable) */
+#define RZ_A2_HYPER_FLASH                  (0x30000000uL)                        /*!< Hyper Flash area (Cacheable) */
+#define RZ_A2_HYPER_RAM                    (0x40000000uL)                        /*!< Hyper RAM area (Cacheable) */
+#define RZ_A2_OCTA_FLASH                   (0x50000000uL)                        /*!< Octa Flash area (Cacheable) */
+#define RZ_A2_OCTA_RAM                     (0x60000000uL)                        /*!< Octa RAM area (Cacheable) */
+#define RZ_A2_ONCHIP_SRAM_BASE             (0x80000000UL)                        /*!< Internal RAM area (Cacheable) */
+#define RZ_A2_PERIPH_BASE0                 (0xe8000000UL)                        /*!< I/O area */
+#define RZ_A2_PERIPH_BASE1                 (0x18000000UL)                        /*!< I/O area */
+
+#define RZ_A2_GIC_DISTRIBUTOR_BASE         (0xe8221000UL)                        /*!< (GIC DIST  ) Base Address */
+#define RZ_A2_GIC_INTERFACE_BASE           (0xe8222000UL)                        /*!< (GIC CPU IF) Base Address */
+#define RZ_A2_PL310_BASE                   (0x1F003000uL)                        /*!< (PL310     ) Base Address */
+//#define RZ_A2_PRIVATE_TIMER                (0x00000600UL + 0x82000000UL)         /*!< (PTIM      ) Base Address */
+
+/* Virtual address */
+#define RZ_A2_HYPER_FLASH_IO               (0xA0000000uL)                        /*!< Hyper Flash area (I/O area) */
+#define RZ_A2_OCTA_FLASH_NC                (0xC0000000uL)                        /*!< Octa Flash area (Non-Cacheable) */
+
+#define GIC_DISTRIBUTOR_BASE               RZ_A2_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                 RZ_A2_GIC_INTERFACE_BASE
+#define L2C_310_BASE                       RZ_A2_PL310_BASE
+//#define TIMER_BASE                         RZ_A2_PRIVATE_TIMER
+
+/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */
+#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#endif
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        0U    /* TIM present                                   */
+#define __L2C_PRESENT        1U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include "nvic_wrapper.h"
+#include <system_RZ_A2M.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/*                         Clock Settings                                     */
+/******************************************************************************/
+#define CM0_RENESAS_RZ_A2_CLKIN  ( 24000000u)
+#define CM0_RENESAS_RZ_A2_I_CLK  (528000000u)
+#define CM0_RENESAS_RZ_A2_G_CLK  (264000000u)
+#define CM0_RENESAS_RZ_A2_B_CLK  (132000000u)
+#define CM0_RENESAS_RZ_A2_P1_CLK ( 66000000u)
+#define CM0_RENESAS_RZ_A2_P0_CLK ( 33000000u)
+
+#define CM1_RENESAS_RZ_A2_CLKIN  ( 24000000u)
+#define CM1_RENESAS_RZ_A2_I_CLK  (528000000u)
+#define CM1_RENESAS_RZ_A2_G_CLK  (264000000u)
+#define CM1_RENESAS_RZ_A2_B_CLK  (132000000u)
+#define CM1_RENESAS_RZ_A2_P1_CLK ( 66000000u)
+#define CM1_RENESAS_RZ_A2_P0_CLK ( 33000000u)
+
+/******************************************************************************/
+/*                         CPG   Settings                                     */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2  (14)
+#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0  (12)
+#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC     (8)
+#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC    (0)
+#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+#if(0)
+#define CPG_STBCR1_BIT_STBY     (0x80u)
+#define CPG_STBCR1_BIT_DEEP     (0x40u)
+#define CPG_STBCR2_BIT_HIZ      (0x80u)
+#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31   (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */
+#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82   (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY   (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3  (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2  (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1  (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0  (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT   (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2      (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9      (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1      (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12     (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7      (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3      (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI       (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR     (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4      (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9      (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8      (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15     (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1      (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2      (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E     (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E     (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E     (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E    (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E     (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E     (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE      (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E     (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E     (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E     (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E    (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E     (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E     (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP     (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F      (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F      (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F      (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F     (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F      (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F      (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF       (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF     (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F      (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F      (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F      (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F     (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F      (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F      (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1   (0x02u)   /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0   (0x01u)   /* EXTAL, XTAL */
+#endif
+
+/******************************************************************************/
+/*                        GPIO   Settings                                     */
+/******************************************************************************/
+#define GPIO_BIT_N0  (1u <<  0)
+#define GPIO_BIT_N1  (1u <<  1)
+#define GPIO_BIT_N2  (1u <<  2)
+#define GPIO_BIT_N3  (1u <<  3)
+#define GPIO_BIT_N4  (1u <<  4)
+#define GPIO_BIT_N5  (1u <<  5)
+#define GPIO_BIT_N6  (1u <<  6)
+#define GPIO_BIT_N7  (1u <<  7)
+#define GPIO_BIT_N8  (1u <<  8)
+#define GPIO_BIT_N9  (1u <<  9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK    (0x3)
+
+#define MD_BOOT10_BM0     (0x0)
+#define MD_BOOT10_BM1     (0x2)
+#define MD_BOOT10_BM3     (0x1)
+#define MD_BOOT10_BM4_5   (0x3)
+
+#define MD_CLK        (1u << 2)
+#define MD_CLKS       (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __RZ_A1H_H__

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmask.h

@@ -0,0 +1,94 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef __RZA2M___IOBITMASK_HEADER__
+#define __RZA2M___IOBITMASK_HEADER__
+
+
+#define IOREG_DIRECT_REG_ACCESS     (0xFFFFFFFFuL)
+#include "iobitmasks/adc_iobitmask.h"
+#include "iobitmasks/bsc_iobitmask.h"
+#include "iobitmasks/ceu_iobitmask.h"
+#include "iobitmasks/cpg_iobitmask.h"
+#include "iobitmasks/csi2link_iobitmask.h"
+#include "iobitmasks/dmac_iobitmask.h"
+#include "iobitmasks/drpk_iobitmask.h"
+#include "iobitmasks/drw_iobitmask.h"
+#include "iobitmasks/edmac_iobitmask.h"
+#include "iobitmasks/eptpc_iobitmask.h"
+#include "iobitmasks/etherc_iobitmask.h"
+#include "iobitmasks/gpio_iobitmask.h"
+#include "iobitmasks/gpt_iobitmask.h"
+#include "iobitmasks/hyper_iobitmask.h"
+#include "iobitmasks/imr2_iobitmask.h"
+#include "iobitmasks/intc_iobitmask.h"
+#include "iobitmasks/irda_iobitmask.h"
+#include "iobitmasks/jcu_iobitmask.h"
+#include "iobitmasks/lvds_iobitmask.h"
+#include "iobitmasks/mtu_iobitmask.h"
+#include "iobitmasks/nandc_iobitmask.h"
+#include "iobitmasks/octa_iobitmask.h"
+#include "iobitmasks/ostm_iobitmask.h"
+#include "iobitmasks/pl310_iobitmask.h"
+#include "iobitmasks/pmg_iobitmask.h"
+#include "iobitmasks/poe3_iobitmask.h"
+#include "iobitmasks/poeg_iobitmask.h"
+#include "iobitmasks/prr_iobitmask.h"
+#include "iobitmasks/ptpedmac_iobitmask.h"
+#include "iobitmasks/rcanfd_iobitmask.h"
+#include "iobitmasks/rcan_iobitmask.h"
+#include "iobitmasks/riic_iobitmask.h"
+#include "iobitmasks/rspi_iobitmask.h"
+#include "iobitmasks/rtc_iobitmask.h"
+#include "iobitmasks/scifa_iobitmask.h"
+#include "iobitmasks/scim_iobitmask.h"
+#include "iobitmasks/sdmmc_iobitmask.h"
+#include "iobitmasks/spdif_iobitmask.h"
+#include "iobitmasks/spibsc_iobitmask.h"
+#include "iobitmasks/sprite_iobitmask.h"
+#include "iobitmasks/ssif_iobitmask.h"
+#include "iobitmasks/usb_iobitmask.h"
+#include "iobitmasks/vdc6_iobitmask.h"
+#include "iobitmasks/vin_iobitmask.h"
+#include "iobitmasks/wdt_iobitmask.h"
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/adc_iobitmask.h

@@ -0,0 +1,186 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef ADC_IOBITMASK_H
+#define ADC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define ADC_ADCSR_DBLANS                                                       (0x001Fu)
+#define ADC_ADCSR_DBLANS_SHIFT                                                 (0u)
+#define ADC_ADCSR_GBADIE                                                       (0x0040u)
+#define ADC_ADCSR_GBADIE_SHIFT                                                 (6u)
+#define ADC_ADCSR_DBLE                                                         (0x0080u)
+#define ADC_ADCSR_DBLE_SHIFT                                                   (7u)
+#define ADC_ADCSR_EXTRG                                                        (0x0100u)
+#define ADC_ADCSR_EXTRG_SHIFT                                                  (8u)
+#define ADC_ADCSR_TRGE                                                         (0x0200u)
+#define ADC_ADCSR_TRGE_SHIFT                                                   (9u)
+#define ADC_ADCSR_ADIE                                                         (0x1000u)
+#define ADC_ADCSR_ADIE_SHIFT                                                   (12u)
+#define ADC_ADCSR_ADCS                                                         (0x6000u)
+#define ADC_ADCSR_ADCS_SHIFT                                                   (13u)
+#define ADC_ADCSR_ADST                                                         (0x8000u)
+#define ADC_ADCSR_ADST_SHIFT                                                   (15u)
+#define ADC_ADANSA0_ANSA0                                                      (0x00FFu)
+#define ADC_ADANSA0_ANSA0_SHIFT                                                (0u)
+#define ADC_ADADS0_ADS0                                                        (0x00FFu)
+#define ADC_ADADS0_ADS0_SHIFT                                                  (0u)
+#define ADC_ADADC_ADC_2_0                                                      (0x07u)
+#define ADC_ADADC_ADC_2_0_SHIFT                                                (0u)
+#define ADC_ADADC_AVEE                                                         (0x80u)
+#define ADC_ADADC_AVEE_SHIFT                                                   (7u)
+#define ADC_ADCER_ADPRC                                                        (0x0006u)
+#define ADC_ADCER_ADPRC_SHIFT                                                  (1u)
+#define ADC_ADCER_ACE                                                          (0x0020u)
+#define ADC_ADCER_ACE_SHIFT                                                    (5u)
+#define ADC_ADCER_DIAGVAL                                                      (0x0300u)
+#define ADC_ADCER_DIAGVAL_SHIFT                                                (8u)
+#define ADC_ADCER_DIAGLD                                                       (0x0400u)
+#define ADC_ADCER_DIAGLD_SHIFT                                                 (10u)
+#define ADC_ADCER_DIAGM                                                        (0x0800u)
+#define ADC_ADCER_DIAGM_SHIFT                                                  (11u)
+#define ADC_ADCER_ADRFMT                                                       (0x8000u)
+#define ADC_ADCER_ADRFMT_SHIFT                                                 (15u)
+#define ADC_ADSTRGR_TRSB                                                       (0x003Fu)
+#define ADC_ADSTRGR_TRSB_SHIFT                                                 (0u)
+#define ADC_ADSTRGR_TRSA                                                       (0x3F00u)
+#define ADC_ADSTRGR_TRSA_SHIFT                                                 (8u)
+#define ADC_ADANSB0_ANSB0                                                      (0x00FFu)
+#define ADC_ADANSB0_ANSB0_SHIFT                                                (0u)
+#define ADC_ADDBLDR_AD                                                         (0xFFFFu)
+#define ADC_ADDBLDR_AD_SHIFT                                                   (0u)
+#define ADC_ADRD_AD                                                            (0xFFFFu)
+#define ADC_ADRD_AD_SHIFT                                                      (0u)
+#define ADC_ADDR0_AD                                                           (0xFFFFu)
+#define ADC_ADDR0_AD_SHIFT                                                     (0u)
+#define ADC_ADDR1_AD                                                           (0xFFFFu)
+#define ADC_ADDR1_AD_SHIFT                                                     (0u)
+#define ADC_ADDR2_AD                                                           (0xFFFFu)
+#define ADC_ADDR2_AD_SHIFT                                                     (0u)
+#define ADC_ADDR3_AD                                                           (0xFFFFu)
+#define ADC_ADDR3_AD_SHIFT                                                     (0u)
+#define ADC_ADDR4_AD                                                           (0xFFFFu)
+#define ADC_ADDR4_AD_SHIFT                                                     (0u)
+#define ADC_ADDR5_AD                                                           (0xFFFFu)
+#define ADC_ADDR5_AD_SHIFT                                                     (0u)
+#define ADC_ADDR6_AD                                                           (0xFFFFu)
+#define ADC_ADDR6_AD_SHIFT                                                     (0u)
+#define ADC_ADDR7_AD                                                           (0xFFFFu)
+#define ADC_ADDR7_AD_SHIFT                                                     (0u)
+#define ADC_ADDISCR_ADNDIS                                                     (0x1Fu)
+#define ADC_ADDISCR_ADNDIS_SHIFT                                               (0u)
+#define ADC_ADGSPCR_PGS                                                        (0x0001u)
+#define ADC_ADGSPCR_PGS_SHIFT                                                  (0u)
+#define ADC_ADGSPCR_GBRSCN                                                     (0x0002u)
+#define ADC_ADGSPCR_GBRSCN_SHIFT                                               (1u)
+#define ADC_ADGSPCR_LGRRS                                                      (0x4000u)
+#define ADC_ADGSPCR_LGRRS_SHIFT                                                (14u)
+#define ADC_ADGSPCR_GBRP                                                       (0x8000u)
+#define ADC_ADGSPCR_GBRP_SHIFT                                                 (15u)
+#define ADC_ADDBLDRA_AD                                                        (0xFFFFu)
+#define ADC_ADDBLDRA_AD_SHIFT                                                  (0u)
+#define ADC_ADDBLDRB_AD                                                        (0xFFFFu)
+#define ADC_ADDBLDRB_AD_SHIFT                                                  (0u)
+#define ADC_ADWINMON_MONCOMB                                                   (0x01u)
+#define ADC_ADWINMON_MONCOMB_SHIFT                                             (0u)
+#define ADC_ADWINMON_MONCMPA                                                   (0x10u)
+#define ADC_ADWINMON_MONCMPA_SHIFT                                             (4u)
+#define ADC_ADWINMON_MONCMPB                                                   (0x20u)
+#define ADC_ADWINMON_MONCMPB_SHIFT                                             (5u)
+#define ADC_ADCMPCR_CMPBE                                                      (0x0200u)
+#define ADC_ADCMPCR_CMPBE_SHIFT                                                (9u)
+#define ADC_ADCMPCR_CMPAE                                                      (0x0800u)
+#define ADC_ADCMPCR_CMPAE_SHIFT                                                (11u)
+#define ADC_ADCMPCR_CMPBIE                                                     (0x2000u)
+#define ADC_ADCMPCR_CMPBIE_SHIFT                                               (13u)
+#define ADC_ADCMPCR_WCMPE                                                      (0x4000u)
+#define ADC_ADCMPCR_WCMPE_SHIFT                                                (14u)
+#define ADC_ADCMPCR_CMPAIE                                                     (0x8000u)
+#define ADC_ADCMPCR_CMPAIE_SHIFT                                               (15u)
+#define ADC_ADCMPANSR0_CMPCHA0                                                 (0x00FFu)
+#define ADC_ADCMPANSR0_CMPCHA0_SHIFT                                           (0u)
+#define ADC_ADCMPLR0_CMPLCHA0                                                  (0x00FFu)
+#define ADC_ADCMPLR0_CMPLCHA0_SHIFT                                            (0u)
+#define ADC_ADCMPDR0_CMPD0                                                     (0xFFFFu)
+#define ADC_ADCMPDR0_CMPD0_SHIFT                                               (0u)
+#define ADC_ADCMPDR1_CMPD1                                                     (0xFFFFu)
+#define ADC_ADCMPDR1_CMPD1_SHIFT                                               (0u)
+#define ADC_ADCMPSR0_CMPSTCHA0                                                 (0x00FFu)
+#define ADC_ADCMPSR0_CMPSTCHA0_SHIFT                                           (0u)
+#define ADC_ADCMPBNSR_CMPCHB                                                   (0x3Fu)
+#define ADC_ADCMPBNSR_CMPCHB_SHIFT                                             (0u)
+#define ADC_ADCMPBNSR_CMPLB                                                    (0x80u)
+#define ADC_ADCMPBNSR_CMPLB_SHIFT                                              (7u)
+#define ADC_ADWINLLB_CMPLLB                                                    (0xFFFFu)
+#define ADC_ADWINLLB_CMPLLB_SHIFT                                              (0u)
+#define ADC_ADWINULB_CMPULB                                                    (0xFFFFu)
+#define ADC_ADWINULB_CMPULB_SHIFT                                              (0u)
+#define ADC_ADCMPBSR_CMPSTB                                                    (0x01u)
+#define ADC_ADCMPBSR_CMPSTB_SHIFT                                              (0u)
+#define ADC_ADANSC0_ANSC0                                                      (0x00FFu)
+#define ADC_ADANSC0_ANSC0_SHIFT                                                (0u)
+#define ADC_ADGCTRGR_TRSC                                                      (0x3Fu)
+#define ADC_ADGCTRGR_TRSC_SHIFT                                                (0u)
+#define ADC_ADGCTRGR_GCADIE                                                    (0x40u)
+#define ADC_ADGCTRGR_GCADIE_SHIFT                                              (6u)
+#define ADC_ADGCTRGR_GRCE                                                      (0x80u)
+#define ADC_ADGCTRGR_GRCE_SHIFT                                                (7u)
+#define ADC_ADSSTR0_SST                                                        (0xFFu)
+#define ADC_ADSSTR0_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR1_SST                                                        (0xFFu)
+#define ADC_ADSSTR1_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR2_SST                                                        (0xFFu)
+#define ADC_ADSSTR2_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR3_SST                                                        (0xFFu)
+#define ADC_ADSSTR3_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR4_SST                                                        (0xFFu)
+#define ADC_ADSSTR4_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR5_SST                                                        (0xFFu)
+#define ADC_ADSSTR5_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR6_SST                                                        (0xFFu)
+#define ADC_ADSSTR6_SST_SHIFT                                                  (0u)
+#define ADC_ADSSTR7_SST                                                        (0xFFu)
+#define ADC_ADSSTR7_SST_SHIFT                                                  (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/bsc_iobitmask.h

@@ -0,0 +1,296 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef BSC_IOBITMASK_H
+#define BSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define BSC_CMNCR_HIZCNT                                                       (0x00000001u)
+#define BSC_CMNCR_HIZCNT_SHIFT                                                 (0u)
+#define BSC_CMNCR_HIZMEM                                                       (0x00000002u)
+#define BSC_CMNCR_HIZMEM_SHIFT                                                 (1u)
+#define BSC_CMNCR_DPRTY                                                        (0x00000600u)
+#define BSC_CMNCR_DPRTY_SHIFT                                                  (9u)
+#define BSC_CMNCR_AL0                                                          (0x01000000u)
+#define BSC_CMNCR_AL0_SHIFT                                                    (24u)
+#define BSC_CMNCR_TL0                                                          (0x10000000u)
+#define BSC_CMNCR_TL0_SHIFT                                                    (28u)
+#define BSC_CS0BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS0BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS0BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS0BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS0BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS0BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS0BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS0BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS0BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS0BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS0BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS0BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS0BCR_IWW                                                         (0x70000000u)
+#define BSC_CS0BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS1BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS1BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS1BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS1BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS1BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS1BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS1BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS1BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS1BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS1BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS1BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS1BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS1BCR_IWW                                                         (0x70000000u)
+#define BSC_CS1BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS2BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS2BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS2BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS2BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS2BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS2BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS2BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS2BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS2BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS2BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS2BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS2BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS2BCR_IWW                                                         (0x70000000u)
+#define BSC_CS2BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS3BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS3BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS3BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS3BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS3BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS3BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS3BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS3BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS3BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS3BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS3BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS3BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS3BCR_IWW                                                         (0x70000000u)
+#define BSC_CS3BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS4BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS4BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS4BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS4BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS4BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS4BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS4BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS4BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS4BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS4BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS4BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS4BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS4BCR_IWW                                                         (0x70000000u)
+#define BSC_CS4BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS5BCR_BSZ                                                         (0x00000600u)
+#define BSC_CS5BCR_BSZ_SHIFT                                                   (9u)
+#define BSC_CS5BCR_TYPE                                                        (0x00007000u)
+#define BSC_CS5BCR_TYPE_SHIFT                                                  (12u)
+#define BSC_CS5BCR_IWRRS                                                       (0x00070000u)
+#define BSC_CS5BCR_IWRRS_SHIFT                                                 (16u)
+#define BSC_CS5BCR_IWRRD                                                       (0x00380000u)
+#define BSC_CS5BCR_IWRRD_SHIFT                                                 (19u)
+#define BSC_CS5BCR_IWRWS                                                       (0x01C00000u)
+#define BSC_CS5BCR_IWRWS_SHIFT                                                 (22u)
+#define BSC_CS5BCR_IWRWD                                                       (0x0E000000u)
+#define BSC_CS5BCR_IWRWD_SHIFT                                                 (25u)
+#define BSC_CS5BCR_IWW                                                         (0x70000000u)
+#define BSC_CS5BCR_IWW_SHIFT                                                   (28u)
+#define BSC_CS0WCR_0_HW                                                        (0x00000003u)
+#define BSC_CS0WCR_0_HW_SHIFT                                                  (0u)
+#define BSC_CS0WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS0WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS0WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS0WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS0WCR_0_SW                                                        (0x00001800u)
+#define BSC_CS0WCR_0_SW_SHIFT                                                  (11u)
+#define BSC_CS0WCR_0_BAS                                                       (0x00100000u)
+#define BSC_CS0WCR_0_BAS_SHIFT                                                 (20u)
+#define BSC_CS0WCR_1_WM                                                        (0x00000040u)
+#define BSC_CS0WCR_1_WM_SHIFT                                                  (6u)
+#define BSC_CS0WCR_1_W                                                         (0x00000780u)
+#define BSC_CS0WCR_1_W_SHIFT                                                   (7u)
+#define BSC_CS0WCR_1_BW                                                        (0x00030000u)
+#define BSC_CS0WCR_1_BW_SHIFT                                                  (16u)
+#define BSC_CS0WCR_1_BST                                                       (0x00300000u)
+#define BSC_CS0WCR_1_BST_SHIFT                                                 (20u)
+#define BSC_CS0WCR_2_WM                                                        (0x00000040u)
+#define BSC_CS0WCR_2_WM_SHIFT                                                  (6u)
+#define BSC_CS0WCR_2_W                                                         (0x00000780u)
+#define BSC_CS0WCR_2_W_SHIFT                                                   (7u)
+#define BSC_CS0WCR_2_BW                                                        (0x00030000u)
+#define BSC_CS0WCR_2_BW_SHIFT                                                  (16u)
+#define BSC_CS1WCR_0_HW                                                        (0x00000003u)
+#define BSC_CS1WCR_0_HW_SHIFT                                                  (0u)
+#define BSC_CS1WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS1WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS1WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS1WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS1WCR_0_SW                                                        (0x00001800u)
+#define BSC_CS1WCR_0_SW_SHIFT                                                  (11u)
+#define BSC_CS1WCR_0_WW                                                        (0x00070000u)
+#define BSC_CS1WCR_0_WW_SHIFT                                                  (16u)
+#define BSC_CS1WCR_0_BAS                                                       (0x00100000u)
+#define BSC_CS1WCR_0_BAS_SHIFT                                                 (20u)
+#define BSC_CS2WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS2WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS2WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS2WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS2WCR_0_BAS                                                       (0x00100000u)
+#define BSC_CS2WCR_0_BAS_SHIFT                                                 (20u)
+#define BSC_CS2WCR_1_A2CL                                                      (0x00000180u)
+#define BSC_CS2WCR_1_A2CL_SHIFT                                                (7u)
+#define BSC_CS3WCR_1_WTRC                                                      (0x00000003u)
+#define BSC_CS3WCR_1_WTRC_SHIFT                                                (0u)
+#define BSC_CS3WCR_1_TRWL                                                      (0x00000018u)
+#define BSC_CS3WCR_1_TRWL_SHIFT                                                (3u)
+#define BSC_CS3WCR_1_A3CL                                                      (0x00000180u)
+#define BSC_CS3WCR_1_A3CL_SHIFT                                                (7u)
+#define BSC_CS3WCR_1_WTRCD                                                     (0x00000C00u)
+#define BSC_CS3WCR_1_WTRCD_SHIFT                                               (10u)
+#define BSC_CS3WCR_1_WTRP                                                      (0x00006000u)
+#define BSC_CS3WCR_1_WTRP_SHIFT                                                (13u)
+#define BSC_CS3WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS3WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS3WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS3WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS3WCR_0_BAS                                                       (0x00100000u)
+#define BSC_CS3WCR_0_BAS_SHIFT                                                 (20u)
+#define BSC_CS4WCR_0_HW                                                        (0x00000003u)
+#define BSC_CS4WCR_0_HW_SHIFT                                                  (0u)
+#define BSC_CS4WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS4WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS4WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS4WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS4WCR_0_SW                                                        (0x00001800u)
+#define BSC_CS4WCR_0_SW_SHIFT                                                  (11u)
+#define BSC_CS4WCR_0_WW                                                        (0x00070000u)
+#define BSC_CS4WCR_0_WW_SHIFT                                                  (16u)
+#define BSC_CS4WCR_0_BAS                                                       (0x00100000u)
+#define BSC_CS4WCR_0_BAS_SHIFT                                                 (20u)
+#define BSC_CS4WCR_1_HW                                                        (0x00000003u)
+#define BSC_CS4WCR_1_HW_SHIFT                                                  (0u)
+#define BSC_CS4WCR_1_WM                                                        (0x00000040u)
+#define BSC_CS4WCR_1_WM_SHIFT                                                  (6u)
+#define BSC_CS4WCR_1_W                                                         (0x00000780u)
+#define BSC_CS4WCR_1_W_SHIFT                                                   (7u)
+#define BSC_CS4WCR_1_SW                                                        (0x00001800u)
+#define BSC_CS4WCR_1_SW_SHIFT                                                  (11u)
+#define BSC_CS4WCR_1_BW                                                        (0x00030000u)
+#define BSC_CS4WCR_1_BW_SHIFT                                                  (16u)
+#define BSC_CS4WCR_1_BST                                                       (0x00300000u)
+#define BSC_CS4WCR_1_BST_SHIFT                                                 (20u)
+#define BSC_CS5WCR_0_HW                                                        (0x00000003u)
+#define BSC_CS5WCR_0_HW_SHIFT                                                  (0u)
+#define BSC_CS5WCR_0_WM                                                        (0x00000040u)
+#define BSC_CS5WCR_0_WM_SHIFT                                                  (6u)
+#define BSC_CS5WCR_0_WR                                                        (0x00000780u)
+#define BSC_CS5WCR_0_WR_SHIFT                                                  (7u)
+#define BSC_CS5WCR_0_SW                                                        (0x00001800u)
+#define BSC_CS5WCR_0_SW_SHIFT                                                  (11u)
+#define BSC_CS5WCR_0_WW                                                        (0x00070000u)
+#define BSC_CS5WCR_0_WW_SHIFT                                                  (16u)
+#define BSC_CS5WCR_0_MPXWBAS                                                   (0x00100000u)
+#define BSC_CS5WCR_0_MPXWBAS_SHIFT                                             (20u)
+#define BSC_CS5WCR_0_SZSEL                                                     (0x00200000u)
+#define BSC_CS5WCR_0_SZSEL_SHIFT                                               (21u)
+#define BSC_SDCR_A3COL                                                         (0x00000003u)
+#define BSC_SDCR_A3COL_SHIFT                                                   (0u)
+#define BSC_SDCR_A3ROW                                                         (0x00000018u)
+#define BSC_SDCR_A3ROW_SHIFT                                                   (3u)
+#define BSC_SDCR_BACTV                                                         (0x00000100u)
+#define BSC_SDCR_BACTV_SHIFT                                                   (8u)
+#define BSC_SDCR_PDOWN                                                         (0x00000200u)
+#define BSC_SDCR_PDOWN_SHIFT                                                   (9u)
+#define BSC_SDCR_RMODE                                                         (0x00000400u)
+#define BSC_SDCR_RMODE_SHIFT                                                   (10u)
+#define BSC_SDCR_RFSH                                                          (0x00000800u)
+#define BSC_SDCR_RFSH_SHIFT                                                    (11u)
+#define BSC_SDCR_DEEP                                                          (0x00002000u)
+#define BSC_SDCR_DEEP_SHIFT                                                    (13u)
+#define BSC_SDCR_A2COL                                                         (0x00030000u)
+#define BSC_SDCR_A2COL_SHIFT                                                   (16u)
+#define BSC_SDCR_A2ROW                                                         (0x00180000u)
+#define BSC_SDCR_A2ROW_SHIFT                                                   (19u)
+#define BSC_RTCSR_RRC                                                          (0x00000007u)
+#define BSC_RTCSR_RRC_SHIFT                                                    (0u)
+#define BSC_RTCSR_CKS                                                          (0x00000038u)
+#define BSC_RTCSR_CKS_SHIFT                                                    (3u)
+#define BSC_RTCSR_CMIE                                                         (0x00000040u)
+#define BSC_RTCSR_CMIE_SHIFT                                                   (6u)
+#define BSC_RTCSR_CMF                                                          (0x00000080u)
+#define BSC_RTCSR_CMF_SHIFT                                                    (7u)
+#define BSC_TOSTR_CS0TOSTF                                                     (0x00000001u)
+#define BSC_TOSTR_CS0TOSTF_SHIFT                                               (0u)
+#define BSC_TOSTR_CS1TOSTF                                                     (0x00000002u)
+#define BSC_TOSTR_CS1TOSTF_SHIFT                                               (1u)
+#define BSC_TOSTR_CS2TOSTF                                                     (0x00000004u)
+#define BSC_TOSTR_CS2TOSTF_SHIFT                                               (2u)
+#define BSC_TOSTR_CS3TOSTF                                                     (0x00000008u)
+#define BSC_TOSTR_CS3TOSTF_SHIFT                                               (3u)
+#define BSC_TOSTR_CS4TOSTF                                                     (0x00000010u)
+#define BSC_TOSTR_CS4TOSTF_SHIFT                                               (4u)
+#define BSC_TOSTR_CS5TOSTF                                                     (0x00000020u)
+#define BSC_TOSTR_CS5TOSTF_SHIFT                                               (5u)
+#define BSC_TOENR_CS0TOEN                                                      (0x00000001u)
+#define BSC_TOENR_CS0TOEN_SHIFT                                                (0u)
+#define BSC_TOENR_CS1TOEN                                                      (0x00000002u)
+#define BSC_TOENR_CS1TOEN_SHIFT                                                (1u)
+#define BSC_TOENR_CS2TOEN                                                      (0x00000004u)
+#define BSC_TOENR_CS2TOEN_SHIFT                                                (2u)
+#define BSC_TOENR_CS3TOEN                                                      (0x00000008u)
+#define BSC_TOENR_CS3TOEN_SHIFT                                                (3u)
+#define BSC_TOENR_CS4TOEN                                                      (0x00000010u)
+#define BSC_TOENR_CS4TOEN_SHIFT                                                (4u)
+#define BSC_TOENR_CS5TOEN                                                      (0x00000020u)
+#define BSC_TOENR_CS5TOEN_SHIFT                                                (5u)
+#define BSC_ACADJ_SDRIDLY                                                      (0x0000000Fu)
+#define BSC_ACADJ_SDRIDLY_SHIFT                                                (0u)
+#define BSC_ACADJ_SDRODLY                                                      (0x000F0000u)
+#define BSC_ACADJ_SDRODLY_SHIFT                                                (16u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ceu_iobitmask.h

@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef CEU_IOBITMASK_H
+#define CEU_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define CEU_CAPSR_CE                                                           (0x00000001u)
+#define CEU_CAPSR_CE_SHIFT                                                     (0u)
+#define CEU_CAPSR_CPKIL                                                        (0x00010000u)
+#define CEU_CAPSR_CPKIL_SHIFT                                                  (16u)
+#define CEU_CAPCR_CTNCP                                                        (0x00010000u)
+#define CEU_CAPCR_CTNCP_SHIFT                                                  (16u)
+#define CEU_CAPCR_MTCM                                                         (0x00300000u)
+#define CEU_CAPCR_MTCM_SHIFT                                                   (20u)
+#define CEU_CAPCR_FDRP                                                         (0xFF000000u)
+#define CEU_CAPCR_FDRP_SHIFT                                                   (24u)
+#define CEU_CAMCR_HDPOL                                                        (0x00000001u)
+#define CEU_CAMCR_HDPOL_SHIFT                                                  (0u)
+#define CEU_CAMCR_VDPOL                                                        (0x00000002u)
+#define CEU_CAMCR_VDPOL_SHIFT                                                  (1u)
+#define CEU_CAMCR_JPG                                                          (0x00000030u)
+#define CEU_CAMCR_JPG_SHIFT                                                    (4u)
+#define CEU_CAMCR_DTARY                                                        (0x00000300u)
+#define CEU_CAMCR_DTARY_SHIFT                                                  (8u)
+#define CEU_CAMCR_DTIF                                                         (0x00001000u)
+#define CEU_CAMCR_DTIF_SHIFT                                                   (12u)
+#define CEU_CAMCR_FLDPOL                                                       (0x00010000u)
+#define CEU_CAMCR_FLDPOL_SHIFT                                                 (16u)
+#define CEU_CAMCR_DSEL                                                         (0x01000000u)
+#define CEU_CAMCR_DSEL_SHIFT                                                   (24u)
+#define CEU_CAMCR_FLDSEL                                                       (0x02000000u)
+#define CEU_CAMCR_FLDSEL_SHIFT                                                 (25u)
+#define CEU_CAMCR_HDSEL                                                        (0x04000000u)
+#define CEU_CAMCR_HDSEL_SHIFT                                                  (26u)
+#define CEU_CAMCR_VDSEL                                                        (0x08000000u)
+#define CEU_CAMCR_VDSEL_SHIFT                                                  (27u)
+#define CEU_CMCYR_HCYL                                                         (0x00003FFFu)
+#define CEU_CMCYR_HCYL_SHIFT                                                   (0u)
+#define CEU_CMCYR_VCYL                                                         (0x3FFF0000u)
+#define CEU_CMCYR_VCYL_SHIFT                                                   (16u)
+#define CEU_CAMOR_A_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_A_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_A_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_A_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_A_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_A_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_A_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_A_VWDTH_SHIFT                                                (16u)
+#define CEU_CAIFR_FCI                                                          (0x00000003u)
+#define CEU_CAIFR_FCI_SHIFT                                                    (0u)
+#define CEU_CAIFR_CIM                                                          (0x00000010u)
+#define CEU_CAIFR_CIM_SHIFT                                                    (4u)
+#define CEU_CAIFR_IFS                                                          (0x00000100u)
+#define CEU_CAIFR_IFS_SHIFT                                                    (8u)
+#define CEU_CRCNTR_RC                                                          (0x00000001u)
+#define CEU_CRCNTR_RC_SHIFT                                                    (0u)
+#define CEU_CRCNTR_RS                                                          (0x00000002u)
+#define CEU_CRCNTR_RS_SHIFT                                                    (1u)
+#define CEU_CRCNTR_RVS                                                         (0x00000010u)
+#define CEU_CRCNTR_RVS_SHIFT                                                   (4u)
+#define CEU_CRCMPR_RA                                                          (0x00000001u)
+#define CEU_CRCMPR_RA_SHIFT                                                    (0u)
+#define CEU_CFLCR_A_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_A_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_A_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_A_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_A_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_A_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_A_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_A_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_A_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_A_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_A_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_A_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_A_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_A_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_A_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_A_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_A_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_A_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_A_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_A_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_A_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_A_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_A_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_A_CBVS_SHIFT                                                 (0u)
+#define CEU_CFWCR_FWE                                                          (0x00000001u)
+#define CEU_CFWCR_FWE_SHIFT                                                    (0u)
+#define CEU_CFWCR_FWV                                                          (0xFFFFFFE0u)
+#define CEU_CFWCR_FWV_SHIFT                                                    (5u)
+#define CEU_CLFCR_A_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_A_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_A_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_A_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_A_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_A_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_A_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_A_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_A_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_A_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_A_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_A_CBE_SHIFT                                                  (16u)
+#define CEU_CEIER_CPEIE                                                        (0x00000001u)
+#define CEU_CEIER_CPEIE_SHIFT                                                  (0u)
+#define CEU_CEIER_CFEIE                                                        (0x00000002u)
+#define CEU_CEIER_CFEIE_SHIFT                                                  (1u)
+#define CEU_CEIER_IGRWIE                                                       (0x00000010u)
+#define CEU_CEIER_IGRWIE_SHIFT                                                 (4u)
+#define CEU_CEIER_HDIE                                                         (0x00000100u)
+#define CEU_CEIER_HDIE_SHIFT                                                   (8u)
+#define CEU_CEIER_VDIE                                                         (0x00000200u)
+#define CEU_CEIER_VDIE_SHIFT                                                   (9u)
+#define CEU_CEIER_CPBE1IE                                                      (0x00001000u)
+#define CEU_CEIER_CPBE1IE_SHIFT                                                (12u)
+#define CEU_CEIER_CPBE2IE                                                      (0x00002000u)
+#define CEU_CEIER_CPBE2IE_SHIFT                                                (13u)
+#define CEU_CEIER_CPBE3IE                                                      (0x00004000u)
+#define CEU_CEIER_CPBE3IE_SHIFT                                                (14u)
+#define CEU_CEIER_CPBE4IE                                                      (0x00008000u)
+#define CEU_CEIER_CPBE4IE_SHIFT                                                (15u)
+#define CEU_CEIER_CDTOFIE                                                      (0x00010000u)
+#define CEU_CEIER_CDTOFIE_SHIFT                                                (16u)
+#define CEU_CEIER_IGHSIE                                                       (0x00020000u)
+#define CEU_CEIER_IGHSIE_SHIFT                                                 (17u)
+#define CEU_CEIER_IGVSIE                                                       (0x00040000u)
+#define CEU_CEIER_IGVSIE_SHIFT                                                 (18u)
+#define CEU_CEIER_VBPIE                                                        (0x00100000u)
+#define CEU_CEIER_VBPIE_SHIFT                                                  (20u)
+#define CEU_CEIER_FWFIE                                                        (0x00800000u)
+#define CEU_CEIER_FWFIE_SHIFT                                                  (23u)
+#define CEU_CEIER_NHDIE                                                        (0x01000000u)
+#define CEU_CEIER_NHDIE_SHIFT                                                  (24u)
+#define CEU_CEIER_NVDIE                                                        (0x02000000u)
+#define CEU_CEIER_NVDIE_SHIFT                                                  (25u)
+#define CEU_CETCR_CPE                                                          (0x00000001u)
+#define CEU_CETCR_CPE_SHIFT                                                    (0u)
+#define CEU_CETCR_CFE                                                          (0x00000002u)
+#define CEU_CETCR_CFE_SHIFT                                                    (1u)
+#define CEU_CETCR_IGRW                                                         (0x00000010u)
+#define CEU_CETCR_IGRW_SHIFT                                                   (4u)
+#define CEU_CETCR_HD                                                           (0x00000100u)
+#define CEU_CETCR_HD_SHIFT                                                     (8u)
+#define CEU_CETCR_VD                                                           (0x00000200u)
+#define CEU_CETCR_VD_SHIFT                                                     (9u)
+#define CEU_CETCR_CPBE1                                                        (0x00001000u)
+#define CEU_CETCR_CPBE1_SHIFT                                                  (12u)
+#define CEU_CETCR_CPBE2                                                        (0x00002000u)
+#define CEU_CETCR_CPBE2_SHIFT                                                  (13u)
+#define CEU_CETCR_CPBE3                                                        (0x00004000u)
+#define CEU_CETCR_CPBE3_SHIFT                                                  (14u)
+#define CEU_CETCR_CPBE4                                                        (0x00008000u)
+#define CEU_CETCR_CPBE4_SHIFT                                                  (15u)
+#define CEU_CETCR_CDTOF                                                        (0x00010000u)
+#define CEU_CETCR_CDTOF_SHIFT                                                  (16u)
+#define CEU_CETCR_IGHS                                                         (0x00020000u)
+#define CEU_CETCR_IGHS_SHIFT                                                   (17u)
+#define CEU_CETCR_IGVS                                                         (0x00040000u)
+#define CEU_CETCR_IGVS_SHIFT                                                   (18u)
+#define CEU_CETCR_VBP                                                          (0x00100000u)
+#define CEU_CETCR_VBP_SHIFT                                                    (20u)
+#define CEU_CETCR_FWF                                                          (0x00800000u)
+#define CEU_CETCR_FWF_SHIFT                                                    (23u)
+#define CEU_CETCR_NHD                                                          (0x01000000u)
+#define CEU_CETCR_NHD_SHIFT                                                    (24u)
+#define CEU_CETCR_NVD                                                          (0x02000000u)
+#define CEU_CETCR_NVD_SHIFT                                                    (25u)
+#define CEU_CSTSR_CPTON                                                        (0x00000001u)
+#define CEU_CSTSR_CPTON_SHIFT                                                  (0u)
+#define CEU_CSTSR_CPFLD                                                        (0x00010000u)
+#define CEU_CSTSR_CPFLD_SHIFT                                                  (16u)
+#define CEU_CSTSR_CRST                                                         (0x01000000u)
+#define CEU_CSTSR_CRST_SHIFT                                                   (24u)
+#define CEU_CDSSR_CDSS                                                         (0xFFFFFFFFu)
+#define CEU_CDSSR_CDSS_SHIFT                                                   (0u)
+#define CEU_CDAYR2_A_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_A_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_A_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_A_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_A_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_A_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_A_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_A_CBCR2_SHIFT                                               (0u)
+#define CEU_CAMOR_B_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_B_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_B_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_B_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_B_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_B_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_B_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_B_VWDTH_SHIFT                                                (16u)
+#define CEU_CFLCR_B_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_B_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_B_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_B_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_B_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_B_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_B_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_B_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_B_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_B_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_B_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_B_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_B_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_B_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_B_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_B_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_B_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_B_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_B_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_B_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_B_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_B_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_B_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_B_CBVS_SHIFT                                                 (0u)
+#define CEU_CLFCR_B_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_B_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_B_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_B_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_B_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_B_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_B_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_B_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_B_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_B_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_B_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_B_CBE_SHIFT                                                  (16u)
+#define CEU_CDAYR2_B_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_B_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_B_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_B_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_B_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_B_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_B_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_B_CBCR2_SHIFT                                               (0u)
+#define CEU_CAMOR_M_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_M_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_M_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_M_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_M_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_M_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_M_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_M_VWDTH_SHIFT                                                (16u)
+#define CEU_CFLCR_M_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_M_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_M_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_M_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_M_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_M_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_M_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_M_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_M_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_M_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_M_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_M_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_M_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_M_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_M_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_M_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_M_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_M_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_M_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_M_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_M_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_M_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_M_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_M_CBVS_SHIFT                                                 (0u)
+#define CEU_CLFCR_M_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_M_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_M_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_M_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_M_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_M_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_M_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_M_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_M_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_M_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_M_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_M_CBE_SHIFT                                                  (16u)
+#define CEU_CDAYR2_M_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_M_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_M_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_M_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_M_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_M_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_M_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_M_CBCR2_SHIFT                                               (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/cpg_iobitmask.h

@@ -0,0 +1,302 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef CPG_IOBITMASK_H
+#define CPG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define CPG_FRQCR_PFC                                                          (0x0003u)
+#define CPG_FRQCR_PFC_SHIFT                                                    (0u)
+#define CPG_FRQCR_BFC                                                          (0x0030u)
+#define CPG_FRQCR_BFC_SHIFT                                                    (4u)
+#define CPG_FRQCR_IFC                                                          (0x0300u)
+#define CPG_FRQCR_IFC_SHIFT                                                    (8u)
+#define CPG_FRQCR_CKOEN                                                        (0x3000u)
+#define CPG_FRQCR_CKOEN_SHIFT                                                  (12u)
+#define CPG_FRQCR_CKOEN2                                                       (0x4000u)
+#define CPG_FRQCR_CKOEN2_SHIFT                                                 (14u)
+#define CPG_CPUSTS_ISBUSY                                                      (0x10u)
+#define CPG_CPUSTS_ISBUSY_SHIFT                                                (4u)
+#define CPG_STBCR1_DEEP                                                        (0x40u)
+#define CPG_STBCR1_DEEP_SHIFT                                                  (6u)
+#define CPG_STBCR1_STBY                                                        (0x80u)
+#define CPG_STBCR1_STBY_SHIFT                                                  (7u)
+#define CPG_STBCR2_MSTP20                                                      (0x01u)
+#define CPG_STBCR2_MSTP20_SHIFT                                                (0u)
+#define CPG_STBCR2_HIZ                                                         (0x80u)
+#define CPG_STBCR2_HIZ_SHIFT                                                   (7u)
+#define CPG_STBREQ1_STBRQ10                                                    (0x01u)
+#define CPG_STBREQ1_STBRQ10_SHIFT                                              (0u)
+#define CPG_STBREQ1_STBRQ11                                                    (0x02u)
+#define CPG_STBREQ1_STBRQ11_SHIFT                                              (1u)
+#define CPG_STBREQ1_STBRQ12                                                    (0x04u)
+#define CPG_STBREQ1_STBRQ12_SHIFT                                              (2u)
+#define CPG_STBREQ1_STBRQ13                                                    (0x08u)
+#define CPG_STBREQ1_STBRQ13_SHIFT                                              (3u)
+#define CPG_STBREQ1_STBRQ15                                                    (0x20u)
+#define CPG_STBREQ1_STBRQ15_SHIFT                                              (5u)
+#define CPG_STBREQ2_STBRQ20                                                    (0x01u)
+#define CPG_STBREQ2_STBRQ20_SHIFT                                              (0u)
+#define CPG_STBREQ2_STBRQ21                                                    (0x02u)
+#define CPG_STBREQ2_STBRQ21_SHIFT                                              (1u)
+#define CPG_STBREQ2_STBRQ22                                                    (0x04u)
+#define CPG_STBREQ2_STBRQ22_SHIFT                                              (2u)
+#define CPG_STBREQ2_STBRQ23                                                    (0x08u)
+#define CPG_STBREQ2_STBRQ23_SHIFT                                              (3u)
+#define CPG_STBREQ2_STBRQ24                                                    (0x10u)
+#define CPG_STBREQ2_STBRQ24_SHIFT                                              (4u)
+#define CPG_STBREQ2_STBRQ25                                                    (0x20u)
+#define CPG_STBREQ2_STBRQ25_SHIFT                                              (5u)
+#define CPG_STBREQ2_STBRQ26                                                    (0x40u)
+#define CPG_STBREQ2_STBRQ26_SHIFT                                              (6u)
+#define CPG_STBREQ2_STBRQ27                                                    (0x80u)
+#define CPG_STBREQ2_STBRQ27_SHIFT                                              (7u)
+#define CPG_STBREQ3_STBRQ30                                                    (0x01u)
+#define CPG_STBREQ3_STBRQ30_SHIFT                                              (0u)
+#define CPG_STBREQ3_STBRQ31                                                    (0x02u)
+#define CPG_STBREQ3_STBRQ31_SHIFT                                              (1u)
+#define CPG_STBREQ3_STBRQ32                                                    (0x04u)
+#define CPG_STBREQ3_STBRQ32_SHIFT                                              (2u)
+#define CPG_STBREQ3_STBRQ33                                                    (0x08u)
+#define CPG_STBREQ3_STBRQ33_SHIFT                                              (3u)
+#define CPG_STBACK1_STBAK10                                                    (0x01u)
+#define CPG_STBACK1_STBAK10_SHIFT                                              (0u)
+#define CPG_STBACK1_STBAK11                                                    (0x02u)
+#define CPG_STBACK1_STBAK11_SHIFT                                              (1u)
+#define CPG_STBACK1_STBAK12                                                    (0x04u)
+#define CPG_STBACK1_STBAK12_SHIFT                                              (2u)
+#define CPG_STBACK1_STBAK13                                                    (0x08u)
+#define CPG_STBACK1_STBAK13_SHIFT                                              (3u)
+#define CPG_STBACK1_STBAK15                                                    (0x20u)
+#define CPG_STBACK1_STBAK15_SHIFT                                              (5u)
+#define CPG_STBACK2_STBAK20                                                    (0x01u)
+#define CPG_STBACK2_STBAK20_SHIFT                                              (0u)
+#define CPG_STBACK2_STBAK21                                                    (0x02u)
+#define CPG_STBACK2_STBAK21_SHIFT                                              (1u)
+#define CPG_STBACK2_STBAK22                                                    (0x04u)
+#define CPG_STBACK2_STBAK22_SHIFT                                              (2u)
+#define CPG_STBACK2_STBAK23                                                    (0x08u)
+#define CPG_STBACK2_STBAK23_SHIFT                                              (3u)
+#define CPG_STBACK2_STBAK24                                                    (0x10u)
+#define CPG_STBACK2_STBAK24_SHIFT                                              (4u)
+#define CPG_STBACK2_STBAK25                                                    (0x20u)
+#define CPG_STBACK2_STBAK25_SHIFT                                              (5u)
+#define CPG_STBACK2_STBAK26                                                    (0x40u)
+#define CPG_STBACK2_STBAK26_SHIFT                                              (6u)
+#define CPG_STBACK2_STBAK27                                                    (0x80u)
+#define CPG_STBACK2_STBAK27_SHIFT                                              (7u)
+#define CPG_STBACK3_STBAK30                                                    (0x01u)
+#define CPG_STBACK3_STBAK30_SHIFT                                              (0u)
+#define CPG_STBACK3_STBAK31                                                    (0x02u)
+#define CPG_STBACK3_STBAK31_SHIFT                                              (1u)
+#define CPG_STBACK3_STBAK32                                                    (0x04u)
+#define CPG_STBACK3_STBAK32_SHIFT                                              (2u)
+#define CPG_STBACK3_STBAK33                                                    (0x08u)
+#define CPG_STBACK3_STBAK33_SHIFT                                              (3u)
+#define CPG_CKIOSEL_CKIOSEL                                                    (0x0003u)
+#define CPG_CKIOSEL_CKIOSEL_SHIFT                                              (0u)
+#define CPG_SCLKSEL_SPICR                                                      (0x0003u)
+#define CPG_SCLKSEL_SPICR_SHIFT                                                (0u)
+#define CPG_SCLKSEL_HYMCR                                                      (0x0030u)
+#define CPG_SCLKSEL_HYMCR_SHIFT                                                (4u)
+#define CPG_SCLKSEL_OCTCR                                                      (0x0300u)
+#define CPG_SCLKSEL_OCTCR_SHIFT                                                (8u)
+#define CPG_SYSCR1_VRAME0                                                      (0x01u)
+#define CPG_SYSCR1_VRAME0_SHIFT                                                (0u)
+#define CPG_SYSCR1_VRAME1                                                      (0x02u)
+#define CPG_SYSCR1_VRAME1_SHIFT                                                (1u)
+#define CPG_SYSCR1_VRAME2                                                      (0x04u)
+#define CPG_SYSCR1_VRAME2_SHIFT                                                (2u)
+#define CPG_SYSCR1_VRAME3                                                      (0x08u)
+#define CPG_SYSCR1_VRAME3_SHIFT                                                (3u)
+#define CPG_SYSCR1_VRAME4                                                      (0x10u)
+#define CPG_SYSCR1_VRAME4_SHIFT                                                (4u)
+#define CPG_SYSCR2_VRAMWE0                                                     (0x01u)
+#define CPG_SYSCR2_VRAMWE0_SHIFT                                               (0u)
+#define CPG_SYSCR2_VRAMWE1                                                     (0x02u)
+#define CPG_SYSCR2_VRAMWE1_SHIFT                                               (1u)
+#define CPG_SYSCR2_VRAMWE2                                                     (0x04u)
+#define CPG_SYSCR2_VRAMWE2_SHIFT                                               (2u)
+#define CPG_SYSCR2_VRAMWE3                                                     (0x08u)
+#define CPG_SYSCR2_VRAMWE3_SHIFT                                               (3u)
+#define CPG_SYSCR2_VRAMWE4                                                     (0x10u)
+#define CPG_SYSCR2_VRAMWE4_SHIFT                                               (4u)
+#define CPG_SYSCR3_RRAMWE0                                                     (0x01u)
+#define CPG_SYSCR3_RRAMWE0_SHIFT                                               (0u)
+#define CPG_SYSCR3_RRAMWE1                                                     (0x02u)
+#define CPG_SYSCR3_RRAMWE1_SHIFT                                               (1u)
+#define CPG_SYSCR3_RRAMWE2                                                     (0x04u)
+#define CPG_SYSCR3_RRAMWE2_SHIFT                                               (2u)
+#define CPG_SYSCR3_RRAMWE3                                                     (0x08u)
+#define CPG_SYSCR3_RRAMWE3_SHIFT                                               (3u)
+#define CPG_STBCR3_MSTP30                                                      (0x01u)
+#define CPG_STBCR3_MSTP30_SHIFT                                                (0u)
+#define CPG_STBCR3_MSTP31                                                      (0x02u)
+#define CPG_STBCR3_MSTP31_SHIFT                                                (1u)
+#define CPG_STBCR3_MSTP32                                                      (0x04u)
+#define CPG_STBCR3_MSTP32_SHIFT                                                (2u)
+#define CPG_STBCR3_MSTP33                                                      (0x08u)
+#define CPG_STBCR3_MSTP33_SHIFT                                                (3u)
+#define CPG_STBCR3_MSTP34                                                      (0x10u)
+#define CPG_STBCR3_MSTP34_SHIFT                                                (4u)
+#define CPG_STBCR3_MSTP35                                                      (0x20u)
+#define CPG_STBCR3_MSTP35_SHIFT                                                (5u)
+#define CPG_STBCR3_MSTP36                                                      (0x40u)
+#define CPG_STBCR3_MSTP36_SHIFT                                                (6u)
+#define CPG_STBCR4_MSTP40                                                      (0x01u)
+#define CPG_STBCR4_MSTP40_SHIFT                                                (0u)
+#define CPG_STBCR4_MSTP41                                                      (0x02u)
+#define CPG_STBCR4_MSTP41_SHIFT                                                (1u)
+#define CPG_STBCR4_MSTP42                                                      (0x04u)
+#define CPG_STBCR4_MSTP42_SHIFT                                                (2u)
+#define CPG_STBCR4_MSTP43                                                      (0x08u)
+#define CPG_STBCR4_MSTP43_SHIFT                                                (3u)
+#define CPG_STBCR4_MSTP44                                                      (0x10u)
+#define CPG_STBCR4_MSTP44_SHIFT                                                (4u)
+#define CPG_STBCR4_MSTP45                                                      (0x20u)
+#define CPG_STBCR4_MSTP45_SHIFT                                                (5u)
+#define CPG_STBCR4_MSTP46                                                      (0x40u)
+#define CPG_STBCR4_MSTP46_SHIFT                                                (6u)
+#define CPG_STBCR4_MSTP47                                                      (0x80u)
+#define CPG_STBCR4_MSTP47_SHIFT                                                (7u)
+#define CPG_STBCR5_MSTP51                                                      (0x02u)
+#define CPG_STBCR5_MSTP51_SHIFT                                                (1u)
+#define CPG_STBCR5_MSTP52                                                      (0x04u)
+#define CPG_STBCR5_MSTP52_SHIFT                                                (2u)
+#define CPG_STBCR5_MSTP53                                                      (0x08u)
+#define CPG_STBCR5_MSTP53_SHIFT                                                (3u)
+#define CPG_STBCR5_MSTP56                                                      (0x40u)
+#define CPG_STBCR5_MSTP56_SHIFT                                                (6u)
+#define CPG_STBCR5_MSTP57                                                      (0x80u)
+#define CPG_STBCR5_MSTP57_SHIFT                                                (7u)
+#define CPG_STBCR6_MSTP60                                                      (0x01u)
+#define CPG_STBCR6_MSTP60_SHIFT                                                (0u)
+#define CPG_STBCR6_MSTP61                                                      (0x02u)
+#define CPG_STBCR6_MSTP61_SHIFT                                                (1u)
+#define CPG_STBCR6_MSTP62                                                      (0x04u)
+#define CPG_STBCR6_MSTP62_SHIFT                                                (2u)
+#define CPG_STBCR6_MSTP63                                                      (0x08u)
+#define CPG_STBCR6_MSTP63_SHIFT                                                (3u)
+#define CPG_STBCR6_MSTP64                                                      (0x10u)
+#define CPG_STBCR6_MSTP64_SHIFT                                                (4u)
+#define CPG_STBCR6_MSTP65                                                      (0x20u)
+#define CPG_STBCR6_MSTP65_SHIFT                                                (5u)
+#define CPG_STBCR6_MSTP66                                                      (0x40u)
+#define CPG_STBCR6_MSTP66_SHIFT                                                (6u)
+#define CPG_STBCR7_MSTP70                                                      (0x01u)
+#define CPG_STBCR7_MSTP70_SHIFT                                                (0u)
+#define CPG_STBCR7_MSTP71                                                      (0x02u)
+#define CPG_STBCR7_MSTP71_SHIFT                                                (1u)
+#define CPG_STBCR7_MSTP72                                                      (0x04u)
+#define CPG_STBCR7_MSTP72_SHIFT                                                (2u)
+#define CPG_STBCR7_MSTP73                                                      (0x08u)
+#define CPG_STBCR7_MSTP73_SHIFT                                                (3u)
+#define CPG_STBCR7_MSTP75                                                      (0x20u)
+#define CPG_STBCR7_MSTP75_SHIFT                                                (5u)
+#define CPG_STBCR7_MSTP76                                                      (0x40u)
+#define CPG_STBCR7_MSTP76_SHIFT                                                (6u)
+#define CPG_STBCR7_MSTP77                                                      (0x80u)
+#define CPG_STBCR7_MSTP77_SHIFT                                                (7u)
+#define CPG_STBCR8_MSTP81                                                      (0x02u)
+#define CPG_STBCR8_MSTP81_SHIFT                                                (1u)
+#define CPG_STBCR8_MSTP83                                                      (0x08u)
+#define CPG_STBCR8_MSTP83_SHIFT                                                (3u)
+#define CPG_STBCR8_MSTP84                                                      (0x10u)
+#define CPG_STBCR8_MSTP84_SHIFT                                                (4u)
+#define CPG_STBCR8_MSTP85                                                      (0x20u)
+#define CPG_STBCR8_MSTP85_SHIFT                                                (5u)
+#define CPG_STBCR8_MSTP86                                                      (0x40u)
+#define CPG_STBCR8_MSTP86_SHIFT                                                (6u)
+#define CPG_STBCR8_MSTP87                                                      (0x80u)
+#define CPG_STBCR8_MSTP87_SHIFT                                                (7u)
+#define CPG_STBCR9_MSTP90                                                      (0x01u)
+#define CPG_STBCR9_MSTP90_SHIFT                                                (0u)
+#define CPG_STBCR9_MSTP91                                                      (0x02u)
+#define CPG_STBCR9_MSTP91_SHIFT                                                (1u)
+#define CPG_STBCR9_MSTP92                                                      (0x04u)
+#define CPG_STBCR9_MSTP92_SHIFT                                                (2u)
+#define CPG_STBCR9_MSTP93                                                      (0x08u)
+#define CPG_STBCR9_MSTP93_SHIFT                                                (3u)
+#define CPG_STBCR9_MSTP95                                                      (0x20u)
+#define CPG_STBCR9_MSTP95_SHIFT                                                (5u)
+#define CPG_STBCR9_MSTP96                                                      (0x40u)
+#define CPG_STBCR9_MSTP96_SHIFT                                                (6u)
+#define CPG_STBCR9_MSTP97                                                      (0x80u)
+#define CPG_STBCR9_MSTP97_SHIFT                                                (7u)
+#define CPG_STBCR10_MSTP100                                                    (0x01u)
+#define CPG_STBCR10_MSTP100_SHIFT                                              (0u)
+#define CPG_STBCR10_MSTP101                                                    (0x02u)
+#define CPG_STBCR10_MSTP101_SHIFT                                              (1u)
+#define CPG_STBCR10_MSTP102                                                    (0x04u)
+#define CPG_STBCR10_MSTP102_SHIFT                                              (2u)
+#define CPG_STBCR10_MSTP103                                                    (0x08u)
+#define CPG_STBCR10_MSTP103_SHIFT                                              (3u)
+#define CPG_STBCR10_MSTP104                                                    (0x10u)
+#define CPG_STBCR10_MSTP104_SHIFT                                              (4u)
+#define CPG_STBCR10_MSTP107                                                    (0x80u)
+#define CPG_STBCR10_MSTP107_SHIFT                                              (7u)
+#define CPG_SWRSTCR1_SRST10                                                    (0x01u)
+#define CPG_SWRSTCR1_SRST10_SHIFT                                              (0u)
+#define CPG_SWRSTCR1_SRST11                                                    (0x02u)
+#define CPG_SWRSTCR1_SRST11_SHIFT                                              (1u)
+#define CPG_SWRSTCR1_SRST12                                                    (0x04u)
+#define CPG_SWRSTCR1_SRST12_SHIFT                                              (2u)
+#define CPG_SWRSTCR1_SRST13                                                    (0x08u)
+#define CPG_SWRSTCR1_SRST13_SHIFT                                              (3u)
+#define CPG_SWRSTCR1_AXTALE                                                    (0x80u)
+#define CPG_SWRSTCR1_AXTALE_SHIFT                                              (7u)
+#define CPG_SWRSTCR2_SRST21                                                    (0x02u)
+#define CPG_SWRSTCR2_SRST21_SHIFT                                              (1u)
+#define CPG_SWRSTCR2_SRST22                                                    (0x04u)
+#define CPG_SWRSTCR2_SRST22_SHIFT                                              (2u)
+#define CPG_SWRSTCR2_SRST23                                                    (0x08u)
+#define CPG_SWRSTCR2_SRST23_SHIFT                                              (3u)
+#define CPG_SWRSTCR2_SRST24                                                    (0x10u)
+#define CPG_SWRSTCR2_SRST24_SHIFT                                              (4u)
+#define CPG_SWRSTCR2_SRST25                                                    (0x20u)
+#define CPG_SWRSTCR2_SRST25_SHIFT                                              (5u)
+#define CPG_SWRSTCR2_SRST26                                                    (0x40u)
+#define CPG_SWRSTCR2_SRST26_SHIFT                                              (6u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/csi2link_iobitmask.h

@@ -0,0 +1,368 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef CSI2LINK_IOBITMASK_H
+#define CSI2LINK_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define CSI2LINK_TREF_TREF                                                     (0x00000001u)
+#define CSI2LINK_TREF_TREF_SHIFT                                               (0u)
+#define CSI2LINK_SRST_SRST                                                     (0x00000001u)
+#define CSI2LINK_SRST_SRST_SHIFT                                               (0u)
+#define CSI2LINK_PHYCNT_ENABLE_0                                               (0x00000001u)
+#define CSI2LINK_PHYCNT_ENABLE_0_SHIFT                                         (0u)
+#define CSI2LINK_PHYCNT_ENABLE_1                                               (0x00000002u)
+#define CSI2LINK_PHYCNT_ENABLE_1_SHIFT                                         (1u)
+#define CSI2LINK_PHYCNT_ENABLECLK                                              (0x00000010u)
+#define CSI2LINK_PHYCNT_ENABLECLK_SHIFT                                        (4u)
+#define CSI2LINK_PHYCNT_RSTZ                                                   (0x00010000u)
+#define CSI2LINK_PHYCNT_RSTZ_SHIFT                                             (16u)
+#define CSI2LINK_PHYCNT_SHUTDOWNZ                                              (0x00020000u)
+#define CSI2LINK_PHYCNT_SHUTDOWNZ_SHIFT                                        (17u)
+#define CSI2LINK_CHKSUM_CRC_EN                                                 (0x00000001u)
+#define CSI2LINK_CHKSUM_CRC_EN_SHIFT                                           (0u)
+#define CSI2LINK_CHKSUM_ECC_EN                                                 (0x00000002u)
+#define CSI2LINK_CHKSUM_ECC_EN_SHIFT                                           (1u)
+#define CSI2LINK_VCDT_SEL_DT                                                   (0x0000003Fu)
+#define CSI2LINK_VCDT_SEL_DT_SHIFT                                             (0u)
+#define CSI2LINK_VCDT_SEL_DT_ON                                                (0x00000040u)
+#define CSI2LINK_VCDT_SEL_DT_ON_SHIFT                                          (6u)
+#define CSI2LINK_VCDT_SEL_VC                                                   (0x00000300u)
+#define CSI2LINK_VCDT_SEL_VC_SHIFT                                             (8u)
+#define CSI2LINK_VCDT_VCDT_EN                                                  (0x00008000u)
+#define CSI2LINK_VCDT_VCDT_EN_SHIFT                                            (15u)
+#define CSI2LINK_FRDT_DT_FE                                                    (0x003F0000u)
+#define CSI2LINK_FRDT_DT_FE_SHIFT                                              (16u)
+#define CSI2LINK_FRDT_DT_FS                                                    (0x3F000000u)
+#define CSI2LINK_FRDT_DT_FS_SHIFT                                              (24u)
+#define CSI2LINK_FLD_FLD_EN                                                    (0x00000001u)
+#define CSI2LINK_FLD_FLD_EN_SHIFT                                              (0u)
+#define CSI2LINK_FLD_FLD_DET_SEL                                               (0x00000030u)
+#define CSI2LINK_FLD_FLD_DET_SEL_SHIFT                                         (4u)
+#define CSI2LINK_FLD_FLD_NUM                                                   (0xFFFF0000u)
+#define CSI2LINK_FLD_FLD_NUM_SHIFT                                             (16u)
+#define CSI2LINK_ASTBY_AUTO_STANDBY_EN                                         (0x0000001Fu)
+#define CSI2LINK_ASTBY_AUTO_STANDBY_EN_SHIFT                                   (0u)
+#define CSI2LINK_ASTBY_VD_MSK_EN                                               (0x00000020u)
+#define CSI2LINK_ASTBY_VD_MSK_EN_SHIFT                                         (5u)
+#define CSI2LINK_ASTBY_VD_MSK_CYCLE                                            (0x00003F00u)
+#define CSI2LINK_ASTBY_VD_MSK_CYCLE_SHIFT                                      (8u)
+#define CSI2LINK_LNGDT0_LNGDT0                                                 (0xFFFFFFFFu)
+#define CSI2LINK_LNGDT0_LNGDT0_SHIFT                                           (0u)
+#define CSI2LINK_LNGDT1_LNGDT1                                                 (0xFFFFFFFFu)
+#define CSI2LINK_LNGDT1_LNGDT1_SHIFT                                           (0u)
+#define CSI2LINK_INTEN_IEN                                                     (0xFFFFFFFFu)
+#define CSI2LINK_INTEN_IEN_SHIFT                                               (0u)
+#define CSI2LINK_INTCLOSE_ICL                                                  (0xFFFFFFFFu)
+#define CSI2LINK_INTCLOSE_ICL_SHIFT                                            (0u)
+#define CSI2LINK_INTSTATE_IST                                                  (0xFFFFFFFFu)
+#define CSI2LINK_INTSTATE_IST_SHIFT                                            (0u)
+#define CSI2LINK_INTERRSTATE_IEST                                              (0x0000FFFFu)
+#define CSI2LINK_INTERRSTATE_IEST_SHIFT                                        (0u)
+#define CSI2LINK_SHPDAT_DT                                                     (0x0000003Fu)
+#define CSI2LINK_SHPDAT_DT_SHIFT                                               (0u)
+#define CSI2LINK_SHPDAT_VC                                                     (0x000000C0u)
+#define CSI2LINK_SHPDAT_VC_SHIFT                                               (6u)
+#define CSI2LINK_SHPDAT_DATA                                                   (0x00FFFF00u)
+#define CSI2LINK_SHPDAT_DATA_SHIFT                                             (8u)
+#define CSI2LINK_SHPDAT_ECC                                                    (0xFF000000u)
+#define CSI2LINK_SHPDAT_ECC_SHIFT                                              (24u)
+#define CSI2LINK_SHPCNT_NUM                                                    (0x0000000Fu)
+#define CSI2LINK_SHPCNT_NUM_SHIFT                                              (0u)
+#define CSI2LINK_SHPCNT_OVF                                                    (0x00010000u)
+#define CSI2LINK_SHPCNT_OVF_SHIFT                                              (16u)
+#define CSI2LINK_LINKCNT_REG_MONI_PACT_EN                                      (0x02000000u)
+#define CSI2LINK_LINKCNT_REG_MONI_PACT_EN_SHIFT                                (25u)
+#define CSI2LINK_LINKCNT_MONITOR_EN                                            (0x80000000u)
+#define CSI2LINK_LINKCNT_MONITOR_EN_SHIFT                                      (31u)
+#define CSI2LINK_LSWAP_L0SEL                                                   (0x00000003u)
+#define CSI2LINK_LSWAP_L0SEL_SHIFT                                             (0u)
+#define CSI2LINK_LSWAP_L1SEL                                                   (0x0000000Cu)
+#define CSI2LINK_LSWAP_L1SEL_SHIFT                                             (2u)
+#define CSI2LINK_PHEERM_ERRCONTROL_0                                           (0x00000001u)
+#define CSI2LINK_PHEERM_ERRCONTROL_0_SHIFT                                     (0u)
+#define CSI2LINK_PHEERM_ERRCONTROL_1                                           (0x00000002u)
+#define CSI2LINK_PHEERM_ERRCONTROL_1_SHIFT                                     (1u)
+#define CSI2LINK_PHEERM_ERRESC_0                                               (0x00000100u)
+#define CSI2LINK_PHEERM_ERRESC_0_SHIFT                                         (8u)
+#define CSI2LINK_PHEERM_ERRESC_1                                               (0x00000200u)
+#define CSI2LINK_PHEERM_ERRESC_1_SHIFT                                         (9u)
+#define CSI2LINK_PHEERM_CL_ERRCONTROL                                          (0x00001000u)
+#define CSI2LINK_PHEERM_CL_ERRCONTROL_SHIFT                                    (12u)
+#define CSI2LINK_PHCLM_STOPSTATECLK                                            (0x00000001u)
+#define CSI2LINK_PHCLM_STOPSTATECLK_SHIFT                                      (0u)
+#define CSI2LINK_PHCLM_RXCLKACTIVEHS                                           (0x00000002u)
+#define CSI2LINK_PHCLM_RXCLKACTIVEHS_SHIFT                                     (1u)
+#define CSI2LINK_PHCLM_RXULPSCLKNOT                                            (0x00000004u)
+#define CSI2LINK_PHCLM_RXULPSCLKNOT_SHIFT                                      (2u)
+#define CSI2LINK_PHCLM_ULPSACTIVENOTCLK                                        (0x00000008u)
+#define CSI2LINK_PHCLM_ULPSACTIVENOTCLK_SHIFT                                  (3u)
+#define CSI2LINK_PHDLM_STOPSTATEDATA_0                                         (0x00000001u)
+#define CSI2LINK_PHDLM_STOPSTATEDATA_0_SHIFT                                   (0u)
+#define CSI2LINK_PHDLM_STOPSTATEDATA_1                                         (0x00000002u)
+#define CSI2LINK_PHDLM_STOPSTATEDATA_1_SHIFT                                   (1u)
+#define CSI2LINK_PHDLM_RXULPSESC_0                                             (0x00000100u)
+#define CSI2LINK_PHDLM_RXULPSESC_0_SHIFT                                       (8u)
+#define CSI2LINK_PHDLM_RXULPSESC_1                                             (0x00000200u)
+#define CSI2LINK_PHDLM_RXULPSESC_1_SHIFT                                       (9u)
+#define CSI2LINK_PHDLM_ULPSACTIVENOT_0                                         (0x00001000u)
+#define CSI2LINK_PHDLM_ULPSACTIVENOT_0_SHIFT                                   (12u)
+#define CSI2LINK_PHDLM_ULPSACTIVENOT_1                                         (0x00002000u)
+#define CSI2LINK_PHDLM_ULPSACTIVENOT_1_SHIFT                                   (13u)
+#define CSI2LINK_PH0M0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PH0M0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PH0M0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PH0M0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PH0M0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PH0M0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PH0M1_PH_CNT                                                  (0x0000FFFFu)
+#define CSI2LINK_PH0M1_PH_CNT_SHIFT                                            (0u)
+#define CSI2LINK_PH1M0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PH1M0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PH1M0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PH1M0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PH1M0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PH1M0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PH1M1_PH_CNT                                                  (0x0000FFFFu)
+#define CSI2LINK_PH1M1_PH_CNT_SHIFT                                            (0u)
+#define CSI2LINK_PH2M0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PH2M0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PH2M0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PH2M0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PH2M0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PH2M0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PH2M1_PH_CNT                                                  (0x0000FFFFu)
+#define CSI2LINK_PH2M1_PH_CNT_SHIFT                                            (0u)
+#define CSI2LINK_PH3M0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PH3M0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PH3M0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PH3M0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PH3M0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PH3M0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PH3M1_PH_CNT                                                  (0x0000FFFFu)
+#define CSI2LINK_PH3M1_PH_CNT_SHIFT                                            (0u)
+#define CSI2LINK_PHRM0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PHRM0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PHRM0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PHRM0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PHRM0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PHRM0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PHRM0_ECC                                                     (0xFF000000u)
+#define CSI2LINK_PHRM0_ECC_SHIFT                                               (24u)
+#define CSI2LINK_PHRM1_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PHRM1_DT_SHIFT                                                (0u)
+#define CSI2LINK_PHRM1_VC                                                      (0x000000C0u)
+#define CSI2LINK_PHRM1_VC_SHIFT                                                (6u)
+#define CSI2LINK_PHRM1_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PHRM1_WC_SHIFT                                                (8u)
+#define CSI2LINK_PHRM1_ECC                                                     (0xFF000000u)
+#define CSI2LINK_PHRM1_ECC_SHIFT                                               (24u)
+#define CSI2LINK_PHRM2_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PHRM2_DT_SHIFT                                                (0u)
+#define CSI2LINK_PHRM2_VC                                                      (0x000000C0u)
+#define CSI2LINK_PHRM2_VC_SHIFT                                                (6u)
+#define CSI2LINK_PHRM2_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PHRM2_WC_SHIFT                                                (8u)
+#define CSI2LINK_PHRM2_ECC                                                     (0xFF000000u)
+#define CSI2LINK_PHRM2_ECC_SHIFT                                               (24u)
+#define CSI2LINK_PHCM0_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PHCM0_DT_SHIFT                                                (0u)
+#define CSI2LINK_PHCM0_VC                                                      (0x000000C0u)
+#define CSI2LINK_PHCM0_VC_SHIFT                                                (6u)
+#define CSI2LINK_PHCM0_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PHCM0_WC_SHIFT                                                (8u)
+#define CSI2LINK_PHCM0_CAL_PARITY                                              (0xFF000000u)
+#define CSI2LINK_PHCM0_CAL_PARITY_SHIFT                                        (24u)
+#define CSI2LINK_PHCM1_DT                                                      (0x0000003Fu)
+#define CSI2LINK_PHCM1_DT_SHIFT                                                (0u)
+#define CSI2LINK_PHCM1_VC                                                      (0x000000C0u)
+#define CSI2LINK_PHCM1_VC_SHIFT                                                (6u)
+#define CSI2LINK_PHCM1_WC                                                      (0x00FFFF00u)
+#define CSI2LINK_PHCM1_WC_SHIFT                                                (8u)
+#define CSI2LINK_PHCM1_CAL_PARITY                                              (0xFF000000u)
+#define CSI2LINK_PHCM1_CAL_PARITY_SHIFT                                        (24u)
+#define CSI2LINK_CRCM0_CAL_CRC                                                 (0x0000FFFFu)
+#define CSI2LINK_CRCM0_CAL_CRC_SHIFT                                           (0u)
+#define CSI2LINK_CRCM0_CRC                                                     (0xFFFF0000u)
+#define CSI2LINK_CRCM0_CRC_SHIFT                                               (16u)
+#define CSI2LINK_CRCM1_CAL_CRC                                                 (0x0000FFFFu)
+#define CSI2LINK_CRCM1_CAL_CRC_SHIFT                                           (0u)
+#define CSI2LINK_CRCM1_CRC                                                     (0xFFFF0000u)
+#define CSI2LINK_CRCM1_CRC_SHIFT                                               (16u)
+#define CSI2LINK_SERRCNT_ERRSOTHS_CNT                                          (0x000000FFu)
+#define CSI2LINK_SERRCNT_ERRSOTHS_CNT_SHIFT                                    (0u)
+#define CSI2LINK_SSERRCNT_ERRSOTSYNCHS                                         (0x0000000Fu)
+#define CSI2LINK_SSERRCNT_ERRSOTSYNCHS_SHIFT                                   (0u)
+#define CSI2LINK_ECCCM_ECC_CRCT_CNT                                            (0x000000FFu)
+#define CSI2LINK_ECCCM_ECC_CRCT_CNT_SHIFT                                      (0u)
+#define CSI2LINK_ECECM_ECC_ERR_CNT                                             (0x000000FFu)
+#define CSI2LINK_ECECM_ECC_ERR_CNT_SHIFT                                       (0u)
+#define CSI2LINK_CRCECM_CRC_ERR_CNT                                            (0x000000FFu)
+#define CSI2LINK_CRCECM_CRC_ERR_CNT_SHIFT                                      (0u)
+#define CSI2LINK_LCNT_LINE_CNT                                                 (0x0000FFFFu)
+#define CSI2LINK_LCNT_LINE_CNT_SHIFT                                           (0u)
+#define CSI2LINK_LCNTM_MONI_LINECNT                                            (0x0000FFFFu)
+#define CSI2LINK_LCNTM_MONI_LINECNT_SHIFT                                      (0u)
+#define CSI2LINK_FCNTM_MONI_FCOUNT                                             (0x0000FFFFu)
+#define CSI2LINK_FCNTM_MONI_FCOUNT_SHIFT                                       (0u)
+#define CSI2LINK_PHYDIM_RXDATAHS_0                                             (0x000000FFu)
+#define CSI2LINK_PHYDIM_RXDATAHS_0_SHIFT                                       (0u)
+#define CSI2LINK_PHYDIM_RXDATAHS_1                                             (0x0000FF00u)
+#define CSI2LINK_PHYDIM_RXDATAHS_1_SHIFT                                       (8u)
+#define CSI2LINK_PHYIM_RXSYNCHS_0_CNT                                          (0x0000000Fu)
+#define CSI2LINK_PHYIM_RXSYNCHS_0_CNT_SHIFT                                    (0u)
+#define CSI2LINK_PHYIM_RXSYNCHS_1_CNT                                          (0x000000F0u)
+#define CSI2LINK_PHYIM_RXSYNCHS_1_CNT_SHIFT                                    (4u)
+#define CSI2LINK_PHYIM_RXACTIVEHS_0                                            (0x00010000u)
+#define CSI2LINK_PHYIM_RXACTIVEHS_0_SHIFT                                      (16u)
+#define CSI2LINK_PHYIM_RXACTIVEHS_1                                            (0x00020000u)
+#define CSI2LINK_PHYIM_RXACTIVEHS_1_SHIFT                                      (17u)
+#define CSI2LINK_PHYIM_RXVALIDHS_0                                             (0x00100000u)
+#define CSI2LINK_PHYIM_RXVALIDHS_0_SHIFT                                       (20u)
+#define CSI2LINK_PHYIM_RXVALIDHS_1                                             (0x00200000u)
+#define CSI2LINK_PHYIM_RXVALIDHS_1_SHIFT                                       (21u)
+#define CSI2LINK_PHYIM_RXCLK_CNT                                               (0x80000000u)
+#define CSI2LINK_PHYIM_RXCLK_CNT_SHIFT                                         (31u)
+#define CSI2LINK_VINDM_CSIR_DAT                                                (0xFFFFFFFFu)
+#define CSI2LINK_VINDM_CSIR_DAT_SHIFT                                          (0u)
+#define CSI2LINK_VINSM1_CSIR_HD_CNT                                            (0x00000FFFu)
+#define CSI2LINK_VINSM1_CSIR_HD_CNT_SHIFT                                      (0u)
+#define CSI2LINK_VINSM1_CSIR_VD_CNT                                            (0x0000F000u)
+#define CSI2LINK_VINSM1_CSIR_VD_CNT_SHIFT                                      (12u)
+#define CSI2LINK_VINSM3_CSIR_PE                                                (0x00000001u)
+#define CSI2LINK_VINSM3_CSIR_PE_SHIFT                                          (0u)
+#define CSI2LINK_VINSM3_CSIR_PEB                                               (0x000000F0u)
+#define CSI2LINK_VINSM3_CSIR_PEB_SHIFT                                         (4u)
+#define CSI2LINK_VINSM3_CSIR_FLD                                               (0x00000F00u)
+#define CSI2LINK_VINSM3_CSIR_FLD_SHIFT                                         (8u)
+#define CSI2LINK_VINSM3_CSIR_TAG                                               (0x00003000u)
+#define CSI2LINK_VINSM3_CSIR_TAG_SHIFT                                         (12u)
+#define CSI2LINK_VINSM3_CSIR_ERRC                                              (0x00004000u)
+#define CSI2LINK_VINSM3_CSIR_ERRC_SHIFT                                        (14u)
+#define CSI2LINK_VINSM3_CSIR_ERRE                                              (0x00008000u)
+#define CSI2LINK_VINSM3_CSIR_ERRE_SHIFT                                        (15u)
+#define CSI2LINK_PHYOM_ENABLE_0                                                (0x00000001u)
+#define CSI2LINK_PHYOM_ENABLE_0_SHIFT                                          (0u)
+#define CSI2LINK_PHYOM_ENABLE_1                                                (0x00000002u)
+#define CSI2LINK_PHYOM_ENABLE_1_SHIFT                                          (1u)
+#define CSI2LINK_PHYOM_ENABLECLK                                               (0x00000010u)
+#define CSI2LINK_PHYOM_ENABLECLK_SHIFT                                         (4u)
+#define CSI2LINK_PHM1_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM1_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM1_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM1_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM1_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM1_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM1_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM1_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM2_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM2_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM2_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM2_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM2_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM2_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM2_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM2_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM3_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM3_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM3_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM3_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM3_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM3_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM3_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM3_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM4_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM4_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM4_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM4_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM4_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM4_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM4_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM4_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM5_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM5_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM5_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM5_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM5_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM5_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM5_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM5_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM6_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM6_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM6_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM6_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM6_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM6_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM6_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM6_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM7_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM7_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM7_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM7_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM7_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM7_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM7_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM7_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHM8_DT                                                       (0x0000003Fu)
+#define CSI2LINK_PHM8_DT_SHIFT                                                 (0u)
+#define CSI2LINK_PHM8_VC                                                       (0x000000C0u)
+#define CSI2LINK_PHM8_VC_SHIFT                                                 (6u)
+#define CSI2LINK_PHM8_WC                                                       (0x00FFFF00u)
+#define CSI2LINK_PHM8_WC_SHIFT                                                 (8u)
+#define CSI2LINK_PHM8_ECC                                                      (0xFF000000u)
+#define CSI2LINK_PHM8_ECC_SHIFT                                                (24u)
+#define CSI2LINK_PHYTIM1_T_INIT_SLAVE                                          (0x0000FFFFu)
+#define CSI2LINK_PHYTIM1_T_INIT_SLAVE_SHIFT                                    (0u)
+#define CSI2LINK_PHYTIM2_TCLK_PREPARE                                          (0x0000001Fu)
+#define CSI2LINK_PHYTIM2_TCLK_PREPARE_SHIFT                                    (0u)
+#define CSI2LINK_PHYTIM2_TCLK_SETTLE                                           (0x00003F00u)
+#define CSI2LINK_PHYTIM2_TCLK_SETTLE_SHIFT                                     (8u)
+#define CSI2LINK_PHYTIM2_TCLK_MISS                                             (0x001F0000u)
+#define CSI2LINK_PHYTIM2_TCLK_MISS_SHIFT                                       (16u)
+#define CSI2LINK_PHYTIM3_THS_PREPARE                                           (0x0000003Fu)
+#define CSI2LINK_PHYTIM3_THS_PREPARE_SHIFT                                     (0u)
+#define CSI2LINK_PHYTIM3_THS_SETTLE                                            (0x00003F00u)
+#define CSI2LINK_PHYTIM3_THS_SETTLE_SHIFT                                      (8u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drpk_iobitmask.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef DRPK_IOBITMASK_H
+#define DRPK_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define DRPK_FIFODATA0_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA0_FIFODATA_SHIFT                                          (0u)
+#define DRPK_FIFODATA1_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA1_FIFODATA_SHIFT                                          (0u)
+#define DRPK_FIFODATA2_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA2_FIFODATA_SHIFT                                          (0u)
+#define DRPK_FIFODATA3_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA3_FIFODATA_SHIFT                                          (0u)
+#define DRPK_FIFODATA4_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA4_FIFODATA_SHIFT                                          (0u)
+#define DRPK_FIFODATA5_FIFODATA                                                (0xFFFFFFFFu)
+#define DRPK_FIFODATA5_FIFODATA_SHIFT                                          (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drw_iobitmask.h

@@ -0,0 +1,288 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef DRW_IOBITMASK_H
+#define DRW_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define DRW_CONTROL_LIM1ENABLE                                                 (0x00000001u)
+#define DRW_CONTROL_LIM1ENABLE_SHIFT                                           (0u)
+#define DRW_CONTROL_LIM2ENABLE                                                 (0x00000002u)
+#define DRW_CONTROL_LIM2ENABLE_SHIFT                                           (1u)
+#define DRW_CONTROL_LIM3ENABLE                                                 (0x00000004u)
+#define DRW_CONTROL_LIM3ENABLE_SHIFT                                           (2u)
+#define DRW_CONTROL_LIM4ENABLE                                                 (0x00000008u)
+#define DRW_CONTROL_LIM4ENABLE_SHIFT                                           (3u)
+#define DRW_CONTROL_LIM5ENABLE                                                 (0x00000010u)
+#define DRW_CONTROL_LIM5ENABLE_SHIFT                                           (4u)
+#define DRW_CONTROL_LIM6ENABLE                                                 (0x00000020u)
+#define DRW_CONTROL_LIM6ENABLE_SHIFT                                           (5u)
+#define DRW_CONTROL_QUAD1ENABLE                                                (0x00000040u)
+#define DRW_CONTROL_QUAD1ENABLE_SHIFT                                          (6u)
+#define DRW_CONTROL_QUAD2ENABLE                                                (0x00000080u)
+#define DRW_CONTROL_QUAD2ENABLE_SHIFT                                          (7u)
+#define DRW_CONTROL_QUAD3ENABLE                                                (0x00000100u)
+#define DRW_CONTROL_QUAD3ENABLE_SHIFT                                          (8u)
+#define DRW_CONTROL_LIM1THRESHOLD                                              (0x00000200u)
+#define DRW_CONTROL_LIM1THRESHOLD_SHIFT                                        (9u)
+#define DRW_CONTROL_LIM2THRESHOLD                                              (0x00000400u)
+#define DRW_CONTROL_LIM2THRESHOLD_SHIFT                                        (10u)
+#define DRW_CONTROL_LIM3THRESHOLD                                              (0x00000800u)
+#define DRW_CONTROL_LIM3THRESHOLD_SHIFT                                        (11u)
+#define DRW_CONTROL_LIM4THRESHOLD                                              (0x00001000u)
+#define DRW_CONTROL_LIM4THRESHOLD_SHIFT                                        (12u)
+#define DRW_CONTROL_LIM5THRESHOLD                                              (0x00002000u)
+#define DRW_CONTROL_LIM5THRESHOLD_SHIFT                                        (13u)
+#define DRW_CONTROL_LIM6THRESHOLD                                              (0x00004000u)
+#define DRW_CONTROL_LIM6THRESHOLD_SHIFT                                        (14u)
+#define DRW_CONTROL_BAND1ENABLE                                                (0x00008000u)
+#define DRW_CONTROL_BAND1ENABLE_SHIFT                                          (15u)
+#define DRW_CONTROL_BAND2ENABLE                                                (0x00010000u)
+#define DRW_CONTROL_BAND2ENABLE_SHIFT                                          (16u)
+#define DRW_CONTROL_UNION12                                                    (0x00020000u)
+#define DRW_CONTROL_UNION12_SHIFT                                              (17u)
+#define DRW_CONTROL_UNION34                                                    (0x00040000u)
+#define DRW_CONTROL_UNION34_SHIFT                                              (18u)
+#define DRW_CONTROL_UNION56                                                    (0x00080000u)
+#define DRW_CONTROL_UNION56_SHIFT                                              (19u)
+#define DRW_CONTROL_UNIONAB                                                    (0x00100000u)
+#define DRW_CONTROL_UNIONAB_SHIFT                                              (20u)
+#define DRW_CONTROL_UNIONCD                                                    (0x00200000u)
+#define DRW_CONTROL_UNIONCD_SHIFT                                              (21u)
+#define DRW_CONTROL_SPANABORT                                                  (0x00400000u)
+#define DRW_CONTROL_SPANABORT_SHIFT                                            (22u)
+#define DRW_CONTROL_SPANSTORE                                                  (0x00800000u)
+#define DRW_CONTROL_SPANSTORE_SHIFT                                            (23u)
+#define DRW_CONTROL2_PATTERNENABLE                                             (0x00000001u)
+#define DRW_CONTROL2_PATTERNENABLE_SHIFT                                       (0u)
+#define DRW_CONTROL2_TEXTUREENABLE                                             (0x00000002u)
+#define DRW_CONTROL2_TEXTUREENABLE_SHIFT                                       (1u)
+#define DRW_CONTROL2_PATTERNSOURCEL5                                           (0x00000004u)
+#define DRW_CONTROL2_PATTERNSOURCEL5_SHIFT                                     (2u)
+#define DRW_CONTROL2_USEACB                                                    (0x00000008u)
+#define DRW_CONTROL2_USEACB_SHIFT                                              (3u)
+#define DRW_CONTROL2_READFORMAT_3_2                                            (0x00000030u)
+#define DRW_CONTROL2_READFORMAT_3_2_SHIFT                                      (4u)
+#define DRW_CONTROL2_BSFA                                                      (0x00000040u)
+#define DRW_CONTROL2_BSFA_SHIFT                                                (6u)
+#define DRW_CONTROL2_BDFA                                                      (0x00000080u)
+#define DRW_CONTROL2_BDFA_SHIFT                                                (7u)
+#define DRW_CONTROL2_WRITEFORMAT_2                                             (0x00000100u)
+#define DRW_CONTROL2_WRITEFORMAT_2_SHIFT                                       (8u)
+#define DRW_CONTROL2_BSF                                                       (0x00000200u)
+#define DRW_CONTROL2_BSF_SHIFT                                                 (9u)
+#define DRW_CONTROL2_BDF                                                       (0x00000400u)
+#define DRW_CONTROL2_BDF_SHIFT                                                 (10u)
+#define DRW_CONTROL2_BSI                                                       (0x00000800u)
+#define DRW_CONTROL2_BSI_SHIFT                                                 (11u)
+#define DRW_CONTROL2_BDI                                                       (0x00001000u)
+#define DRW_CONTROL2_BDI_SHIFT                                                 (12u)
+#define DRW_CONTROL2_BC2                                                       (0x00002000u)
+#define DRW_CONTROL2_BC2_SHIFT                                                 (13u)
+#define DRW_CONTROL2_TEXTURECLAMPX                                             (0x00004000u)
+#define DRW_CONTROL2_TEXTURECLAMPX_SHIFT                                       (14u)
+#define DRW_CONTROL2_TEXTURECLAMPY                                             (0x00008000u)
+#define DRW_CONTROL2_TEXTURECLAMPY_SHIFT                                       (15u)
+#define DRW_CONTROL2_TEXTUREFILTERX                                            (0x00010000u)
+#define DRW_CONTROL2_TEXTUREFILTERX_SHIFT                                      (16u)
+#define DRW_CONTROL2_TEXTUREFILTERY                                            (0x00020000u)
+#define DRW_CONTROL2_TEXTUREFILTERY_SHIFT                                      (17u)
+#define DRW_CONTROL2_READFORMAT_1_0                                            (0x000C0000u)
+#define DRW_CONTROL2_READFORMAT_1_0_SHIFT                                      (18u)
+#define DRW_CONTROL2_WRITEFORMAT_1_0                                           (0x00300000u)
+#define DRW_CONTROL2_WRITEFORMAT_1_0_SHIFT                                     (20u)
+#define DRW_CONTROL2_WRITEALPHA                                                (0x00C00000u)
+#define DRW_CONTROL2_WRITEALPHA_SHIFT                                          (22u)
+#define DRW_CONTROL2_RLEENABLE                                                 (0x01000000u)
+#define DRW_CONTROL2_RLEENABLE_SHIFT                                           (24u)
+#define DRW_CONTROL2_CLUTENABLE                                                (0x02000000u)
+#define DRW_CONTROL2_CLUTENABLE_SHIFT                                          (25u)
+#define DRW_CONTROL2_COLKEYENABLE                                              (0x04000000u)
+#define DRW_CONTROL2_COLKEYENABLE_SHIFT                                        (26u)
+#define DRW_CONTROL2_CLUTFORMAT                                                (0x08000000u)
+#define DRW_CONTROL2_CLUTFORMAT_SHIFT                                          (27u)
+#define DRW_CONTROL2_BSIA                                                      (0x10000000u)
+#define DRW_CONTROL2_BSIA_SHIFT                                                (28u)
+#define DRW_CONTROL2_BDIA                                                      (0x20000000u)
+#define DRW_CONTROL2_BDIA_SHIFT                                                (29u)
+#define DRW_CONTROL2_RLEPIXELWIDTH                                             (0xC0000000u)
+#define DRW_CONTROL2_RLEPIXELWIDTH_SHIFT                                       (30u)
+#define DRW_L1START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L1START_LSTART_SHIFT                                               (0u)
+#define DRW_L2START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L2START_LSTART_SHIFT                                               (0u)
+#define DRW_L3START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L3START_LSTART_SHIFT                                               (0u)
+#define DRW_L4START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L4START_LSTART_SHIFT                                               (0u)
+#define DRW_L5START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L5START_LSTART_SHIFT                                               (0u)
+#define DRW_L6START_LSTART                                                     (0xFFFFFFFFu)
+#define DRW_L6START_LSTART_SHIFT                                               (0u)
+#define DRW_L1XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L1XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L2XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L2XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L3XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L3XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L4XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L4XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L5XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L5XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L6XADD_LXADD                                                       (0xFFFFFFFFu)
+#define DRW_L6XADD_LXADD_SHIFT                                                 (0u)
+#define DRW_L1YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L1YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L2YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L2YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L3YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L3YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L4YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L4YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L5YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L5YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L6YADD_LYADD                                                       (0xFFFFFFFFu)
+#define DRW_L6YADD_LYADD_SHIFT                                                 (0u)
+#define DRW_L1BAND_LBAND                                                       (0xFFFFFFFFu)
+#define DRW_L1BAND_LBAND_SHIFT                                                 (0u)
+#define DRW_L2BAND_LBAND                                                       (0xFFFFFFFFu)
+#define DRW_L2BAND_LBAND_SHIFT                                                 (0u)
+#define DRW_COLOR1_COLOR1B                                                     (0x000000FFu)
+#define DRW_COLOR1_COLOR1B_SHIFT                                               (0u)
+#define DRW_COLOR1_COLOR1G                                                     (0x0000FF00u)
+#define DRW_COLOR1_COLOR1G_SHIFT                                               (8u)
+#define DRW_COLOR1_COLOR1R                                                     (0x00FF0000u)
+#define DRW_COLOR1_COLOR1R_SHIFT                                               (16u)
+#define DRW_COLOR1_COLOR1A                                                     (0xFF000000u)
+#define DRW_COLOR1_COLOR1A_SHIFT                                               (24u)
+#define DRW_COLOR2_COLOR2B                                                     (0x000000FFu)
+#define DRW_COLOR2_COLOR2B_SHIFT                                               (0u)
+#define DRW_COLOR2_COLOR2G                                                     (0x0000FF00u)
+#define DRW_COLOR2_COLOR2G_SHIFT                                               (8u)
+#define DRW_COLOR2_COLOR2R                                                     (0x00FF0000u)
+#define DRW_COLOR2_COLOR2R_SHIFT                                               (16u)
+#define DRW_COLOR2_COLOR2A                                                     (0xFF000000u)
+#define DRW_COLOR2_COLOR2A_SHIFT                                               (24u)
+#define DRW_PATTERN_PATTERN                                                    (0x000000FFu)
+#define DRW_PATTERN_PATTERN_SHIFT                                              (0u)
+#define DRW_SIZE_SIZEX                                                         (0x0000FFFFu)
+#define DRW_SIZE_SIZEX_SHIFT                                                   (0u)
+#define DRW_SIZE_SIZEY                                                         (0xFFFF0000u)
+#define DRW_SIZE_SIZEY_SHIFT                                                   (16u)
+#define DRW_PITCH_PITCH                                                        (0x0000FFFFu)
+#define DRW_PITCH_PITCH_SHIFT                                                  (0u)
+#define DRW_PITCH_SSD                                                          (0xFFFF0000u)
+#define DRW_PITCH_SSD_SHIFT                                                    (16u)
+#define DRW_ORIGIN_ORIGIN                                                      (0xFFFFFFFFu)
+#define DRW_ORIGIN_ORIGIN_SHIFT                                                (0u)
+#define DRW_LUSTART_LUSTART                                                    (0xFFFFFFFFu)
+#define DRW_LUSTART_LUSTART_SHIFT                                              (0u)
+#define DRW_LUXADD_LUXADD                                                      (0xFFFFFFFFu)
+#define DRW_LUXADD_LUXADD_SHIFT                                                (0u)
+#define DRW_LUYADD_LUYADD                                                      (0xFFFFFFFFu)
+#define DRW_LUYADD_LUYADD_SHIFT                                                (0u)
+#define DRW_LVSTARTI_LVSTARTI                                                  (0xFFFFFFFFu)
+#define DRW_LVSTARTI_LVSTARTI_SHIFT                                            (0u)
+#define DRW_LVSTARTF_LVSTARTF                                                  (0x0000FFFFu)
+#define DRW_LVSTARTF_LVSTARTF_SHIFT                                            (0u)
+#define DRW_LVXADDI_LVXADDI                                                    (0xFFFFFFFFu)
+#define DRW_LVXADDI_LVXADDI_SHIFT                                              (0u)
+#define DRW_LVYADDI_LVYADDI                                                    (0xFFFFFFFFu)
+#define DRW_LVYADDI_LVYADDI_SHIFT                                              (0u)
+#define DRW_LVYXADDF_LVXADDF                                                   (0x0000FFFFu)
+#define DRW_LVYXADDF_LVXADDF_SHIFT                                             (0u)
+#define DRW_LVYXADDF_LVYADDF                                                   (0xFFFF0000u)
+#define DRW_LVYXADDF_LVYADDF_SHIFT                                             (16u)
+#define DRW_TEXPITCH_TEXPITCH                                                  (0x000007FFu)
+#define DRW_TEXPITCH_TEXPITCH_SHIFT                                            (0u)
+#define DRW_TEXMASK_TEXUMASK                                                   (0x000007FFu)
+#define DRW_TEXMASK_TEXUMASK_SHIFT                                             (0u)
+#define DRW_TEXMASK_TEXVMASK                                                   (0xFFFFF800u)
+#define DRW_TEXMASK_TEXVMASK_SHIFT                                             (11u)
+#define DRW_TEXORIGIN_TEXORIGIN                                                (0xFFFFFFFFu)
+#define DRW_TEXORIGIN_TEXORIGIN_SHIFT                                          (0u)
+#define DRW_IRQCTL_ENUMIRQEN                                                   (0x00000001u)
+#define DRW_IRQCTL_ENUMIRQEN_SHIFT                                             (0u)
+#define DRW_IRQCTL_DLISTIRQEN                                                  (0x00000002u)
+#define DRW_IRQCTL_DLISTIRQEN_SHIFT                                            (1u)
+#define DRW_IRQCTL_ENUMIRQCLR                                                  (0x00000004u)
+#define DRW_IRQCTL_ENUMIRQCLR_SHIFT                                            (2u)
+#define DRW_IRQCTL_DLISTIRQCLR                                                 (0x00000008u)
+#define DRW_IRQCTL_DLISTIRQCLR_SHIFT                                           (3u)
+#define DRW_IRQCTL_BUSIRQEN                                                    (0x00000010u)
+#define DRW_IRQCTL_BUSIRQEN_SHIFT                                              (4u)
+#define DRW_IRQCTL_BUSIRQCLR                                                   (0x00000020u)
+#define DRW_IRQCTL_BUSIRQCLR_SHIFT                                             (5u)
+#define DRW_CACHECTL_CENABLEFX                                                 (0x00000001u)
+#define DRW_CACHECTL_CENABLEFX_SHIFT                                           (0u)
+#define DRW_CACHECTL_CFLUSHFX                                                  (0x00000002u)
+#define DRW_CACHECTL_CFLUSHFX_SHIFT                                            (1u)
+#define DRW_CACHECTL_CENABLETX                                                 (0x00000004u)
+#define DRW_CACHECTL_CENABLETX_SHIFT                                           (2u)
+#define DRW_CACHECTL_CFLUSHTX                                                  (0x00000008u)
+#define DRW_CACHECTL_CFLUSHTX_SHIFT                                            (3u)
+#define DRW_DLISTSTART_DLISTSTART                                              (0xFFFFFFFFu)
+#define DRW_DLISTSTART_DLISTSTART_SHIFT                                        (0u)
+#define DRW_PERFCOUNT1_PERFCOUNT                                               (0xFFFFFFFFu)
+#define DRW_PERFCOUNT1_PERFCOUNT_SHIFT                                         (0u)
+#define DRW_PERFCOUNT2_PERFCOUNT                                               (0xFFFFFFFFu)
+#define DRW_PERFCOUNT2_PERFCOUNT_SHIFT                                         (0u)
+#define DRW_PERFTRIGGER_PERFTRIGGER1                                           (0x0000001Fu)
+#define DRW_PERFTRIGGER_PERFTRIGGER1_SHIFT                                     (0u)
+#define DRW_PERFTRIGGER_PERFTRIGGER2                                           (0x001F0000u)
+#define DRW_PERFTRIGGER_PERFTRIGGER2_SHIFT                                     (16u)
+#define DRW_TEXCLADDR_CLADDR                                                   (0x000000FFu)
+#define DRW_TEXCLADDR_CLADDR_SHIFT                                             (0u)
+#define DRW_TEXCLDATA_CLDATA                                                   (0xFFFFFFFFu)
+#define DRW_TEXCLDATA_CLDATA_SHIFT                                             (0u)
+#define DRW_TEXCLOFFSET_CLOFFSET                                               (0x000000FFu)
+#define DRW_TEXCLOFFSET_CLOFFSET_SHIFT                                         (0u)
+#define DRW_COLKEY_COLKEYB                                                     (0x000000FFu)
+#define DRW_COLKEY_COLKEYB_SHIFT                                               (0u)
+#define DRW_COLKEY_COLKEYG                                                     (0x0000FF00u)
+#define DRW_COLKEY_COLKEYG_SHIFT                                               (8u)
+#define DRW_COLKEY_COLKEYR                                                     (0x00FF0000u)
+#define DRW_COLKEY_COLKEYR_SHIFT                                               (16u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/edmac_iobitmask.h

@@ -0,0 +1,188 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef EDMAC_IOBITMASK_H
+#define EDMAC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define EDMAC_EDMR_SWR                                                         (0x00000001u)
+#define EDMAC_EDMR_SWR_SHIFT                                                   (0u)
+#define EDMAC_EDMR_DL                                                          (0x00000030u)
+#define EDMAC_EDMR_DL_SHIFT                                                    (4u)
+#define EDMAC_EDMR_DE                                                          (0x00000040u)
+#define EDMAC_EDMR_DE_SHIFT                                                    (6u)
+#define EDMAC_EDTRR_TR                                                         (0x00000001u)
+#define EDMAC_EDTRR_TR_SHIFT                                                   (0u)
+#define EDMAC_EDRRR_RR                                                         (0x00000001u)
+#define EDMAC_EDRRR_RR_SHIFT                                                   (0u)
+#define EDMAC_TDLAR_TDLAR                                                      (0xFFFFFFFFu)
+#define EDMAC_TDLAR_TDLAR_SHIFT                                                (0u)
+#define EDMAC_RDLAR_RDLAR                                                      (0xFFFFFFFFu)
+#define EDMAC_RDLAR_RDLAR_SHIFT                                                (0u)
+#define EDMAC_EESR_CERF                                                        (0x00000001u)
+#define EDMAC_EESR_CERF_SHIFT                                                  (0u)
+#define EDMAC_EESR_PRE                                                         (0x00000002u)
+#define EDMAC_EESR_PRE_SHIFT                                                   (1u)
+#define EDMAC_EESR_RTSF                                                        (0x00000004u)
+#define EDMAC_EESR_RTSF_SHIFT                                                  (2u)
+#define EDMAC_EESR_RTLF                                                        (0x00000008u)
+#define EDMAC_EESR_RTLF_SHIFT                                                  (3u)
+#define EDMAC_EESR_RRF                                                         (0x00000010u)
+#define EDMAC_EESR_RRF_SHIFT                                                   (4u)
+#define EDMAC_EESR_RMAF                                                        (0x00000080u)
+#define EDMAC_EESR_RMAF_SHIFT                                                  (7u)
+#define EDMAC_EESR_TRO                                                         (0x00000100u)
+#define EDMAC_EESR_TRO_SHIFT                                                   (8u)
+#define EDMAC_EESR_CD                                                          (0x00000200u)
+#define EDMAC_EESR_CD_SHIFT                                                    (9u)
+#define EDMAC_EESR_DLC                                                         (0x00000400u)
+#define EDMAC_EESR_DLC_SHIFT                                                   (10u)
+#define EDMAC_EESR_CND                                                         (0x00000800u)
+#define EDMAC_EESR_CND_SHIFT                                                   (11u)
+#define EDMAC_EESR_RFOF                                                        (0x00010000u)
+#define EDMAC_EESR_RFOF_SHIFT                                                  (16u)
+#define EDMAC_EESR_RDE                                                         (0x00020000u)
+#define EDMAC_EESR_RDE_SHIFT                                                   (17u)
+#define EDMAC_EESR_FR                                                          (0x00040000u)
+#define EDMAC_EESR_FR_SHIFT                                                    (18u)
+#define EDMAC_EESR_TFUF                                                        (0x00080000u)
+#define EDMAC_EESR_TFUF_SHIFT                                                  (19u)
+#define EDMAC_EESR_TDE                                                         (0x00100000u)
+#define EDMAC_EESR_TDE_SHIFT                                                   (20u)
+#define EDMAC_EESR_TC                                                          (0x00200000u)
+#define EDMAC_EESR_TC_SHIFT                                                    (21u)
+#define EDMAC_EESR_ECI                                                         (0x00400000u)
+#define EDMAC_EESR_ECI_SHIFT                                                   (22u)
+#define EDMAC_EESR_RFCOF                                                       (0x01000000u)
+#define EDMAC_EESR_RFCOF_SHIFT                                                 (24u)
+#define EDMAC_EESR_RABT                                                        (0x02000000u)
+#define EDMAC_EESR_RABT_SHIFT                                                  (25u)
+#define EDMAC_EESR_TABT                                                        (0x04000000u)
+#define EDMAC_EESR_TABT_SHIFT                                                  (26u)
+#define EDMAC_EESR_TWB                                                         (0x40000000u)
+#define EDMAC_EESR_TWB_SHIFT                                                   (30u)
+#define EDMAC_EESIPR_CERFIP                                                    (0x00000001u)
+#define EDMAC_EESIPR_CERFIP_SHIFT                                              (0u)
+#define EDMAC_EESIPR_PREIP                                                     (0x00000002u)
+#define EDMAC_EESIPR_PREIP_SHIFT                                               (1u)
+#define EDMAC_EESIPR_RTSFIP                                                    (0x00000004u)
+#define EDMAC_EESIPR_RTSFIP_SHIFT                                              (2u)
+#define EDMAC_EESIPR_RTLFIP                                                    (0x00000008u)
+#define EDMAC_EESIPR_RTLFIP_SHIFT                                              (3u)
+#define EDMAC_EESIPR_RRFIP                                                     (0x00000010u)
+#define EDMAC_EESIPR_RRFIP_SHIFT                                               (4u)
+#define EDMAC_EESIPR_RMAFIP                                                    (0x00000080u)
+#define EDMAC_EESIPR_RMAFIP_SHIFT                                              (7u)
+#define EDMAC_EESIPR_TROIP                                                     (0x00000100u)
+#define EDMAC_EESIPR_TROIP_SHIFT                                               (8u)
+#define EDMAC_EESIPR_CDIP                                                      (0x00000200u)
+#define EDMAC_EESIPR_CDIP_SHIFT                                                (9u)
+#define EDMAC_EESIPR_DLCIP                                                     (0x00000400u)
+#define EDMAC_EESIPR_DLCIP_SHIFT                                               (10u)
+#define EDMAC_EESIPR_CNDIP                                                     (0x00000800u)
+#define EDMAC_EESIPR_CNDIP_SHIFT                                               (11u)
+#define EDMAC_EESIPR_RFOFIP                                                    (0x00010000u)
+#define EDMAC_EESIPR_RFOFIP_SHIFT                                              (16u)
+#define EDMAC_EESIPR_RDEIP                                                     (0x00020000u)
+#define EDMAC_EESIPR_RDEIP_SHIFT                                               (17u)
+#define EDMAC_EESIPR_FRIP                                                      (0x00040000u)
+#define EDMAC_EESIPR_FRIP_SHIFT                                                (18u)
+#define EDMAC_EESIPR_TFUFIP                                                    (0x00080000u)
+#define EDMAC_EESIPR_TFUFIP_SHIFT                                              (19u)
+#define EDMAC_EESIPR_TDEIP                                                     (0x00100000u)
+#define EDMAC_EESIPR_TDEIP_SHIFT                                               (20u)
+#define EDMAC_EESIPR_TCIP                                                      (0x00200000u)
+#define EDMAC_EESIPR_TCIP_SHIFT                                                (21u)
+#define EDMAC_EESIPR_ECIIP                                                     (0x00400000u)
+#define EDMAC_EESIPR_ECIIP_SHIFT                                               (22u)
+#define EDMAC_EESIPR_RFCOFIP                                                   (0x01000000u)
+#define EDMAC_EESIPR_RFCOFIP_SHIFT                                             (24u)
+#define EDMAC_EESIPR_RABTIP                                                    (0x02000000u)
+#define EDMAC_EESIPR_RABTIP_SHIFT                                              (25u)
+#define EDMAC_EESIPR_TABTIP                                                    (0x04000000u)
+#define EDMAC_EESIPR_TABTIP_SHIFT                                              (26u)
+#define EDMAC_EESIPR_TWBIP                                                     (0x40000000u)
+#define EDMAC_EESIPR_TWBIP_SHIFT                                               (30u)
+#define EDMAC_TRSCER_RRFCE                                                     (0x00000010u)
+#define EDMAC_TRSCER_RRFCE_SHIFT                                               (4u)
+#define EDMAC_TRSCER_RMAFCE                                                    (0x00000080u)
+#define EDMAC_TRSCER_RMAFCE_SHIFT                                              (7u)
+#define EDMAC_RMFCR_MFC                                                        (0x0000FFFFu)
+#define EDMAC_RMFCR_MFC_SHIFT                                                  (0u)
+#define EDMAC_TFTR_TFT                                                         (0x000007FFu)
+#define EDMAC_TFTR_TFT_SHIFT                                                   (0u)
+#define EDMAC_FDR_RFD                                                          (0x0000001Fu)
+#define EDMAC_FDR_RFD_SHIFT                                                    (0u)
+#define EDMAC_FDR_TFD                                                          (0x00001F00u)
+#define EDMAC_FDR_TFD_SHIFT                                                    (8u)
+#define EDMAC_RMCR_RNR                                                         (0x00000001u)
+#define EDMAC_RMCR_RNR_SHIFT                                                   (0u)
+#define EDMAC_TFUCR_UNDER                                                      (0x0000FFFFu)
+#define EDMAC_TFUCR_UNDER_SHIFT                                                (0u)
+#define EDMAC_RFOCR_OVER                                                       (0x0000FFFFu)
+#define EDMAC_RFOCR_OVER_SHIFT                                                 (0u)
+#define EDMAC_IOSR_ELB                                                         (0x00000001u)
+#define EDMAC_IOSR_ELB_SHIFT                                                   (0u)
+#define EDMAC_FCFTR_RFDO                                                       (0x00000007u)
+#define EDMAC_FCFTR_RFDO_SHIFT                                                 (0u)
+#define EDMAC_FCFTR_RFFO                                                       (0x00070000u)
+#define EDMAC_FCFTR_RFFO_SHIFT                                                 (16u)
+#define EDMAC_RPADIR_PADR                                                      (0x0000003Fu)
+#define EDMAC_RPADIR_PADR_SHIFT                                                (0u)
+#define EDMAC_RPADIR_PADS                                                      (0x00030000u)
+#define EDMAC_RPADIR_PADS_SHIFT                                                (16u)
+#define EDMAC_TRIMD_TIS                                                        (0x00000001u)
+#define EDMAC_TRIMD_TIS_SHIFT                                                  (0u)
+#define EDMAC_TRIMD_TIM                                                        (0x00000010u)
+#define EDMAC_TRIMD_TIM_SHIFT                                                  (4u)
+#define EDMAC_RBWAR_RBWAR                                                      (0xFFFFFFFFu)
+#define EDMAC_RBWAR_RBWAR_SHIFT                                                (0u)
+#define EDMAC_RDFAR_RDFAR                                                      (0xFFFFFFFFu)
+#define EDMAC_RDFAR_RDFAR_SHIFT                                                (0u)
+#define EDMAC_TBRAR_TBRAR                                                      (0xFFFFFFFFu)
+#define EDMAC_TBRAR_TBRAR_SHIFT                                                (0u)
+#define EDMAC_TDFAR_TDFAR                                                      (0xFFFFFFFFu)
+#define EDMAC_TDFAR_TDFAR_SHIFT                                                (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/eptpc_iobitmask.h

@@ -0,0 +1,568 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef EPTPC_IOBITMASK_H
+#define EPTPC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define EPTPC_PTRSTR_RESET                                                     (0x00000001u)
+#define EPTPC_PTRSTR_RESET_SHIFT                                               (0u)
+#define EPTPC_STCSELR_SCLKSEL                                                  (0x00000700u)
+#define EPTPC_STCSELR_SCLKSEL_SHIFT                                            (8u)
+#define EPTPC_BYPASS_BYPASS0                                                   (0x00000001u)
+#define EPTPC_BYPASS_BYPASS0_SHIFT                                             (0u)
+#define EPTPC_BYPASS_BYPASS1                                                   (0x00010000u)
+#define EPTPC_BYPASS_BYPASS1_SHIFT                                             (16u)
+#define EPTPC_MIESR_ST                                                         (0x00000001u)
+#define EPTPC_MIESR_ST_SHIFT                                                   (0u)
+#define EPTPC_MIESR_SY0                                                        (0x00000002u)
+#define EPTPC_MIESR_SY0_SHIFT                                                  (1u)
+#define EPTPC_MIESR_SY1                                                        (0x00000004u)
+#define EPTPC_MIESR_SY1_SHIFT                                                  (2u)
+#define EPTPC_MIESR_PRC                                                        (0x00000008u)
+#define EPTPC_MIESR_PRC_SHIFT                                                  (3u)
+#define EPTPC_MIESR_CYC0                                                       (0x00010000u)
+#define EPTPC_MIESR_CYC0_SHIFT                                                 (16u)
+#define EPTPC_MIESR_CYC1                                                       (0x00020000u)
+#define EPTPC_MIESR_CYC1_SHIFT                                                 (17u)
+#define EPTPC_MIESR_CYC2                                                       (0x00040000u)
+#define EPTPC_MIESR_CYC2_SHIFT                                                 (18u)
+#define EPTPC_MIESR_CYC3                                                       (0x00080000u)
+#define EPTPC_MIESR_CYC3_SHIFT                                                 (19u)
+#define EPTPC_MIESR_CYC4                                                       (0x00100000u)
+#define EPTPC_MIESR_CYC4_SHIFT                                                 (20u)
+#define EPTPC_MIESR_CYC5                                                       (0x00200000u)
+#define EPTPC_MIESR_CYC5_SHIFT                                                 (21u)
+#define EPTPC_MIEIPR_ST                                                        (0x00000001u)
+#define EPTPC_MIEIPR_ST_SHIFT                                                  (0u)
+#define EPTPC_MIEIPR_SY0                                                       (0x00000002u)
+#define EPTPC_MIEIPR_SY0_SHIFT                                                 (1u)
+#define EPTPC_MIEIPR_SY1                                                       (0x00000004u)
+#define EPTPC_MIEIPR_SY1_SHIFT                                                 (2u)
+#define EPTPC_MIEIPR_PR                                                        (0x00000008u)
+#define EPTPC_MIEIPR_PR_SHIFT                                                  (3u)
+#define EPTPC_MIEIPR_CYC0                                                      (0x00010000u)
+#define EPTPC_MIEIPR_CYC0_SHIFT                                                (16u)
+#define EPTPC_MIEIPR_CYC1                                                      (0x00020000u)
+#define EPTPC_MIEIPR_CYC1_SHIFT                                                (17u)
+#define EPTPC_MIEIPR_CYC2                                                      (0x00040000u)
+#define EPTPC_MIEIPR_CYC2_SHIFT                                                (18u)
+#define EPTPC_MIEIPR_CYC3                                                      (0x00080000u)
+#define EPTPC_MIEIPR_CYC3_SHIFT                                                (19u)
+#define EPTPC_MIEIPR_CYC4                                                      (0x00100000u)
+#define EPTPC_MIEIPR_CYC4_SHIFT                                                (20u)
+#define EPTPC_MIEIPR_CYC5                                                      (0x00200000u)
+#define EPTPC_MIEIPR_CYC5_SHIFT                                                (21u)
+#define EPTPC_ELIPPR_PLSP                                                      (0x00010000u)
+#define EPTPC_ELIPPR_PLSP_SHIFT                                                (16u)
+#define EPTPC_ELIPPR_PLSN                                                      (0x01000000u)
+#define EPTPC_ELIPPR_PLSN_SHIFT                                                (24u)
+#define EPTPC_ELIPACR_PLSP                                                     (0x00010000u)
+#define EPTPC_ELIPACR_PLSP_SHIFT                                               (16u)
+#define EPTPC_ELIPACR_PLSN                                                     (0x01000000u)
+#define EPTPC_ELIPACR_PLSN_SHIFT                                               (24u)
+#define EPTPC_STSR_SYNC                                                        (0x00000001u)
+#define EPTPC_STSR_SYNC_SHIFT                                                  (0u)
+#define EPTPC_STSR_SYNCOUT                                                     (0x00000002u)
+#define EPTPC_STSR_SYNCOUT_SHIFT                                               (1u)
+#define EPTPC_STSR_SYNTOUT                                                     (0x00000008u)
+#define EPTPC_STSR_SYNTOUT_SHIFT                                               (3u)
+#define EPTPC_STSR_W10D                                                        (0x00000010u)
+#define EPTPC_STSR_W10D_SHIFT                                                  (4u)
+#define EPTPC_STIPR_SYNC                                                       (0x00000001u)
+#define EPTPC_STIPR_SYNC_SHIFT                                                 (0u)
+#define EPTPC_STIPR_SYNCOUT                                                    (0x00000002u)
+#define EPTPC_STIPR_SYNCOUT_SHIFT                                              (1u)
+#define EPTPC_STIPR_SYNTOUT                                                    (0x00000008u)
+#define EPTPC_STIPR_SYNTOUT_SHIFT                                              (3u)
+#define EPTPC_STIPR_W10D                                                       (0x00000010u)
+#define EPTPC_STIPR_W10D_SHIFT                                                 (4u)
+#define EPTPC_STCFR_STCF                                                       (0x00000003u)
+#define EPTPC_STCFR_STCF_SHIFT                                                 (0u)
+#define EPTPC_STMR_WINT                                                        (0x000000FFu)
+#define EPTPC_STMR_WINT_SHIFT                                                  (0u)
+#define EPTPC_STMR_CMOD                                                        (0x00002000u)
+#define EPTPC_STMR_CMOD_SHIFT                                                  (13u)
+#define EPTPC_STMR_W10S                                                        (0x00008000u)
+#define EPTPC_STMR_W10S_SHIFT                                                  (15u)
+#define EPTPC_STMR_SYTH                                                        (0x000F0000u)
+#define EPTPC_STMR_SYTH_SHIFT                                                  (16u)
+#define EPTPC_STMR_DVTH                                                        (0x00F00000u)
+#define EPTPC_STMR_DVTH_SHIFT                                                  (20u)
+#define EPTPC_STMR_ALEN0                                                       (0x10000000u)
+#define EPTPC_STMR_ALEN0_SHIFT                                                 (28u)
+#define EPTPC_STMR_ALEN1                                                       (0x20000000u)
+#define EPTPC_STMR_ALEN1_SHIFT                                                 (29u)
+#define EPTPC_SYNTOR_SYNTOR                                                    (0xFFFFFFFFu)
+#define EPTPC_SYNTOR_SYNTOR_SHIFT                                              (0u)
+#define EPTPC_IPTSELR_IPTSEL0                                                  (0x00000001u)
+#define EPTPC_IPTSELR_IPTSEL0_SHIFT                                            (0u)
+#define EPTPC_IPTSELR_IPTSEL1                                                  (0x00000002u)
+#define EPTPC_IPTSELR_IPTSEL1_SHIFT                                            (1u)
+#define EPTPC_IPTSELR_IPTSEL2                                                  (0x00000004u)
+#define EPTPC_IPTSELR_IPTSEL2_SHIFT                                            (2u)
+#define EPTPC_IPTSELR_IPTSEL3                                                  (0x00000008u)
+#define EPTPC_IPTSELR_IPTSEL3_SHIFT                                            (3u)
+#define EPTPC_IPTSELR_IPTSEL4                                                  (0x00000010u)
+#define EPTPC_IPTSELR_IPTSEL4_SHIFT                                            (4u)
+#define EPTPC_IPTSELR_IPTSEL5                                                  (0x00000020u)
+#define EPTPC_IPTSELR_IPTSEL5_SHIFT                                            (5u)
+#define EPTPC_MITSELR_MINTEN0                                                  (0x00000001u)
+#define EPTPC_MITSELR_MINTEN0_SHIFT                                            (0u)
+#define EPTPC_MITSELR_MINTEN1                                                  (0x00000002u)
+#define EPTPC_MITSELR_MINTEN1_SHIFT                                            (1u)
+#define EPTPC_MITSELR_MINTEN2                                                  (0x00000004u)
+#define EPTPC_MITSELR_MINTEN2_SHIFT                                            (2u)
+#define EPTPC_MITSELR_MINTEN3                                                  (0x00000008u)
+#define EPTPC_MITSELR_MINTEN3_SHIFT                                            (3u)
+#define EPTPC_MITSELR_MINTEN4                                                  (0x00000010u)
+#define EPTPC_MITSELR_MINTEN4_SHIFT                                            (4u)
+#define EPTPC_MITSELR_MINTEN5                                                  (0x00000020u)
+#define EPTPC_MITSELR_MINTEN5_SHIFT                                            (5u)
+#define EPTPC_STCHSELR_SYSEL                                                   (0x00000001u)
+#define EPTPC_STCHSELR_SYSEL_SHIFT                                             (0u)
+#define EPTPC_SYNSTARTR_STR                                                    (0x00000001u)
+#define EPTPC_SYNSTARTR_STR_SHIFT                                              (0u)
+#define EPTPC_LCIVLDR_LOAD                                                     (0x00000001u)
+#define EPTPC_LCIVLDR_LOAD_SHIFT                                               (0u)
+#define EPTPC_SYNTDARU_SYNTDARU                                                (0xFFFFFFFFu)
+#define EPTPC_SYNTDARU_SYNTDARU_SHIFT                                          (0u)
+#define EPTPC_SYNTDARL_SYNTDARL                                                (0xFFFFFFFFu)
+#define EPTPC_SYNTDARL_SYNTDARL_SHIFT                                          (0u)
+#define EPTPC_SYNTDBRU_SYNTDBRU                                                (0xFFFFFFFFu)
+#define EPTPC_SYNTDBRU_SYNTDBRU_SHIFT                                          (0u)
+#define EPTPC_SYNTDBRL_SYNTDBRL                                                (0xFFFFFFFFu)
+#define EPTPC_SYNTDBRL_SYNTDBRL_SHIFT                                          (0u)
+#define EPTPC_LCIVRU_LCIVRU                                                    (0x0000FFFFu)
+#define EPTPC_LCIVRU_LCIVRU_SHIFT                                              (0u)
+#define EPTPC_LCIVRM_LCIVRM                                                    (0x0000FFFFu)
+#define EPTPC_LCIVRM_LCIVRM_SHIFT                                              (0u)
+#define EPTPC_LCIVRL_LCIVRL                                                    (0x0000FFFFu)
+#define EPTPC_LCIVRL_LCIVRL_SHIFT                                              (0u)
+#define EPTPC_GETW10R_GW10                                                     (0x00000001u)
+#define EPTPC_GETW10R_GW10_SHIFT                                               (0u)
+#define EPTPC_PLIMITRU_PLIMITRU                                                (0x7FFFFFFFu)
+#define EPTPC_PLIMITRU_PLIMITRU_SHIFT                                          (0u)
+#define EPTPC_PLIMITRM_PLIMITRM                                                (0xFFFFFFFFu)
+#define EPTPC_PLIMITRM_PLIMITRM_SHIFT                                          (0u)
+#define EPTPC_PLIMITRL_PLIMITRL                                                (0xFFFFFFFFu)
+#define EPTPC_PLIMITRL_PLIMITRL_SHIFT                                          (0u)
+#define EPTPC_MLIMITRU_MLIMITRU                                                (0x7FFFFFFFu)
+#define EPTPC_MLIMITRU_MLIMITRU_SHIFT                                          (0u)
+#define EPTPC_MLIMITRM_MLIMITRM                                                (0xFFFFFFFFu)
+#define EPTPC_MLIMITRM_MLIMITRM_SHIFT                                          (0u)
+#define EPTPC_MLIMITRL_MLIMITRL                                                (0xFFFFFFFFu)
+#define EPTPC_MLIMITRL_MLIMITRL_SHIFT                                          (0u)
+#define EPTPC_GETINFOR_INFO                                                    (0x00000001u)
+#define EPTPC_GETINFOR_INFO_SHIFT                                              (0u)
+#define EPTPC_LCCVRU_LCCVRU                                                    (0x0000FFFFu)
+#define EPTPC_LCCVRU_LCCVRU_SHIFT                                              (0u)
+#define EPTPC_LCCVRM_LCCVRM                                                    (0xFFFFFFFFu)
+#define EPTPC_LCCVRM_LCCVRM_SHIFT                                              (0u)
+#define EPTPC_LCCVRL_LCCVRL                                                    (0xFFFFFFFFu)
+#define EPTPC_LCCVRL_LCCVRL_SHIFT                                              (0u)
+#define EPTPC_PW10VRU_PW10VRU                                                  (0xFFFFFFFFu)
+#define EPTPC_PW10VRU_PW10VRU_SHIFT                                            (0u)
+#define EPTPC_PW10VRM_PW10VRM                                                  (0xFFFFFFFFu)
+#define EPTPC_PW10VRM_PW10VRM_SHIFT                                            (0u)
+#define EPTPC_PW10VRL_PW10VRL                                                  (0xFFFFFFFFu)
+#define EPTPC_PW10VRL_PW10VRL_SHIFT                                            (0u)
+#define EPTPC_MW10RU_MW10RU                                                    (0xFFFFFFFFu)
+#define EPTPC_MW10RU_MW10RU_SHIFT                                              (0u)
+#define EPTPC_MW10RM_MW10RM                                                    (0xFFFFFFFFu)
+#define EPTPC_MW10RM_MW10RM_SHIFT                                              (0u)
+#define EPTPC_MW10RL_MW10RL                                                    (0xFFFFFFFFu)
+#define EPTPC_MW10RL_MW10RL_SHIFT                                              (0u)
+#define EPTPC_TMSTTRU0_TMSTTRU0                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU0_TMSTTRU0_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL0_TMSTTRL0                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL0_TMSTTRL0_SHIFT                                          (0u)
+#define EPTPC_TMCYCR0_TMCYCR0                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR0_TMCYCR0_SHIFT                                            (0u)
+#define EPTPC_TMPLSR0_TMPLSR0                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR0_TMPLSR0_SHIFT                                            (0u)
+#define EPTPC_TMSTTRU1_TMSTTRU1                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU1_TMSTTRU1_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL1_TMSTTRL1                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL1_TMSTTRL1_SHIFT                                          (0u)
+#define EPTPC_TMCYCR1_TMCYCR1                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR1_TMCYCR1_SHIFT                                            (0u)
+#define EPTPC_TMPLSR1_TMPLSR1                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR1_TMPLSR1_SHIFT                                            (0u)
+#define EPTPC_TMSTTRU2_TMSTTRU2                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU2_TMSTTRU2_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL2_TMSTTRL2                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL2_TMSTTRL2_SHIFT                                          (0u)
+#define EPTPC_TMCYCR2_TMCYCR2                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR2_TMCYCR2_SHIFT                                            (0u)
+#define EPTPC_TMPLSR2_TMPLSR2                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR2_TMPLSR2_SHIFT                                            (0u)
+#define EPTPC_TMSTTRU3_TMSTTRU3                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU3_TMSTTRU3_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL3_TMSTTRL3                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL3_TMSTTRL3_SHIFT                                          (0u)
+#define EPTPC_TMCYCR3_TMCYCR3                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR3_TMCYCR3_SHIFT                                            (0u)
+#define EPTPC_TMPLSR3_TMPLSR3                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR3_TMPLSR3_SHIFT                                            (0u)
+#define EPTPC_TMSTTRU4_TMSTTRU4                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU4_TMSTTRU4_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL4_TMSTTRL4                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL4_TMSTTRL4_SHIFT                                          (0u)
+#define EPTPC_TMCYCR4_TMCYCR4                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR4_TMCYCR4_SHIFT                                            (0u)
+#define EPTPC_TMPLSR4_TMPLSR4                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR4_TMPLSR4_SHIFT                                            (0u)
+#define EPTPC_TMSTTRU5_TMSTTRU5                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRU5_TMSTTRU5_SHIFT                                          (0u)
+#define EPTPC_TMSTTRL5_TMSTTRL5                                                (0xFFFFFFFFu)
+#define EPTPC_TMSTTRL5_TMSTTRL5_SHIFT                                          (0u)
+#define EPTPC_TMCYCR5_TMCYCR5                                                  (0xFFFFFFFFu)
+#define EPTPC_TMCYCR5_TMCYCR5_SHIFT                                            (0u)
+#define EPTPC_TMPLSR5_TMPLSR5                                                  (0x1FFFFFFFu)
+#define EPTPC_TMPLSR5_TMPLSR5_SHIFT                                            (0u)
+#define EPTPC_TMSTARTR_EN0                                                     (0x00000001u)
+#define EPTPC_TMSTARTR_EN0_SHIFT                                               (0u)
+#define EPTPC_TMSTARTR_EN1                                                     (0x00000002u)
+#define EPTPC_TMSTARTR_EN1_SHIFT                                               (1u)
+#define EPTPC_TMSTARTR_EN2                                                     (0x00000004u)
+#define EPTPC_TMSTARTR_EN2_SHIFT                                               (2u)
+#define EPTPC_TMSTARTR_EN3                                                     (0x00000008u)
+#define EPTPC_TMSTARTR_EN3_SHIFT                                               (3u)
+#define EPTPC_TMSTARTR_EN4                                                     (0x00000010u)
+#define EPTPC_TMSTARTR_EN4_SHIFT                                               (4u)
+#define EPTPC_TMSTARTR_EN5                                                     (0x00000020u)
+#define EPTPC_TMSTARTR_EN5_SHIFT                                               (5u)
+#define EPTPC_PRSR_OVRE0                                                       (0x00000001u)
+#define EPTPC_PRSR_OVRE0_SHIFT                                                 (0u)
+#define EPTPC_PRSR_OVRE1                                                       (0x00000002u)
+#define EPTPC_PRSR_OVRE1_SHIFT                                                 (1u)
+#define EPTPC_PRSR_OVRE2                                                       (0x00000004u)
+#define EPTPC_PRSR_OVRE2_SHIFT                                                 (2u)
+#define EPTPC_PRSR_OVRE3                                                       (0x00000008u)
+#define EPTPC_PRSR_OVRE3_SHIFT                                                 (3u)
+#define EPTPC_PRSR_MACE                                                        (0x00000100u)
+#define EPTPC_PRSR_MACE_SHIFT                                                  (8u)
+#define EPTPC_PRSR_URE0                                                        (0x10000000u)
+#define EPTPC_PRSR_URE0_SHIFT                                                  (28u)
+#define EPTPC_PRSR_URE1                                                        (0x20000000u)
+#define EPTPC_PRSR_URE1_SHIFT                                                  (29u)
+#define EPTPC_PRIPR_OVRE0                                                      (0x00000001u)
+#define EPTPC_PRIPR_OVRE0_SHIFT                                                (0u)
+#define EPTPC_PRIPR_OVRE1                                                      (0x00000002u)
+#define EPTPC_PRIPR_OVRE1_SHIFT                                                (1u)
+#define EPTPC_PRIPR_OVRE2                                                      (0x00000004u)
+#define EPTPC_PRIPR_OVRE2_SHIFT                                                (2u)
+#define EPTPC_PRIPR_OVRE3                                                      (0x00000008u)
+#define EPTPC_PRIPR_OVRE3_SHIFT                                                (3u)
+#define EPTPC_PRIPR_MACE                                                       (0x00000100u)
+#define EPTPC_PRIPR_MACE_SHIFT                                                 (8u)
+#define EPTPC_PRIPR_URE0                                                       (0x10000000u)
+#define EPTPC_PRIPR_URE0_SHIFT                                                 (28u)
+#define EPTPC_PRIPR_URE1                                                       (0x20000000u)
+#define EPTPC_PRIPR_URE1_SHIFT                                                 (29u)
+#define EPTPC_PRMACRU0_PRMACRU0                                                (0x00FFFFFFu)
+#define EPTPC_PRMACRU0_PRMACRU0_SHIFT                                          (0u)
+#define EPTPC_PRMACRL0_PRMACRL0                                                (0x00FFFFFFu)
+#define EPTPC_PRMACRL0_PRMACRL0_SHIFT                                          (0u)
+#define EPTPC_PRMACRU1_PRMACRU1                                                (0x00FFFFFFu)
+#define EPTPC_PRMACRU1_PRMACRU1_SHIFT                                          (0u)
+#define EPTPC_PRMACRL1_PRMACRL1                                                (0x00FFFFFFu)
+#define EPTPC_PRMACRL1_PRMACRL1_SHIFT                                          (0u)
+#define EPTPC_TRNDISR_TDIS                                                     (0x00000003u)
+#define EPTPC_TRNDISR_TDIS_SHIFT                                               (0u)
+#define EPTPC_TRNMR_MOD                                                        (0x00000001u)
+#define EPTPC_TRNMR_MOD_SHIFT                                                  (0u)
+#define EPTPC_TRNMR_FWD0                                                       (0x00000100u)
+#define EPTPC_TRNMR_FWD0_SHIFT                                                 (8u)
+#define EPTPC_TRNMR_FWD1                                                       (0x00000200u)
+#define EPTPC_TRNMR_FWD1_SHIFT                                                 (9u)
+#define EPTPC_TRNCTTDR_THVAL                                                   (0x000007FFu)
+#define EPTPC_TRNCTTDR_THVAL_SHIFT                                             (0u)
+#define EPTPC_SYSR_OFMUD                                                       (0x00000001u)
+#define EPTPC_SYSR_OFMUD_SHIFT                                                 (0u)
+#define EPTPC_SYSR_INTCHG                                                      (0x00000002u)
+#define EPTPC_SYSR_INTCHG_SHIFT                                                (1u)
+#define EPTPC_SYSR_MPDUD                                                       (0x00000004u)
+#define EPTPC_SYSR_MPDUD_SHIFT                                                 (2u)
+#define EPTPC_SYSR_DRPTO                                                       (0x00000010u)
+#define EPTPC_SYSR_DRPTO_SHIFT                                                 (4u)
+#define EPTPC_SYSR_INTDEV                                                      (0x00000020u)
+#define EPTPC_SYSR_INTDEV_SHIFT                                                (5u)
+#define EPTPC_SYSR_DRQOVR                                                      (0x00000040u)
+#define EPTPC_SYSR_DRQOVR_SHIFT                                                (6u)
+#define EPTPC_SYSR_RECLP                                                       (0x00001000u)
+#define EPTPC_SYSR_RECLP_SHIFT                                                 (12u)
+#define EPTPC_SYSR_INFABT                                                      (0x00004000u)
+#define EPTPC_SYSR_INFABT_SHIFT                                                (14u)
+#define EPTPC_SYSR_RESDN                                                       (0x00010000u)
+#define EPTPC_SYSR_RESDN_SHIFT                                                 (16u)
+#define EPTPC_SYSR_GENDN                                                       (0x00020000u)
+#define EPTPC_SYSR_GENDN_SHIFT                                                 (17u)
+#define EPTPC_SYIPR_OFMUD                                                      (0x00000001u)
+#define EPTPC_SYIPR_OFMUD_SHIFT                                                (0u)
+#define EPTPC_SYIPR_INTCHG                                                     (0x00000002u)
+#define EPTPC_SYIPR_INTCHG_SHIFT                                               (1u)
+#define EPTPC_SYIPR_MPDUD                                                      (0x00000004u)
+#define EPTPC_SYIPR_MPDUD_SHIFT                                                (2u)
+#define EPTPC_SYIPR_DRPTO                                                      (0x00000010u)
+#define EPTPC_SYIPR_DRPTO_SHIFT                                                (4u)
+#define EPTPC_SYIPR_INTDEV                                                     (0x00000020u)
+#define EPTPC_SYIPR_INTDEV_SHIFT                                               (5u)
+#define EPTPC_SYIPR_DRQOVR                                                     (0x00000040u)
+#define EPTPC_SYIPR_DRQOVR_SHIFT                                               (6u)
+#define EPTPC_SYIPR_RECLP                                                      (0x00001000u)
+#define EPTPC_SYIPR_RECLP_SHIFT                                                (12u)
+#define EPTPC_SYIPR_INFABT                                                     (0x00004000u)
+#define EPTPC_SYIPR_INFABT_SHIFT                                               (14u)
+#define EPTPC_SYIPR_RESDN                                                      (0x00010000u)
+#define EPTPC_SYIPR_RESDN_SHIFT                                                (16u)
+#define EPTPC_SYIPR_GENDN                                                      (0x00020000u)
+#define EPTPC_SYIPR_GENDN_SHIFT                                                (17u)
+#define EPTPC_SYMACRU_SYMACRU                                                  (0x00FFFFFFu)
+#define EPTPC_SYMACRU_SYMACRU_SHIFT                                            (0u)
+#define EPTPC_SYMACRL_SYMACRL                                                  (0x00FFFFFFu)
+#define EPTPC_SYMACRL_SYMACRL_SHIFT                                            (0u)
+#define EPTPC_SYLLCCTLR_CTL                                                    (0x000000FFu)
+#define EPTPC_SYLLCCTLR_CTL_SHIFT                                              (0u)
+#define EPTPC_SYIPADDRR_SYIPADDRR                                              (0xFFFFFFFFu)
+#define EPTPC_SYIPADDRR_SYIPADDRR_SHIFT                                        (0u)
+#define EPTPC_SYSPVRR_VER                                                      (0x0000000Fu)
+#define EPTPC_SYSPVRR_VER_SHIFT                                                (0u)
+#define EPTPC_SYSPVRR_TRSP                                                     (0x000000F0u)
+#define EPTPC_SYSPVRR_TRSP_SHIFT                                               (4u)
+#define EPTPC_SYDOMR_DNUM                                                      (0x000000FFu)
+#define EPTPC_SYDOMR_DNUM_SHIFT                                                (0u)
+#define EPTPC_ANFR_FLAG0                                                       (0x00000001u)
+#define EPTPC_ANFR_FLAG0_SHIFT                                                 (0u)
+#define EPTPC_ANFR_FLAG1                                                       (0x00000002u)
+#define EPTPC_ANFR_FLAG1_SHIFT                                                 (1u)
+#define EPTPC_ANFR_FLAG2                                                       (0x00000004u)
+#define EPTPC_ANFR_FLAG2_SHIFT                                                 (2u)
+#define EPTPC_ANFR_FLAG3                                                       (0x00000008u)
+#define EPTPC_ANFR_FLAG3_SHIFT                                                 (3u)
+#define EPTPC_ANFR_FLAG4                                                       (0x00000010u)
+#define EPTPC_ANFR_FLAG4_SHIFT                                                 (4u)
+#define EPTPC_ANFR_FLAG5                                                       (0x00000020u)
+#define EPTPC_ANFR_FLAG5_SHIFT                                                 (5u)
+#define EPTPC_ANFR_FLAG8                                                       (0x00000100u)
+#define EPTPC_ANFR_FLAG8_SHIFT                                                 (8u)
+#define EPTPC_ANFR_FLAG10                                                      (0x00000400u)
+#define EPTPC_ANFR_FLAG10_SHIFT                                                (10u)
+#define EPTPC_ANFR_FLAG13                                                      (0x00002000u)
+#define EPTPC_ANFR_FLAG13_SHIFT                                                (13u)
+#define EPTPC_ANFR_FLAG14                                                      (0x00004000u)
+#define EPTPC_ANFR_FLAG14_SHIFT                                                (14u)
+#define EPTPC_SYNFR_FLAG10                                                     (0x00000400u)
+#define EPTPC_SYNFR_FLAG10_SHIFT                                               (10u)
+#define EPTPC_SYNFR_FLAG13                                                     (0x00002000u)
+#define EPTPC_SYNFR_FLAG13_SHIFT                                               (13u)
+#define EPTPC_SYNFR_FLAG14                                                     (0x00004000u)
+#define EPTPC_SYNFR_FLAG14_SHIFT                                               (14u)
+#define EPTPC_DYRQFR_FLAG10                                                    (0x00000400u)
+#define EPTPC_DYRQFR_FLAG10_SHIFT                                              (10u)
+#define EPTPC_DYRQFR_FLAG13                                                    (0x00002000u)
+#define EPTPC_DYRQFR_FLAG13_SHIFT                                              (13u)
+#define EPTPC_DYRQFR_FLAG14                                                    (0x00004000u)
+#define EPTPC_DYRQFR_FLAG14_SHIFT                                              (14u)
+#define EPTPC_DYRPFR_FLAG8                                                     (0x00000100u)
+#define EPTPC_DYRPFR_FLAG8_SHIFT                                               (8u)
+#define EPTPC_DYRPFR_FLAG9                                                     (0x00000200u)
+#define EPTPC_DYRPFR_FLAG9_SHIFT                                               (9u)
+#define EPTPC_DYRPFR_FLAG10                                                    (0x00000400u)
+#define EPTPC_DYRPFR_FLAG10_SHIFT                                              (10u)
+#define EPTPC_DYRPFR_FLAG13                                                    (0x00002000u)
+#define EPTPC_DYRPFR_FLAG13_SHIFT                                              (13u)
+#define EPTPC_DYRPFR_FLAG14                                                    (0x00004000u)
+#define EPTPC_DYRPFR_FLAG14_SHIFT                                              (14u)
+#define EPTPC_SYCIDRL_SYCIDRL                                                  (0xFFFFFFFFu)
+#define EPTPC_SYCIDRL_SYCIDRL_SHIFT                                            (0u)
+#define EPTPC_SYCIDRU_SYCIDRU                                                  (0xFFFFFFFFu)
+#define EPTPC_SYCIDRU_SYCIDRU_SHIFT                                            (0u)
+#define EPTPC_SYPNUMR_PNUM                                                     (0x0000FFFFu)
+#define EPTPC_SYPNUMR_PNUM_SHIFT                                               (0u)
+#define EPTPC_SYRVLDR_BMUP                                                     (0x00000001u)
+#define EPTPC_SYRVLDR_BMUP_SHIFT                                               (0u)
+#define EPTPC_SYRVLDR_STUP                                                     (0x00000002u)
+#define EPTPC_SYRVLDR_STUP_SHIFT                                               (1u)
+#define EPTPC_SYRVLDR_ANUP                                                     (0x00000004u)
+#define EPTPC_SYRVLDR_ANUP_SHIFT                                               (2u)
+#define EPTPC_SYRFL1R_ANCE                                                     (0x00000003u)
+#define EPTPC_SYRFL1R_ANCE_SHIFT                                               (0u)
+#define EPTPC_SYRFL1R_SYNC                                                     (0x00000070u)
+#define EPTPC_SYRFL1R_SYNC_SHIFT                                               (4u)
+#define EPTPC_SYRFL1R_FUP                                                      (0x00000700u)
+#define EPTPC_SYRFL1R_FUP_SHIFT                                                (8u)
+#define EPTPC_SYRFL1R_DRQ                                                      (0x00007000u)
+#define EPTPC_SYRFL1R_DRQ_SHIFT                                                (12u)
+#define EPTPC_SYRFL1R_DRP                                                      (0x00070000u)
+#define EPTPC_SYRFL1R_DRP_SHIFT                                                (16u)
+#define EPTPC_SYRFL1R_PDRQ                                                     (0x00700000u)
+#define EPTPC_SYRFL1R_PDRQ_SHIFT                                               (20u)
+#define EPTPC_SYRFL1R_PDRP                                                     (0x07000000u)
+#define EPTPC_SYRFL1R_PDRP_SHIFT                                               (24u)
+#define EPTPC_SYRFL1R_PDFUP                                                    (0x70000000u)
+#define EPTPC_SYRFL1R_PDFUP_SHIFT                                              (28u)
+#define EPTPC_SYRFL2R_MAN                                                      (0x00000003u)
+#define EPTPC_SYRFL2R_MAN_SHIFT                                                (0u)
+#define EPTPC_SYRFL2R_SIG                                                      (0x00000030u)
+#define EPTPC_SYRFL2R_SIG_SHIFT                                                (4u)
+#define EPTPC_SYRFL2R_ILL                                                      (0x30000000u)
+#define EPTPC_SYRFL2R_ILL_SHIFT                                                (28u)
+#define EPTPC_SYTRENR_ANCE                                                     (0x00000001u)
+#define EPTPC_SYTRENR_ANCE_SHIFT                                               (0u)
+#define EPTPC_SYTRENR_SYNC                                                     (0x00000010u)
+#define EPTPC_SYTRENR_SYNC_SHIFT                                               (4u)
+#define EPTPC_SYTRENR_DRQ                                                      (0x00000100u)
+#define EPTPC_SYTRENR_DRQ_SHIFT                                                (8u)
+#define EPTPC_SYTRENR_PDRQ                                                     (0x00001000u)
+#define EPTPC_SYTRENR_PDRQ_SHIFT                                               (12u)
+#define EPTPC_MTCIDL_MTCIDL                                                    (0xFFFFFFFFu)
+#define EPTPC_MTCIDL_MTCIDL_SHIFT                                              (0u)
+#define EPTPC_MTCIDU_MTCIDU                                                    (0xFFFFFFFFu)
+#define EPTPC_MTCIDU_MTCIDU_SHIFT                                              (0u)
+#define EPTPC_MTPID_PNUM                                                       (0x0000FFFFu)
+#define EPTPC_MTPID_PNUM_SHIFT                                                 (0u)
+#define EPTPC_SYTLIR_ANCE                                                      (0x000000FFu)
+#define EPTPC_SYTLIR_ANCE_SHIFT                                                (0u)
+#define EPTPC_SYTLIR_SYNC                                                      (0x0000FF00u)
+#define EPTPC_SYTLIR_SYNC_SHIFT                                                (8u)
+#define EPTPC_SYTLIR_DREQ                                                      (0x00FF0000u)
+#define EPTPC_SYTLIR_DREQ_SHIFT                                                (16u)
+#define EPTPC_SYRLIR_ANCE                                                      (0x000000FFu)
+#define EPTPC_SYRLIR_ANCE_SHIFT                                                (0u)
+#define EPTPC_SYRLIR_SYNC                                                      (0x0000FF00u)
+#define EPTPC_SYRLIR_SYNC_SHIFT                                                (8u)
+#define EPTPC_SYRLIR_DRESP                                                     (0x00FF0000u)
+#define EPTPC_SYRLIR_DRESP_SHIFT                                               (16u)
+#define EPTPC_OFMRL_OFMRL                                                      (0xFFFFFFFFu)
+#define EPTPC_OFMRL_OFMRL_SHIFT                                                (0u)
+#define EPTPC_OFMRU_OFMRU                                                      (0xFFFFFFFFu)
+#define EPTPC_OFMRU_OFMRU_SHIFT                                                (0u)
+#define EPTPC_MPDRU_MPDRU                                                      (0xFFFFFFFFu)
+#define EPTPC_MPDRU_MPDRU_SHIFT                                                (0u)
+#define EPTPC_MPDRL_MPDRL                                                      (0xFFFFFFFFu)
+#define EPTPC_MPDRL_MPDRL_SHIFT                                                (0u)
+#define EPTPC_GMPR_GMPR2                                                       (0x000000FFu)
+#define EPTPC_GMPR_GMPR2_SHIFT                                                 (0u)
+#define EPTPC_GMPR_GMPR1                                                       (0x00FF0000u)
+#define EPTPC_GMPR_GMPR1_SHIFT                                                 (16u)
+#define EPTPC_GMCQR_GMCQR                                                      (0xFFFFFFFFu)
+#define EPTPC_GMCQR_GMCQR_SHIFT                                                (0u)
+#define EPTPC_GMIDRU_GMIDRU                                                    (0xFFFFFFFFu)
+#define EPTPC_GMIDRU_GMIDRU_SHIFT                                              (0u)
+#define EPTPC_GMIDRL_GMIDRL                                                    (0xFFFFFFFFu)
+#define EPTPC_GMIDRL_GMIDRL_SHIFT                                              (0u)
+#define EPTPC_CUOTSR_TSRC                                                      (0x000000FFu)
+#define EPTPC_CUOTSR_TSRC_SHIFT                                                (0u)
+#define EPTPC_CUOTSR_CUTO                                                      (0xFFFF0000u)
+#define EPTPC_CUOTSR_CUTO_SHIFT                                                (16u)
+#define EPTPC_SRR_SRMV                                                         (0x0000FFFFu)
+#define EPTPC_SRR_SRMV_SHIFT                                                   (0u)
+#define EPTPC_PPMACRU_PPMACRU                                                  (0x00FFFFFFu)
+#define EPTPC_PPMACRU_PPMACRU_SHIFT                                            (0u)
+#define EPTPC_PPMACRL_PPMACRL                                                  (0x00FFFFFFu)
+#define EPTPC_PPMACRL_PPMACRL_SHIFT                                            (0u)
+#define EPTPC_PDMACRU_PDMACRU                                                  (0x00FFFFFFu)
+#define EPTPC_PDMACRU_PDMACRU_SHIFT                                            (0u)
+#define EPTPC_PDMACRL_PDMACRL                                                  (0x00FFFFFFu)
+#define EPTPC_PDMACRL_PDMACRL_SHIFT                                            (0u)
+#define EPTPC_PETYPER_TYPE                                                     (0x0000FFFFu)
+#define EPTPC_PETYPER_TYPE_SHIFT                                               (0u)
+#define EPTPC_PPIPR_PPIPR                                                      (0xFFFFFFFFu)
+#define EPTPC_PPIPR_PPIPR_SHIFT                                                (0u)
+#define EPTPC_PDIPR_PDIPR                                                      (0xFFFFFFFFu)
+#define EPTPC_PDIPR_PDIPR_SHIFT                                                (0u)
+#define EPTPC_PETOSR_EVTO                                                      (0x000000FFu)
+#define EPTPC_PETOSR_EVTO_SHIFT                                                (0u)
+#define EPTPC_PGTOSR_GETO                                                      (0x000000FFu)
+#define EPTPC_PGTOSR_GETO_SHIFT                                                (0u)
+#define EPTPC_PPTTLR_PRTL                                                      (0x000000FFu)
+#define EPTPC_PPTTLR_PRTL_SHIFT                                                (0u)
+#define EPTPC_PDTTLR_PDTL                                                      (0x000000FFu)
+#define EPTPC_PDTTLR_PDTL_SHIFT                                                (0u)
+#define EPTPC_PEUDPR_EVUPT                                                     (0x0000FFFFu)
+#define EPTPC_PEUDPR_EVUPT_SHIFT                                               (0u)
+#define EPTPC_PGUDPR_GEUPT                                                     (0x0000FFFFu)
+#define EPTPC_PGUDPR_GEUPT_SHIFT                                               (0u)
+#define EPTPC_FFLTR_SEL                                                        (0x00000001u)
+#define EPTPC_FFLTR_SEL_SHIFT                                                  (0u)
+#define EPTPC_FFLTR_PRT                                                        (0x00000002u)
+#define EPTPC_FFLTR_PRT_SHIFT                                                  (1u)
+#define EPTPC_FFLTR_ENB                                                        (0x00000004u)
+#define EPTPC_FFLTR_ENB_SHIFT                                                  (2u)
+#define EPTPC_FFLTR_EXTPRM                                                     (0x00010000u)
+#define EPTPC_FFLTR_EXTPRM_SHIFT                                               (16u)
+#define EPTPC_FMAC0RU_FMAC0RU                                                  (0x00FFFFFFu)
+#define EPTPC_FMAC0RU_FMAC0RU_SHIFT                                            (0u)
+#define EPTPC_FMAC0RL_FMAC0RL                                                  (0x00FFFFFFu)
+#define EPTPC_FMAC0RL_FMAC0RL_SHIFT                                            (0u)
+#define EPTPC_FMAC1RU_FMAC1RU                                                  (0x00FFFFFFu)
+#define EPTPC_FMAC1RU_FMAC1RU_SHIFT                                            (0u)
+#define EPTPC_FMAC1RL_FMAC1RL                                                  (0x00FFFFFFu)
+#define EPTPC_FMAC1RL_FMAC1RL_SHIFT                                            (0u)
+#define EPTPC_DASYMRU_DASYMRU                                                  (0x0000FFFFu)
+#define EPTPC_DASYMRU_DASYMRU_SHIFT                                            (0u)
+#define EPTPC_DASYMRL_DASYMRL                                                  (0xFFFFFFFFu)
+#define EPTPC_DASYMRL_DASYMRL_SHIFT                                            (0u)
+#define EPTPC_TSLATR_EGP                                                       (0x0000FFFFu)
+#define EPTPC_TSLATR_EGP_SHIFT                                                 (0u)
+#define EPTPC_TSLATR_INGP                                                      (0xFFFF0000u)
+#define EPTPC_TSLATR_INGP_SHIFT                                                (16u)
+#define EPTPC_SYCONFR_TCYC                                                     (0x000000FFu)
+#define EPTPC_SYCONFR_TCYC_SHIFT                                               (0u)
+#define EPTPC_SYCONFR_SBDIS                                                    (0x00001000u)
+#define EPTPC_SYCONFR_SBDIS_SHIFT                                              (12u)
+#define EPTPC_SYCONFR_FILDIS                                                   (0x00010000u)
+#define EPTPC_SYCONFR_FILDIS_SHIFT                                             (16u)
+#define EPTPC_SYCONFR_TCMOD                                                    (0x00100000u)
+#define EPTPC_SYCONFR_TCMOD_SHIFT                                              (20u)
+#define EPTPC_SYFORMR_FORM0                                                    (0x00000001u)
+#define EPTPC_SYFORMR_FORM0_SHIFT                                              (0u)
+#define EPTPC_SYFORMR_FORM1                                                    (0x00000002u)
+#define EPTPC_SYFORMR_FORM1_SHIFT                                              (1u)
+#define EPTPC_RSTOUTR_RSTOUTR                                                  (0xFFFFFFFFu)
+#define EPTPC_RSTOUTR_RSTOUTR_SHIFT                                            (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/etherc_iobitmask.h

@@ -0,0 +1,148 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef ETHERC_IOBITMASK_H
+#define ETHERC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define ETHERC_ECMR_PRM                                                        (0x00000001u)
+#define ETHERC_ECMR_PRM_SHIFT                                                  (0u)
+#define ETHERC_ECMR_DM                                                         (0x00000002u)
+#define ETHERC_ECMR_DM_SHIFT                                                   (1u)
+#define ETHERC_ECMR_RTM                                                        (0x00000004u)
+#define ETHERC_ECMR_RTM_SHIFT                                                  (2u)
+#define ETHERC_ECMR_ILB                                                        (0x00000008u)
+#define ETHERC_ECMR_ILB_SHIFT                                                  (3u)
+#define ETHERC_ECMR_TE                                                         (0x00000020u)
+#define ETHERC_ECMR_TE_SHIFT                                                   (5u)
+#define ETHERC_ECMR_RE                                                         (0x00000040u)
+#define ETHERC_ECMR_RE_SHIFT                                                   (6u)
+#define ETHERC_ECMR_MPDE                                                       (0x00000200u)
+#define ETHERC_ECMR_MPDE_SHIFT                                                 (9u)
+#define ETHERC_ECMR_PRCEF                                                      (0x00001000u)
+#define ETHERC_ECMR_PRCEF_SHIFT                                                (12u)
+#define ETHERC_ECMR_TXF                                                        (0x00010000u)
+#define ETHERC_ECMR_TXF_SHIFT                                                  (16u)
+#define ETHERC_ECMR_RXF                                                        (0x00020000u)
+#define ETHERC_ECMR_RXF_SHIFT                                                  (17u)
+#define ETHERC_ECMR_PFR                                                        (0x00040000u)
+#define ETHERC_ECMR_PFR_SHIFT                                                  (18u)
+#define ETHERC_ECMR_ZPF                                                        (0x00080000u)
+#define ETHERC_ECMR_ZPF_SHIFT                                                  (19u)
+#define ETHERC_ECMR_TPC                                                        (0x00100000u)
+#define ETHERC_ECMR_TPC_SHIFT                                                  (20u)
+#define ETHERC_RFLR_RFL                                                        (0x00000FFFu)
+#define ETHERC_RFLR_RFL_SHIFT                                                  (0u)
+#define ETHERC_ECSR_ICD                                                        (0x00000001u)
+#define ETHERC_ECSR_ICD_SHIFT                                                  (0u)
+#define ETHERC_ECSR_MPD                                                        (0x00000002u)
+#define ETHERC_ECSR_MPD_SHIFT                                                  (1u)
+#define ETHERC_ECSR_LCHNG                                                      (0x00000004u)
+#define ETHERC_ECSR_LCHNG_SHIFT                                                (2u)
+#define ETHERC_ECSR_PSRTO                                                      (0x00000010u)
+#define ETHERC_ECSR_PSRTO_SHIFT                                                (4u)
+#define ETHERC_ECSR_BFR                                                        (0x00000020u)
+#define ETHERC_ECSR_BFR_SHIFT                                                  (5u)
+#define ETHERC_ECSIPR_ICDIP                                                    (0x00000001u)
+#define ETHERC_ECSIPR_ICDIP_SHIFT                                              (0u)
+#define ETHERC_ECSIPR_MPDIP                                                    (0x00000002u)
+#define ETHERC_ECSIPR_MPDIP_SHIFT                                              (1u)
+#define ETHERC_ECSIPR_LCHNGIP                                                  (0x00000004u)
+#define ETHERC_ECSIPR_LCHNGIP_SHIFT                                            (2u)
+#define ETHERC_ECSIPR_PSRTOIP                                                  (0x00000010u)
+#define ETHERC_ECSIPR_PSRTOIP_SHIFT                                            (4u)
+#define ETHERC_ECSIPR_BFSIPR                                                   (0x00000020u)
+#define ETHERC_ECSIPR_BFSIPR_SHIFT                                             (5u)
+#define ETHERC_PIR_MDC                                                         (0x00000001u)
+#define ETHERC_PIR_MDC_SHIFT                                                   (0u)
+#define ETHERC_PIR_MMD                                                         (0x00000002u)
+#define ETHERC_PIR_MMD_SHIFT                                                   (1u)
+#define ETHERC_PIR_MDO                                                         (0x00000004u)
+#define ETHERC_PIR_MDO_SHIFT                                                   (2u)
+#define ETHERC_PIR_MDI                                                         (0x00000008u)
+#define ETHERC_PIR_MDI_SHIFT                                                   (3u)
+#define ETHERC_PSR_LMON                                                        (0x00000001u)
+#define ETHERC_PSR_LMON_SHIFT                                                  (0u)
+#define ETHERC_RDMLR_RMD                                                       (0x000FFFFFu)
+#define ETHERC_RDMLR_RMD_SHIFT                                                 (0u)
+#define ETHERC_IPGR_IPG                                                        (0x0000001Fu)
+#define ETHERC_IPGR_IPG_SHIFT                                                  (0u)
+#define ETHERC_APR_AP                                                          (0x0000FFFFu)
+#define ETHERC_APR_AP_SHIFT                                                    (0u)
+#define ETHERC_MPR_MP                                                          (0x0000FFFFu)
+#define ETHERC_MPR_MP_SHIFT                                                    (0u)
+#define ETHERC_RFCF_RPAUSE                                                     (0x000000FFu)
+#define ETHERC_RFCF_RPAUSE_SHIFT                                               (0u)
+#define ETHERC_TPAUSER_TPAUSE                                                  (0x0000FFFFu)
+#define ETHERC_TPAUSER_TPAUSE_SHIFT                                            (0u)
+#define ETHERC_TPAUSECR_TXP                                                    (0x000000FFu)
+#define ETHERC_TPAUSECR_TXP_SHIFT                                              (0u)
+#define ETHERC_BCFRR_BCF                                                       (0x0000FFFFu)
+#define ETHERC_BCFRR_BCF_SHIFT                                                 (0u)
+#define ETHERC_MAHR_MAHR                                                       (0xFFFFFFFFu)
+#define ETHERC_MAHR_MAHR_SHIFT                                                 (0u)
+#define ETHERC_MALR_MALR                                                       (0x0000FFFFu)
+#define ETHERC_MALR_MALR_SHIFT                                                 (0u)
+#define ETHERC_TROCR_TROCR                                                     (0xFFFFFFFFu)
+#define ETHERC_TROCR_TROCR_SHIFT                                               (0u)
+#define ETHERC_CDCR_CDCR                                                       (0xFFFFFFFFu)
+#define ETHERC_CDCR_CDCR_SHIFT                                                 (0u)
+#define ETHERC_LCCR_LCCR                                                       (0xFFFFFFFFu)
+#define ETHERC_LCCR_LCCR_SHIFT                                                 (0u)
+#define ETHERC_CNDCR_CNDCR                                                     (0xFFFFFFFFu)
+#define ETHERC_CNDCR_CNDCR_SHIFT                                               (0u)
+#define ETHERC_CEFCR_CEFCR                                                     (0xFFFFFFFFu)
+#define ETHERC_CEFCR_CEFCR_SHIFT                                               (0u)
+#define ETHERC_FRECR_FRECR                                                     (0xFFFFFFFFu)
+#define ETHERC_FRECR_FRECR_SHIFT                                               (0u)
+#define ETHERC_TSFRCR_TSFRCR                                                   (0xFFFFFFFFu)
+#define ETHERC_TSFRCR_TSFRCR_SHIFT                                             (0u)
+#define ETHERC_TLFRCR_TLFRCR                                                   (0xFFFFFFFFu)
+#define ETHERC_TLFRCR_TLFRCR_SHIFT                                             (0u)
+#define ETHERC_RFCR_RFCR                                                       (0xFFFFFFFFu)
+#define ETHERC_RFCR_RFCR_SHIFT                                                 (0u)
+#define ETHERC_MAFCR_MAFCR                                                     (0xFFFFFFFFu)
+#define ETHERC_MAFCR_MAFCR_SHIFT                                               (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpio_iobitmask.h

@@ -0,0 +1,828 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef GPIO_IOBITMASK_H
+#define GPIO_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define GPIO_P00PFS_PSEL                                                       (0x07u)
+#define GPIO_P00PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P00PFS_ISEL                                                       (0x40u)
+#define GPIO_P00PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P01PFS_PSEL                                                       (0x07u)
+#define GPIO_P01PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P01PFS_ISEL                                                       (0x40u)
+#define GPIO_P01PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P02PFS_PSEL                                                       (0x07u)
+#define GPIO_P02PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P02PFS_ISEL                                                       (0x40u)
+#define GPIO_P02PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P03PFS_PSEL                                                       (0x07u)
+#define GPIO_P03PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P03PFS_ISEL                                                       (0x40u)
+#define GPIO_P03PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P04PFS_PSEL                                                       (0x07u)
+#define GPIO_P04PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P04PFS_ISEL                                                       (0x40u)
+#define GPIO_P04PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P05PFS_PSEL                                                       (0x07u)
+#define GPIO_P05PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P05PFS_ISEL                                                       (0x40u)
+#define GPIO_P05PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P06PFS_PSEL                                                       (0x07u)
+#define GPIO_P06PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P06PFS_ISEL                                                       (0x40u)
+#define GPIO_P06PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P10PFS_PSEL                                                       (0x07u)
+#define GPIO_P10PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P10PFS_ISEL                                                       (0x40u)
+#define GPIO_P10PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P11PFS_PSEL                                                       (0x07u)
+#define GPIO_P11PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P11PFS_ISEL                                                       (0x40u)
+#define GPIO_P11PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P12PFS_PSEL                                                       (0x07u)
+#define GPIO_P12PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P12PFS_ISEL                                                       (0x40u)
+#define GPIO_P12PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P13PFS_PSEL                                                       (0x07u)
+#define GPIO_P13PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P13PFS_ISEL                                                       (0x40u)
+#define GPIO_P13PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P14PFS_PSEL                                                       (0x07u)
+#define GPIO_P14PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P14PFS_ISEL                                                       (0x40u)
+#define GPIO_P14PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P20PFS_PSEL                                                       (0x07u)
+#define GPIO_P20PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P20PFS_ISEL                                                       (0x40u)
+#define GPIO_P20PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P21PFS_PSEL                                                       (0x07u)
+#define GPIO_P21PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P21PFS_ISEL                                                       (0x40u)
+#define GPIO_P21PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P22PFS_PSEL                                                       (0x07u)
+#define GPIO_P22PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P22PFS_ISEL                                                       (0x40u)
+#define GPIO_P22PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P23PFS_PSEL                                                       (0x07u)
+#define GPIO_P23PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P23PFS_ISEL                                                       (0x40u)
+#define GPIO_P23PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P30PFS_PSEL                                                       (0x07u)
+#define GPIO_P30PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P30PFS_ISEL                                                       (0x40u)
+#define GPIO_P30PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P31PFS_PSEL                                                       (0x07u)
+#define GPIO_P31PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P31PFS_ISEL                                                       (0x40u)
+#define GPIO_P31PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P32PFS_PSEL                                                       (0x07u)
+#define GPIO_P32PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P32PFS_ISEL                                                       (0x40u)
+#define GPIO_P32PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P33PFS_PSEL                                                       (0x07u)
+#define GPIO_P33PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P33PFS_ISEL                                                       (0x40u)
+#define GPIO_P33PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P34PFS_PSEL                                                       (0x07u)
+#define GPIO_P34PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P34PFS_ISEL                                                       (0x40u)
+#define GPIO_P34PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P35PFS_PSEL                                                       (0x07u)
+#define GPIO_P35PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P35PFS_ISEL                                                       (0x40u)
+#define GPIO_P35PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P40PFS_PSEL                                                       (0x07u)
+#define GPIO_P40PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P40PFS_ISEL                                                       (0x40u)
+#define GPIO_P40PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P41PFS_PSEL                                                       (0x07u)
+#define GPIO_P41PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P41PFS_ISEL                                                       (0x40u)
+#define GPIO_P41PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P42PFS_PSEL                                                       (0x07u)
+#define GPIO_P42PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P42PFS_ISEL                                                       (0x40u)
+#define GPIO_P42PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P43PFS_PSEL                                                       (0x07u)
+#define GPIO_P43PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P43PFS_ISEL                                                       (0x40u)
+#define GPIO_P43PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P44PFS_PSEL                                                       (0x07u)
+#define GPIO_P44PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P44PFS_ISEL                                                       (0x40u)
+#define GPIO_P44PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P45PFS_PSEL                                                       (0x07u)
+#define GPIO_P45PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P45PFS_ISEL                                                       (0x40u)
+#define GPIO_P45PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P46PFS_PSEL                                                       (0x07u)
+#define GPIO_P46PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P46PFS_ISEL                                                       (0x40u)
+#define GPIO_P46PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P47PFS_PSEL                                                       (0x07u)
+#define GPIO_P47PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P47PFS_ISEL                                                       (0x40u)
+#define GPIO_P47PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P50PFS_PSEL                                                       (0x07u)
+#define GPIO_P50PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P50PFS_ISEL                                                       (0x40u)
+#define GPIO_P50PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P51PFS_PSEL                                                       (0x07u)
+#define GPIO_P51PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P51PFS_ISEL                                                       (0x40u)
+#define GPIO_P51PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P52PFS_PSEL                                                       (0x07u)
+#define GPIO_P52PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P52PFS_ISEL                                                       (0x40u)
+#define GPIO_P52PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P53PFS_PSEL                                                       (0x07u)
+#define GPIO_P53PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P53PFS_ISEL                                                       (0x40u)
+#define GPIO_P53PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P54PFS_PSEL                                                       (0x07u)
+#define GPIO_P54PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P54PFS_ISEL                                                       (0x40u)
+#define GPIO_P54PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P55PFS_PSEL                                                       (0x07u)
+#define GPIO_P55PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P55PFS_ISEL                                                       (0x40u)
+#define GPIO_P55PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P56PFS_PSEL                                                       (0x07u)
+#define GPIO_P56PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P56PFS_ISEL                                                       (0x40u)
+#define GPIO_P56PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P57PFS_PSEL                                                       (0x07u)
+#define GPIO_P57PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P57PFS_ISEL                                                       (0x40u)
+#define GPIO_P57PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P60PFS_PSEL                                                       (0x07u)
+#define GPIO_P60PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P60PFS_ISEL                                                       (0x40u)
+#define GPIO_P60PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P61PFS_PSEL                                                       (0x07u)
+#define GPIO_P61PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P61PFS_ISEL                                                       (0x40u)
+#define GPIO_P61PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P62PFS_PSEL                                                       (0x07u)
+#define GPIO_P62PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P62PFS_ISEL                                                       (0x40u)
+#define GPIO_P62PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P63PFS_PSEL                                                       (0x07u)
+#define GPIO_P63PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P63PFS_ISEL                                                       (0x40u)
+#define GPIO_P63PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P64PFS_PSEL                                                       (0x07u)
+#define GPIO_P64PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P64PFS_ISEL                                                       (0x40u)
+#define GPIO_P64PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P65PFS_PSEL                                                       (0x07u)
+#define GPIO_P65PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P65PFS_ISEL                                                       (0x40u)
+#define GPIO_P65PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P66PFS_PSEL                                                       (0x07u)
+#define GPIO_P66PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P66PFS_ISEL                                                       (0x40u)
+#define GPIO_P66PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P67PFS_PSEL                                                       (0x07u)
+#define GPIO_P67PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P67PFS_ISEL                                                       (0x40u)
+#define GPIO_P67PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P70PFS_PSEL                                                       (0x07u)
+#define GPIO_P70PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P70PFS_ISEL                                                       (0x40u)
+#define GPIO_P70PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P71PFS_PSEL                                                       (0x07u)
+#define GPIO_P71PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P71PFS_ISEL                                                       (0x40u)
+#define GPIO_P71PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P72PFS_PSEL                                                       (0x07u)
+#define GPIO_P72PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P72PFS_ISEL                                                       (0x40u)
+#define GPIO_P72PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P73PFS_PSEL                                                       (0x07u)
+#define GPIO_P73PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P73PFS_ISEL                                                       (0x40u)
+#define GPIO_P73PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P74PFS_PSEL                                                       (0x07u)
+#define GPIO_P74PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P74PFS_ISEL                                                       (0x40u)
+#define GPIO_P74PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P75PFS_PSEL                                                       (0x07u)
+#define GPIO_P75PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P75PFS_ISEL                                                       (0x40u)
+#define GPIO_P75PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P76PFS_PSEL                                                       (0x07u)
+#define GPIO_P76PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P76PFS_ISEL                                                       (0x40u)
+#define GPIO_P76PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P77PFS_PSEL                                                       (0x07u)
+#define GPIO_P77PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P77PFS_ISEL                                                       (0x40u)
+#define GPIO_P77PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P80PFS_PSEL                                                       (0x07u)
+#define GPIO_P80PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P80PFS_ISEL                                                       (0x40u)
+#define GPIO_P80PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P81PFS_PSEL                                                       (0x07u)
+#define GPIO_P81PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P81PFS_ISEL                                                       (0x40u)
+#define GPIO_P81PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P82PFS_PSEL                                                       (0x07u)
+#define GPIO_P82PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P82PFS_ISEL                                                       (0x40u)
+#define GPIO_P82PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P83PFS_PSEL                                                       (0x07u)
+#define GPIO_P83PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P83PFS_ISEL                                                       (0x40u)
+#define GPIO_P83PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P84PFS_PSEL                                                       (0x07u)
+#define GPIO_P84PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P84PFS_ISEL                                                       (0x40u)
+#define GPIO_P84PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P85PFS_PSEL                                                       (0x07u)
+#define GPIO_P85PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P85PFS_ISEL                                                       (0x40u)
+#define GPIO_P85PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P86PFS_PSEL                                                       (0x07u)
+#define GPIO_P86PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P86PFS_ISEL                                                       (0x40u)
+#define GPIO_P86PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P87PFS_PSEL                                                       (0x07u)
+#define GPIO_P87PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P87PFS_ISEL                                                       (0x40u)
+#define GPIO_P87PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P90PFS_PSEL                                                       (0x07u)
+#define GPIO_P90PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P90PFS_ISEL                                                       (0x40u)
+#define GPIO_P90PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P91PFS_PSEL                                                       (0x07u)
+#define GPIO_P91PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P91PFS_ISEL                                                       (0x40u)
+#define GPIO_P91PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P92PFS_PSEL                                                       (0x07u)
+#define GPIO_P92PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P92PFS_ISEL                                                       (0x40u)
+#define GPIO_P92PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P93PFS_PSEL                                                       (0x07u)
+#define GPIO_P93PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P93PFS_ISEL                                                       (0x40u)
+#define GPIO_P93PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P94PFS_PSEL                                                       (0x07u)
+#define GPIO_P94PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P94PFS_ISEL                                                       (0x40u)
+#define GPIO_P94PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P95PFS_PSEL                                                       (0x07u)
+#define GPIO_P95PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P95PFS_ISEL                                                       (0x40u)
+#define GPIO_P95PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P96PFS_PSEL                                                       (0x07u)
+#define GPIO_P96PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P96PFS_ISEL                                                       (0x40u)
+#define GPIO_P96PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_P97PFS_PSEL                                                       (0x07u)
+#define GPIO_P97PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_P97PFS_ISEL                                                       (0x40u)
+#define GPIO_P97PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA0PFS_PSEL                                                       (0x07u)
+#define GPIO_PA0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA0PFS_ISEL                                                       (0x40u)
+#define GPIO_PA0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA1PFS_PSEL                                                       (0x07u)
+#define GPIO_PA1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA1PFS_ISEL                                                       (0x40u)
+#define GPIO_PA1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA2PFS_PSEL                                                       (0x07u)
+#define GPIO_PA2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA2PFS_ISEL                                                       (0x40u)
+#define GPIO_PA2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA3PFS_PSEL                                                       (0x07u)
+#define GPIO_PA3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA3PFS_ISEL                                                       (0x40u)
+#define GPIO_PA3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA4PFS_PSEL                                                       (0x07u)
+#define GPIO_PA4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA4PFS_ISEL                                                       (0x40u)
+#define GPIO_PA4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA5PFS_PSEL                                                       (0x07u)
+#define GPIO_PA5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA5PFS_ISEL                                                       (0x40u)
+#define GPIO_PA5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA6PFS_PSEL                                                       (0x07u)
+#define GPIO_PA6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA6PFS_ISEL                                                       (0x40u)
+#define GPIO_PA6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PA7PFS_PSEL                                                       (0x07u)
+#define GPIO_PA7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PA7PFS_ISEL                                                       (0x40u)
+#define GPIO_PA7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB0PFS_PSEL                                                       (0x07u)
+#define GPIO_PB0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB0PFS_ISEL                                                       (0x40u)
+#define GPIO_PB0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB1PFS_PSEL                                                       (0x07u)
+#define GPIO_PB1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB1PFS_ISEL                                                       (0x40u)
+#define GPIO_PB1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB2PFS_PSEL                                                       (0x07u)
+#define GPIO_PB2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB2PFS_ISEL                                                       (0x40u)
+#define GPIO_PB2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB3PFS_PSEL                                                       (0x07u)
+#define GPIO_PB3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB3PFS_ISEL                                                       (0x40u)
+#define GPIO_PB3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB4PFS_PSEL                                                       (0x07u)
+#define GPIO_PB4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB4PFS_ISEL                                                       (0x40u)
+#define GPIO_PB4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PB5PFS_PSEL                                                       (0x07u)
+#define GPIO_PB5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PB5PFS_ISEL                                                       (0x40u)
+#define GPIO_PB5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC0PFS_PSEL                                                       (0x07u)
+#define GPIO_PC0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC0PFS_ISEL                                                       (0x40u)
+#define GPIO_PC0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC1PFS_PSEL                                                       (0x07u)
+#define GPIO_PC1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC1PFS_ISEL                                                       (0x40u)
+#define GPIO_PC1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC2PFS_PSEL                                                       (0x07u)
+#define GPIO_PC2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC2PFS_ISEL                                                       (0x40u)
+#define GPIO_PC2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC3PFS_PSEL                                                       (0x07u)
+#define GPIO_PC3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC3PFS_ISEL                                                       (0x40u)
+#define GPIO_PC3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC4PFS_PSEL                                                       (0x07u)
+#define GPIO_PC4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC4PFS_ISEL                                                       (0x40u)
+#define GPIO_PC4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC5PFS_PSEL                                                       (0x07u)
+#define GPIO_PC5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC5PFS_ISEL                                                       (0x40u)
+#define GPIO_PC5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC6PFS_PSEL                                                       (0x07u)
+#define GPIO_PC6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC6PFS_ISEL                                                       (0x40u)
+#define GPIO_PC6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PC7PFS_PSEL                                                       (0x07u)
+#define GPIO_PC7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PC7PFS_ISEL                                                       (0x40u)
+#define GPIO_PC7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD0PFS_PSEL                                                       (0x07u)
+#define GPIO_PD0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD0PFS_ISEL                                                       (0x40u)
+#define GPIO_PD0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD1PFS_PSEL                                                       (0x07u)
+#define GPIO_PD1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD1PFS_ISEL                                                       (0x40u)
+#define GPIO_PD1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD2PFS_PSEL                                                       (0x07u)
+#define GPIO_PD2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD2PFS_ISEL                                                       (0x40u)
+#define GPIO_PD2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD3PFS_PSEL                                                       (0x07u)
+#define GPIO_PD3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD3PFS_ISEL                                                       (0x40u)
+#define GPIO_PD3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD4PFS_PSEL                                                       (0x07u)
+#define GPIO_PD4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD4PFS_ISEL                                                       (0x40u)
+#define GPIO_PD4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD5PFS_PSEL                                                       (0x07u)
+#define GPIO_PD5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD5PFS_ISEL                                                       (0x40u)
+#define GPIO_PD5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD6PFS_PSEL                                                       (0x07u)
+#define GPIO_PD6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD6PFS_ISEL                                                       (0x40u)
+#define GPIO_PD6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PD7PFS_PSEL                                                       (0x07u)
+#define GPIO_PD7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PD7PFS_ISEL                                                       (0x40u)
+#define GPIO_PD7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE0PFS_PSEL                                                       (0x07u)
+#define GPIO_PE0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE0PFS_ISEL                                                       (0x40u)
+#define GPIO_PE0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE1PFS_PSEL                                                       (0x07u)
+#define GPIO_PE1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE1PFS_ISEL                                                       (0x40u)
+#define GPIO_PE1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE2PFS_PSEL                                                       (0x07u)
+#define GPIO_PE2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE2PFS_ISEL                                                       (0x40u)
+#define GPIO_PE2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE3PFS_PSEL                                                       (0x07u)
+#define GPIO_PE3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE3PFS_ISEL                                                       (0x40u)
+#define GPIO_PE3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE4PFS_PSEL                                                       (0x07u)
+#define GPIO_PE4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE4PFS_ISEL                                                       (0x40u)
+#define GPIO_PE4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE5PFS_PSEL                                                       (0x07u)
+#define GPIO_PE5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE5PFS_ISEL                                                       (0x40u)
+#define GPIO_PE5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PE6PFS_PSEL                                                       (0x07u)
+#define GPIO_PE6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PE6PFS_ISEL                                                       (0x40u)
+#define GPIO_PE6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF0PFS_PSEL                                                       (0x07u)
+#define GPIO_PF0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF0PFS_ISEL                                                       (0x40u)
+#define GPIO_PF0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF1PFS_PSEL                                                       (0x07u)
+#define GPIO_PF1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF1PFS_ISEL                                                       (0x40u)
+#define GPIO_PF1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF2PFS_PSEL                                                       (0x07u)
+#define GPIO_PF2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF2PFS_ISEL                                                       (0x40u)
+#define GPIO_PF2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF3PFS_PSEL                                                       (0x07u)
+#define GPIO_PF3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF3PFS_ISEL                                                       (0x40u)
+#define GPIO_PF3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF4PFS_PSEL                                                       (0x07u)
+#define GPIO_PF4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF4PFS_ISEL                                                       (0x40u)
+#define GPIO_PF4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF5PFS_PSEL                                                       (0x07u)
+#define GPIO_PF5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF5PFS_ISEL                                                       (0x40u)
+#define GPIO_PF5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF6PFS_PSEL                                                       (0x07u)
+#define GPIO_PF6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF6PFS_ISEL                                                       (0x40u)
+#define GPIO_PF6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PF7PFS_PSEL                                                       (0x07u)
+#define GPIO_PF7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PF7PFS_ISEL                                                       (0x40u)
+#define GPIO_PF7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG0PFS_PSEL                                                       (0x07u)
+#define GPIO_PG0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG0PFS_ISEL                                                       (0x40u)
+#define GPIO_PG0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG1PFS_PSEL                                                       (0x07u)
+#define GPIO_PG1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG1PFS_ISEL                                                       (0x40u)
+#define GPIO_PG1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG2PFS_PSEL                                                       (0x07u)
+#define GPIO_PG2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG2PFS_ISEL                                                       (0x40u)
+#define GPIO_PG2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG3PFS_PSEL                                                       (0x07u)
+#define GPIO_PG3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG3PFS_ISEL                                                       (0x40u)
+#define GPIO_PG3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG4PFS_PSEL                                                       (0x07u)
+#define GPIO_PG4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG4PFS_ISEL                                                       (0x40u)
+#define GPIO_PG4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG5PFS_PSEL                                                       (0x07u)
+#define GPIO_PG5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG5PFS_ISEL                                                       (0x40u)
+#define GPIO_PG5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG6PFS_PSEL                                                       (0x07u)
+#define GPIO_PG6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG6PFS_ISEL                                                       (0x40u)
+#define GPIO_PG6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PG7PFS_PSEL                                                       (0x07u)
+#define GPIO_PG7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PG7PFS_ISEL                                                       (0x40u)
+#define GPIO_PG7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH0PFS_PSEL                                                       (0x07u)
+#define GPIO_PH0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH0PFS_ISEL                                                       (0x40u)
+#define GPIO_PH0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH1PFS_PSEL                                                       (0x07u)
+#define GPIO_PH1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH1PFS_ISEL                                                       (0x40u)
+#define GPIO_PH1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH2PFS_PSEL                                                       (0x07u)
+#define GPIO_PH2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH2PFS_ISEL                                                       (0x40u)
+#define GPIO_PH2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH3PFS_PSEL                                                       (0x07u)
+#define GPIO_PH3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH3PFS_ISEL                                                       (0x40u)
+#define GPIO_PH3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH4PFS_PSEL                                                       (0x07u)
+#define GPIO_PH4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH4PFS_ISEL                                                       (0x40u)
+#define GPIO_PH4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH5PFS_PSEL                                                       (0x07u)
+#define GPIO_PH5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH5PFS_ISEL                                                       (0x40u)
+#define GPIO_PH5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PH6PFS_PSEL                                                       (0x07u)
+#define GPIO_PH6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PH6PFS_ISEL                                                       (0x40u)
+#define GPIO_PH6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ0PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ0PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ1PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ1PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ2PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ2PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ3PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ3PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ4PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ4PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ5PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ5PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ6PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ6PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ6PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ6PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PJ7PFS_PSEL                                                       (0x07u)
+#define GPIO_PJ7PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PJ7PFS_ISEL                                                       (0x40u)
+#define GPIO_PJ7PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK0PFS_PSEL                                                       (0x07u)
+#define GPIO_PK0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK0PFS_ISEL                                                       (0x40u)
+#define GPIO_PK0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK1PFS_PSEL                                                       (0x07u)
+#define GPIO_PK1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK1PFS_ISEL                                                       (0x40u)
+#define GPIO_PK1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK2PFS_PSEL                                                       (0x07u)
+#define GPIO_PK2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK2PFS_ISEL                                                       (0x40u)
+#define GPIO_PK2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK3PFS_PSEL                                                       (0x07u)
+#define GPIO_PK3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK3PFS_ISEL                                                       (0x40u)
+#define GPIO_PK3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK4PFS_PSEL                                                       (0x07u)
+#define GPIO_PK4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK4PFS_ISEL                                                       (0x40u)
+#define GPIO_PK4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PK5PFS_PSEL                                                       (0x07u)
+#define GPIO_PK5PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PK5PFS_ISEL                                                       (0x40u)
+#define GPIO_PK5PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PL0PFS_PSEL                                                       (0x07u)
+#define GPIO_PL0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PL0PFS_ISEL                                                       (0x40u)
+#define GPIO_PL0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PL1PFS_PSEL                                                       (0x07u)
+#define GPIO_PL1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PL1PFS_ISEL                                                       (0x40u)
+#define GPIO_PL1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PL2PFS_PSEL                                                       (0x07u)
+#define GPIO_PL2PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PL2PFS_ISEL                                                       (0x40u)
+#define GPIO_PL2PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PL3PFS_PSEL                                                       (0x07u)
+#define GPIO_PL3PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PL3PFS_ISEL                                                       (0x40u)
+#define GPIO_PL3PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PL4PFS_PSEL                                                       (0x07u)
+#define GPIO_PL4PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PL4PFS_ISEL                                                       (0x40u)
+#define GPIO_PL4PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PM0PFS_PSEL                                                       (0x07u)
+#define GPIO_PM0PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PM0PFS_ISEL                                                       (0x40u)
+#define GPIO_PM0PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PM1PFS_PSEL                                                       (0x07u)
+#define GPIO_PM1PFS_PSEL_SHIFT                                                 (0u)
+#define GPIO_PM1PFS_ISEL                                                       (0x40u)
+#define GPIO_PM1PFS_ISEL_SHIFT                                                 (6u)
+#define GPIO_PWPR_PFSWE                                                        (0x40u)
+#define GPIO_PWPR_PFSWE_SHIFT                                                  (6u)
+#define GPIO_PWPR_B0WI                                                         (0x80u)
+#define GPIO_PWPR_B0WI_SHIFT                                                   (7u)
+#define GPIO_PFENET_PHYMODE0                                                   (0x01u)
+#define GPIO_PFENET_PHYMODE0_SHIFT                                             (0u)
+#define GPIO_PFENET_PHYMODE1                                                   (0x02u)
+#define GPIO_PFENET_PHYMODE1_SHIFT                                             (1u)
+#define GPIO_PPOC_POC0                                                         (0x00000001u)
+#define GPIO_PPOC_POC0_SHIFT                                                   (0u)
+#define GPIO_PPOC_POC2                                                         (0x00000004u)
+#define GPIO_PPOC_POC2_SHIFT                                                   (2u)
+#define GPIO_PPOC_POC3                                                         (0x00000008u)
+#define GPIO_PPOC_POC3_SHIFT                                                   (3u)
+#define GPIO_PPOC_POCSEL0                                                      (0x00000100u)
+#define GPIO_PPOC_POCSEL0_SHIFT                                                (8u)
+#define GPIO_PSDMMC0_SD0_CLK_DRV                                               (0x00000003u)
+#define GPIO_PSDMMC0_SD0_CLK_DRV_SHIFT                                         (0u)
+#define GPIO_PSDMMC0_SD0_CMD_DRV                                               (0x0000000Cu)
+#define GPIO_PSDMMC0_SD0_CMD_DRV_SHIFT                                         (2u)
+#define GPIO_PSDMMC0_SD0_DAT0_DRV                                              (0x00000030u)
+#define GPIO_PSDMMC0_SD0_DAT0_DRV_SHIFT                                        (4u)
+#define GPIO_PSDMMC0_SD0_DAT1_DRV                                              (0x000000C0u)
+#define GPIO_PSDMMC0_SD0_DAT1_DRV_SHIFT                                        (6u)
+#define GPIO_PSDMMC0_SD0_DAT2_DRV                                              (0x00000300u)
+#define GPIO_PSDMMC0_SD0_DAT2_DRV_SHIFT                                        (8u)
+#define GPIO_PSDMMC0_SD0_DAT3_DRV                                              (0x00000C00u)
+#define GPIO_PSDMMC0_SD0_DAT3_DRV_SHIFT                                        (10u)
+#define GPIO_PSDMMC0_SD0_CLK_TDSEL                                             (0x00003000u)
+#define GPIO_PSDMMC0_SD0_CLK_TDSEL_SHIFT                                       (12u)
+#define GPIO_PSDMMC1_SD0_DAT4_DRV                                              (0x00000003u)
+#define GPIO_PSDMMC1_SD0_DAT4_DRV_SHIFT                                        (0u)
+#define GPIO_PSDMMC1_SD0_DAT5_DRV                                              (0x0000000Cu)
+#define GPIO_PSDMMC1_SD0_DAT5_DRV_SHIFT                                        (2u)
+#define GPIO_PSDMMC1_SD0_DAT6_DRV                                              (0x00000030u)
+#define GPIO_PSDMMC1_SD0_DAT6_DRV_SHIFT                                        (4u)
+#define GPIO_PSDMMC1_SD0_DAT7_DRV                                              (0x000000C0u)
+#define GPIO_PSDMMC1_SD0_DAT7_DRV_SHIFT                                        (6u)
+#define GPIO_PSDMMC1_SD0_RSTN_DRV                                              (0x00000300u)
+#define GPIO_PSDMMC1_SD0_RSTN_DRV_SHIFT                                        (8u)
+#define GPIO_PSDMMC2_SD1_CLK_DRV                                               (0x00000003u)
+#define GPIO_PSDMMC2_SD1_CLK_DRV_SHIFT                                         (0u)
+#define GPIO_PSDMMC2_SD1_CMD_DRV                                               (0x0000000Cu)
+#define GPIO_PSDMMC2_SD1_CMD_DRV_SHIFT                                         (2u)
+#define GPIO_PSDMMC2_SD1_DAT0_DRV                                              (0x00000030u)
+#define GPIO_PSDMMC2_SD1_DAT0_DRV_SHIFT                                        (4u)
+#define GPIO_PSDMMC2_SD1_DAT1_DRV                                              (0x000000C0u)
+#define GPIO_PSDMMC2_SD1_DAT1_DRV_SHIFT                                        (6u)
+#define GPIO_PSDMMC2_SD1_DAT2_DRV                                              (0x00000300u)
+#define GPIO_PSDMMC2_SD1_DAT2_DRV_SHIFT                                        (8u)
+#define GPIO_PSDMMC2_SD1_DAT3_DRV                                              (0x00000C00u)
+#define GPIO_PSDMMC2_SD1_DAT3_DRV_SHIFT                                        (10u)
+#define GPIO_PSDMMC2_SD1_CLK_TDSEL                                             (0x00003000u)
+#define GPIO_PSDMMC2_SD1_CLK_TDSEL_SHIFT                                       (12u)
+#define GPIO_PSPIBSC_QSPI0_SPCLK_DRV                                           (0x00000003u)
+#define GPIO_PSPIBSC_QSPI0_SPCLK_DRV_SHIFT                                     (0u)
+#define GPIO_PSPIBSC_QSPI0_IO0_DRV                                             (0x0000000Cu)
+#define GPIO_PSPIBSC_QSPI0_IO0_DRV_SHIFT                                       (2u)
+#define GPIO_PSPIBSC_QSPI0_IO1_DRV                                             (0x00000030u)
+#define GPIO_PSPIBSC_QSPI0_IO1_DRV_SHIFT                                       (4u)
+#define GPIO_PSPIBSC_QSPI0_IO2_DRV                                             (0x000000C0u)
+#define GPIO_PSPIBSC_QSPI0_IO2_DRV_SHIFT                                       (6u)
+#define GPIO_PSPIBSC_QSPI0_IO3_DRV                                             (0x00000300u)
+#define GPIO_PSPIBSC_QSPI0_IO3_DRV_SHIFT                                       (8u)
+#define GPIO_PSPIBSC_QSPI0_SSL_DRV                                             (0x00000C00u)
+#define GPIO_PSPIBSC_QSPI0_SSL_DRV_SHIFT                                       (10u)
+#define GPIO_PSPIBSC_RPC_RESETN_DRV                                            (0x00003000u)
+#define GPIO_PSPIBSC_RPC_RESETN_DRV_SHIFT                                      (12u)
+#define GPIO_PSPIBSC_RPC_WPN_DRV                                               (0x0000C000u)
+#define GPIO_PSPIBSC_RPC_WPN_DRV_SHIFT                                         (14u)
+#define GPIO_PSPIBSC_QSPI1_SPCLK_DRV                                           (0x00030000u)
+#define GPIO_PSPIBSC_QSPI1_SPCLK_DRV_SHIFT                                     (16u)
+#define GPIO_PSPIBSC_QSPI1_IO0_DRV                                             (0x000C0000u)
+#define GPIO_PSPIBSC_QSPI1_IO0_DRV_SHIFT                                       (18u)
+#define GPIO_PSPIBSC_QSPI1_IO1_DRV                                             (0x00300000u)
+#define GPIO_PSPIBSC_QSPI1_IO1_DRV_SHIFT                                       (20u)
+#define GPIO_PSPIBSC_QSPI1_IO2_DRV                                             (0x00C00000u)
+#define GPIO_PSPIBSC_QSPI1_IO2_DRV_SHIFT                                       (22u)
+#define GPIO_PSPIBSC_QSPI1_IO3_DRV                                             (0x03000000u)
+#define GPIO_PSPIBSC_QSPI1_IO3_DRV_SHIFT                                       (24u)
+#define GPIO_PSPIBSC_QSPI1_SSL_DRV                                             (0x0C000000u)
+#define GPIO_PSPIBSC_QSPI1_SSL_DRV_SHIFT                                       (26u)
+#define GPIO_PHMOM0_HOSEL                                                      (0x00000001u)
+#define GPIO_PHMOM0_HOSEL_SHIFT                                                (0u)
+#define GPIO_PMODEPFS_ET0_EXOUT_SEL                                            (0x00000001u)
+#define GPIO_PMODEPFS_ET0_EXOUT_SEL_SHIFT                                      (0u)
+#define GPIO_PMODEPFS_ET1_EXOUT_SEL                                            (0x00000002u)
+#define GPIO_PMODEPFS_ET1_EXOUT_SEL_SHIFT                                      (1u)
+#define GPIO_PMODEPFS_VBUS0_SEL                                                (0x00000004u)
+#define GPIO_PMODEPFS_VBUS0_SEL_SHIFT                                          (2u)
+#define GPIO_PMODEPFS_VBUS1_SEL                                                (0x00000008u)
+#define GPIO_PMODEPFS_VBUS1_SEL_SHIFT                                          (3u)
+#define GPIO_PCKIO_CKIO_DRV                                                    (0x03u)
+#define GPIO_PCKIO_CKIO_DRV_SHIFT                                              (0u)
+#define GPIO_PDR_PDR0                                                          (0x0003u)
+#define GPIO_PDR_PDR0_SHIFT                                                    (0u)
+#define GPIO_PDR_PDR1                                                          (0x000Cu)
+#define GPIO_PDR_PDR1_SHIFT                                                    (2u)
+#define GPIO_PDR_PDR2                                                          (0x0030u)
+#define GPIO_PDR_PDR2_SHIFT                                                    (4u)
+#define GPIO_PDR_PDR3                                                          (0x00C0u)
+#define GPIO_PDR_PDR3_SHIFT                                                    (6u)
+#define GPIO_PDR_PDR4                                                          (0x0300u)
+#define GPIO_PDR_PDR4_SHIFT                                                    (8u)
+#define GPIO_PDR_PDR5                                                          (0x0C00u)
+#define GPIO_PDR_PDR5_SHIFT                                                    (10u)
+#define GPIO_PDR_PDR6                                                          (0x3000u)
+#define GPIO_PDR_PDR6_SHIFT                                                    (12u)
+#define GPIO_PODR_PODR0                                                        (0x01u)
+#define GPIO_PODR_PODR0_SHIFT                                                  (0u)
+#define GPIO_PODR_PODR1                                                        (0x02u)
+#define GPIO_PODR_PODR1_SHIFT                                                  (1u)
+#define GPIO_PODR_PODR2                                                        (0x04u)
+#define GPIO_PODR_PODR2_SHIFT                                                  (2u)
+#define GPIO_PODR_PODR3                                                        (0x08u)
+#define GPIO_PODR_PODR3_SHIFT                                                  (3u)
+#define GPIO_PODR_PODR4                                                        (0x10u)
+#define GPIO_PODR_PODR4_SHIFT                                                  (4u)
+#define GPIO_PODR_PODR5                                                        (0x20u)
+#define GPIO_PODR_PODR5_SHIFT                                                  (5u)
+#define GPIO_PODR_PODR6                                                        (0x40u)
+#define GPIO_PODR_PODR6_SHIFT                                                  (6u)
+#define GPIO_PIDR_PIDR0                                                        (0x01u)
+#define GPIO_PIDR_PIDR0_SHIFT                                                  (0u)
+#define GPIO_PIDR_PIDR1                                                        (0x02u)
+#define GPIO_PIDR_PIDR1_SHIFT                                                  (1u)
+#define GPIO_PIDR_PIDR2                                                        (0x04u)
+#define GPIO_PIDR_PIDR2_SHIFT                                                  (2u)
+#define GPIO_PIDR_PIDR3                                                        (0x08u)
+#define GPIO_PIDR_PIDR3_SHIFT                                                  (3u)
+#define GPIO_PIDR_PIDR4                                                        (0x10u)
+#define GPIO_PIDR_PIDR4_SHIFT                                                  (4u)
+#define GPIO_PIDR_PIDR5                                                        (0x20u)
+#define GPIO_PIDR_PIDR5_SHIFT                                                  (5u)
+#define GPIO_PIDR_PIDR6                                                        (0x40u)
+#define GPIO_PIDR_PIDR6_SHIFT                                                  (6u)
+#define GPIO_PMR_PMR0                                                          (0x01u)
+#define GPIO_PMR_PMR0_SHIFT                                                    (0u)
+#define GPIO_PMR_PMR1                                                          (0x02u)
+#define GPIO_PMR_PMR1_SHIFT                                                    (1u)
+#define GPIO_PMR_PMR2                                                          (0x04u)
+#define GPIO_PMR_PMR2_SHIFT                                                    (2u)
+#define GPIO_PMR_PMR3                                                          (0x08u)
+#define GPIO_PMR_PMR3_SHIFT                                                    (3u)
+#define GPIO_PMR_PMR4                                                          (0x10u)
+#define GPIO_PMR_PMR4_SHIFT                                                    (4u)
+#define GPIO_PMR_PMR5                                                          (0x20u)
+#define GPIO_PMR_PMR5_SHIFT                                                    (5u)
+#define GPIO_PMR_PMR6                                                          (0x40u)
+#define GPIO_PMR_PMR6_SHIFT                                                    (6u)
+#define GPIO_DSCR_DSCR0                                                        (0x0003u)
+#define GPIO_DSCR_DSCR0_SHIFT                                                  (0u)
+#define GPIO_DSCR_DSCR1                                                        (0x000Cu)
+#define GPIO_DSCR_DSCR1_SHIFT                                                  (2u)
+#define GPIO_DSCR_DSCR2                                                        (0x0030u)
+#define GPIO_DSCR_DSCR2_SHIFT                                                  (4u)
+#define GPIO_DSCR_DSCR3                                                        (0x00C0u)
+#define GPIO_DSCR_DSCR3_SHIFT                                                  (6u)
+#define GPIO_DSCR_DSCR4                                                        (0x0300u)
+#define GPIO_DSCR_DSCR4_SHIFT                                                  (8u)
+#define GPIO_DSCR_DSCR5                                                        (0x0C00u)
+#define GPIO_DSCR_DSCR5_SHIFT                                                  (10u)
+#define GPIO_DSCR_DSCR6                                                        (0x3000u)
+#define GPIO_DSCR_DSCR6_SHIFT                                                  (12u)
+#define GPIO_PDR_PDR7                                                          (0xC000u)
+#define GPIO_PDR_PDR7_SHIFT                                                    (14u)
+#define GPIO_PODR_PODR7                                                        (0x80u)
+#define GPIO_PODR_PODR7_SHIFT                                                  (7u)
+#define GPIO_PIDR_PIDR7                                                        (0x80u)
+#define GPIO_PIDR_PIDR7_SHIFT                                                  (7u)
+#define GPIO_PMR_PMR7                                                          (0x80u)
+#define GPIO_PMR_PMR7_SHIFT                                                    (7u)
+#define GPIO_DSCR_DSCR7                                                        (0xC000u)
+#define GPIO_DSCR_DSCR7_SHIFT                                                  (14u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpt_iobitmask.h

@@ -0,0 +1,668 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef GPT_IOBITMASK_H
+#define GPT_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define GPT_GTECR_EVCON                                                        (0x80u)
+#define GPT_GTECR_EVCON_SHIFT                                                  (7u)
+#define GPT_GTESR0_EVS                                                         (0x007Fu)
+#define GPT_GTESR0_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR1_EVS                                                         (0x007Fu)
+#define GPT_GTESR1_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR2_EVS                                                         (0x007Fu)
+#define GPT_GTESR2_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR3_EVS                                                         (0x007Fu)
+#define GPT_GTESR3_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR4_EVS                                                         (0x007Fu)
+#define GPT_GTESR4_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR5_EVS                                                         (0x007Fu)
+#define GPT_GTESR5_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR6_EVS                                                         (0x007Fu)
+#define GPT_GTESR6_EVS_SHIFT                                                   (0u)
+#define GPT_GTESR7_EVS                                                         (0x007Fu)
+#define GPT_GTESR7_EVS_SHIFT                                                   (0u)
+#define GPT_GTWP_WP                                                            (0x00000001u)
+#define GPT_GTWP_WP_SHIFT                                                      (0u)
+#define GPT_GTWP_PRKEY                                                         (0x0000FF00u)
+#define GPT_GTWP_PRKEY_SHIFT                                                   (8u)
+#define GPT_GTSTR_CSTRT0                                                       (0x00000001u)
+#define GPT_GTSTR_CSTRT0_SHIFT                                                 (0u)
+#define GPT_GTSTR_CSTRT1                                                       (0x00000002u)
+#define GPT_GTSTR_CSTRT1_SHIFT                                                 (1u)
+#define GPT_GTSTR_CSTRT2                                                       (0x00000004u)
+#define GPT_GTSTR_CSTRT2_SHIFT                                                 (2u)
+#define GPT_GTSTR_CSTRT3                                                       (0x00000008u)
+#define GPT_GTSTR_CSTRT3_SHIFT                                                 (3u)
+#define GPT_GTSTR_CSTRT4                                                       (0x00000010u)
+#define GPT_GTSTR_CSTRT4_SHIFT                                                 (4u)
+#define GPT_GTSTR_CSTRT5                                                       (0x00000020u)
+#define GPT_GTSTR_CSTRT5_SHIFT                                                 (5u)
+#define GPT_GTSTR_CSTRT6                                                       (0x00000040u)
+#define GPT_GTSTR_CSTRT6_SHIFT                                                 (6u)
+#define GPT_GTSTR_CSTRT7                                                       (0x00000080u)
+#define GPT_GTSTR_CSTRT7_SHIFT                                                 (7u)
+#define GPT_GTSTP_CSTOP0                                                       (0x00000001u)
+#define GPT_GTSTP_CSTOP0_SHIFT                                                 (0u)
+#define GPT_GTSTP_CSTOP1                                                       (0x00000002u)
+#define GPT_GTSTP_CSTOP1_SHIFT                                                 (1u)
+#define GPT_GTSTP_CSTOP2                                                       (0x00000004u)
+#define GPT_GTSTP_CSTOP2_SHIFT                                                 (2u)
+#define GPT_GTSTP_CSTOP3                                                       (0x00000008u)
+#define GPT_GTSTP_CSTOP3_SHIFT                                                 (3u)
+#define GPT_GTSTP_CSTOP4                                                       (0x00000010u)
+#define GPT_GTSTP_CSTOP4_SHIFT                                                 (4u)
+#define GPT_GTSTP_CSTOP5                                                       (0x00000020u)
+#define GPT_GTSTP_CSTOP5_SHIFT                                                 (5u)
+#define GPT_GTSTP_CSTOP6                                                       (0x00000040u)
+#define GPT_GTSTP_CSTOP6_SHIFT                                                 (6u)
+#define GPT_GTSTP_CSTOP7                                                       (0x00000080u)
+#define GPT_GTSTP_CSTOP7_SHIFT                                                 (7u)
+#define GPT_GTCLR_CCLR0                                                        (0x00000001u)
+#define GPT_GTCLR_CCLR0_SHIFT                                                  (0u)
+#define GPT_GTCLR_CCLR1                                                        (0x00000002u)
+#define GPT_GTCLR_CCLR1_SHIFT                                                  (1u)
+#define GPT_GTCLR_CCLR2                                                        (0x00000004u)
+#define GPT_GTCLR_CCLR2_SHIFT                                                  (2u)
+#define GPT_GTCLR_CCLR3                                                        (0x00000008u)
+#define GPT_GTCLR_CCLR3_SHIFT                                                  (3u)
+#define GPT_GTCLR_CCLR4                                                        (0x00000010u)
+#define GPT_GTCLR_CCLR4_SHIFT                                                  (4u)
+#define GPT_GTCLR_CCLR5                                                        (0x00000020u)
+#define GPT_GTCLR_CCLR5_SHIFT                                                  (5u)
+#define GPT_GTCLR_CCLR6                                                        (0x00000040u)
+#define GPT_GTCLR_CCLR6_SHIFT                                                  (6u)
+#define GPT_GTCLR_CCLR7                                                        (0x00000080u)
+#define GPT_GTCLR_CCLR7_SHIFT                                                  (7u)
+#define GPT_GTSSR_SSGTRGAR                                                     (0x00000001u)
+#define GPT_GTSSR_SSGTRGAR_SHIFT                                               (0u)
+#define GPT_GTSSR_SSGTRGAF                                                     (0x00000002u)
+#define GPT_GTSSR_SSGTRGAF_SHIFT                                               (1u)
+#define GPT_GTSSR_SSGTRGBR                                                     (0x00000004u)
+#define GPT_GTSSR_SSGTRGBR_SHIFT                                               (2u)
+#define GPT_GTSSR_SSGTRGBF                                                     (0x00000008u)
+#define GPT_GTSSR_SSGTRGBF_SHIFT                                               (3u)
+#define GPT_GTSSR_SSGTRGCR                                                     (0x00000010u)
+#define GPT_GTSSR_SSGTRGCR_SHIFT                                               (4u)
+#define GPT_GTSSR_SSGTRGCF                                                     (0x00000020u)
+#define GPT_GTSSR_SSGTRGCF_SHIFT                                               (5u)
+#define GPT_GTSSR_SSGTRGDR                                                     (0x00000040u)
+#define GPT_GTSSR_SSGTRGDR_SHIFT                                               (6u)
+#define GPT_GTSSR_SSGTRGDF                                                     (0x00000080u)
+#define GPT_GTSSR_SSGTRGDF_SHIFT                                               (7u)
+#define GPT_GTSSR_SSCARBL                                                      (0x00000100u)
+#define GPT_GTSSR_SSCARBL_SHIFT                                                (8u)
+#define GPT_GTSSR_SSCARBH                                                      (0x00000200u)
+#define GPT_GTSSR_SSCARBH_SHIFT                                                (9u)
+#define GPT_GTSSR_SSCAFBL                                                      (0x00000400u)
+#define GPT_GTSSR_SSCAFBL_SHIFT                                                (10u)
+#define GPT_GTSSR_SSCAFBH                                                      (0x00000800u)
+#define GPT_GTSSR_SSCAFBH_SHIFT                                                (11u)
+#define GPT_GTSSR_SSCBRAL                                                      (0x00001000u)
+#define GPT_GTSSR_SSCBRAL_SHIFT                                                (12u)
+#define GPT_GTSSR_SSCBRAH                                                      (0x00002000u)
+#define GPT_GTSSR_SSCBRAH_SHIFT                                                (13u)
+#define GPT_GTSSR_SSCBFAL                                                      (0x00004000u)
+#define GPT_GTSSR_SSCBFAL_SHIFT                                                (14u)
+#define GPT_GTSSR_SSCBFAH                                                      (0x00008000u)
+#define GPT_GTSSR_SSCBFAH_SHIFT                                                (15u)
+#define GPT_GTSSR_SSEVTA                                                       (0x00010000u)
+#define GPT_GTSSR_SSEVTA_SHIFT                                                 (16u)
+#define GPT_GTSSR_SSEVTB                                                       (0x00020000u)
+#define GPT_GTSSR_SSEVTB_SHIFT                                                 (17u)
+#define GPT_GTSSR_SSEVTC                                                       (0x00040000u)
+#define GPT_GTSSR_SSEVTC_SHIFT                                                 (18u)
+#define GPT_GTSSR_SSEVTD                                                       (0x00080000u)
+#define GPT_GTSSR_SSEVTD_SHIFT                                                 (19u)
+#define GPT_GTSSR_SSEVTE                                                       (0x00100000u)
+#define GPT_GTSSR_SSEVTE_SHIFT                                                 (20u)
+#define GPT_GTSSR_SSEVTF                                                       (0x00200000u)
+#define GPT_GTSSR_SSEVTF_SHIFT                                                 (21u)
+#define GPT_GTSSR_SSEVTG                                                       (0x00400000u)
+#define GPT_GTSSR_SSEVTG_SHIFT                                                 (22u)
+#define GPT_GTSSR_SSEVTH                                                       (0x00800000u)
+#define GPT_GTSSR_SSEVTH_SHIFT                                                 (23u)
+#define GPT_GTSSR_CSTRT                                                        (0x80000000u)
+#define GPT_GTSSR_CSTRT_SHIFT                                                  (31u)
+#define GPT_GTPSR_PSGTRGAR                                                     (0x00000001u)
+#define GPT_GTPSR_PSGTRGAR_SHIFT                                               (0u)
+#define GPT_GTPSR_PSGTRGAF                                                     (0x00000002u)
+#define GPT_GTPSR_PSGTRGAF_SHIFT                                               (1u)
+#define GPT_GTPSR_PSGTRGBR                                                     (0x00000004u)
+#define GPT_GTPSR_PSGTRGBR_SHIFT                                               (2u)
+#define GPT_GTPSR_PSGTRGBF                                                     (0x00000008u)
+#define GPT_GTPSR_PSGTRGBF_SHIFT                                               (3u)
+#define GPT_GTPSR_PSGTRGCR                                                     (0x00000010u)
+#define GPT_GTPSR_PSGTRGCR_SHIFT                                               (4u)
+#define GPT_GTPSR_PSGTRGCF                                                     (0x00000020u)
+#define GPT_GTPSR_PSGTRGCF_SHIFT                                               (5u)
+#define GPT_GTPSR_PSGTRGDR                                                     (0x00000040u)
+#define GPT_GTPSR_PSGTRGDR_SHIFT                                               (6u)
+#define GPT_GTPSR_PSGTRGDF                                                     (0x00000080u)
+#define GPT_GTPSR_PSGTRGDF_SHIFT                                               (7u)
+#define GPT_GTPSR_PSCARBL                                                      (0x00000100u)
+#define GPT_GTPSR_PSCARBL_SHIFT                                                (8u)
+#define GPT_GTPSR_PSCARBH                                                      (0x00000200u)
+#define GPT_GTPSR_PSCARBH_SHIFT                                                (9u)
+#define GPT_GTPSR_PSCAFBL                                                      (0x00000400u)
+#define GPT_GTPSR_PSCAFBL_SHIFT                                                (10u)
+#define GPT_GTPSR_PSCAFBH                                                      (0x00000800u)
+#define GPT_GTPSR_PSCAFBH_SHIFT                                                (11u)
+#define GPT_GTPSR_PSCBRAL                                                      (0x00001000u)
+#define GPT_GTPSR_PSCBRAL_SHIFT                                                (12u)
+#define GPT_GTPSR_PSCBRAH                                                      (0x00002000u)
+#define GPT_GTPSR_PSCBRAH_SHIFT                                                (13u)
+#define GPT_GTPSR_PSCBFAL                                                      (0x00004000u)
+#define GPT_GTPSR_PSCBFAL_SHIFT                                                (14u)
+#define GPT_GTPSR_PSCBFAH                                                      (0x00008000u)
+#define GPT_GTPSR_PSCBFAH_SHIFT                                                (15u)
+#define GPT_GTPSR_PSEVTA                                                       (0x00010000u)
+#define GPT_GTPSR_PSEVTA_SHIFT                                                 (16u)
+#define GPT_GTPSR_PSEVTB                                                       (0x00020000u)
+#define GPT_GTPSR_PSEVTB_SHIFT                                                 (17u)
+#define GPT_GTPSR_PSEVTC                                                       (0x00040000u)
+#define GPT_GTPSR_PSEVTC_SHIFT                                                 (18u)
+#define GPT_GTPSR_PSEVTD                                                       (0x00080000u)
+#define GPT_GTPSR_PSEVTD_SHIFT                                                 (19u)
+#define GPT_GTPSR_PSEVTE                                                       (0x00100000u)
+#define GPT_GTPSR_PSEVTE_SHIFT                                                 (20u)
+#define GPT_GTPSR_PSEVTF                                                       (0x00200000u)
+#define GPT_GTPSR_PSEVTF_SHIFT                                                 (21u)
+#define GPT_GTPSR_PSEVTG                                                       (0x00400000u)
+#define GPT_GTPSR_PSEVTG_SHIFT                                                 (22u)
+#define GPT_GTPSR_PSEVTH                                                       (0x00800000u)
+#define GPT_GTPSR_PSEVTH_SHIFT                                                 (23u)
+#define GPT_GTPSR_CSTOP                                                        (0x80000000u)
+#define GPT_GTPSR_CSTOP_SHIFT                                                  (31u)
+#define GPT_GTCSR_CSGTRGAR                                                     (0x00000001u)
+#define GPT_GTCSR_CSGTRGAR_SHIFT                                               (0u)
+#define GPT_GTCSR_CSGTRGAF                                                     (0x00000002u)
+#define GPT_GTCSR_CSGTRGAF_SHIFT                                               (1u)
+#define GPT_GTCSR_CSGTRGBR                                                     (0x00000004u)
+#define GPT_GTCSR_CSGTRGBR_SHIFT                                               (2u)
+#define GPT_GTCSR_CSGTRGBF                                                     (0x00000008u)
+#define GPT_GTCSR_CSGTRGBF_SHIFT                                               (3u)
+#define GPT_GTCSR_CSGTRGCR                                                     (0x00000010u)
+#define GPT_GTCSR_CSGTRGCR_SHIFT                                               (4u)
+#define GPT_GTCSR_CSGTRGCF                                                     (0x00000020u)
+#define GPT_GTCSR_CSGTRGCF_SHIFT                                               (5u)
+#define GPT_GTCSR_CSGTRGDR                                                     (0x00000040u)
+#define GPT_GTCSR_CSGTRGDR_SHIFT                                               (6u)
+#define GPT_GTCSR_CSGTRGDF                                                     (0x00000080u)
+#define GPT_GTCSR_CSGTRGDF_SHIFT                                               (7u)
+#define GPT_GTCSR_CSCARBL                                                      (0x00000100u)
+#define GPT_GTCSR_CSCARBL_SHIFT                                                (8u)
+#define GPT_GTCSR_CSCARBH                                                      (0x00000200u)
+#define GPT_GTCSR_CSCARBH_SHIFT                                                (9u)
+#define GPT_GTCSR_CSCAFBL                                                      (0x00000400u)
+#define GPT_GTCSR_CSCAFBL_SHIFT                                                (10u)
+#define GPT_GTCSR_CSCAFBH                                                      (0x00000800u)
+#define GPT_GTCSR_CSCAFBH_SHIFT                                                (11u)
+#define GPT_GTCSR_CSCBRAL                                                      (0x00001000u)
+#define GPT_GTCSR_CSCBRAL_SHIFT                                                (12u)
+#define GPT_GTCSR_CSCBRAH                                                      (0x00002000u)
+#define GPT_GTCSR_CSCBRAH_SHIFT                                                (13u)
+#define GPT_GTCSR_CSCBFAL                                                      (0x00004000u)
+#define GPT_GTCSR_CSCBFAL_SHIFT                                                (14u)
+#define GPT_GTCSR_CSCBFAH                                                      (0x00008000u)
+#define GPT_GTCSR_CSCBFAH_SHIFT                                                (15u)
+#define GPT_GTCSR_CSEVTA                                                       (0x00010000u)
+#define GPT_GTCSR_CSEVTA_SHIFT                                                 (16u)
+#define GPT_GTCSR_CSEVTB                                                       (0x00020000u)
+#define GPT_GTCSR_CSEVTB_SHIFT                                                 (17u)
+#define GPT_GTCSR_CSEVTC                                                       (0x00040000u)
+#define GPT_GTCSR_CSEVTC_SHIFT                                                 (18u)
+#define GPT_GTCSR_CSEVTD                                                       (0x00080000u)
+#define GPT_GTCSR_CSEVTD_SHIFT                                                 (19u)
+#define GPT_GTCSR_CSEVTE                                                       (0x00100000u)
+#define GPT_GTCSR_CSEVTE_SHIFT                                                 (20u)
+#define GPT_GTCSR_CSEVTF                                                       (0x00200000u)
+#define GPT_GTCSR_CSEVTF_SHIFT                                                 (21u)
+#define GPT_GTCSR_CSEVTG                                                       (0x00400000u)
+#define GPT_GTCSR_CSEVTG_SHIFT                                                 (22u)
+#define GPT_GTCSR_CSEVTH                                                       (0x00800000u)
+#define GPT_GTCSR_CSEVTH_SHIFT                                                 (23u)
+#define GPT_GTCSR_CCLR                                                         (0x80000000u)
+#define GPT_GTCSR_CCLR_SHIFT                                                   (31u)
+#define GPT_GTUPSR_USGTRGAR                                                    (0x00000001u)
+#define GPT_GTUPSR_USGTRGAR_SHIFT                                              (0u)
+#define GPT_GTUPSR_USGTRGAF                                                    (0x00000002u)
+#define GPT_GTUPSR_USGTRGAF_SHIFT                                              (1u)
+#define GPT_GTUPSR_USGTRGBR                                                    (0x00000004u)
+#define GPT_GTUPSR_USGTRGBR_SHIFT                                              (2u)
+#define GPT_GTUPSR_USGTRGBF                                                    (0x00000008u)
+#define GPT_GTUPSR_USGTRGBF_SHIFT                                              (3u)
+#define GPT_GTUPSR_USGTRGCR                                                    (0x00000010u)
+#define GPT_GTUPSR_USGTRGCR_SHIFT                                              (4u)
+#define GPT_GTUPSR_USGTRGCF                                                    (0x00000020u)
+#define GPT_GTUPSR_USGTRGCF_SHIFT                                              (5u)
+#define GPT_GTUPSR_USGTRGDR                                                    (0x00000040u)
+#define GPT_GTUPSR_USGTRGDR_SHIFT                                              (6u)
+#define GPT_GTUPSR_USGTRGDF                                                    (0x00000080u)
+#define GPT_GTUPSR_USGTRGDF_SHIFT                                              (7u)
+#define GPT_GTUPSR_USCARBL                                                     (0x00000100u)
+#define GPT_GTUPSR_USCARBL_SHIFT                                               (8u)
+#define GPT_GTUPSR_USCARBH                                                     (0x00000200u)
+#define GPT_GTUPSR_USCARBH_SHIFT                                               (9u)
+#define GPT_GTUPSR_USCAFBL                                                     (0x00000400u)
+#define GPT_GTUPSR_USCAFBL_SHIFT                                               (10u)
+#define GPT_GTUPSR_USCAFBH                                                     (0x00000800u)
+#define GPT_GTUPSR_USCAFBH_SHIFT                                               (11u)
+#define GPT_GTUPSR_USCBRAL                                                     (0x00001000u)
+#define GPT_GTUPSR_USCBRAL_SHIFT                                               (12u)
+#define GPT_GTUPSR_USCBRAH                                                     (0x00002000u)
+#define GPT_GTUPSR_USCBRAH_SHIFT                                               (13u)
+#define GPT_GTUPSR_USCBFAL                                                     (0x00004000u)
+#define GPT_GTUPSR_USCBFAL_SHIFT                                               (14u)
+#define GPT_GTUPSR_USCBFAH                                                     (0x00008000u)
+#define GPT_GTUPSR_USCBFAH_SHIFT                                               (15u)
+#define GPT_GTUPSR_USEVTA                                                      (0x00010000u)
+#define GPT_GTUPSR_USEVTA_SHIFT                                                (16u)
+#define GPT_GTUPSR_USEVTB                                                      (0x00020000u)
+#define GPT_GTUPSR_USEVTB_SHIFT                                                (17u)
+#define GPT_GTUPSR_USEVTC                                                      (0x00040000u)
+#define GPT_GTUPSR_USEVTC_SHIFT                                                (18u)
+#define GPT_GTUPSR_USEVTD                                                      (0x00080000u)
+#define GPT_GTUPSR_USEVTD_SHIFT                                                (19u)
+#define GPT_GTUPSR_USEVTE                                                      (0x00100000u)
+#define GPT_GTUPSR_USEVTE_SHIFT                                                (20u)
+#define GPT_GTUPSR_USEVTF                                                      (0x00200000u)
+#define GPT_GTUPSR_USEVTF_SHIFT                                                (21u)
+#define GPT_GTUPSR_USEVTG                                                      (0x00400000u)
+#define GPT_GTUPSR_USEVTG_SHIFT                                                (22u)
+#define GPT_GTUPSR_USEVTH                                                      (0x00800000u)
+#define GPT_GTUPSR_USEVTH_SHIFT                                                (23u)
+#define GPT_GTDNSR_DSGTRGAR                                                    (0x00000001u)
+#define GPT_GTDNSR_DSGTRGAR_SHIFT                                              (0u)
+#define GPT_GTDNSR_DSGTRGAF                                                    (0x00000002u)
+#define GPT_GTDNSR_DSGTRGAF_SHIFT                                              (1u)
+#define GPT_GTDNSR_DSGTRGBR                                                    (0x00000004u)
+#define GPT_GTDNSR_DSGTRGBR_SHIFT                                              (2u)
+#define GPT_GTDNSR_DSGTRGBF                                                    (0x00000008u)
+#define GPT_GTDNSR_DSGTRGBF_SHIFT                                              (3u)
+#define GPT_GTDNSR_DSGTRGCR                                                    (0x00000010u)
+#define GPT_GTDNSR_DSGTRGCR_SHIFT                                              (4u)
+#define GPT_GTDNSR_DSGTRGCF                                                    (0x00000020u)
+#define GPT_GTDNSR_DSGTRGCF_SHIFT                                              (5u)
+#define GPT_GTDNSR_DSGTRGDR                                                    (0x00000040u)
+#define GPT_GTDNSR_DSGTRGDR_SHIFT                                              (6u)
+#define GPT_GTDNSR_DSGTRGDF                                                    (0x00000080u)
+#define GPT_GTDNSR_DSGTRGDF_SHIFT                                              (7u)
+#define GPT_GTDNSR_DSCARBL                                                     (0x00000100u)
+#define GPT_GTDNSR_DSCARBL_SHIFT                                               (8u)
+#define GPT_GTDNSR_DSCARBH                                                     (0x00000200u)
+#define GPT_GTDNSR_DSCARBH_SHIFT                                               (9u)
+#define GPT_GTDNSR_DSCAFBL                                                     (0x00000400u)
+#define GPT_GTDNSR_DSCAFBL_SHIFT                                               (10u)
+#define GPT_GTDNSR_DSCAFBH                                                     (0x00000800u)
+#define GPT_GTDNSR_DSCAFBH_SHIFT                                               (11u)
+#define GPT_GTDNSR_DSCBRAL                                                     (0x00001000u)
+#define GPT_GTDNSR_DSCBRAL_SHIFT                                               (12u)
+#define GPT_GTDNSR_DSCBRAH                                                     (0x00002000u)
+#define GPT_GTDNSR_DSCBRAH_SHIFT                                               (13u)
+#define GPT_GTDNSR_DSCBFAL                                                     (0x00004000u)
+#define GPT_GTDNSR_DSCBFAL_SHIFT                                               (14u)
+#define GPT_GTDNSR_DSCBFAH                                                     (0x00008000u)
+#define GPT_GTDNSR_DSCBFAH_SHIFT                                               (15u)
+#define GPT_GTDNSR_DSEVTA                                                      (0x00010000u)
+#define GPT_GTDNSR_DSEVTA_SHIFT                                                (16u)
+#define GPT_GTDNSR_DSEVTB                                                      (0x00020000u)
+#define GPT_GTDNSR_DSEVTB_SHIFT                                                (17u)
+#define GPT_GTDNSR_DSEVTC                                                      (0x00040000u)
+#define GPT_GTDNSR_DSEVTC_SHIFT                                                (18u)
+#define GPT_GTDNSR_DSEVTD                                                      (0x00080000u)
+#define GPT_GTDNSR_DSEVTD_SHIFT                                                (19u)
+#define GPT_GTDNSR_DSEVTE                                                      (0x00100000u)
+#define GPT_GTDNSR_DSEVTE_SHIFT                                                (20u)
+#define GPT_GTDNSR_DSEVTF                                                      (0x00200000u)
+#define GPT_GTDNSR_DSEVTF_SHIFT                                                (21u)
+#define GPT_GTDNSR_DSEVTG                                                      (0x00400000u)
+#define GPT_GTDNSR_DSEVTG_SHIFT                                                (22u)
+#define GPT_GTDNSR_DSEVTH                                                      (0x00800000u)
+#define GPT_GTDNSR_DSEVTH_SHIFT                                                (23u)
+#define GPT_GTICASR_ASGTRGAR                                                   (0x00000001u)
+#define GPT_GTICASR_ASGTRGAR_SHIFT                                             (0u)
+#define GPT_GTICASR_ASGTRGAF                                                   (0x00000002u)
+#define GPT_GTICASR_ASGTRGAF_SHIFT                                             (1u)
+#define GPT_GTICASR_ASGTRGBR                                                   (0x00000004u)
+#define GPT_GTICASR_ASGTRGBR_SHIFT                                             (2u)
+#define GPT_GTICASR_ASGTRGBF                                                   (0x00000008u)
+#define GPT_GTICASR_ASGTRGBF_SHIFT                                             (3u)
+#define GPT_GTICASR_ASGTRGCR                                                   (0x00000010u)
+#define GPT_GTICASR_ASGTRGCR_SHIFT                                             (4u)
+#define GPT_GTICASR_ASGTRGCF                                                   (0x00000020u)
+#define GPT_GTICASR_ASGTRGCF_SHIFT                                             (5u)
+#define GPT_GTICASR_ASGTRGDR                                                   (0x00000040u)
+#define GPT_GTICASR_ASGTRGDR_SHIFT                                             (6u)
+#define GPT_GTICASR_ASGTRGDF                                                   (0x00000080u)
+#define GPT_GTICASR_ASGTRGDF_SHIFT                                             (7u)
+#define GPT_GTICASR_ASCARBL                                                    (0x00000100u)
+#define GPT_GTICASR_ASCARBL_SHIFT                                              (8u)
+#define GPT_GTICASR_ASCARBH                                                    (0x00000200u)
+#define GPT_GTICASR_ASCARBH_SHIFT                                              (9u)
+#define GPT_GTICASR_ASCAFBL                                                    (0x00000400u)
+#define GPT_GTICASR_ASCAFBL_SHIFT                                              (10u)
+#define GPT_GTICASR_ASCAFBH                                                    (0x00000800u)
+#define GPT_GTICASR_ASCAFBH_SHIFT                                              (11u)
+#define GPT_GTICASR_ASCBRAL                                                    (0x00001000u)
+#define GPT_GTICASR_ASCBRAL_SHIFT                                              (12u)
+#define GPT_GTICASR_ASCBRAH                                                    (0x00002000u)
+#define GPT_GTICASR_ASCBRAH_SHIFT                                              (13u)
+#define GPT_GTICASR_ASCBFAL                                                    (0x00004000u)
+#define GPT_GTICASR_ASCBFAL_SHIFT                                              (14u)
+#define GPT_GTICASR_ASCBFAH                                                    (0x00008000u)
+#define GPT_GTICASR_ASCBFAH_SHIFT                                              (15u)
+#define GPT_GTICASR_ASEVTA                                                     (0x00010000u)
+#define GPT_GTICASR_ASEVTA_SHIFT                                               (16u)
+#define GPT_GTICASR_ASEVTB                                                     (0x00020000u)
+#define GPT_GTICASR_ASEVTB_SHIFT                                               (17u)
+#define GPT_GTICASR_ASEVTC                                                     (0x00040000u)
+#define GPT_GTICASR_ASEVTC_SHIFT                                               (18u)
+#define GPT_GTICASR_ASEVTD                                                     (0x00080000u)
+#define GPT_GTICASR_ASEVTD_SHIFT                                               (19u)
+#define GPT_GTICASR_ASEVTE                                                     (0x00100000u)
+#define GPT_GTICASR_ASEVTE_SHIFT                                               (20u)
+#define GPT_GTICASR_ASEVTF                                                     (0x00200000u)
+#define GPT_GTICASR_ASEVTF_SHIFT                                               (21u)
+#define GPT_GTICASR_ASEVTG                                                     (0x00400000u)
+#define GPT_GTICASR_ASEVTG_SHIFT                                               (22u)
+#define GPT_GTICASR_ASEVTH                                                     (0x00800000u)
+#define GPT_GTICASR_ASEVTH_SHIFT                                               (23u)
+#define GPT_GTICBSR_BSGTRGAR                                                   (0x00000001u)
+#define GPT_GTICBSR_BSGTRGAR_SHIFT                                             (0u)
+#define GPT_GTICBSR_BSGTRGAF                                                   (0x00000002u)
+#define GPT_GTICBSR_BSGTRGAF_SHIFT                                             (1u)
+#define GPT_GTICBSR_BSGTRGBR                                                   (0x00000004u)
+#define GPT_GTICBSR_BSGTRGBR_SHIFT                                             (2u)
+#define GPT_GTICBSR_BSGTRGBF                                                   (0x00000008u)
+#define GPT_GTICBSR_BSGTRGBF_SHIFT                                             (3u)
+#define GPT_GTICBSR_BSGTRGCR                                                   (0x00000010u)
+#define GPT_GTICBSR_BSGTRGCR_SHIFT                                             (4u)
+#define GPT_GTICBSR_BSGTRGCF                                                   (0x00000020u)
+#define GPT_GTICBSR_BSGTRGCF_SHIFT                                             (5u)
+#define GPT_GTICBSR_BSGTRGDR                                                   (0x00000040u)
+#define GPT_GTICBSR_BSGTRGDR_SHIFT                                             (6u)
+#define GPT_GTICBSR_BSGTRGDF                                                   (0x00000080u)
+#define GPT_GTICBSR_BSGTRGDF_SHIFT                                             (7u)
+#define GPT_GTICBSR_BSCARBL                                                    (0x00000100u)
+#define GPT_GTICBSR_BSCARBL_SHIFT                                              (8u)
+#define GPT_GTICBSR_BSCARBH                                                    (0x00000200u)
+#define GPT_GTICBSR_BSCARBH_SHIFT                                              (9u)
+#define GPT_GTICBSR_BSCAFBL                                                    (0x00000400u)
+#define GPT_GTICBSR_BSCAFBL_SHIFT                                              (10u)
+#define GPT_GTICBSR_BSCAFBH                                                    (0x00000800u)
+#define GPT_GTICBSR_BSCAFBH_SHIFT                                              (11u)
+#define GPT_GTICBSR_BSCBRAL                                                    (0x00001000u)
+#define GPT_GTICBSR_BSCBRAL_SHIFT                                              (12u)
+#define GPT_GTICBSR_BSCBRAH                                                    (0x00002000u)
+#define GPT_GTICBSR_BSCBRAH_SHIFT                                              (13u)
+#define GPT_GTICBSR_BSCBFAL                                                    (0x00004000u)
+#define GPT_GTICBSR_BSCBFAL_SHIFT                                              (14u)
+#define GPT_GTICBSR_BSCBFAH                                                    (0x00008000u)
+#define GPT_GTICBSR_BSCBFAH_SHIFT                                              (15u)
+#define GPT_GTICBSR_BSEVTA                                                     (0x00010000u)
+#define GPT_GTICBSR_BSEVTA_SHIFT                                               (16u)
+#define GPT_GTICBSR_BSEVTB                                                     (0x00020000u)
+#define GPT_GTICBSR_BSEVTB_SHIFT                                               (17u)
+#define GPT_GTICBSR_BSEVTC                                                     (0x00040000u)
+#define GPT_GTICBSR_BSEVTC_SHIFT                                               (18u)
+#define GPT_GTICBSR_BSEVTD                                                     (0x00080000u)
+#define GPT_GTICBSR_BSEVTD_SHIFT                                               (19u)
+#define GPT_GTICBSR_BSEVTE                                                     (0x00100000u)
+#define GPT_GTICBSR_BSEVTE_SHIFT                                               (20u)
+#define GPT_GTICBSR_BSEVTF                                                     (0x00200000u)
+#define GPT_GTICBSR_BSEVTF_SHIFT                                               (21u)
+#define GPT_GTICBSR_BSEVTG                                                     (0x00400000u)
+#define GPT_GTICBSR_BSEVTG_SHIFT                                               (22u)
+#define GPT_GTICBSR_BSEVTH                                                     (0x00800000u)
+#define GPT_GTICBSR_BSEVTH_SHIFT                                               (23u)
+#define GPT_GTCR_CST                                                           (0x00000001u)
+#define GPT_GTCR_CST_SHIFT                                                     (0u)
+#define GPT_GTCR_MD                                                            (0x00070000u)
+#define GPT_GTCR_MD_SHIFT                                                      (16u)
+#define GPT_GTCR_TPCS                                                          (0x07000000u)
+#define GPT_GTCR_TPCS_SHIFT                                                    (24u)
+#define GPT_GTUDDTYC_UD                                                        (0x00000001u)
+#define GPT_GTUDDTYC_UD_SHIFT                                                  (0u)
+#define GPT_GTUDDTYC_UDF                                                       (0x00000002u)
+#define GPT_GTUDDTYC_UDF_SHIFT                                                 (1u)
+#define GPT_GTUDDTYC_OADTY                                                     (0x00030000u)
+#define GPT_GTUDDTYC_OADTY_SHIFT                                               (16u)
+#define GPT_GTUDDTYC_OADTYF                                                    (0x00040000u)
+#define GPT_GTUDDTYC_OADTYF_SHIFT                                              (18u)
+#define GPT_GTUDDTYC_OADTYR                                                    (0x00080000u)
+#define GPT_GTUDDTYC_OADTYR_SHIFT                                              (19u)
+#define GPT_GTUDDTYC_OBDTY                                                     (0x03000000u)
+#define GPT_GTUDDTYC_OBDTY_SHIFT                                               (24u)
+#define GPT_GTUDDTYC_OBDTYF                                                    (0x04000000u)
+#define GPT_GTUDDTYC_OBDTYF_SHIFT                                              (26u)
+#define GPT_GTUDDTYC_OBDTYR                                                    (0x08000000u)
+#define GPT_GTUDDTYC_OBDTYR_SHIFT                                              (27u)
+#define GPT_GTIOR_GTIOA                                                        (0x0000001Fu)
+#define GPT_GTIOR_GTIOA_SHIFT                                                  (0u)
+#define GPT_GTIOR_OADFLT                                                       (0x00000040u)
+#define GPT_GTIOR_OADFLT_SHIFT                                                 (6u)
+#define GPT_GTIOR_OAHLD                                                        (0x00000080u)
+#define GPT_GTIOR_OAHLD_SHIFT                                                  (7u)
+#define GPT_GTIOR_OAE                                                          (0x00000100u)
+#define GPT_GTIOR_OAE_SHIFT                                                    (8u)
+#define GPT_GTIOR_OADF                                                         (0x00000600u)
+#define GPT_GTIOR_OADF_SHIFT                                                   (9u)
+#define GPT_GTIOR_NFAEN                                                        (0x00002000u)
+#define GPT_GTIOR_NFAEN_SHIFT                                                  (13u)
+#define GPT_GTIOR_NFCSA                                                        (0x0000C000u)
+#define GPT_GTIOR_NFCSA_SHIFT                                                  (14u)
+#define GPT_GTIOR_GTIOB                                                        (0x001F0000u)
+#define GPT_GTIOR_GTIOB_SHIFT                                                  (16u)
+#define GPT_GTIOR_OBDFLT                                                       (0x00400000u)
+#define GPT_GTIOR_OBDFLT_SHIFT                                                 (22u)
+#define GPT_GTIOR_OBHLD                                                        (0x00800000u)
+#define GPT_GTIOR_OBHLD_SHIFT                                                  (23u)
+#define GPT_GTIOR_OBE                                                          (0x01000000u)
+#define GPT_GTIOR_OBE_SHIFT                                                    (24u)
+#define GPT_GTIOR_OBDF                                                         (0x06000000u)
+#define GPT_GTIOR_OBDF_SHIFT                                                   (25u)
+#define GPT_GTIOR_NFBEN                                                        (0x20000000u)
+#define GPT_GTIOR_NFBEN_SHIFT                                                  (29u)
+#define GPT_GTIOR_NFCSB                                                        (0xC0000000u)
+#define GPT_GTIOR_NFCSB_SHIFT                                                  (30u)
+#define GPT_GTINTAD_GTINTA                                                     (0x00000001u)
+#define GPT_GTINTAD_GTINTA_SHIFT                                               (0u)
+#define GPT_GTINTAD_GTINTB                                                     (0x00000002u)
+#define GPT_GTINTAD_GTINTB_SHIFT                                               (1u)
+#define GPT_GTINTAD_GTINTC                                                     (0x00000004u)
+#define GPT_GTINTAD_GTINTC_SHIFT                                               (2u)
+#define GPT_GTINTAD_GTINTD                                                     (0x00000008u)
+#define GPT_GTINTAD_GTINTD_SHIFT                                               (3u)
+#define GPT_GTINTAD_GTINTE                                                     (0x00000010u)
+#define GPT_GTINTAD_GTINTE_SHIFT                                               (4u)
+#define GPT_GTINTAD_GTINTF                                                     (0x00000020u)
+#define GPT_GTINTAD_GTINTF_SHIFT                                               (5u)
+#define GPT_GTINTAD_GTINTPR                                                    (0x000000C0u)
+#define GPT_GTINTAD_GTINTPR_SHIFT                                              (6u)
+#define GPT_GTINTAD_ADTRAUEN                                                   (0x00010000u)
+#define GPT_GTINTAD_ADTRAUEN_SHIFT                                             (16u)
+#define GPT_GTINTAD_ADTRADEN                                                   (0x00020000u)
+#define GPT_GTINTAD_ADTRADEN_SHIFT                                             (17u)
+#define GPT_GTINTAD_ADTRBUEN                                                   (0x00040000u)
+#define GPT_GTINTAD_ADTRBUEN_SHIFT                                             (18u)
+#define GPT_GTINTAD_ADTRBDEN                                                   (0x00080000u)
+#define GPT_GTINTAD_ADTRBDEN_SHIFT                                             (19u)
+#define GPT_GTINTAD_GRP                                                        (0x03000000u)
+#define GPT_GTINTAD_GRP_SHIFT                                                  (24u)
+#define GPT_GTINTAD_GRPDTE                                                     (0x10000000u)
+#define GPT_GTINTAD_GRPDTE_SHIFT                                               (28u)
+#define GPT_GTINTAD_GRPABH                                                     (0x20000000u)
+#define GPT_GTINTAD_GRPABH_SHIFT                                               (29u)
+#define GPT_GTINTAD_GRPABL                                                     (0x40000000u)
+#define GPT_GTINTAD_GRPABL_SHIFT                                               (30u)
+#define GPT_GTST_TCFA                                                          (0x00000001u)
+#define GPT_GTST_TCFA_SHIFT                                                    (0u)
+#define GPT_GTST_TCFB                                                          (0x00000002u)
+#define GPT_GTST_TCFB_SHIFT                                                    (1u)
+#define GPT_GTST_TCFC                                                          (0x00000004u)
+#define GPT_GTST_TCFC_SHIFT                                                    (2u)
+#define GPT_GTST_TCFD                                                          (0x00000008u)
+#define GPT_GTST_TCFD_SHIFT                                                    (3u)
+#define GPT_GTST_TCFE                                                          (0x00000010u)
+#define GPT_GTST_TCFE_SHIFT                                                    (4u)
+#define GPT_GTST_TCFF                                                          (0x00000020u)
+#define GPT_GTST_TCFF_SHIFT                                                    (5u)
+#define GPT_GTST_TCFPO                                                         (0x00000040u)
+#define GPT_GTST_TCFPO_SHIFT                                                   (6u)
+#define GPT_GTST_TCFPU                                                         (0x00000080u)
+#define GPT_GTST_TCFPU_SHIFT                                                   (7u)
+#define GPT_GTST_ITCNT                                                         (0x00000700u)
+#define GPT_GTST_ITCNT_SHIFT                                                   (8u)
+#define GPT_GTST_TUCF                                                          (0x00008000u)
+#define GPT_GTST_TUCF_SHIFT                                                    (15u)
+#define GPT_GTST_ADTRAUF                                                       (0x00010000u)
+#define GPT_GTST_ADTRAUF_SHIFT                                                 (16u)
+#define GPT_GTST_ADTRADF                                                       (0x00020000u)
+#define GPT_GTST_ADTRADF_SHIFT                                                 (17u)
+#define GPT_GTST_ADTRBUF                                                       (0x00040000u)
+#define GPT_GTST_ADTRBUF_SHIFT                                                 (18u)
+#define GPT_GTST_ADTRBDF                                                       (0x00080000u)
+#define GPT_GTST_ADTRBDF_SHIFT                                                 (19u)
+#define GPT_GTST_ODF                                                           (0x01000000u)
+#define GPT_GTST_ODF_SHIFT                                                     (24u)
+#define GPT_GTST_DTEF                                                          (0x10000000u)
+#define GPT_GTST_DTEF_SHIFT                                                    (28u)
+#define GPT_GTST_OABHF                                                         (0x20000000u)
+#define GPT_GTST_OABHF_SHIFT                                                   (29u)
+#define GPT_GTST_OABLF                                                         (0x40000000u)
+#define GPT_GTST_OABLF_SHIFT                                                   (30u)
+#define GPT_GTBER_BD                                                           (0x0000000Fu)
+#define GPT_GTBER_BD_SHIFT                                                     (0u)
+#define GPT_GTBER_CCRA                                                         (0x00030000u)
+#define GPT_GTBER_CCRA_SHIFT                                                   (16u)
+#define GPT_GTBER_CCRB                                                         (0x000C0000u)
+#define GPT_GTBER_CCRB_SHIFT                                                   (18u)
+#define GPT_GTBER_PR                                                           (0x00300000u)
+#define GPT_GTBER_PR_SHIFT                                                     (20u)
+#define GPT_GTBER_CCRSWT                                                       (0x00400000u)
+#define GPT_GTBER_CCRSWT_SHIFT                                                 (22u)
+#define GPT_GTBER_ADTTA                                                        (0x03000000u)
+#define GPT_GTBER_ADTTA_SHIFT                                                  (24u)
+#define GPT_GTBER_ADTDA                                                        (0x04000000u)
+#define GPT_GTBER_ADTDA_SHIFT                                                  (26u)
+#define GPT_GTBER_ADTTB                                                        (0x30000000u)
+#define GPT_GTBER_ADTTB_SHIFT                                                  (28u)
+#define GPT_GTBER_ADTDB                                                        (0x40000000u)
+#define GPT_GTBER_ADTDB_SHIFT                                                  (30u)
+#define GPT_GTITC_ITLA                                                         (0x00000001u)
+#define GPT_GTITC_ITLA_SHIFT                                                   (0u)
+#define GPT_GTITC_ITLB                                                         (0x00000002u)
+#define GPT_GTITC_ITLB_SHIFT                                                   (1u)
+#define GPT_GTITC_ITLC                                                         (0x00000004u)
+#define GPT_GTITC_ITLC_SHIFT                                                   (2u)
+#define GPT_GTITC_ITLD                                                         (0x00000008u)
+#define GPT_GTITC_ITLD_SHIFT                                                   (3u)
+#define GPT_GTITC_ITLE                                                         (0x00000010u)
+#define GPT_GTITC_ITLE_SHIFT                                                   (4u)
+#define GPT_GTITC_ITLF                                                         (0x00000020u)
+#define GPT_GTITC_ITLF_SHIFT                                                   (5u)
+#define GPT_GTITC_IVTC                                                         (0x000000C0u)
+#define GPT_GTITC_IVTC_SHIFT                                                   (6u)
+#define GPT_GTITC_IVTT                                                         (0x00000700u)
+#define GPT_GTITC_IVTT_SHIFT                                                   (8u)
+#define GPT_GTITC_ADTAL                                                        (0x00001000u)
+#define GPT_GTITC_ADTAL_SHIFT                                                  (12u)
+#define GPT_GTITC_ADTBL                                                        (0x00004000u)
+#define GPT_GTITC_ADTBL_SHIFT                                                  (14u)
+#define GPT_GTCNT_GTCNT                                                        (0xFFFFFFFFu)
+#define GPT_GTCNT_GTCNT_SHIFT                                                  (0u)
+#define GPT_GTCCRA_GTCCRA                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRA_GTCCRA_SHIFT                                                (0u)
+#define GPT_GTCCRB_GTCCRB                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRB_GTCCRB_SHIFT                                                (0u)
+#define GPT_GTCCRC_GTCCRC                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRC_GTCCRC_SHIFT                                                (0u)
+#define GPT_GTCCRE_GTCCRE                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRE_GTCCRE_SHIFT                                                (0u)
+#define GPT_GTCCRD_GTCCRD                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRD_GTCCRD_SHIFT                                                (0u)
+#define GPT_GTCCRF_GTCCRF                                                      (0xFFFFFFFFu)
+#define GPT_GTCCRF_GTCCRF_SHIFT                                                (0u)
+#define GPT_GTPR_GTPR                                                          (0xFFFFFFFFu)
+#define GPT_GTPR_GTPR_SHIFT                                                    (0u)
+#define GPT_GTPBR_GTPBR                                                        (0xFFFFFFFFu)
+#define GPT_GTPBR_GTPBR_SHIFT                                                  (0u)
+#define GPT_GTPDBR_GTPDBR                                                      (0xFFFFFFFFu)
+#define GPT_GTPDBR_GTPDBR_SHIFT                                                (0u)
+#define GPT_GTADTRA_GTADTRA                                                    (0xFFFFFFFFu)
+#define GPT_GTADTRA_GTADTRA_SHIFT                                              (0u)
+#define GPT_GTADTBRA_GTADTBRA                                                  (0xFFFFFFFFu)
+#define GPT_GTADTBRA_GTADTBRA_SHIFT                                            (0u)
+#define GPT_GTADTDBRA_GTADTDBRA                                                (0xFFFFFFFFu)
+#define GPT_GTADTDBRA_GTADTDBRA_SHIFT                                          (0u)
+#define GPT_GTADTRB_GTADTRB                                                    (0xFFFFFFFFu)
+#define GPT_GTADTRB_GTADTRB_SHIFT                                              (0u)
+#define GPT_GTADTBRB_GTADTBRB                                                  (0xFFFFFFFFu)
+#define GPT_GTADTBRB_GTADTBRB_SHIFT                                            (0u)
+#define GPT_GTADTDBRB_GTADTDBRB                                                (0xFFFFFFFFu)
+#define GPT_GTADTDBRB_GTADTDBRB_SHIFT                                          (0u)
+#define GPT_GTDTCR_TDE                                                         (0x00000001u)
+#define GPT_GTDTCR_TDE_SHIFT                                                   (0u)
+#define GPT_GTDTCR_TDBUE                                                       (0x00000010u)
+#define GPT_GTDTCR_TDBUE_SHIFT                                                 (4u)
+#define GPT_GTDTCR_TDBDE                                                       (0x00000020u)
+#define GPT_GTDTCR_TDBDE_SHIFT                                                 (5u)
+#define GPT_GTDTCR_TDFER                                                       (0x00000100u)
+#define GPT_GTDTCR_TDFER_SHIFT                                                 (8u)
+#define GPT_GTDVU_GTDVU                                                        (0xFFFFFFFFu)
+#define GPT_GTDVU_GTDVU_SHIFT                                                  (0u)
+#define GPT_GTDVD_GTDVD                                                        (0xFFFFFFFFu)
+#define GPT_GTDVD_GTDVD_SHIFT                                                  (0u)
+#define GPT_GTDBU_GTDBU                                                        (0xFFFFFFFFu)
+#define GPT_GTDBU_GTDBU_SHIFT                                                  (0u)
+#define GPT_GTDBD_GTDBD                                                        (0xFFFFFFFFu)
+#define GPT_GTDBD_GTDBD_SHIFT                                                  (0u)
+#define GPT_GTSOS_SOS                                                          (0x00000003u)
+#define GPT_GTSOS_SOS_SHIFT                                                    (0u)
+#define GPT_GTSOTR_SOTR                                                        (0x00000001u)
+#define GPT_GTSOTR_SOTR_SHIFT                                                  (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/hyper_iobitmask.h

@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef HYPER_IOBITMASK_H
+#define HYPER_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define HYPER_CSR_RACT                                                         (0x00000001u)
+#define HYPER_CSR_RACT_SHIFT                                                   (0u)
+#define HYPER_CSR_RDECERR                                                      (0x00000100u)
+#define HYPER_CSR_RDECERR_SHIFT                                                (8u)
+#define HYPER_CSR_RTRSERR                                                      (0x00000200u)
+#define HYPER_CSR_RTRSERR_SHIFT                                                (9u)
+#define HYPER_CSR_RRSTOERR                                                     (0x00000400u)
+#define HYPER_CSR_RRSTOERR_SHIFT                                               (10u)
+#define HYPER_CSR_RDSSTALL                                                     (0x00000800u)
+#define HYPER_CSR_RDSSTALL_SHIFT                                               (11u)
+#define HYPER_CSR_WACT                                                         (0x00010000u)
+#define HYPER_CSR_WACT_SHIFT                                                   (16u)
+#define HYPER_CSR_WDECERR                                                      (0x01000000u)
+#define HYPER_CSR_WDECERR_SHIFT                                                (24u)
+#define HYPER_CSR_WTRSERR                                                      (0x02000000u)
+#define HYPER_CSR_WTRSERR_SHIFT                                                (25u)
+#define HYPER_CSR_WRSTOERR                                                     (0x04000000u)
+#define HYPER_CSR_WRSTOERR_SHIFT                                               (26u)
+#define HYPER_IEN_RPCINTE                                                      (0x00000001u)
+#define HYPER_IEN_RPCINTE_SHIFT                                                (0u)
+#define HYPER_IEN_INTP                                                         (0x80000000u)
+#define HYPER_IEN_INTP_SHIFT                                                   (31u)
+#define HYPER_ISR_RPCINTS                                                      (0x00000001u)
+#define HYPER_ISR_RPCINTS_SHIFT                                                (0u)
+#define HYPER_MCR0_MAXLEN                                                      (0x07FC0000u)
+#define HYPER_MCR0_MAXLEN_SHIFT                                                (18u)
+#define HYPER_MCR0_MAXEN                                                       (0x80000000u)
+#define HYPER_MCR0_MAXEN_SHIFT                                                 (31u)
+#define HYPER_MCR1_DEVTYPE                                                     (0x00000010u)
+#define HYPER_MCR1_DEVTYPE_SHIFT                                               (4u)
+#define HYPER_MCR1_CRT                                                         (0x00000020u)
+#define HYPER_MCR1_CRT_SHIFT                                                   (5u)
+#define HYPER_MCR1_MAXLEN                                                      (0x07FC0000u)
+#define HYPER_MCR1_MAXLEN_SHIFT                                                (18u)
+#define HYPER_MCR1_MAXEN                                                       (0x80000000u)
+#define HYPER_MCR1_MAXEN_SHIFT                                                 (31u)
+#define HYPER_MTR0_WCSH                                                        (0x00000F00u)
+#define HYPER_MTR0_WCSH_SHIFT                                                  (8u)
+#define HYPER_MTR0_RCSH                                                        (0x0000F000u)
+#define HYPER_MTR0_RCSH_SHIFT                                                  (12u)
+#define HYPER_MTR0_WCSS                                                        (0x000F0000u)
+#define HYPER_MTR0_WCSS_SHIFT                                                  (16u)
+#define HYPER_MTR0_RCSS                                                        (0x00F00000u)
+#define HYPER_MTR0_RCSS_SHIFT                                                  (20u)
+#define HYPER_MTR0_WCSHI                                                       (0x0F000000u)
+#define HYPER_MTR0_WCSHI_SHIFT                                                 (24u)
+#define HYPER_MTR0_RCSHI                                                       (0xF0000000u)
+#define HYPER_MTR0_RCSHI_SHIFT                                                 (28u)
+#define HYPER_MTR1_LTCY                                                        (0x0000000Fu)
+#define HYPER_MTR1_LTCY_SHIFT                                                  (0u)
+#define HYPER_MTR1_WCSH                                                        (0x00000F00u)
+#define HYPER_MTR1_WCSH_SHIFT                                                  (8u)
+#define HYPER_MTR1_RCSH                                                        (0x0000F000u)
+#define HYPER_MTR1_RCSH_SHIFT                                                  (12u)
+#define HYPER_MTR1_WCSS                                                        (0x000F0000u)
+#define HYPER_MTR1_WCSS_SHIFT                                                  (16u)
+#define HYPER_MTR1_RCSS                                                        (0x00F00000u)
+#define HYPER_MTR1_RCSS_SHIFT                                                  (20u)
+#define HYPER_MTR1_WCSHI                                                       (0x0F000000u)
+#define HYPER_MTR1_WCSHI_SHIFT                                                 (24u)
+#define HYPER_MTR1_RCSHI                                                       (0xF0000000u)
+#define HYPER_MTR1_RCSHI_SHIFT                                                 (28u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/imr2_iobitmask.h

@@ -0,0 +1,186 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef IMR2_IOBITMASK_H
+#define IMR2_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define IMR2_CR_RS                                                             (0x00000001u)
+#define IMR2_CR_RS_SHIFT                                                       (0u)
+#define IMR2_CR_ARS                                                            (0x00000002u)
+#define IMR2_CR_ARS_SHIFT                                                      (1u)
+#define IMR2_CR_SFE                                                            (0x00000004u)
+#define IMR2_CR_SFE_SHIFT                                                      (2u)
+#define IMR2_CR_SWRST                                                          (0x00008000u)
+#define IMR2_CR_SWRST_SHIFT                                                    (15u)
+#define IMR2_SR_TRA                                                            (0x00000001u)
+#define IMR2_SR_TRA_SHIFT                                                      (0u)
+#define IMR2_SR_IER                                                            (0x00000002u)
+#define IMR2_SR_IER_SHIFT                                                      (1u)
+#define IMR2_SR_INT                                                            (0x00000004u)
+#define IMR2_SR_INT_SHIFT                                                      (2u)
+#define IMR2_SR_DSA                                                            (0x00000040u)
+#define IMR2_SR_DSA_SHIFT                                                      (6u)
+#define IMR2_SR_SFS                                                            (0x00000080u)
+#define IMR2_SR_SFS_SHIFT                                                      (7u)
+#define IMR2_SRCR_TRACLR                                                       (0x00000001u)
+#define IMR2_SRCR_TRACLR_SHIFT                                                 (0u)
+#define IMR2_SRCR_IERCLR                                                       (0x00000002u)
+#define IMR2_SRCR_IERCLR_SHIFT                                                 (1u)
+#define IMR2_SRCR_INTCLR                                                       (0x00000004u)
+#define IMR2_SRCR_INTCLR_SHIFT                                                 (2u)
+#define IMR2_ICR_TRAENB                                                        (0x00000001u)
+#define IMR2_ICR_TRAENB_SHIFT                                                  (0u)
+#define IMR2_ICR_IERENB                                                        (0x00000002u)
+#define IMR2_ICR_IERENB_SHIFT                                                  (1u)
+#define IMR2_ICR_INTENB                                                        (0x00000004u)
+#define IMR2_ICR_INTENB_SHIFT                                                  (2u)
+#define IMR2_IMR_TEAM                                                          (0x00000001u)
+#define IMR2_IMR_TEAM_SHIFT                                                    (0u)
+#define IMR2_IMR_IEM                                                           (0x00000002u)
+#define IMR2_IMR_IEM_SHIFT                                                     (1u)
+#define IMR2_IMR_INM                                                           (0x00000004u)
+#define IMR2_IMR_INM_SHIFT                                                     (2u)
+#define IMR2_DLPR_DLP                                                          (0xFFFFFFFFu)
+#define IMR2_DLPR_DLP_SHIFT                                                    (0u)
+#define IMR2_DLSAR_DLSA                                                        (0xFFFFFFC0u)
+#define IMR2_DLSAR_DLSA_SHIFT                                                  (3u)
+#define IMR2_DSAR_DSA                                                          (0xFFFFFC00u)
+#define IMR2_DSAR_DSA_SHIFT                                                    (5u)
+#define IMR2_DSTR_DST                                                          (0x00003FFFu)
+#define IMR2_DSTR_DST_SHIFT                                                    (0u)
+#define IMR2_DSAR2_DSA2                                                        (0xFFFFFC00u)
+#define IMR2_DSAR2_DSA2_SHIFT                                                  (5u)
+#define IMR2_DLSAR2_DLSA2                                                      (0xFFFFFFC0u)
+#define IMR2_DLSAR2_DLSA2_SHIFT                                                (3u)
+#define IMR2_TRIMR_TME                                                         (0x00000001u)
+#define IMR2_TRIMR_TME_SHIFT                                                   (0u)
+#define IMR2_TRIMR_BFE                                                         (0x00000002u)
+#define IMR2_TRIMR_BFE_SHIFT                                                   (1u)
+#define IMR2_TRIMR_AUTODG                                                      (0x00000004u)
+#define IMR2_TRIMR_AUTODG_SHIFT                                                (2u)
+#define IMR2_TRIMR_AUTOSG                                                      (0x00000008u)
+#define IMR2_TRIMR_AUTOSG_SHIFT                                                (3u)
+#define IMR2_TRIMR_DXDYM                                                       (0x00000010u)
+#define IMR2_TRIMR_DXDYM_SHIFT                                                 (4u)
+#define IMR2_TRIMR_DUDVM                                                       (0x00000020u)
+#define IMR2_TRIMR_DUDVM_SHIFT                                                 (5u)
+#define IMR2_TRIMR_TCM                                                         (0x00000040u)
+#define IMR2_TRIMR_TCM_SHIFT                                                   (6u)
+#define IMR2_TRIMSR_TMES                                                       (0x00000001u)
+#define IMR2_TRIMSR_TMES_SHIFT                                                 (0u)
+#define IMR2_TRIMSR_BFES                                                       (0x00000002u)
+#define IMR2_TRIMSR_BFES_SHIFT                                                 (1u)
+#define IMR2_TRIMSR_AUTODGS                                                    (0x00000004u)
+#define IMR2_TRIMSR_AUTODGS_SHIFT                                              (2u)
+#define IMR2_TRIMSR_AUTOSGS                                                    (0x00000008u)
+#define IMR2_TRIMSR_AUTOSGS_SHIFT                                              (3u)
+#define IMR2_TRIMSR_DXDYMS                                                     (0x00000010u)
+#define IMR2_TRIMSR_DXDYMS_SHIFT                                               (4u)
+#define IMR2_TRIMSR_DUDVMS                                                     (0x00000020u)
+#define IMR2_TRIMSR_DUDVMS_SHIFT                                               (5u)
+#define IMR2_TRIMSR_TCMS                                                       (0x00000040u)
+#define IMR2_TRIMSR_TCMS_SHIFT                                                 (6u)
+#define IMR2_TRIMCR_TMEC                                                       (0x00000001u)
+#define IMR2_TRIMCR_TMEC_SHIFT                                                 (0u)
+#define IMR2_TRIMCR_BFEC                                                       (0x00000002u)
+#define IMR2_TRIMCR_BFEC_SHIFT                                                 (1u)
+#define IMR2_TRIMCR_AUTODGC                                                    (0x00000004u)
+#define IMR2_TRIMCR_AUTODGC_SHIFT                                              (2u)
+#define IMR2_TRIMCR_AUTOSGC                                                    (0x00000008u)
+#define IMR2_TRIMCR_AUTOSGC_SHIFT                                              (3u)
+#define IMR2_TRIMCR_DXDYMC                                                     (0x00000010u)
+#define IMR2_TRIMCR_DXDYMC_SHIFT                                               (4u)
+#define IMR2_TRIMCR_DUDVMC                                                     (0x00000020u)
+#define IMR2_TRIMCR_DUDVMC_SHIFT                                               (5u)
+#define IMR2_TRIMCR_TCMC                                                       (0x00000040u)
+#define IMR2_TRIMCR_TCMC_SHIFT                                                 (6u)
+#define IMR2_TRICR_TCY                                                         (0x000000FFu)
+#define IMR2_TRICR_TCY_SHIFT                                                   (0u)
+#define IMR2_TRICR_TCU                                                         (0x0000FF00u)
+#define IMR2_TRICR_TCU_SHIFT                                                   (8u)
+#define IMR2_TRICR_TCV                                                         (0x00FF0000u)
+#define IMR2_TRICR_TCV_SHIFT                                                   (16u)
+#define IMR2_TRICR_YCFORM                                                      (0x80000000u)
+#define IMR2_TRICR_YCFORM_SHIFT                                                (31u)
+#define IMR2_UVDPOR_UVDPO                                                      (0x00000007u)
+#define IMR2_UVDPOR_UVDPO_SHIFT                                                (0u)
+#define IMR2_UVDPOR_DDP                                                        (0x00000100u)
+#define IMR2_UVDPOR_DDP_SHIFT                                                  (8u)
+#define IMR2_SUSR_SVW                                                          (0x000007FFu)
+#define IMR2_SUSR_SVW_SHIFT                                                    (0u)
+#define IMR2_SUSR_SUW                                                          (0x07FF0000u)
+#define IMR2_SUSR_SUW_SHIFT                                                    (16u)
+#define IMR2_SVSR_SVS                                                          (0x000007FFu)
+#define IMR2_SVSR_SVS_SHIFT                                                    (0u)
+#define IMR2_XMINR_XMIN                                                        (0x00001FFFu)
+#define IMR2_XMINR_XMIN_SHIFT                                                  (0u)
+#define IMR2_YMINR_YMIN                                                        (0x00001FFFu)
+#define IMR2_YMINR_YMIN_SHIFT                                                  (0u)
+#define IMR2_XMAXR_XMAX                                                        (0x00001FFFu)
+#define IMR2_XMAXR_XMAX_SHIFT                                                  (0u)
+#define IMR2_YMAXR_YMAX                                                        (0x00001FFFu)
+#define IMR2_YMAXR_YMAX_SHIFT                                                  (0u)
+#define IMR2_AMXSR_AMXS                                                        (0x00001FFFu)
+#define IMR2_AMXSR_AMXS_SHIFT                                                  (0u)
+#define IMR2_AMYSR_AMYS                                                        (0x00001FFFu)
+#define IMR2_AMYSR_AMYS_SHIFT                                                  (0u)
+#define IMR2_AMXOR_AMXO                                                        (0x00001FFFu)
+#define IMR2_AMXOR_AMXO_SHIFT                                                  (0u)
+#define IMR2_AMYOR_AMYO                                                        (0x00001FFFu)
+#define IMR2_AMYOR_AMYO_SHIFT                                                  (0u)
+#define IMR2_MACR1_EMAM                                                        (0x00001000u)
+#define IMR2_MACR1_EMAM_SHIFT                                                  (12u)
+#define IMR2_LSPR_LSPR                                                         (0x000003FFu)
+#define IMR2_LSPR_LSPR_SHIFT                                                   (0u)
+#define IMR2_LEPR_LEPR                                                         (0x000003FFu)
+#define IMR2_LEPR_LEPR_SHIFT                                                   (0u)
+#define IMR2_LMSR_LMSR                                                         (0x00000007u)
+#define IMR2_LMSR_LMSR_SHIFT                                                   (0u)
+#define IMR2_LMSPPCR_SPPC                                                      (0x000007FFu)
+#define IMR2_LMSPPCR_SPPC_SHIFT                                                (0u)
+#define IMR2_LMEPPCR_EPPC                                                      (0x000007FFu)
+#define IMR2_LMEPPCR_EPPC_SHIFT                                                (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/irda_iobitmask.h

@@ -0,0 +1,58 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef IRDA_IOBITMASK_H
+#define IRDA_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define IRDA_IRCR_IRRXINV                                                      (0x04u)
+#define IRDA_IRCR_IRRXINV_SHIFT                                                (2u)
+#define IRDA_IRCR_IRTXINV                                                      (0x08u)
+#define IRDA_IRCR_IRTXINV_SHIFT                                                (3u)
+#define IRDA_IRCR_IRCKS                                                        (0x70u)
+#define IRDA_IRCR_IRCKS_SHIFT                                                  (4u)
+#define IRDA_IRCR_IRE                                                          (0x80u)
+#define IRDA_IRCR_IRE_SHIFT                                                    (7u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/jcu_iobitmask.h

@@ -0,0 +1,204 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef JCU_IOBITMASK_H
+#define JCU_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define JCU_JCMOD_REDU                                                         (0x07u)
+#define JCU_JCMOD_REDU_SHIFT                                                   (0u)
+#define JCU_JCMOD_DSP                                                          (0x08u)
+#define JCU_JCMOD_DSP_SHIFT                                                    (3u)
+#define JCU_JCCMD_JSRT                                                         (0x01u)
+#define JCU_JCCMD_JSRT_SHIFT                                                   (0u)
+#define JCU_JCCMD_JRST                                                         (0x02u)
+#define JCU_JCCMD_JRST_SHIFT                                                   (1u)
+#define JCU_JCCMD_JEND                                                         (0x04u)
+#define JCU_JCCMD_JEND_SHIFT                                                   (2u)
+#define JCU_JCCMD_BRST                                                         (0x80u)
+#define JCU_JCCMD_BRST_SHIFT                                                   (7u)
+#define JCU_JCQTN_QT1                                                          (0x03u)
+#define JCU_JCQTN_QT1_SHIFT                                                    (0u)
+#define JCU_JCQTN_QT2                                                          (0x0Cu)
+#define JCU_JCQTN_QT2_SHIFT                                                    (2u)
+#define JCU_JCQTN_QT3                                                          (0x30u)
+#define JCU_JCQTN_QT3_SHIFT                                                    (4u)
+#define JCU_JCHTN_HTD1                                                         (0x01u)
+#define JCU_JCHTN_HTD1_SHIFT                                                   (0u)
+#define JCU_JCHTN_HTA1                                                         (0x02u)
+#define JCU_JCHTN_HTA1_SHIFT                                                   (1u)
+#define JCU_JCHTN_HTD2                                                         (0x04u)
+#define JCU_JCHTN_HTD2_SHIFT                                                   (2u)
+#define JCU_JCHTN_HTA2                                                         (0x08u)
+#define JCU_JCHTN_HTA2_SHIFT                                                   (3u)
+#define JCU_JCHTN_HTD3                                                         (0x10u)
+#define JCU_JCHTN_HTD3_SHIFT                                                   (4u)
+#define JCU_JCHTN_HTA3                                                         (0x20u)
+#define JCU_JCHTN_HTA3_SHIFT                                                   (5u)
+#define JCU_JCDRIU_DRIU                                                        (0xFFu)
+#define JCU_JCDRIU_DRIU_SHIFT                                                  (0u)
+#define JCU_JCDRID_DRID                                                        (0xFFu)
+#define JCU_JCDRID_DRID_SHIFT                                                  (0u)
+#define JCU_JCVSZU_VSZU                                                        (0xFFu)
+#define JCU_JCVSZU_VSZU_SHIFT                                                  (0u)
+#define JCU_JCVSZD_VSZD                                                        (0xFFu)
+#define JCU_JCVSZD_VSZD_SHIFT                                                  (0u)
+#define JCU_JCHSZU_HSZU                                                        (0xFFu)
+#define JCU_JCHSZU_HSZU_SHIFT                                                  (0u)
+#define JCU_JCHSZD_HSZD                                                        (0xFFu)
+#define JCU_JCHSZD_HSZD_SHIFT                                                  (0u)
+#define JCU_JCDTCU_DCU                                                         (0xFFu)
+#define JCU_JCDTCU_DCU_SHIFT                                                   (0u)
+#define JCU_JCDTCM_DCM                                                         (0xFFu)
+#define JCU_JCDTCM_DCM_SHIFT                                                   (0u)
+#define JCU_JCDTCD_DCD                                                         (0xFFu)
+#define JCU_JCDTCD_DCD_SHIFT                                                   (0u)
+#define JCU_JINTE0_INT3                                                        (0x08u)
+#define JCU_JINTE0_INT3_SHIFT                                                  (3u)
+#define JCU_JINTE0_INT5                                                        (0x20u)
+#define JCU_JINTE0_INT5_SHIFT                                                  (5u)
+#define JCU_JINTE0_INT6                                                        (0x40u)
+#define JCU_JINTE0_INT6_SHIFT                                                  (6u)
+#define JCU_JINTE0_INT7                                                        (0x80u)
+#define JCU_JINTE0_INT7_SHIFT                                                  (7u)
+#define JCU_JINTS0_INS3                                                        (0x08u)
+#define JCU_JINTS0_INS3_SHIFT                                                  (3u)
+#define JCU_JINTS0_INS5                                                        (0x20u)
+#define JCU_JINTS0_INS5_SHIFT                                                  (5u)
+#define JCU_JINTS0_INS6                                                        (0x40u)
+#define JCU_JINTS0_INS6_SHIFT                                                  (6u)
+#define JCU_JCDERR_ERR                                                         (0x0Fu)
+#define JCU_JCDERR_ERR_SHIFT                                                   (0u)
+#define JCU_JCRST_RST                                                          (0x01u)
+#define JCU_JCRST_RST_SHIFT                                                    (0u)
+#define JCU_JIFECNT_DINSWAP                                                    (0x00000007u)
+#define JCU_JIFECNT_DINSWAP_SHIFT                                              (0u)
+#define JCU_JIFECNT_DINLC                                                      (0x00000010u)
+#define JCU_JIFECNT_DINLC_SHIFT                                                (4u)
+#define JCU_JIFECNT_DINRCMD                                                    (0x00000020u)
+#define JCU_JIFECNT_DINRCMD_SHIFT                                              (5u)
+#define JCU_JIFECNT_DINRINI                                                    (0x00000040u)
+#define JCU_JIFECNT_DINRINI_SHIFT                                              (6u)
+#define JCU_JIFECNT_JOUTSWAP                                                   (0x00000700u)
+#define JCU_JIFECNT_JOUTSWAP_SHIFT                                             (8u)
+#define JCU_JIFECNT_JOUTC                                                      (0x00001000u)
+#define JCU_JIFECNT_JOUTC_SHIFT                                                (12u)
+#define JCU_JIFECNT_JOUTRCMD                                                   (0x00002000u)
+#define JCU_JIFECNT_JOUTRCMD_SHIFT                                             (13u)
+#define JCU_JIFECNT_JOUTRINI                                                   (0x00004000u)
+#define JCU_JIFECNT_JOUTRINI_SHIFT                                             (14u)
+#define JCU_JIFESA_ESA                                                         (0xFFFFFFFFu)
+#define JCU_JIFESA_ESA_SHIFT                                                   (0u)
+#define JCU_JIFESOFST_ESMW                                                     (0x00007FFFu)
+#define JCU_JIFESOFST_ESMW_SHIFT                                               (0u)
+#define JCU_JIFEDA_EDA                                                         (0xFFFFFFFFu)
+#define JCU_JIFEDA_EDA_SHIFT                                                   (0u)
+#define JCU_JIFESLC_LINES                                                      (0x0000FFFFu)
+#define JCU_JIFESLC_LINES_SHIFT                                                (0u)
+#define JCU_JIFEDDC_JDATAS                                                     (0x0000FFFFu)
+#define JCU_JIFEDDC_JDATAS_SHIFT                                               (0u)
+#define JCU_JIFDCNT_DOUTSWAP                                                   (0x00000007u)
+#define JCU_JIFDCNT_DOUTSWAP_SHIFT                                             (0u)
+#define JCU_JIFDCNT_DOUTLC                                                     (0x00000010u)
+#define JCU_JIFDCNT_DOUTLC_SHIFT                                               (4u)
+#define JCU_JIFDCNT_DOUTRCMD                                                   (0x00000020u)
+#define JCU_JIFDCNT_DOUTRCMD_SHIFT                                             (5u)
+#define JCU_JIFDCNT_DOUTRINI                                                   (0x00000040u)
+#define JCU_JIFDCNT_DOUTRINI_SHIFT                                             (6u)
+#define JCU_JIFDCNT_JINSWAP                                                    (0x00000700u)
+#define JCU_JIFDCNT_JINSWAP_SHIFT                                              (8u)
+#define JCU_JIFDCNT_JINC                                                       (0x00001000u)
+#define JCU_JIFDCNT_JINC_SHIFT                                                 (12u)
+#define JCU_JIFDCNT_JINRCMD                                                    (0x00002000u)
+#define JCU_JIFDCNT_JINRCMD_SHIFT                                              (13u)
+#define JCU_JIFDCNT_JINRINI                                                    (0x00004000u)
+#define JCU_JIFDCNT_JINRINI_SHIFT                                              (14u)
+#define JCU_JIFDCNT_OPF                                                        (0x03000000u)
+#define JCU_JIFDCNT_OPF_SHIFT                                                  (24u)
+#define JCU_JIFDCNT_HINTER                                                     (0x0C000000u)
+#define JCU_JIFDCNT_HINTER_SHIFT                                               (26u)
+#define JCU_JIFDCNT_VINTER                                                     (0x30000000u)
+#define JCU_JIFDCNT_VINTER_SHIFT                                               (28u)
+#define JCU_JIFDSA_DSA                                                         (0xFFFFFFFFu)
+#define JCU_JIFDSA_DSA_SHIFT                                                   (0u)
+#define JCU_JIFDDOFST_DDMW                                                     (0x00007FFFu)
+#define JCU_JIFDDOFST_DDMW_SHIFT                                               (0u)
+#define JCU_JIFDDA_DDA                                                         (0xFFFFFFFFu)
+#define JCU_JIFDDA_DDA_SHIFT                                                   (0u)
+#define JCU_JIFDSDC_JDATAS                                                     (0x0000FFFFu)
+#define JCU_JIFDSDC_JDATAS_SHIFT                                               (0u)
+#define JCU_JIFDDLC_LINES                                                      (0x0000FFFFu)
+#define JCU_JIFDDLC_LINES_SHIFT                                                (0u)
+#define JCU_JIFDADT_ALPHA                                                      (0x000000FFu)
+#define JCU_JIFDADT_ALPHA_SHIFT                                                (0u)
+#define JCU_JINTE1_DOUTLEN                                                     (0x00000001u)
+#define JCU_JINTE1_DOUTLEN_SHIFT                                               (0u)
+#define JCU_JINTE1_JINEN                                                       (0x00000002u)
+#define JCU_JINTE1_JINEN_SHIFT                                                 (1u)
+#define JCU_JINTE1_DBTEN                                                       (0x00000004u)
+#define JCU_JINTE1_DBTEN_SHIFT                                                 (2u)
+#define JCU_JINTE1_JOUTEN                                                      (0x00000010u)
+#define JCU_JINTE1_JOUTEN_SHIFT                                                (4u)
+#define JCU_JINTE1_DINLEN                                                      (0x00000020u)
+#define JCU_JINTE1_DINLEN_SHIFT                                                (5u)
+#define JCU_JINTE1_CBTEN                                                       (0x00000040u)
+#define JCU_JINTE1_CBTEN_SHIFT                                                 (6u)
+#define JCU_JINTS1_DOUTLF                                                      (0x00000001u)
+#define JCU_JINTS1_DOUTLF_SHIFT                                                (0u)
+#define JCU_JINTS1_JINF                                                        (0x00000002u)
+#define JCU_JINTS1_JINF_SHIFT                                                  (1u)
+#define JCU_JINTS1_DBTF                                                        (0x00000004u)
+#define JCU_JINTS1_DBTF_SHIFT                                                  (2u)
+#define JCU_JINTS1_JOUTF                                                       (0x00000010u)
+#define JCU_JINTS1_JOUTF_SHIFT                                                 (4u)
+#define JCU_JINTS1_DINLF                                                       (0x00000020u)
+#define JCU_JINTS1_DINLF_SHIFT                                                 (5u)
+#define JCU_JINTS1_CBTF                                                        (0x00000040u)
+#define JCU_JINTS1_CBTF_SHIFT                                                  (6u)
+#define JCU_JIFESVSZ_DINYCHG                                                   (0x00008000u)
+#define JCU_JIFESVSZ_DINYCHG_SHIFT                                             (15u)
+#define JCU_JIFESHSZ_DOUTYCHG                                                  (0x00008000u)
+#define JCU_JIFESHSZ_DOUTYCHG_SHIFT                                            (15u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/lvds_iobitmask.h

@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef LVDS_IOBITMASK_H
+#define LVDS_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define LVDS_LVDS_UPDATE_LVDS_UPDATE                                           (0x00010000u)
+#define LVDS_LVDS_UPDATE_LVDS_UPDATE_SHIFT                                     (16u)
+#define LVDS_LVDSFCL_LVDS_SEL0                                                 (0x0000000Fu)
+#define LVDS_LVDSFCL_LVDS_SEL0_SHIFT                                           (0u)
+#define LVDS_LVDSFCL_LVDS_SEL1                                                 (0x000000F0u)
+#define LVDS_LVDSFCL_LVDS_SEL1_SHIFT                                           (4u)
+#define LVDS_LVDSFCL_LVDS_SEL2                                                 (0x00000F00u)
+#define LVDS_LVDSFCL_LVDS_SEL2_SHIFT                                           (8u)
+#define LVDS_LVDSFCL_SYNC_POL                                                  (0x00C00000u)
+#define LVDS_LVDSFCL_SYNC_POL_SHIFT                                            (22u)
+#define LVDS_LVDSFCL_SYNC_MODE                                                 (0x10000000u)
+#define LVDS_LVDSFCL_SYNC_MODE_SHIFT                                           (28u)
+#define LVDS_LCLKSELR_LVDS_CLK_EN                                              (0x00000010u)
+#define LVDS_LCLKSELR_LVDS_CLK_EN_SHIFT                                        (4u)
+#define LVDS_LCLKSELR_LVDS_ODIV_SET                                            (0x00000300u)
+#define LVDS_LCLKSELR_LVDS_ODIV_SET_SHIFT                                      (8u)
+#define LVDS_LCLKSELR_LVDSPLL_TST                                              (0x0000FC00u)
+#define LVDS_LCLKSELR_LVDSPLL_TST_SHIFT                                        (10u)
+#define LVDS_LCLKSELR_LVDS_IN_CLK_SEL                                          (0x03000000u)
+#define LVDS_LCLKSELR_LVDS_IN_CLK_SEL_SHIFT                                    (24u)
+#define LVDS_LPLLSETR_LVDSPLL_PD                                               (0x00000001u)
+#define LVDS_LPLLSETR_LVDSPLL_PD_SHIFT                                         (0u)
+#define LVDS_LPLLSETR_LVDSPLL_OD                                               (0x00000030u)
+#define LVDS_LPLLSETR_LVDSPLL_OD_SHIFT                                         (4u)
+#define LVDS_LPLLSETR_LVDSPLL_RD                                               (0x00000700u)
+#define LVDS_LPLLSETR_LVDSPLL_RD_SHIFT                                         (8u)
+#define LVDS_LPLLSETR_LVDSPLL_FD                                               (0x007F0000u)
+#define LVDS_LPLLSETR_LVDSPLL_FD_SHIFT                                         (16u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/mtu_iobitmask.h

@@ -0,0 +1,586 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef MTU_IOBITMASK_H
+#define MTU_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define MTU_TOERA_OE3B                                                         (0x01u)
+#define MTU_TOERA_OE3B_SHIFT                                                   (0u)
+#define MTU_TOERA_OE4A                                                         (0x02u)
+#define MTU_TOERA_OE4A_SHIFT                                                   (1u)
+#define MTU_TOERA_OE4B                                                         (0x04u)
+#define MTU_TOERA_OE4B_SHIFT                                                   (2u)
+#define MTU_TOERA_OE3D                                                         (0x08u)
+#define MTU_TOERA_OE3D_SHIFT                                                   (3u)
+#define MTU_TOERA_OE4C                                                         (0x10u)
+#define MTU_TOERA_OE4C_SHIFT                                                   (4u)
+#define MTU_TOERA_OE4D                                                         (0x20u)
+#define MTU_TOERA_OE4D_SHIFT                                                   (5u)
+#define MTU_TGCRA_UF                                                           (0x01u)
+#define MTU_TGCRA_UF_SHIFT                                                     (0u)
+#define MTU_TGCRA_VF                                                           (0x02u)
+#define MTU_TGCRA_VF_SHIFT                                                     (1u)
+#define MTU_TGCRA_WF                                                           (0x04u)
+#define MTU_TGCRA_WF_SHIFT                                                     (2u)
+#define MTU_TGCRA_FB                                                           (0x08u)
+#define MTU_TGCRA_FB_SHIFT                                                     (3u)
+#define MTU_TGCRA_P                                                            (0x10u)
+#define MTU_TGCRA_P_SHIFT                                                      (4u)
+#define MTU_TGCRA_N                                                            (0x20u)
+#define MTU_TGCRA_N_SHIFT                                                      (5u)
+#define MTU_TGCRA_BDC                                                          (0x40u)
+#define MTU_TGCRA_BDC_SHIFT                                                    (6u)
+#define MTU_TOCR1A_OLSP                                                        (0x01u)
+#define MTU_TOCR1A_OLSP_SHIFT                                                  (0u)
+#define MTU_TOCR1A_OLSN                                                        (0x02u)
+#define MTU_TOCR1A_OLSN_SHIFT                                                  (1u)
+#define MTU_TOCR1A_TOCS                                                        (0x04u)
+#define MTU_TOCR1A_TOCS_SHIFT                                                  (2u)
+#define MTU_TOCR1A_TOCL                                                        (0x08u)
+#define MTU_TOCR1A_TOCL_SHIFT                                                  (3u)
+#define MTU_TOCR1A_PSYE                                                        (0x40u)
+#define MTU_TOCR1A_PSYE_SHIFT                                                  (6u)
+#define MTU_TOCR2A_OLS1P                                                       (0x01u)
+#define MTU_TOCR2A_OLS1P_SHIFT                                                 (0u)
+#define MTU_TOCR2A_OLS1N                                                       (0x02u)
+#define MTU_TOCR2A_OLS1N_SHIFT                                                 (1u)
+#define MTU_TOCR2A_OLS2P                                                       (0x04u)
+#define MTU_TOCR2A_OLS2P_SHIFT                                                 (2u)
+#define MTU_TOCR2A_OLS2N                                                       (0x08u)
+#define MTU_TOCR2A_OLS2N_SHIFT                                                 (3u)
+#define MTU_TOCR2A_OLS3P                                                       (0x10u)
+#define MTU_TOCR2A_OLS3P_SHIFT                                                 (4u)
+#define MTU_TOCR2A_OLS3N                                                       (0x20u)
+#define MTU_TOCR2A_OLS3N_SHIFT                                                 (5u)
+#define MTU_TOCR2A_BF                                                          (0xC0u)
+#define MTU_TOCR2A_BF_SHIFT                                                    (6u)
+#define MTU_TCDRA_TCDRA                                                        (0xFFFFu)
+#define MTU_TCDRA_TCDRA_SHIFT                                                  (0u)
+#define MTU_TDDRA_TDDRA                                                        (0xFFFFu)
+#define MTU_TDDRA_TDDRA_SHIFT                                                  (0u)
+#define MTU_TCNTSA_TCNTSA                                                      (0xFFFFu)
+#define MTU_TCNTSA_TCNTSA_SHIFT                                                (0u)
+#define MTU_TCBRA_TCBRA                                                        (0xFFFFu)
+#define MTU_TCBRA_TCBRA_SHIFT                                                  (0u)
+#define MTU_TITCR1A_T4VCOR                                                     (0x07u)
+#define MTU_TITCR1A_T4VCOR_SHIFT                                               (0u)
+#define MTU_TITCR1A_T4VEN                                                      (0x08u)
+#define MTU_TITCR1A_T4VEN_SHIFT                                                (3u)
+#define MTU_TITCR1A_T3ACOR                                                     (0x70u)
+#define MTU_TITCR1A_T3ACOR_SHIFT                                               (4u)
+#define MTU_TITCR1A_T3AEN                                                      (0x80u)
+#define MTU_TITCR1A_T3AEN_SHIFT                                                (7u)
+#define MTU_TITCNT1A_T4VCNT                                                    (0x07u)
+#define MTU_TITCNT1A_T4VCNT_SHIFT                                              (0u)
+#define MTU_TITCNT1A_T3ACNT                                                    (0x70u)
+#define MTU_TITCNT1A_T3ACNT_SHIFT                                              (4u)
+#define MTU_TBTERA_BTE                                                         (0x03u)
+#define MTU_TBTERA_BTE_SHIFT                                                   (0u)
+#define MTU_TDERA_TDER                                                         (0x01u)
+#define MTU_TDERA_TDER_SHIFT                                                   (0u)
+#define MTU_TOLBRA_OLS1P                                                       (0x01u)
+#define MTU_TOLBRA_OLS1P_SHIFT                                                 (0u)
+#define MTU_TOLBRA_OLS1N                                                       (0x02u)
+#define MTU_TOLBRA_OLS1N_SHIFT                                                 (1u)
+#define MTU_TOLBRA_OLS2P                                                       (0x04u)
+#define MTU_TOLBRA_OLS2P_SHIFT                                                 (2u)
+#define MTU_TOLBRA_OLS2N                                                       (0x08u)
+#define MTU_TOLBRA_OLS2N_SHIFT                                                 (3u)
+#define MTU_TOLBRA_OLS3P                                                       (0x10u)
+#define MTU_TOLBRA_OLS3P_SHIFT                                                 (4u)
+#define MTU_TOLBRA_OLS3N                                                       (0x20u)
+#define MTU_TOLBRA_OLS3N_SHIFT                                                 (5u)
+#define MTU_TITMRA_TITM                                                        (0x01u)
+#define MTU_TITMRA_TITM_SHIFT                                                  (0u)
+#define MTU_TITCR2A_TRG4COR                                                    (0x07u)
+#define MTU_TITCR2A_TRG4COR_SHIFT                                              (0u)
+#define MTU_TITCNT2A_TRG4CNT                                                   (0x07u)
+#define MTU_TITCNT2A_TRG4CNT_SHIFT                                             (0u)
+#define MTU_TWCRA_WRE                                                          (0x01u)
+#define MTU_TWCRA_WRE_SHIFT                                                    (0u)
+#define MTU_TWCRA_SCC                                                          (0x02u)
+#define MTU_TWCRA_SCC_SHIFT                                                    (1u)
+#define MTU_TWCRA_CCE                                                          (0x80u)
+#define MTU_TWCRA_CCE_SHIFT                                                    (7u)
+#define MTU_TMDR2A_DRS                                                         (0x01u)
+#define MTU_TMDR2A_DRS_SHIFT                                                   (0u)
+#define MTU_TSTRA_CST0                                                         (0x01u)
+#define MTU_TSTRA_CST0_SHIFT                                                   (0u)
+#define MTU_TSTRA_CST1                                                         (0x02u)
+#define MTU_TSTRA_CST1_SHIFT                                                   (1u)
+#define MTU_TSTRA_CST2                                                         (0x04u)
+#define MTU_TSTRA_CST2_SHIFT                                                   (2u)
+#define MTU_TSTRA_CST8                                                         (0x08u)
+#define MTU_TSTRA_CST8_SHIFT                                                   (3u)
+#define MTU_TSTRA_CST3                                                         (0x40u)
+#define MTU_TSTRA_CST3_SHIFT                                                   (6u)
+#define MTU_TSTRA_CST4                                                         (0x80u)
+#define MTU_TSTRA_CST4_SHIFT                                                   (7u)
+#define MTU_TSYRA_SYNC0                                                        (0x01u)
+#define MTU_TSYRA_SYNC0_SHIFT                                                  (0u)
+#define MTU_TSYRA_SYNC1                                                        (0x02u)
+#define MTU_TSYRA_SYNC1_SHIFT                                                  (1u)
+#define MTU_TSYRA_SYNC2                                                        (0x04u)
+#define MTU_TSYRA_SYNC2_SHIFT                                                  (2u)
+#define MTU_TSYRA_SYNC3                                                        (0x40u)
+#define MTU_TSYRA_SYNC3_SHIFT                                                  (6u)
+#define MTU_TSYRA_SYNC4                                                        (0x80u)
+#define MTU_TSYRA_SYNC4_SHIFT                                                  (7u)
+#define MTU_TCSYSTR_SCH7                                                       (0x01u)
+#define MTU_TCSYSTR_SCH7_SHIFT                                                 (0u)
+#define MTU_TCSYSTR_SCH6                                                       (0x02u)
+#define MTU_TCSYSTR_SCH6_SHIFT                                                 (1u)
+#define MTU_TCSYSTR_SCH4                                                       (0x08u)
+#define MTU_TCSYSTR_SCH4_SHIFT                                                 (3u)
+#define MTU_TCSYSTR_SCH3                                                       (0x10u)
+#define MTU_TCSYSTR_SCH3_SHIFT                                                 (4u)
+#define MTU_TCSYSTR_SCH2                                                       (0x20u)
+#define MTU_TCSYSTR_SCH2_SHIFT                                                 (5u)
+#define MTU_TCSYSTR_SCH1                                                       (0x40u)
+#define MTU_TCSYSTR_SCH1_SHIFT                                                 (6u)
+#define MTU_TCSYSTR_SCH0                                                       (0x80u)
+#define MTU_TCSYSTR_SCH0_SHIFT                                                 (7u)
+#define MTU_TRWERA_RWE                                                         (0x01u)
+#define MTU_TRWERA_RWE_SHIFT                                                   (0u)
+#define MTU_TOERB_OE6B                                                         (0x01u)
+#define MTU_TOERB_OE6B_SHIFT                                                   (0u)
+#define MTU_TOERB_OE7A                                                         (0x02u)
+#define MTU_TOERB_OE7A_SHIFT                                                   (1u)
+#define MTU_TOERB_OE7B                                                         (0x04u)
+#define MTU_TOERB_OE7B_SHIFT                                                   (2u)
+#define MTU_TOERB_OE6D                                                         (0x08u)
+#define MTU_TOERB_OE6D_SHIFT                                                   (3u)
+#define MTU_TOERB_OE7C                                                         (0x10u)
+#define MTU_TOERB_OE7C_SHIFT                                                   (4u)
+#define MTU_TOERB_OE7D                                                         (0x20u)
+#define MTU_TOERB_OE7D_SHIFT                                                   (5u)
+#define MTU_TOCR1B_OLSP                                                        (0x01u)
+#define MTU_TOCR1B_OLSP_SHIFT                                                  (0u)
+#define MTU_TOCR1B_OLSN                                                        (0x02u)
+#define MTU_TOCR1B_OLSN_SHIFT                                                  (1u)
+#define MTU_TOCR1B_TOCS                                                        (0x04u)
+#define MTU_TOCR1B_TOCS_SHIFT                                                  (2u)
+#define MTU_TOCR1B_TOCL                                                        (0x08u)
+#define MTU_TOCR1B_TOCL_SHIFT                                                  (3u)
+#define MTU_TOCR1B_PSYE                                                        (0x40u)
+#define MTU_TOCR1B_PSYE_SHIFT                                                  (6u)
+#define MTU_TOCR2B_OLS1P                                                       (0x01u)
+#define MTU_TOCR2B_OLS1P_SHIFT                                                 (0u)
+#define MTU_TOCR2B_OLS1N                                                       (0x02u)
+#define MTU_TOCR2B_OLS1N_SHIFT                                                 (1u)
+#define MTU_TOCR2B_OLS2P                                                       (0x04u)
+#define MTU_TOCR2B_OLS2P_SHIFT                                                 (2u)
+#define MTU_TOCR2B_OLS2N                                                       (0x08u)
+#define MTU_TOCR2B_OLS2N_SHIFT                                                 (3u)
+#define MTU_TOCR2B_OLS3P                                                       (0x10u)
+#define MTU_TOCR2B_OLS3P_SHIFT                                                 (4u)
+#define MTU_TOCR2B_OLS3N                                                       (0x20u)
+#define MTU_TOCR2B_OLS3N_SHIFT                                                 (5u)
+#define MTU_TOCR2B_BF                                                          (0xC0u)
+#define MTU_TOCR2B_BF_SHIFT                                                    (6u)
+#define MTU_TCDRB_TCDRB                                                        (0xFFFFu)
+#define MTU_TCDRB_TCDRB_SHIFT                                                  (0u)
+#define MTU_TDDRB_TDDRB                                                        (0xFFFFu)
+#define MTU_TDDRB_TDDRB_SHIFT                                                  (0u)
+#define MTU_TCNTSB_TCNTSB                                                      (0xFFFFu)
+#define MTU_TCNTSB_TCNTSB_SHIFT                                                (0u)
+#define MTU_TCBRB_TCBRB                                                        (0xFFFFu)
+#define MTU_TCBRB_TCBRB_SHIFT                                                  (0u)
+#define MTU_TITCR1B_T7VCOR                                                     (0x07u)
+#define MTU_TITCR1B_T7VCOR_SHIFT                                               (0u)
+#define MTU_TITCR1B_T7VEN                                                      (0x08u)
+#define MTU_TITCR1B_T7VEN_SHIFT                                                (3u)
+#define MTU_TITCR1B_T6ACOR                                                     (0x70u)
+#define MTU_TITCR1B_T6ACOR_SHIFT                                               (4u)
+#define MTU_TITCR1B_T6AEN                                                      (0x80u)
+#define MTU_TITCR1B_T6AEN_SHIFT                                                (7u)
+#define MTU_TITCNT1B_T7VCNT                                                    (0x07u)
+#define MTU_TITCNT1B_T7VCNT_SHIFT                                              (0u)
+#define MTU_TITCNT1B_T6ACNT                                                    (0x70u)
+#define MTU_TITCNT1B_T6ACNT_SHIFT                                              (4u)
+#define MTU_TBTERB_BTE                                                         (0x03u)
+#define MTU_TBTERB_BTE_SHIFT                                                   (0u)
+#define MTU_TDERB_TDER                                                         (0x01u)
+#define MTU_TDERB_TDER_SHIFT                                                   (0u)
+#define MTU_TOLBRB_OLS1P                                                       (0x01u)
+#define MTU_TOLBRB_OLS1P_SHIFT                                                 (0u)
+#define MTU_TOLBRB_OLS1N                                                       (0x02u)
+#define MTU_TOLBRB_OLS1N_SHIFT                                                 (1u)
+#define MTU_TOLBRB_OLS2P                                                       (0x04u)
+#define MTU_TOLBRB_OLS2P_SHIFT                                                 (2u)
+#define MTU_TOLBRB_OLS2N                                                       (0x08u)
+#define MTU_TOLBRB_OLS2N_SHIFT                                                 (3u)
+#define MTU_TOLBRB_OLS3P                                                       (0x10u)
+#define MTU_TOLBRB_OLS3P_SHIFT                                                 (4u)
+#define MTU_TOLBRB_OLS3N                                                       (0x20u)
+#define MTU_TOLBRB_OLS3N_SHIFT                                                 (5u)
+#define MTU_TITMRB_TITM                                                        (0x01u)
+#define MTU_TITMRB_TITM_SHIFT                                                  (0u)
+#define MTU_TITCR2B_TRG7COR                                                    (0x07u)
+#define MTU_TITCR2B_TRG7COR_SHIFT                                              (0u)
+#define MTU_TITCNT2B_TRG7CNT                                                   (0x07u)
+#define MTU_TITCNT2B_TRG7CNT_SHIFT                                             (0u)
+#define MTU_TWCRB_WRE                                                          (0x01u)
+#define MTU_TWCRB_WRE_SHIFT                                                    (0u)
+#define MTU_TWCRB_SCC                                                          (0x02u)
+#define MTU_TWCRB_SCC_SHIFT                                                    (1u)
+#define MTU_TWCRB_CCE                                                          (0x80u)
+#define MTU_TWCRB_CCE_SHIFT                                                    (7u)
+#define MTU_TMDR2B_DRS                                                         (0x01u)
+#define MTU_TMDR2B_DRS_SHIFT                                                   (0u)
+#define MTU_TSTRB_CST6                                                         (0x40u)
+#define MTU_TSTRB_CST6_SHIFT                                                   (6u)
+#define MTU_TSTRB_CST7                                                         (0x80u)
+#define MTU_TSTRB_CST7_SHIFT                                                   (7u)
+#define MTU_TSYRB_SYNC6                                                        (0x40u)
+#define MTU_TSYRB_SYNC6_SHIFT                                                  (6u)
+#define MTU_TSYRB_SYNC7                                                        (0x80u)
+#define MTU_TSYRB_SYNC7_SHIFT                                                  (7u)
+#define MTU_TRWERB_RWE                                                         (0x01u)
+#define MTU_TRWERB_RWE_SHIFT                                                   (0u)
+#define MTU_NFCR0_NFAEN                                                        (0x01u)
+#define MTU_NFCR0_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR0_NFBEN                                                        (0x02u)
+#define MTU_NFCR0_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR0_NFCEN                                                        (0x04u)
+#define MTU_NFCR0_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR0_NFDEN                                                        (0x08u)
+#define MTU_NFCR0_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR0_NFCS                                                         (0x30u)
+#define MTU_NFCR0_NFCS_SHIFT                                                   (4u)
+#define MTU_NFCRC_NFAEN                                                        (0x01u)
+#define MTU_NFCRC_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCRC_NFBEN                                                        (0x02u)
+#define MTU_NFCRC_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCRC_NFCEN                                                        (0x04u)
+#define MTU_NFCRC_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCRC_NFDEN                                                        (0x08u)
+#define MTU_NFCRC_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCRC_NFCSC                                                        (0x30u)
+#define MTU_NFCRC_NFCSC_SHIFT                                                  (4u)
+#define MTU_TCR_TPSC                                                           (0x07u)
+#define MTU_TCR_TPSC_SHIFT                                                     (0u)
+#define MTU_TCR_CKEG                                                           (0x18u)
+#define MTU_TCR_CKEG_SHIFT                                                     (3u)
+#define MTU_TCR_CCLR                                                           (0xE0u)
+#define MTU_TCR_CCLR_SHIFT                                                     (5u)
+#define MTU_TMDR1_MD                                                           (0x0Fu)
+#define MTU_TMDR1_MD_SHIFT                                                     (0u)
+#define MTU_TMDR1_BFA                                                          (0x10u)
+#define MTU_TMDR1_BFA_SHIFT                                                    (4u)
+#define MTU_TMDR1_BFB                                                          (0x20u)
+#define MTU_TMDR1_BFB_SHIFT                                                    (5u)
+#define MTU_TMDR1_BFE                                                          (0x40u)
+#define MTU_TMDR1_BFE_SHIFT                                                    (6u)
+#define MTU_TIORH_IOA                                                          (0x0Fu)
+#define MTU_TIORH_IOA_SHIFT                                                    (0u)
+#define MTU_TIORH_IOB                                                          (0xF0u)
+#define MTU_TIORH_IOB_SHIFT                                                    (4u)
+#define MTU_TIORL_IOC                                                          (0x0Fu)
+#define MTU_TIORL_IOC_SHIFT                                                    (0u)
+#define MTU_TIORL_IOD                                                          (0xF0u)
+#define MTU_TIORL_IOD_SHIFT                                                    (4u)
+#define MTU_TIER_TGIEA                                                         (0x01u)
+#define MTU_TIER_TGIEA_SHIFT                                                   (0u)
+#define MTU_TIER_TGIEB                                                         (0x02u)
+#define MTU_TIER_TGIEB_SHIFT                                                   (1u)
+#define MTU_TIER_TGIEC                                                         (0x04u)
+#define MTU_TIER_TGIEC_SHIFT                                                   (2u)
+#define MTU_TIER_TGIED                                                         (0x08u)
+#define MTU_TIER_TGIED_SHIFT                                                   (3u)
+#define MTU_TIER_TCIEV                                                         (0x10u)
+#define MTU_TIER_TCIEV_SHIFT                                                   (4u)
+#define MTU_TIER_TTGE                                                          (0x80u)
+#define MTU_TIER_TTGE_SHIFT                                                    (7u)
+#define MTU_TCNT_TCNT                                                          (0xFFFFu)
+#define MTU_TCNT_TCNT_SHIFT                                                    (0u)
+#define MTU_TGRA_TGRA                                                          (0xFFFFu)
+#define MTU_TGRA_TGRA_SHIFT                                                    (0u)
+#define MTU_TGRB_TGRB                                                          (0xFFFFu)
+#define MTU_TGRB_TGRB_SHIFT                                                    (0u)
+#define MTU_TGRC_TGRC                                                          (0xFFFFu)
+#define MTU_TGRC_TGRC_SHIFT                                                    (0u)
+#define MTU_TGRD_TGRD                                                          (0xFFFFu)
+#define MTU_TGRD_TGRD_SHIFT                                                    (0u)
+#define MTU_TGRE_TGRE                                                          (0xFFFFu)
+#define MTU_TGRE_TGRE_SHIFT                                                    (0u)
+#define MTU_TGRF_TGRF                                                          (0xFFFFu)
+#define MTU_TGRF_TGRF_SHIFT                                                    (0u)
+#define MTU_TIER2_TGIEE                                                        (0x01u)
+#define MTU_TIER2_TGIEE_SHIFT                                                  (0u)
+#define MTU_TIER2_TGIEF                                                        (0x02u)
+#define MTU_TIER2_TGIEF_SHIFT                                                  (1u)
+#define MTU_TIER2_TTGE2                                                        (0x80u)
+#define MTU_TIER2_TTGE2_SHIFT                                                  (7u)
+#define MTU_TBTM_TTSA                                                          (0x01u)
+#define MTU_TBTM_TTSA_SHIFT                                                    (0u)
+#define MTU_TBTM_TTSB                                                          (0x02u)
+#define MTU_TBTM_TTSB_SHIFT                                                    (1u)
+#define MTU_TBTM_TTSE                                                          (0x04u)
+#define MTU_TBTM_TTSE_SHIFT                                                    (2u)
+#define MTU_TCR2_TPSC2                                                         (0x07u)
+#define MTU_TCR2_TPSC2_SHIFT                                                   (0u)
+#define MTU_NFCR1_NFAEN                                                        (0x01u)
+#define MTU_NFCR1_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR1_NFBEN                                                        (0x02u)
+#define MTU_NFCR1_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR1_NFCEN                                                        (0x04u)
+#define MTU_NFCR1_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR1_NFDEN                                                        (0x08u)
+#define MTU_NFCR1_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR1_NFCS                                                         (0x30u)
+#define MTU_NFCR1_NFCS_SHIFT                                                   (4u)
+#define MTU_TIOR_IOA                                                           (0x0Fu)
+#define MTU_TIOR_IOA_SHIFT                                                     (0u)
+#define MTU_TIOR_IOB                                                           (0xF0u)
+#define MTU_TIOR_IOB_SHIFT                                                     (4u)
+#define MTU_TIER_TCIEU                                                         (0x20u)
+#define MTU_TIER_TCIEU_SHIFT                                                   (5u)
+#define MTU_TSR_TCFD                                                           (0x80u)
+#define MTU_TSR_TCFD_SHIFT                                                     (7u)
+#define MTU_TICCR_I1AE                                                         (0x01u)
+#define MTU_TICCR_I1AE_SHIFT                                                   (0u)
+#define MTU_TICCR_I1BE                                                         (0x02u)
+#define MTU_TICCR_I1BE_SHIFT                                                   (1u)
+#define MTU_TICCR_I2AE                                                         (0x04u)
+#define MTU_TICCR_I2AE_SHIFT                                                   (2u)
+#define MTU_TICCR_I2BE                                                         (0x08u)
+#define MTU_TICCR_I2BE_SHIFT                                                   (3u)
+#define MTU_TMDR3_LWA                                                          (0x01u)
+#define MTU_TMDR3_LWA_SHIFT                                                    (0u)
+#define MTU_TMDR3_PHCKSEL                                                      (0x02u)
+#define MTU_TMDR3_PHCKSEL_SHIFT                                                (1u)
+#define MTU_TCR2_PCB                                                           (0x18u)
+#define MTU_TCR2_PCB_SHIFT                                                     (3u)
+#define MTU_TCNTLW_TCNTLW                                                      (0xFFFFFFFFu)
+#define MTU_TCNTLW_TCNTLW_SHIFT                                                (0u)
+#define MTU_TGRALW_TGRALW                                                      (0xFFFFFFFFu)
+#define MTU_TGRALW_TGRALW_SHIFT                                                (0u)
+#define MTU_TGRBLW_TGRBLW                                                      (0xFFFFFFFFu)
+#define MTU_TGRBLW_TGRBLW_SHIFT                                                (0u)
+#define MTU_NFCR2_NFAEN                                                        (0x01u)
+#define MTU_NFCR2_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR2_NFBEN                                                        (0x02u)
+#define MTU_NFCR2_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR2_NFCEN                                                        (0x04u)
+#define MTU_NFCR2_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR2_NFDEN                                                        (0x08u)
+#define MTU_NFCR2_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR2_NFCS                                                         (0x30u)
+#define MTU_NFCR2_NFCS_SHIFT                                                   (4u)
+#define MTU_NFCR3_NFAEN                                                        (0x01u)
+#define MTU_NFCR3_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR3_NFBEN                                                        (0x02u)
+#define MTU_NFCR3_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR3_NFCEN                                                        (0x04u)
+#define MTU_NFCR3_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR3_NFDEN                                                        (0x08u)
+#define MTU_NFCR3_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR3_NFCS                                                         (0x30u)
+#define MTU_NFCR3_NFCS_SHIFT                                                   (4u)
+#define MTU_TIER_TTGE2                                                         (0x40u)
+#define MTU_TIER_TTGE2_SHIFT                                                   (6u)
+#define MTU_TADCR_ITB4VE                                                       (0x0001u)
+#define MTU_TADCR_ITB4VE_SHIFT                                                 (0u)
+#define MTU_TADCR_ITB3AE                                                       (0x0002u)
+#define MTU_TADCR_ITB3AE_SHIFT                                                 (1u)
+#define MTU_TADCR_ITA4VE                                                       (0x0004u)
+#define MTU_TADCR_ITA4VE_SHIFT                                                 (2u)
+#define MTU_TADCR_ITA3AE                                                       (0x0008u)
+#define MTU_TADCR_ITA3AE_SHIFT                                                 (3u)
+#define MTU_TADCR_DT4BE                                                        (0x0010u)
+#define MTU_TADCR_DT4BE_SHIFT                                                  (4u)
+#define MTU_TADCR_UT4BE                                                        (0x0020u)
+#define MTU_TADCR_UT4BE_SHIFT                                                  (5u)
+#define MTU_TADCR_DT4AE                                                        (0x0040u)
+#define MTU_TADCR_DT4AE_SHIFT                                                  (6u)
+#define MTU_TADCR_UT4AE                                                        (0x0080u)
+#define MTU_TADCR_UT4AE_SHIFT                                                  (7u)
+#define MTU_TADCR_BF                                                           (0xC000u)
+#define MTU_TADCR_BF_SHIFT                                                     (14u)
+#define MTU_TADCORA_TADCORA                                                    (0xFFFFu)
+#define MTU_TADCORA_TADCORA_SHIFT                                              (0u)
+#define MTU_TADCORB_TADCORB                                                    (0xFFFFu)
+#define MTU_TADCORB_TADCORB_SHIFT                                              (0u)
+#define MTU_TADCOBRA_TADCOBRA                                                  (0xFFFFu)
+#define MTU_TADCOBRA_TADCOBRA_SHIFT                                            (0u)
+#define MTU_TADCOBRB_TADCOBRB                                                  (0xFFFFu)
+#define MTU_TADCOBRB_TADCOBRB_SHIFT                                            (0u)
+#define MTU_NFCR4_NFAEN                                                        (0x01u)
+#define MTU_NFCR4_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR4_NFBEN                                                        (0x02u)
+#define MTU_NFCR4_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR4_NFCEN                                                        (0x04u)
+#define MTU_NFCR4_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR4_NFDEN                                                        (0x08u)
+#define MTU_NFCR4_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR4_NFCS                                                         (0x30u)
+#define MTU_NFCR4_NFCS_SHIFT                                                   (4u)
+#define MTU_NFCR5_NFUEN                                                        (0x01u)
+#define MTU_NFCR5_NFUEN_SHIFT                                                  (0u)
+#define MTU_NFCR5_NFVEN                                                        (0x02u)
+#define MTU_NFCR5_NFVEN_SHIFT                                                  (1u)
+#define MTU_NFCR5_NFWEN                                                        (0x04u)
+#define MTU_NFCR5_NFWEN_SHIFT                                                  (2u)
+#define MTU_NFCR5_NFCS                                                         (0x30u)
+#define MTU_NFCR5_NFCS_SHIFT                                                   (4u)
+#define MTU_TCNTU_TCNTU                                                        (0xFFFFu)
+#define MTU_TCNTU_TCNTU_SHIFT                                                  (0u)
+#define MTU_TGRU_TGRU                                                          (0xFFFFu)
+#define MTU_TGRU_TGRU_SHIFT                                                    (0u)
+#define MTU_TCRU_TPSC                                                          (0x03u)
+#define MTU_TCRU_TPSC_SHIFT                                                    (0u)
+#define MTU_TCR2U_TPSC2                                                        (0x07u)
+#define MTU_TCR2U_TPSC2_SHIFT                                                  (0u)
+#define MTU_TCR2U_CKEG                                                         (0x18u)
+#define MTU_TCR2U_CKEG_SHIFT                                                   (3u)
+#define MTU_TIORU_IOC                                                          (0x1Fu)
+#define MTU_TIORU_IOC_SHIFT                                                    (0u)
+#define MTU_TCNTV_TCNTV                                                        (0xFFFFu)
+#define MTU_TCNTV_TCNTV_SHIFT                                                  (0u)
+#define MTU_TGRV_TGRV                                                          (0xFFFFu)
+#define MTU_TGRV_TGRV_SHIFT                                                    (0u)
+#define MTU_TCRV_TPSC                                                          (0x03u)
+#define MTU_TCRV_TPSC_SHIFT                                                    (0u)
+#define MTU_TCR2V_TPSC2                                                        (0x07u)
+#define MTU_TCR2V_TPSC2_SHIFT                                                  (0u)
+#define MTU_TCR2V_CKEG                                                         (0x18u)
+#define MTU_TCR2V_CKEG_SHIFT                                                   (3u)
+#define MTU_TIORV_IOC                                                          (0x1Fu)
+#define MTU_TIORV_IOC_SHIFT                                                    (0u)
+#define MTU_TCNTW_TCNTW                                                        (0xFFFFu)
+#define MTU_TCNTW_TCNTW_SHIFT                                                  (0u)
+#define MTU_TGRW_TGRW                                                          (0xFFFFu)
+#define MTU_TGRW_TGRW_SHIFT                                                    (0u)
+#define MTU_TCRW_TPSC                                                          (0x03u)
+#define MTU_TCRW_TPSC_SHIFT                                                    (0u)
+#define MTU_TCR2W_TPSC2                                                        (0x07u)
+#define MTU_TCR2W_TPSC2_SHIFT                                                  (0u)
+#define MTU_TCR2W_CKEG                                                         (0x18u)
+#define MTU_TCR2W_CKEG_SHIFT                                                   (3u)
+#define MTU_TIORW_IOC                                                          (0x1Fu)
+#define MTU_TIORW_IOC_SHIFT                                                    (0u)
+#define MTU_TIER_TGIE5W                                                        (0x01u)
+#define MTU_TIER_TGIE5W_SHIFT                                                  (0u)
+#define MTU_TIER_TGIE5V                                                        (0x02u)
+#define MTU_TIER_TGIE5V_SHIFT                                                  (1u)
+#define MTU_TIER_TGIE5U                                                        (0x04u)
+#define MTU_TIER_TGIE5U_SHIFT                                                  (2u)
+#define MTU_TSTR_CSTW5                                                         (0x01u)
+#define MTU_TSTR_CSTW5_SHIFT                                                   (0u)
+#define MTU_TSTR_CSTV5                                                         (0x02u)
+#define MTU_TSTR_CSTV5_SHIFT                                                   (1u)
+#define MTU_TSTR_CSTU5                                                         (0x04u)
+#define MTU_TSTR_CSTU5_SHIFT                                                   (2u)
+#define MTU_TCNTCMPCLR_CMPCLR5W                                                (0x01u)
+#define MTU_TCNTCMPCLR_CMPCLR5W_SHIFT                                          (0u)
+#define MTU_TCNTCMPCLR_CMPCLR5V                                                (0x02u)
+#define MTU_TCNTCMPCLR_CMPCLR5V_SHIFT                                          (1u)
+#define MTU_TCNTCMPCLR_CMPCLR5U                                                (0x04u)
+#define MTU_TCNTCMPCLR_CMPCLR5U_SHIFT                                          (2u)
+#define MTU_TSYCR_CE2B                                                         (0x01u)
+#define MTU_TSYCR_CE2B_SHIFT                                                   (0u)
+#define MTU_TSYCR_CE2A                                                         (0x02u)
+#define MTU_TSYCR_CE2A_SHIFT                                                   (1u)
+#define MTU_TSYCR_CE1B                                                         (0x04u)
+#define MTU_TSYCR_CE1B_SHIFT                                                   (2u)
+#define MTU_TSYCR_CE1A                                                         (0x08u)
+#define MTU_TSYCR_CE1A_SHIFT                                                   (3u)
+#define MTU_TSYCR_CE0D                                                         (0x10u)
+#define MTU_TSYCR_CE0D_SHIFT                                                   (4u)
+#define MTU_TSYCR_CE0C                                                         (0x20u)
+#define MTU_TSYCR_CE0C_SHIFT                                                   (5u)
+#define MTU_TSYCR_CE0B                                                         (0x40u)
+#define MTU_TSYCR_CE0B_SHIFT                                                   (6u)
+#define MTU_TSYCR_CE0A                                                         (0x80u)
+#define MTU_TSYCR_CE0A_SHIFT                                                   (7u)
+#define MTU_NFCR6_NFAEN                                                        (0x01u)
+#define MTU_NFCR6_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR6_NFBEN                                                        (0x02u)
+#define MTU_NFCR6_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR6_NFCEN                                                        (0x04u)
+#define MTU_NFCR6_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR6_NFDEN                                                        (0x08u)
+#define MTU_NFCR6_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR6_NFCS                                                         (0x30u)
+#define MTU_NFCR6_NFCS_SHIFT                                                   (4u)
+#define MTU_TADCR_ITB7VE                                                       (0x0001u)
+#define MTU_TADCR_ITB7VE_SHIFT                                                 (0u)
+#define MTU_TADCR_ITB6AE                                                       (0x0002u)
+#define MTU_TADCR_ITB6AE_SHIFT                                                 (1u)
+#define MTU_TADCR_ITA7VE                                                       (0x0004u)
+#define MTU_TADCR_ITA7VE_SHIFT                                                 (2u)
+#define MTU_TADCR_ITA6AE                                                       (0x0008u)
+#define MTU_TADCR_ITA6AE_SHIFT                                                 (3u)
+#define MTU_TADCR_DT7BE                                                        (0x0010u)
+#define MTU_TADCR_DT7BE_SHIFT                                                  (4u)
+#define MTU_TADCR_UT7BE                                                        (0x0020u)
+#define MTU_TADCR_UT7BE_SHIFT                                                  (5u)
+#define MTU_TADCR_DT7AE                                                        (0x0040u)
+#define MTU_TADCR_DT7AE_SHIFT                                                  (6u)
+#define MTU_TADCR_UT7AE                                                        (0x0080u)
+#define MTU_TADCR_UT7AE_SHIFT                                                  (7u)
+#define MTU_NFCR7_NFAEN                                                        (0x01u)
+#define MTU_NFCR7_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR7_NFBEN                                                        (0x02u)
+#define MTU_NFCR7_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR7_NFCEN                                                        (0x04u)
+#define MTU_NFCR7_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR7_NFDEN                                                        (0x08u)
+#define MTU_NFCR7_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR7_NFCS                                                         (0x30u)
+#define MTU_NFCR7_NFCS_SHIFT                                                   (4u)
+#define MTU_NFCR8_NFAEN                                                        (0x01u)
+#define MTU_NFCR8_NFAEN_SHIFT                                                  (0u)
+#define MTU_NFCR8_NFBEN                                                        (0x02u)
+#define MTU_NFCR8_NFBEN_SHIFT                                                  (1u)
+#define MTU_NFCR8_NFCEN                                                        (0x04u)
+#define MTU_NFCR8_NFCEN_SHIFT                                                  (2u)
+#define MTU_NFCR8_NFDEN                                                        (0x08u)
+#define MTU_NFCR8_NFDEN_SHIFT                                                  (3u)
+#define MTU_NFCR8_NFCS                                                         (0x30u)
+#define MTU_NFCR8_NFCS_SHIFT                                                   (4u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/nandc_iobitmask.h

@@ -0,0 +1,280 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef NANDC_IOBITMASK_H
+#define NANDC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define NANDC_COMMAND_CMD_SEQ                                                  (0x0000003Fu)
+#define NANDC_COMMAND_CMD_SEQ_SHIFT                                            (0u)
+#define NANDC_COMMAND_INPUT_SEL                                                (0x00000040u)
+#define NANDC_COMMAND_INPUT_SEL_SHIFT                                          (6u)
+#define NANDC_COMMAND_DATA_SEL                                                 (0x00000080u)
+#define NANDC_COMMAND_DATA_SEL_SHIFT                                           (7u)
+#define NANDC_COMMAND_CMD_0                                                    (0x0000FF00u)
+#define NANDC_COMMAND_CMD_0_SHIFT                                              (8u)
+#define NANDC_COMMAND_CMD_1                                                    (0x00FF0000u)
+#define NANDC_COMMAND_CMD_1_SHIFT                                              (16u)
+#define NANDC_COMMAND_CMD_2                                                    (0xFF000000u)
+#define NANDC_COMMAND_CMD_2_SHIFT                                              (24u)
+#define NANDC_CONTROL_READ_STATUS_EN                                           (0x00000001u)
+#define NANDC_CONTROL_READ_STATUS_EN_SHIFT                                     (0u)
+#define NANDC_CONTROL_ECC_BLOCK_SIZE                                           (0x00000006u)
+#define NANDC_CONTROL_ECC_BLOCK_SIZE_SHIFT                                     (1u)
+#define NANDC_CONTROL_INT_EN                                                   (0x00000010u)
+#define NANDC_CONTROL_INT_EN_SHIFT                                             (4u)
+#define NANDC_CONTROL_ECC_EN                                                   (0x00000020u)
+#define NANDC_CONTROL_ECC_EN_SHIFT                                             (5u)
+#define NANDC_CONTROL_BLOCK_SIZE                                               (0x000000C0u)
+#define NANDC_CONTROL_BLOCK_SIZE_SHIFT                                         (6u)
+#define NANDC_CONTROL_BBM_EN                                                   (0x00002000u)
+#define NANDC_CONTROL_BBM_EN_SHIFT                                             (13u)
+#define NANDC_CONTROL_PROT_EN                                                  (0x00004000u)
+#define NANDC_CONTROL_PROT_EN_SHIFT                                            (14u)
+#define NANDC_CONTROL_ADDR0_AUTO_INCR                                          (0x00010000u)
+#define NANDC_CONTROL_ADDR0_AUTO_INCR_SHIFT                                    (16u)
+#define NANDC_CONTROL_ADDR1_AUTO_INCR                                          (0x00020000u)
+#define NANDC_CONTROL_ADDR1_AUTO_INCR_SHIFT                                    (17u)
+#define NANDC_CONTROL_SMALL_BLOCK_EN                                           (0x00200000u)
+#define NANDC_CONTROL_SMALL_BLOCK_EN_SHIFT                                     (21u)
+#define NANDC_CONTROL_MLUN_EN                                                  (0x00400000u)
+#define NANDC_CONTROL_MLUN_EN_SHIFT                                            (22u)
+#define NANDC_CONTROL_AUTO_READ_STAT_EN                                        (0x00800000u)
+#define NANDC_CONTROL_AUTO_READ_STAT_EN_SHIFT                                  (23u)
+#define NANDC_STATUS_MEM0_ST                                                   (0x00000001u)
+#define NANDC_STATUS_MEM0_ST_SHIFT                                             (0u)
+#define NANDC_STATUS_CTRL_STAT                                                 (0x00000100u)
+#define NANDC_STATUS_CTRL_STAT_SHIFT                                           (8u)
+#define NANDC_STATUS_DATASIZE_ERROR_ST                                         (0x00000200u)
+#define NANDC_STATUS_DATASIZE_ERROR_ST_SHIFT                                   (9u)
+#define NANDC_STATUS_DATA_REG_ST                                               (0x00000400u)
+#define NANDC_STATUS_DATA_REG_ST_SHIFT                                         (10u)
+#define NANDC_STATUS_CMD_ID                                                    (0x00FF0000u)
+#define NANDC_STATUS_CMD_ID_SHIFT                                              (16u)
+#define NANDC_STATUS_MASK_STATE_MASK                                           (0x000000FFu)
+#define NANDC_STATUS_MASK_STATE_MASK_SHIFT                                     (0u)
+#define NANDC_STATUS_MASK_ERROR_MASK                                           (0x0000FF00u)
+#define NANDC_STATUS_MASK_ERROR_MASK_SHIFT                                     (8u)
+#define NANDC_INT_MASK_PROT_INT_EN                                             (0x00000001u)
+#define NANDC_INT_MASK_PROT_INT_EN_SHIFT                                       (0u)
+#define NANDC_INT_MASK_CMD_END_INT_EN                                          (0x00000002u)
+#define NANDC_INT_MASK_CMD_END_INT_EN_SHIFT                                    (1u)
+#define NANDC_INT_MASK_DATA_REG_INT_EN                                         (0x00000004u)
+#define NANDC_INT_MASK_DATA_REG_INT_EN_SHIFT                                   (2u)
+#define NANDC_INT_MASK_DMA_INT_EN                                              (0x00000008u)
+#define NANDC_INT_MASK_DMA_INT_EN_SHIFT                                        (3u)
+#define NANDC_INT_MASK_TRANS_ERR_EN                                            (0x00000010u)
+#define NANDC_INT_MASK_TRANS_ERR_EN_SHIFT                                      (4u)
+#define NANDC_INT_MASK_PG_SZ_ERR_INT_EN                                        (0x00000040u)
+#define NANDC_INT_MASK_PG_SZ_ERR_INT_EN_SHIFT                                  (6u)
+#define NANDC_INT_MASK_MEM0_RDY_INT_EN                                         (0x00000100u)
+#define NANDC_INT_MASK_MEM0_RDY_INT_EN_SHIFT                                   (8u)
+#define NANDC_INT_MASK_STAT_ERR_INT0_EN                                        (0x00010000u)
+#define NANDC_INT_MASK_STAT_ERR_INT0_EN_SHIFT                                  (16u)
+#define NANDC_INT_MASK_ECC_INT0_EN                                             (0x01000000u)
+#define NANDC_INT_MASK_ECC_INT0_EN_SHIFT                                       (24u)
+#define NANDC_INT_STATUS_PROT_INT_FL                                           (0x00000001u)
+#define NANDC_INT_STATUS_PROT_INT_FL_SHIFT                                     (0u)
+#define NANDC_INT_STATUS_CMD_END_INT_FL                                        (0x00000002u)
+#define NANDC_INT_STATUS_CMD_END_INT_FL_SHIFT                                  (1u)
+#define NANDC_INT_STATUS_DATA_REG_INT_FL                                       (0x00000004u)
+#define NANDC_INT_STATUS_DATA_REG_INT_FL_SHIFT                                 (2u)
+#define NANDC_INT_STATUS_DMA_INT_FL                                            (0x00000008u)
+#define NANDC_INT_STATUS_DMA_INT_FL_SHIFT                                      (3u)
+#define NANDC_INT_STATUS_TRANS_ERR_FL                                          (0x00000010u)
+#define NANDC_INT_STATUS_TRANS_ERR_FL_SHIFT                                    (4u)
+#define NANDC_INT_STATUS_PG_SZ_ERR_INT_FL                                      (0x00000040u)
+#define NANDC_INT_STATUS_PG_SZ_ERR_INT_FL_SHIFT                                (6u)
+#define NANDC_INT_STATUS_MEM0_RDY_INT_FL                                       (0x00000100u)
+#define NANDC_INT_STATUS_MEM0_RDY_INT_FL_SHIFT                                 (8u)
+#define NANDC_INT_STATUS_STAT_ERR_INT0_FL                                      (0x00010000u)
+#define NANDC_INT_STATUS_STAT_ERR_INT0_FL_SHIFT                                (16u)
+#define NANDC_INT_STATUS_ECC_INT0_FL                                           (0x01000000u)
+#define NANDC_INT_STATUS_ECC_INT0_FL_SHIFT                                     (24u)
+#define NANDC_ECC_CTRL_ECC_CAP                                                 (0x00000007u)
+#define NANDC_ECC_CTRL_ECC_CAP_SHIFT                                           (0u)
+#define NANDC_ECC_CTRL_ERR_THRESHOLD                                           (0x00003F00u)
+#define NANDC_ECC_CTRL_ERR_THRESHOLD_SHIFT                                     (8u)
+#define NANDC_ECC_CTRL_ECC_SEL                                                 (0x00030000u)
+#define NANDC_ECC_CTRL_ECC_SEL_SHIFT                                           (16u)
+#define NANDC_ECC_OFFSET_ECC_OFFSET                                            (0x0000FFFFu)
+#define NANDC_ECC_OFFSET_ECC_OFFSET_SHIFT                                      (0u)
+#define NANDC_ECC_STAT_ECC_ERROR_0                                             (0x00000001u)
+#define NANDC_ECC_STAT_ECC_ERROR_0_SHIFT                                       (0u)
+#define NANDC_ECC_STAT_ECC_UNC_0                                               (0x00000100u)
+#define NANDC_ECC_STAT_ECC_UNC_0_SHIFT                                         (8u)
+#define NANDC_ECC_STAT_ECC_OVER_0                                              (0x00010000u)
+#define NANDC_ECC_STAT_ECC_OVER_0_SHIFT                                        (16u)
+#define NANDC_ADDR0_COL_ADDR0_COL                                              (0x0000FFFFu)
+#define NANDC_ADDR0_COL_ADDR0_COL_SHIFT                                        (0u)
+#define NANDC_ADDR0_ROW_ADDR0_ROW                                              (0x00FFFFFFu)
+#define NANDC_ADDR0_ROW_ADDR0_ROW_SHIFT                                        (0u)
+#define NANDC_ADDR1_COL_ADDR1_COL                                              (0x0000FFFFu)
+#define NANDC_ADDR1_COL_ADDR1_COL_SHIFT                                        (0u)
+#define NANDC_ADDR1_ROW_ADDR1_ROW                                              (0x00FFFFFFu)
+#define NANDC_ADDR1_ROW_ADDR1_ROW_SHIFT                                        (0u)
+#define NANDC_FIFO_DATA_FIFO_DATA                                              (0xFFFFFFFFu)
+#define NANDC_FIFO_DATA_FIFO_DATA_SHIFT                                        (0u)
+#define NANDC_DATA_REG_DATA_REG                                                (0xFFFFFFFFu)
+#define NANDC_DATA_REG_DATA_REG_SHIFT                                          (0u)
+#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE                                      (0x00000003u)
+#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE_SHIFT                                (0u)
+#define NANDC_DEV0_PTR_PTR_ADDR                                                (0x00000FF0u)
+#define NANDC_DEV0_PTR_PTR_ADDR_SHIFT                                          (2u)
+#define NANDC_DMA_ADDR_L_DMA_ADDR_L                                            (0xFFFFFFFFu)
+#define NANDC_DMA_ADDR_L_DMA_ADDR_L_SHIFT                                      (0u)
+#define NANDC_DMA_CNT_CNT_INIT                                                 (0xFFFFFFFFu)
+#define NANDC_DMA_CNT_CNT_INIT_SHIFT                                           (0u)
+#define NANDC_DMA_CTRL_DMA_READY                                               (0x00000001u)
+#define NANDC_DMA_CTRL_DMA_READY_SHIFT                                         (0u)
+#define NANDC_DMA_CTRL_DMA_BURST                                               (0x0000001Cu)
+#define NANDC_DMA_CTRL_DMA_BURST_SHIFT                                         (2u)
+#define NANDC_DMA_CTRL_DMA_MODE                                                (0x00000020u)
+#define NANDC_DMA_CTRL_DMA_MODE_SHIFT                                          (5u)
+#define NANDC_DMA_CTRL_DMA_START                                               (0x00000080u)
+#define NANDC_DMA_CTRL_DMA_START_SHIFT                                         (7u)
+#define NANDC_BBM_CTRL_RMP_INIT                                                (0x00000001u)
+#define NANDC_BBM_CTRL_RMP_INIT_SHIFT                                          (0u)
+#define NANDC_DATA_SIZE_DATA_SIZE                                              (0x00007FFFu)
+#define NANDC_DATA_SIZE_DATA_SIZE_SHIFT                                        (0u)
+#define NANDC_TIMINGS_ASYN_TRWP                                                (0x0000000Fu)
+#define NANDC_TIMINGS_ASYN_TRWP_SHIFT                                          (0u)
+#define NANDC_TIMINGS_ASYN_TRWH                                                (0x000000F0u)
+#define NANDC_TIMINGS_ASYN_TRWH_SHIFT                                          (4u)
+#define NANDC_TIME_SEQ_0_TCCS                                                  (0x0000003Fu)
+#define NANDC_TIME_SEQ_0_TCCS_SHIFT                                            (0u)
+#define NANDC_TIME_SEQ_0_TADL                                                  (0x00003F00u)
+#define NANDC_TIME_SEQ_0_TADL_SHIFT                                            (8u)
+#define NANDC_TIME_SEQ_0_TRHW                                                  (0x003F0000u)
+#define NANDC_TIME_SEQ_0_TRHW_SHIFT                                            (16u)
+#define NANDC_TIME_SEQ_0_TWHR                                                  (0x3F000000u)
+#define NANDC_TIME_SEQ_0_TWHR_SHIFT                                            (24u)
+#define NANDC_TIME_SEQ_1_TWB                                                   (0x0000003Fu)
+#define NANDC_TIME_SEQ_1_TWB_SHIFT                                             (0u)
+#define NANDC_TIME_SEQ_1_TRR                                                   (0x00003F00u)
+#define NANDC_TIME_SEQ_1_TRR_SHIFT                                             (8u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d0                                             (0x0000003Fu)
+#define NANDC_TIME_GEN_SEQ_0_t0_d0_SHIFT                                       (0u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d1                                             (0x00003F00u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d1_SHIFT                                       (8u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d2                                             (0x003F0000u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d2_SHIFT                                       (16u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d3                                             (0x3F000000u)
+#define NANDC_TIME_GEN_SEQ_0_t0_d3_SHIFT                                       (24u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d4                                             (0x0000003Fu)
+#define NANDC_TIME_GEN_SEQ_1_t0_d4_SHIFT                                       (0u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d5                                             (0x00003F00u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d5_SHIFT                                       (8u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d6                                             (0x003F0000u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d6_SHIFT                                       (16u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d7                                             (0x3F000000u)
+#define NANDC_TIME_GEN_SEQ_1_t0_d7_SHIFT                                       (24u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d8                                             (0x0000003Fu)
+#define NANDC_TIME_GEN_SEQ_2_t0_d8_SHIFT                                       (0u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d9                                             (0x00003F00u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d9_SHIFT                                       (8u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d10                                            (0x003F0000u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d10_SHIFT                                      (16u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d11                                            (0x3F000000u)
+#define NANDC_TIME_GEN_SEQ_2_t0_d11_SHIFT                                      (24u)
+#define NANDC_FIFO_INIT_FIFO_INIT                                              (0x00000001u)
+#define NANDC_FIFO_INIT_FIFO_INIT_SHIFT                                        (0u)
+#define NANDC_FIFO_STATE_DF_R_EMPTY                                            (0x00000001u)
+#define NANDC_FIFO_STATE_DF_R_EMPTY_SHIFT                                      (0u)
+#define NANDC_FIFO_STATE_DF_W_FULL                                             (0x00000002u)
+#define NANDC_FIFO_STATE_DF_W_FULL_SHIFT                                       (1u)
+#define NANDC_FIFO_STATE_CF_EMPTY                                              (0x00000004u)
+#define NANDC_FIFO_STATE_CF_EMPTY_SHIFT                                        (2u)
+#define NANDC_FIFO_STATE_CF_FULL                                               (0x00000008u)
+#define NANDC_FIFO_STATE_CF_FULL_SHIFT                                         (3u)
+#define NANDC_FIFO_STATE_CF_ACCPT_R                                            (0x00000010u)
+#define NANDC_FIFO_STATE_CF_ACCPT_R_SHIFT                                      (4u)
+#define NANDC_FIFO_STATE_CF_ACCPT_W                                            (0x00000020u)
+#define NANDC_FIFO_STATE_CF_ACCPT_W_SHIFT                                      (5u)
+#define NANDC_FIFO_STATE_DF_R_FULL                                             (0x00000040u)
+#define NANDC_FIFO_STATE_DF_R_FULL_SHIFT                                       (6u)
+#define NANDC_FIFO_STATE_DF_W_EMPTY                                            (0x00000080u)
+#define NANDC_FIFO_STATE_DF_W_EMPTY_SHIFT                                      (7u)
+#define NANDC_GEN_SEQ_CTRL_CMD0_EN                                             (0x00000001u)
+#define NANDC_GEN_SEQ_CTRL_CMD0_EN_SHIFT                                       (0u)
+#define NANDC_GEN_SEQ_CTRL_CMD1_EN                                             (0x00000002u)
+#define NANDC_GEN_SEQ_CTRL_CMD1_EN_SHIFT                                       (1u)
+#define NANDC_GEN_SEQ_CTRL_CMD2_EN                                             (0x00000004u)
+#define NANDC_GEN_SEQ_CTRL_CMD2_EN_SHIFT                                       (2u)
+#define NANDC_GEN_SEQ_CTRL_CMD3_EN                                             (0x00000008u)
+#define NANDC_GEN_SEQ_CTRL_CMD3_EN_SHIFT                                       (3u)
+#define NANDC_GEN_SEQ_CTRL_COL_A0                                              (0x00000030u)
+#define NANDC_GEN_SEQ_CTRL_COL_A0_SHIFT                                        (4u)
+#define NANDC_GEN_SEQ_CTRL_COL_A1                                              (0x000000C0u)
+#define NANDC_GEN_SEQ_CTRL_COL_A1_SHIFT                                        (6u)
+#define NANDC_GEN_SEQ_CTRL_ROW_A0                                              (0x00000300u)
+#define NANDC_GEN_SEQ_CTRL_ROW_A0_SHIFT                                        (8u)
+#define NANDC_GEN_SEQ_CTRL_ROW_A1                                              (0x00000C00u)
+#define NANDC_GEN_SEQ_CTRL_ROW_A1_SHIFT                                        (10u)
+#define NANDC_GEN_SEQ_CTRL_DATA_EN                                             (0x00001000u)
+#define NANDC_GEN_SEQ_CTRL_DATA_EN_SHIFT                                       (12u)
+#define NANDC_GEN_SEQ_CTRL_DELAY_EN                                            (0x00006000u)
+#define NANDC_GEN_SEQ_CTRL_DELAY_EN_SHIFT                                      (13u)
+#define NANDC_GEN_SEQ_CTRL_IMD_SEQ                                             (0x00008000u)
+#define NANDC_GEN_SEQ_CTRL_IMD_SEQ_SHIFT                                       (15u)
+#define NANDC_GEN_SEQ_CTRL_CMD_3                                               (0x00FF0000u)
+#define NANDC_GEN_SEQ_CTRL_CMD_3_SHIFT                                         (16u)
+#define NANDC_MLUN_MLUN_IDX                                                    (0x00000007u)
+#define NANDC_MLUN_MLUN_IDX_SHIFT                                              (0u)
+#define NANDC_MLUN_LUN_SEL                                                     (0x00000300u)
+#define NANDC_MLUN_LUN_SEL_SHIFT                                               (8u)
+#define NANDC_DEV0_SIZE_DEV_SIZE                                               (0x00000FFFu)
+#define NANDC_DEV0_SIZE_DEV_SIZE_SHIFT                                         (0u)
+#define NANDC_DMA_TRIG_TLVL_DMA_TRIG_TLVL                                      (0x000000FFu)
+#define NANDC_DMA_TRIG_TLVL_DMA_TRIG_TLVL_SHIFT                                (0u)
+#define NANDC_CMD_MARK_CMD_ID                                                  (0x000000FFu)
+#define NANDC_CMD_MARK_CMD_ID_SHIFT                                            (0u)
+#define NANDC_LUN_STATUS0_MEM0_LUN                                             (0x000000FFu)
+#define NANDC_LUN_STATUS0_MEM0_LUN_SHIFT                                       (0u)
+#define NANDC_TIME_GEN_SEQ_3_t0_d12                                            (0x0000003Fu)
+#define NANDC_TIME_GEN_SEQ_3_t0_d12_SHIFT                                      (0u)
+#define NANDC_ECC_CNT_ERR_LVL                                                  (0x0000003Fu)
+#define NANDC_ECC_CNT_ERR_LVL_SHIFT                                            (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/octa_iobitmask.h

@@ -0,0 +1,222 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef OCTA_IOBITMASK_H
+#define OCTA_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define OCTA_DCR_DVCMD0                                                        (0x000000FFu)
+#define OCTA_DCR_DVCMD0_SHIFT                                                  (0u)
+#define OCTA_DCR_DVCMD1                                                        (0x0000FF00u)
+#define OCTA_DCR_DVCMD1_SHIFT                                                  (8u)
+#define OCTA_DAR_DVAD0                                                         (0x000000FFu)
+#define OCTA_DAR_DVAD0_SHIFT                                                   (0u)
+#define OCTA_DAR_DVAD1                                                         (0x0000FF00u)
+#define OCTA_DAR_DVAD1_SHIFT                                                   (8u)
+#define OCTA_DAR_DVAD2                                                         (0x00FF0000u)
+#define OCTA_DAR_DVAD2_SHIFT                                                   (16u)
+#define OCTA_DAR_DVAD3                                                         (0xFF000000u)
+#define OCTA_DAR_DVAD3_SHIFT                                                   (24u)
+#define OCTA_DCSR_DALEN                                                        (0x000000FFu)
+#define OCTA_DCSR_DALEN_SHIFT                                                  (0u)
+#define OCTA_DCSR_DMLEN                                                        (0x0000FF00u)
+#define OCTA_DCSR_DMLEN_SHIFT                                                  (8u)
+#define OCTA_DCSR_ACDV                                                         (0x00080000u)
+#define OCTA_DCSR_ACDV_SHIFT                                                   (19u)
+#define OCTA_DCSR_CMDLEN                                                       (0x00700000u)
+#define OCTA_DCSR_CMDLEN_SHIFT                                                 (20u)
+#define OCTA_DCSR_DAOR                                                         (0x00800000u)
+#define OCTA_DCSR_DAOR_SHIFT                                                   (23u)
+#define OCTA_DCSR_ADLEN                                                        (0x07000000u)
+#define OCTA_DCSR_ADLEN_SHIFT                                                  (24u)
+#define OCTA_DCSR_DOPI                                                         (0x08000000u)
+#define OCTA_DCSR_DOPI_SHIFT                                                   (27u)
+#define OCTA_DCSR_ACDA                                                         (0x10000000u)
+#define OCTA_DCSR_ACDA_SHIFT                                                   (28u)
+#define OCTA_DSR0_DV0SZ                                                        (0x3FFFFFFFu)
+#define OCTA_DSR0_DV0SZ_SHIFT                                                  (0u)
+#define OCTA_DSR0_DV0TYP                                                       (0xC0000000u)
+#define OCTA_DSR0_DV0TYP_SHIFT                                                 (30u)
+#define OCTA_DSR1_DV1SZ                                                        (0x3FFFFFFFu)
+#define OCTA_DSR1_DV1SZ_SHIFT                                                  (0u)
+#define OCTA_DSR1_DV1TYP                                                       (0xC0000000u)
+#define OCTA_DSR1_DV1TYP_SHIFT                                                 (30u)
+#define OCTA_MDTR_DV0DEL                                                       (0x000000FFu)
+#define OCTA_MDTR_DV0DEL_SHIFT                                                 (0u)
+#define OCTA_MDTR_DQSERAM                                                      (0x00000F00u)
+#define OCTA_MDTR_DQSERAM_SHIFT                                                (8u)
+#define OCTA_MDTR_DQSESOPI                                                     (0x0000F000u)
+#define OCTA_MDTR_DQSESOPI_SHIFT                                               (12u)
+#define OCTA_MDTR_DV1DEL                                                       (0x00FF0000u)
+#define OCTA_MDTR_DV1DEL_SHIFT                                                 (16u)
+#define OCTA_MDTR_DQSEDOPI                                                     (0x0F000000u)
+#define OCTA_MDTR_DQSEDOPI_SHIFT                                               (24u)
+#define OCTA_ACTR_CTP                                                          (0xFFFFFFFFu)
+#define OCTA_ACTR_CTP_SHIFT                                                    (0u)
+#define OCTA_ACAR0_CAD0                                                        (0xFFFFFFFFu)
+#define OCTA_ACAR0_CAD0_SHIFT                                                  (0u)
+#define OCTA_ACAR1_CAD1                                                        (0xFFFFFFFFu)
+#define OCTA_ACAR1_CAD1_SHIFT                                                  (0u)
+#define OCTA_DRCSTR_CTRW0                                                      (0x0000007Fu)
+#define OCTA_DRCSTR_CTRW0_SHIFT                                                (0u)
+#define OCTA_DRCSTR_CTR0                                                       (0x00000080u)
+#define OCTA_DRCSTR_CTR0_SHIFT                                                 (7u)
+#define OCTA_DRCSTR_DVRDCMD0                                                   (0x00000700u)
+#define OCTA_DRCSTR_DVRDCMD0_SHIFT                                             (8u)
+#define OCTA_DRCSTR_DVRDHI0                                                    (0x00003800u)
+#define OCTA_DRCSTR_DVRDHI0_SHIFT                                              (11u)
+#define OCTA_DRCSTR_DVRDLO0                                                    (0x0000C000u)
+#define OCTA_DRCSTR_DVRDLO0_SHIFT                                              (14u)
+#define OCTA_DRCSTR_CTRW1                                                      (0x007F0000u)
+#define OCTA_DRCSTR_CTRW1_SHIFT                                                (16u)
+#define OCTA_DRCSTR_CTR1                                                       (0x00800000u)
+#define OCTA_DRCSTR_CTR1_SHIFT                                                 (23u)
+#define OCTA_DRCSTR_DVRDCMD1                                                   (0x07000000u)
+#define OCTA_DRCSTR_DVRDCMD1_SHIFT                                             (24u)
+#define OCTA_DRCSTR_DVRDHI1                                                    (0x38000000u)
+#define OCTA_DRCSTR_DVRDHI1_SHIFT                                              (27u)
+#define OCTA_DRCSTR_DVRDLO1                                                    (0xC0000000u)
+#define OCTA_DRCSTR_DVRDLO1_SHIFT                                              (30u)
+#define OCTA_DWCSTR_DVWCMD0                                                    (0x00000700u)
+#define OCTA_DWCSTR_DVWCMD0_SHIFT                                              (8u)
+#define OCTA_DWCSTR_DVWHI0                                                     (0x00003800u)
+#define OCTA_DWCSTR_DVWHI0_SHIFT                                               (11u)
+#define OCTA_DWCSTR_DVWLO0                                                     (0x0000C000u)
+#define OCTA_DWCSTR_DVWLO0_SHIFT                                               (14u)
+#define OCTA_DWCSTR_DVWCMD1                                                    (0x07000000u)
+#define OCTA_DWCSTR_DVWCMD1_SHIFT                                              (24u)
+#define OCTA_DWCSTR_DVWHI1                                                     (0x38000000u)
+#define OCTA_DWCSTR_DVWHI1_SHIFT                                               (27u)
+#define OCTA_DWCSTR_DVWLO1                                                     (0xC0000000u)
+#define OCTA_DWCSTR_DVWLO1_SHIFT                                               (30u)
+#define OCTA_DCSTR_DVSELCMD                                                    (0x00000700u)
+#define OCTA_DCSTR_DVSELCMD_SHIFT                                              (8u)
+#define OCTA_DCSTR_DVSELHI                                                     (0x00003800u)
+#define OCTA_DCSTR_DVSELHI_SHIFT                                               (11u)
+#define OCTA_DCSTR_DVSELLO                                                     (0x0000C000u)
+#define OCTA_DCSTR_DVSELLO_SHIFT                                               (14u)
+#define OCTA_CDSR_DV0TTYP                                                      (0x00000003u)
+#define OCTA_CDSR_DV0TTYP_SHIFT                                                (0u)
+#define OCTA_CDSR_DV1TTYP                                                      (0x0000000Cu)
+#define OCTA_CDSR_DV1TTYP_SHIFT                                                (2u)
+#define OCTA_CDSR_DV0PC                                                        (0x00000010u)
+#define OCTA_CDSR_DV0PC_SHIFT                                                  (4u)
+#define OCTA_CDSR_DV1PC                                                        (0x00000020u)
+#define OCTA_CDSR_DV1PC_SHIFT                                                  (5u)
+#define OCTA_CDSR_ACMEME                                                       (0x00000C00u)
+#define OCTA_CDSR_ACMEME_SHIFT                                                 (10u)
+#define OCTA_CDSR_ACMODE                                                       (0x00003000u)
+#define OCTA_CDSR_ACMODE_SHIFT                                                 (12u)
+#define OCTA_CDSR_DLFT                                                         (0x80000000u)
+#define OCTA_CDSR_DLFT_SHIFT                                                   (31u)
+#define OCTA_MDLR_DV0RDL                                                       (0x000000FFu)
+#define OCTA_MDLR_DV0RDL_SHIFT                                                 (0u)
+#define OCTA_MDLR_DV0WDL                                                       (0x0000FF00u)
+#define OCTA_MDLR_DV0WDL_SHIFT                                                 (8u)
+#define OCTA_MDLR_DV1RDL                                                       (0x00FF0000u)
+#define OCTA_MDLR_DV1RDL_SHIFT                                                 (16u)
+#define OCTA_MDLR_DV1WDL                                                       (0xFF000000u)
+#define OCTA_MDLR_DV1WDL_SHIFT                                                 (24u)
+#define OCTA_MRWCR0_D0MRCMD0                                                   (0x000000FFu)
+#define OCTA_MRWCR0_D0MRCMD0_SHIFT                                             (0u)
+#define OCTA_MRWCR0_D0MRCMD1                                                   (0x0000FF00u)
+#define OCTA_MRWCR0_D0MRCMD1_SHIFT                                             (8u)
+#define OCTA_MRWCR0_D0MWCMD0                                                   (0x00FF0000u)
+#define OCTA_MRWCR0_D0MWCMD0_SHIFT                                             (16u)
+#define OCTA_MRWCR0_D0MWCMD1                                                   (0xFF000000u)
+#define OCTA_MRWCR0_D0MWCMD1_SHIFT                                             (24u)
+#define OCTA_MRWCR1_D1MRCMD0                                                   (0x000000FFu)
+#define OCTA_MRWCR1_D1MRCMD0_SHIFT                                             (0u)
+#define OCTA_MRWCR1_D1MRCMD1                                                   (0x0000FF00u)
+#define OCTA_MRWCR1_D1MRCMD1_SHIFT                                             (8u)
+#define OCTA_MRWCR1_D1MWCMD0                                                   (0x00FF0000u)
+#define OCTA_MRWCR1_D1MWCMD0_SHIFT                                             (16u)
+#define OCTA_MRWCR1_D1MWCMD1                                                   (0xFF000000u)
+#define OCTA_MRWCR1_D1MWCMD1_SHIFT                                             (24u)
+#define OCTA_MRWCSR_MRAL0                                                      (0x00000007u)
+#define OCTA_MRWCSR_MRAL0_SHIFT                                                (0u)
+#define OCTA_MRWCSR_MRCL0                                                      (0x00000038u)
+#define OCTA_MRWCSR_MRCL0_SHIFT                                                (3u)
+#define OCTA_MRWCSR_MRO0                                                       (0x00000040u)
+#define OCTA_MRWCSR_MRO0_SHIFT                                                 (6u)
+#define OCTA_MRWCSR_MWAL0                                                      (0x00000700u)
+#define OCTA_MRWCSR_MWAL0_SHIFT                                                (8u)
+#define OCTA_MRWCSR_MWCL0                                                      (0x00003800u)
+#define OCTA_MRWCSR_MWCL0_SHIFT                                                (11u)
+#define OCTA_MRWCSR_MWO0                                                       (0x00004000u)
+#define OCTA_MRWCSR_MWO0_SHIFT                                                 (14u)
+#define OCTA_MRWCSR_MRAL1                                                      (0x00070000u)
+#define OCTA_MRWCSR_MRAL1_SHIFT                                                (16u)
+#define OCTA_MRWCSR_MRCL1                                                      (0x00380000u)
+#define OCTA_MRWCSR_MRCL1_SHIFT                                                (19u)
+#define OCTA_MRWCSR_MRO1                                                       (0x00400000u)
+#define OCTA_MRWCSR_MRO1_SHIFT                                                 (22u)
+#define OCTA_MRWCSR_MWAL1                                                      (0x07000000u)
+#define OCTA_MRWCSR_MWAL1_SHIFT                                                (24u)
+#define OCTA_MRWCSR_MWCL1                                                      (0x38000000u)
+#define OCTA_MRWCSR_MWCL1_SHIFT                                                (27u)
+#define OCTA_MRWCSR_MWO1                                                       (0x40000000u)
+#define OCTA_MRWCSR_MWO1_SHIFT                                                 (30u)
+#define OCTA_ESR_MRESR                                                         (0x000000FFu)
+#define OCTA_ESR_MRESR_SHIFT                                                   (0u)
+#define OCTA_ESR_MWESR                                                         (0x0000FF00u)
+#define OCTA_ESR_MWESR_SHIFT                                                   (8u)
+#define OCTA_CWDR_WD0                                                          (0x000000FFu)
+#define OCTA_CWDR_WD0_SHIFT                                                    (0u)
+#define OCTA_CWDR_WD1                                                          (0x0000FF00u)
+#define OCTA_CWDR_WD1_SHIFT                                                    (8u)
+#define OCTA_CWDR_WD2                                                          (0x00FF0000u)
+#define OCTA_CWDR_WD2_SHIFT                                                    (16u)
+#define OCTA_CWDR_WD3                                                          (0xFF000000u)
+#define OCTA_CWDR_WD3_SHIFT                                                    (24u)
+#define OCTA_CRR_RD0                                                           (0x000000FFu)
+#define OCTA_CRR_RD0_SHIFT                                                     (0u)
+#define OCTA_CRR_RD1                                                           (0x0000FF00u)
+#define OCTA_CRR_RD1_SHIFT                                                     (8u)
+#define OCTA_CRR_RD2                                                           (0x00FF0000u)
+#define OCTA_CRR_RD2_SHIFT                                                     (16u)
+#define OCTA_CRR_RD3                                                           (0xFF000000u)
+#define OCTA_CRR_RD3_SHIFT                                                     (24u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ostm_iobitmask.h

@@ -0,0 +1,64 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef OSTM_IOBITMASK_H
+#define OSTM_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define OSTM_OSTMnCMP_OSTMnCMP                                                 (0xFFFFFFFFu)
+#define OSTM_OSTMnCMP_OSTMnCMP_SHIFT                                           (0u)
+#define OSTM_OSTMnCNT_OSTMnCNT                                                 (0xFFFFFFFFu)
+#define OSTM_OSTMnCNT_OSTMnCNT_SHIFT                                           (0u)
+#define OSTM_OSTMnTE_OSTMnTE                                                   (0x01u)
+#define OSTM_OSTMnTE_OSTMnTE_SHIFT                                             (0u)
+#define OSTM_OSTMnTS_OSTMnTS                                                   (0x01u)
+#define OSTM_OSTMnTS_OSTMnTS_SHIFT                                             (0u)
+#define OSTM_OSTMnTT_OSTMnTT                                                   (0x01u)
+#define OSTM_OSTMnTT_OSTMnTT_SHIFT                                             (0u)
+#define OSTM_OSTMnCTL_OSTMnMD0                                                 (0x01u)
+#define OSTM_OSTMnCTL_OSTMnMD0_SHIFT                                           (0u)
+#define OSTM_OSTMnCTL_OSTMnMD1                                                 (0x02u)
+#define OSTM_OSTMnCTL_OSTMnMD1_SHIFT                                           (1u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pl310_iobitmask.h

@@ -0,0 +1,318 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef PL310_IOBITMASK_H
+#define PL310_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define PL310_REG0_CACHE_ID_RTLrelease                                         (0x0000003Fu)
+#define PL310_REG0_CACHE_ID_RTLrelease_SHIFT                                   (0u)
+#define PL310_REG0_CACHE_ID_Partnumber                                         (0x000003C0u)
+#define PL310_REG0_CACHE_ID_Partnumber_SHIFT                                   (6u)
+#define PL310_REG0_CACHE_ID_CACHEID                                            (0x0000FC00u)
+#define PL310_REG0_CACHE_ID_CACHEID_SHIFT                                      (10u)
+#define PL310_REG0_CACHE_ID_Implementer                                        (0xFF000000u)
+#define PL310_REG0_CACHE_ID_Implementer_SHIFT                                  (24u)
+#define PL310_REG0_CACHE_TYPE_L2cachelinelength1                               (0x00000003u)
+#define PL310_REG0_CACHE_TYPE_L2cachelinelength1_SHIFT                         (0u)
+#define PL310_REG0_CACHE_TYPE_L2associativity1                                 (0x00000040u)
+#define PL310_REG0_CACHE_TYPE_L2associativity1_SHIFT                           (6u)
+#define PL310_REG0_CACHE_TYPE_Isize                                            (0x00000F80u)
+#define PL310_REG0_CACHE_TYPE_Isize_SHIFT                                      (7u)
+#define PL310_REG0_CACHE_TYPE_L2cachelinelength0                               (0x00003000u)
+#define PL310_REG0_CACHE_TYPE_L2cachelinelength0_SHIFT                         (12u)
+#define PL310_REG0_CACHE_TYPE_L2associativity0                                 (0x00040000u)
+#define PL310_REG0_CACHE_TYPE_L2associativity0_SHIFT                           (18u)
+#define PL310_REG0_CACHE_TYPE_Dsize                                            (0x00F80000u)
+#define PL310_REG0_CACHE_TYPE_Dsize_SHIFT                                      (19u)
+#define PL310_REG0_CACHE_TYPE_H                                                (0x01000000u)
+#define PL310_REG0_CACHE_TYPE_H_SHIFT                                          (24u)
+#define PL310_REG0_CACHE_TYPE_ctype                                            (0x1E000000u)
+#define PL310_REG0_CACHE_TYPE_ctype_SHIFT                                      (25u)
+#define PL310_REG0_CACHE_TYPE_Databanking                                      (0x80000000u)
+#define PL310_REG0_CACHE_TYPE_Databanking_SHIFT                                (31u)
+#define PL310_REG1_CONTROL_L2Cacheenable                                       (0x00000001u)
+#define PL310_REG1_CONTROL_L2Cacheenable_SHIFT                                 (0u)
+#define PL310_REG1_AUX_CONTROL_FullLineofZeroEnable                            (0x00000001u)
+#define PL310_REG1_AUX_CONTROL_FullLineofZeroEnable_SHIFT                      (0u)
+#define PL310_REG1_AUX_CONTROL_HighPriorityforSOandDevReadsEnable              (0x00000400u)
+#define PL310_REG1_AUX_CONTROL_HighPriorityforSOandDevReadsEnable_SHIFT        (10u)
+#define PL310_REG1_AUX_CONTROL_StorebufferdevicelimitationEnable               (0x00000800u)
+#define PL310_REG1_AUX_CONTROL_StorebufferdevicelimitationEnable_SHIFT         (11u)
+#define PL310_REG1_AUX_CONTROL_Exclusivecacheconfiguration                     (0x00001000u)
+#define PL310_REG1_AUX_CONTROL_Exclusivecacheconfiguration_SHIFT               (12u)
+#define PL310_REG1_AUX_CONTROL_SharedAttributeInvalidateEnable                 (0x00002000u)
+#define PL310_REG1_AUX_CONTROL_SharedAttributeInvalidateEnable_SHIFT           (13u)
+#define PL310_REG1_AUX_CONTROL_Associativity                                   (0x00010000u)
+#define PL310_REG1_AUX_CONTROL_Associativity_SHIFT                             (16u)
+#define PL310_REG1_AUX_CONTROL_Waysize                                         (0x000E0000u)
+#define PL310_REG1_AUX_CONTROL_Waysize_SHIFT                                   (17u)
+#define PL310_REG1_AUX_CONTROL_Eventmonitorbusenable                           (0x00100000u)
+#define PL310_REG1_AUX_CONTROL_Eventmonitorbusenable_SHIFT                     (20u)
+#define PL310_REG1_AUX_CONTROL_Parityenable                                    (0x00200000u)
+#define PL310_REG1_AUX_CONTROL_Parityenable_SHIFT                              (21u)
+#define PL310_REG1_AUX_CONTROL_Sharedattributeoverrideenable                   (0x00400000u)
+#define PL310_REG1_AUX_CONTROL_Sharedattributeoverrideenable_SHIFT             (22u)
+#define PL310_REG1_AUX_CONTROL_Forcewriteallocate                              (0x01800000u)
+#define PL310_REG1_AUX_CONTROL_Forcewriteallocate_SHIFT                        (23u)
+#define PL310_REG1_AUX_CONTROL_Cachereplacementpolicy                          (0x02000000u)
+#define PL310_REG1_AUX_CONTROL_Cachereplacementpolicy_SHIFT                    (25u)
+#define PL310_REG1_AUX_CONTROL_Nonsecurelockdownenable                         (0x04000000u)
+#define PL310_REG1_AUX_CONTROL_Nonsecurelockdownenable_SHIFT                   (26u)
+#define PL310_REG1_AUX_CONTROL_Nonsecureinterruptaccesscontrol                 (0x08000000u)
+#define PL310_REG1_AUX_CONTROL_Nonsecureinterruptaccesscontrol_SHIFT           (27u)
+#define PL310_REG1_AUX_CONTROL_Dataprefetchenable                              (0x10000000u)
+#define PL310_REG1_AUX_CONTROL_Dataprefetchenable_SHIFT                        (28u)
+#define PL310_REG1_AUX_CONTROL_Instructionprefetchenable                       (0x20000000u)
+#define PL310_REG1_AUX_CONTROL_Instructionprefetchenable_SHIFT                 (29u)
+#define PL310_REG1_AUX_CONTROL_EarlyBRESPenable                                (0x40000000u)
+#define PL310_REG1_AUX_CONTROL_EarlyBRESPenable_SHIFT                          (30u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMsetuplatency                             (0x00000007u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMsetuplatency_SHIFT                       (0u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMreadaccesslatency                        (0x00000070u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMreadaccesslatency_SHIFT                  (4u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMwriteaccesslatency                       (0x00000700u)
+#define PL310_REG1_TAG_RAM_CONTROL_RAMwriteaccesslatency_SHIFT                 (8u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMsetuplatency                            (0x00000007u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMsetuplatency_SHIFT                      (0u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMreadaccesslatency                       (0x00000070u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMreadaccesslatency_SHIFT                 (4u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMwriteaccesslatency                      (0x00000700u)
+#define PL310_REG1_DATA_RAM_CONTROL_RAMwriteaccesslatency_SHIFT                (8u)
+#define PL310_REG2_EV_COUNTER_CTRL_Eventcounterenable                          (0x00000001u)
+#define PL310_REG2_EV_COUNTER_CTRL_Eventcounterenable_SHIFT                    (0u)
+#define PL310_REG2_EV_COUNTER_CTRL_Counterreset                                (0x00000006u)
+#define PL310_REG2_EV_COUNTER_CTRL_Counterreset_SHIFT                          (1u)
+#define PL310_REG2_EV_COUNTER1_CFG_Eventcounterinterruptgeneration             (0x00000003u)
+#define PL310_REG2_EV_COUNTER1_CFG_Eventcounterinterruptgeneration_SHIFT       (0u)
+#define PL310_REG2_EV_COUNTER1_CFG_Countereventsource                          (0x0000003Cu)
+#define PL310_REG2_EV_COUNTER1_CFG_Countereventsource_SHIFT                    (2u)
+#define PL310_REG2_EV_COUNTER0_CFG_Eventcounterinterruptgeneration             (0x00000003u)
+#define PL310_REG2_EV_COUNTER0_CFG_Eventcounterinterruptgeneration_SHIFT       (0u)
+#define PL310_REG2_EV_COUNTER0_CFG_Countereventsource                          (0x0000003Cu)
+#define PL310_REG2_EV_COUNTER0_CFG_Countereventsource_SHIFT                    (2u)
+#define PL310_REG2_EV_COUNTER1_Countervalue                                    (0xFFFFFFFFu)
+#define PL310_REG2_EV_COUNTER1_Countervalue_SHIFT                              (0u)
+#define PL310_REG2_EV_COUNTER0_Countervalue                                    (0xFFFFFFFFu)
+#define PL310_REG2_EV_COUNTER0_Countervalue_SHIFT                              (0u)
+#define PL310_REG2_INT_MASK_ECNTR                                              (0x00000001u)
+#define PL310_REG2_INT_MASK_ECNTR_SHIFT                                        (0u)
+#define PL310_REG2_INT_MASK_PARRT                                              (0x00000002u)
+#define PL310_REG2_INT_MASK_PARRT_SHIFT                                        (1u)
+#define PL310_REG2_INT_MASK_PARRD                                              (0x00000004u)
+#define PL310_REG2_INT_MASK_PARRD_SHIFT                                        (2u)
+#define PL310_REG2_INT_MASK_ERRWT                                              (0x00000008u)
+#define PL310_REG2_INT_MASK_ERRWT_SHIFT                                        (3u)
+#define PL310_REG2_INT_MASK_ERRWD                                              (0x00000010u)
+#define PL310_REG2_INT_MASK_ERRWD_SHIFT                                        (4u)
+#define PL310_REG2_INT_MASK_ERRRT                                              (0x00000020u)
+#define PL310_REG2_INT_MASK_ERRRT_SHIFT                                        (5u)
+#define PL310_REG2_INT_MASK_ERRRD                                              (0x00000040u)
+#define PL310_REG2_INT_MASK_ERRRD_SHIFT                                        (6u)
+#define PL310_REG2_INT_MASK_SLVERR                                             (0x00000080u)
+#define PL310_REG2_INT_MASK_SLVERR_SHIFT                                       (7u)
+#define PL310_REG2_INT_MASK_DECERR                                             (0x00000100u)
+#define PL310_REG2_INT_MASK_DECERR_SHIFT                                       (8u)
+#define PL310_REG2_INT_MASK_STATUS_ECNTR                                       (0x00000001u)
+#define PL310_REG2_INT_MASK_STATUS_ECNTR_SHIFT                                 (0u)
+#define PL310_REG2_INT_MASK_STATUS_PARRT                                       (0x00000002u)
+#define PL310_REG2_INT_MASK_STATUS_PARRT_SHIFT                                 (1u)
+#define PL310_REG2_INT_MASK_STATUS_PARRD                                       (0x00000004u)
+#define PL310_REG2_INT_MASK_STATUS_PARRD_SHIFT                                 (2u)
+#define PL310_REG2_INT_MASK_STATUS_ERRWT                                       (0x00000008u)
+#define PL310_REG2_INT_MASK_STATUS_ERRWT_SHIFT                                 (3u)
+#define PL310_REG2_INT_MASK_STATUS_ERRWD                                       (0x00000010u)
+#define PL310_REG2_INT_MASK_STATUS_ERRWD_SHIFT                                 (4u)
+#define PL310_REG2_INT_MASK_STATUS_ERRRT                                       (0x00000020u)
+#define PL310_REG2_INT_MASK_STATUS_ERRRT_SHIFT                                 (5u)
+#define PL310_REG2_INT_MASK_STATUS_ERRRD                                       (0x00000040u)
+#define PL310_REG2_INT_MASK_STATUS_ERRRD_SHIFT                                 (6u)
+#define PL310_REG2_INT_MASK_STATUS_SLVERR                                      (0x00000080u)
+#define PL310_REG2_INT_MASK_STATUS_SLVERR_SHIFT                                (7u)
+#define PL310_REG2_INT_MASK_STATUS_DECERR                                      (0x00000100u)
+#define PL310_REG2_INT_MASK_STATUS_DECERR_SHIFT                                (8u)
+#define PL310_REG2_INT_RAW_STATUS_ECNTR                                        (0x00000001u)
+#define PL310_REG2_INT_RAW_STATUS_ECNTR_SHIFT                                  (0u)
+#define PL310_REG2_INT_RAW_STATUS_PARRT                                        (0x00000002u)
+#define PL310_REG2_INT_RAW_STATUS_PARRT_SHIFT                                  (1u)
+#define PL310_REG2_INT_RAW_STATUS_PARRD                                        (0x00000004u)
+#define PL310_REG2_INT_RAW_STATUS_PARRD_SHIFT                                  (2u)
+#define PL310_REG2_INT_RAW_STATUS_ERRWT                                        (0x00000008u)
+#define PL310_REG2_INT_RAW_STATUS_ERRWT_SHIFT                                  (3u)
+#define PL310_REG2_INT_RAW_STATUS_ERRWD                                        (0x00000010u)
+#define PL310_REG2_INT_RAW_STATUS_ERRWD_SHIFT                                  (4u)
+#define PL310_REG2_INT_RAW_STATUS_ERRRT                                        (0x00000020u)
+#define PL310_REG2_INT_RAW_STATUS_ERRRT_SHIFT                                  (5u)
+#define PL310_REG2_INT_RAW_STATUS_ERRRD                                        (0x00000040u)
+#define PL310_REG2_INT_RAW_STATUS_ERRRD_SHIFT                                  (6u)
+#define PL310_REG2_INT_RAW_STATUS_SLVERR                                       (0x00000080u)
+#define PL310_REG2_INT_RAW_STATUS_SLVERR_SHIFT                                 (7u)
+#define PL310_REG2_INT_RAW_STATUS_DECERR                                       (0x00000100u)
+#define PL310_REG2_INT_RAW_STATUS_DECERR_SHIFT                                 (8u)
+#define PL310_REG2_INT_CLEAR_ECNTR                                             (0x00000001u)
+#define PL310_REG2_INT_CLEAR_ECNTR_SHIFT                                       (0u)
+#define PL310_REG2_INT_CLEAR_PARRT                                             (0x00000002u)
+#define PL310_REG2_INT_CLEAR_PARRT_SHIFT                                       (1u)
+#define PL310_REG2_INT_CLEAR_PARRD                                             (0x00000004u)
+#define PL310_REG2_INT_CLEAR_PARRD_SHIFT                                       (2u)
+#define PL310_REG2_INT_CLEAR_ERRWT                                             (0x00000008u)
+#define PL310_REG2_INT_CLEAR_ERRWT_SHIFT                                       (3u)
+#define PL310_REG2_INT_CLEAR_ERRWD                                             (0x00000010u)
+#define PL310_REG2_INT_CLEAR_ERRWD_SHIFT                                       (4u)
+#define PL310_REG2_INT_CLEAR_ERRRT                                             (0x00000020u)
+#define PL310_REG2_INT_CLEAR_ERRRT_SHIFT                                       (5u)
+#define PL310_REG2_INT_CLEAR_ERRRD                                             (0x00000040u)
+#define PL310_REG2_INT_CLEAR_ERRRD_SHIFT                                       (6u)
+#define PL310_REG2_INT_CLEAR_SLVERR                                            (0x00000080u)
+#define PL310_REG2_INT_CLEAR_SLVERR_SHIFT                                      (7u)
+#define PL310_REG2_INT_CLEAR_DECERR                                            (0x00000100u)
+#define PL310_REG2_INT_CLEAR_DECERR_SHIFT                                      (8u)
+#define PL310_REG7_CACHE_SYNC_C                                                (0x00000001u)
+#define PL310_REG7_CACHE_SYNC_C_SHIFT                                          (0u)
+#define PL310_REG7_INV_PA_C                                                    (0x00000001u)
+#define PL310_REG7_INV_PA_C_SHIFT                                              (0u)
+#define PL310_REG7_INV_PA_INDEX                                                (0x00003FE0u)
+#define PL310_REG7_INV_PA_INDEX_SHIFT                                          (5u)
+#define PL310_REG7_INV_PA_TAG                                                  (0xFFFFC000u)
+#define PL310_REG7_INV_PA_TAG_SHIFT                                            (14u)
+#define PL310_REG7_INV_WAY_Way_bits                                            (0x000000FFu)
+#define PL310_REG7_INV_WAY_Way_bits_SHIFT                                      (0u)
+#define PL310_REG7_CLEAN_PA_C                                                  (0x00000001u)
+#define PL310_REG7_CLEAN_PA_C_SHIFT                                            (0u)
+#define PL310_REG7_CLEAN_PA_INDEX                                              (0x00003FE0u)
+#define PL310_REG7_CLEAN_PA_INDEX_SHIFT                                        (5u)
+#define PL310_REG7_CLEAN_PA_TAG                                                (0xFFFFC000u)
+#define PL310_REG7_CLEAN_PA_TAG_SHIFT                                          (14u)
+#define PL310_REG7_CLEAN_INDEX_C                                               (0x00000001u)
+#define PL310_REG7_CLEAN_INDEX_C_SHIFT                                         (0u)
+#define PL310_REG7_CLEAN_INDEX_INDEX                                           (0x00003FE0u)
+#define PL310_REG7_CLEAN_INDEX_INDEX_SHIFT                                     (5u)
+#define PL310_REG7_CLEAN_INDEX_Way                                             (0x70000000u)
+#define PL310_REG7_CLEAN_INDEX_Way_SHIFT                                       (28u)
+#define PL310_REG7_CLEAN_WAY_Way_bits                                          (0x000000FFu)
+#define PL310_REG7_CLEAN_WAY_Way_bits_SHIFT                                    (0u)
+#define PL310_REG7_CLEAN_INV_PA_C                                              (0x00000001u)
+#define PL310_REG7_CLEAN_INV_PA_C_SHIFT                                        (0u)
+#define PL310_REG7_CLEAN_INV_PA_INDEX                                          (0x00003FE0u)
+#define PL310_REG7_CLEAN_INV_PA_INDEX_SHIFT                                    (5u)
+#define PL310_REG7_CLEAN_INV_PA_TAG                                            (0xFFFFC000u)
+#define PL310_REG7_CLEAN_INV_PA_TAG_SHIFT                                      (14u)
+#define PL310_REG7_CLEAN_INV_INDEX_C                                           (0x00000001u)
+#define PL310_REG7_CLEAN_INV_INDEX_C_SHIFT                                     (0u)
+#define PL310_REG7_CLEAN_INV_INDEX_INDEX                                       (0x00003FE0u)
+#define PL310_REG7_CLEAN_INV_INDEX_INDEX_SHIFT                                 (5u)
+#define PL310_REG7_CLEAN_INV_INDEX_Way                                         (0x70000000u)
+#define PL310_REG7_CLEAN_INV_INDEX_Way_SHIFT                                   (28u)
+#define PL310_REG7_CLEAN_INV_WAY_Way_bits                                      (0x000000FFu)
+#define PL310_REG7_CLEAN_INV_WAY_Way_bits_SHIFT                                (0u)
+#define PL310_REG9_D_LOCKDOWN0_DATALOCK000                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN0_DATALOCK000_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN0_INSTRLOCK000                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN0_INSTRLOCK000_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN1_DATALOCK001                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN1_DATALOCK001_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN1_INSTRLOCK001                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN1_INSTRLOCK001_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN2_DATALOCK002                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN2_DATALOCK002_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN2_INSTRLOCK002                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN2_INSTRLOCK002_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN3_DATALOCK003                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN3_DATALOCK003_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN3_INSTRLOCK003                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN3_INSTRLOCK003_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN4_DATALOCK004                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN4_DATALOCK004_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN4_INSTRLOCK004                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN4_INSTRLOCK004_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN5_DATALOCK005                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN5_DATALOCK005_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN5_INSTRLOCK005                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN5_INSTRLOCK005_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN6_DATALOCK006                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN6_DATALOCK006_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN6_INSTRLOCK006                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN6_INSTRLOCK006_SHIFT                              (0u)
+#define PL310_REG9_D_LOCKDOWN7_DATALOCK007                                     (0x000000FFu)
+#define PL310_REG9_D_LOCKDOWN7_DATALOCK007_SHIFT                               (0u)
+#define PL310_REG9_I_LOCKDOWN7_INSTRLOCK007                                    (0x000000FFu)
+#define PL310_REG9_I_LOCKDOWN7_INSTRLOCK007_SHIFT                              (0u)
+#define PL310_REG9_LOCK_LINE_EN_lockdown_by_line_enable                        (0x00000001u)
+#define PL310_REG9_LOCK_LINE_EN_lockdown_by_line_enable_SHIFT                  (0u)
+#define PL310_REG9_UNLOCK_WAY_unlock_all_lines_by_way_operation                (0x000000FFu)
+#define PL310_REG9_UNLOCK_WAY_unlock_all_lines_by_way_operation_SHIFT          (0u)
+#define PL310_REG12_ADDR_FILTERING_START_address_filtering_enable              (0x00000001u)
+#define PL310_REG12_ADDR_FILTERING_START_address_filtering_enable_SHIFT        (0u)
+#define PL310_REG12_ADDR_FILTERING_START_address_filtering_start               (0xFFF00000u)
+#define PL310_REG12_ADDR_FILTERING_START_address_filtering_start_SHIFT         (20u)
+#define PL310_REG12_ADDR_FILTERING_END_address_filtering_end                   (0xFFF00000u)
+#define PL310_REG12_ADDR_FILTERING_END_address_filtering_end_SHIFT             (20u)
+#define PL310_REG15_DEBUG_CTRL_DCL                                             (0x00000001u)
+#define PL310_REG15_DEBUG_CTRL_DCL_SHIFT                                       (0u)
+#define PL310_REG15_DEBUG_CTRL_DWB                                             (0x00000002u)
+#define PL310_REG15_DEBUG_CTRL_DWB_SHIFT                                       (1u)
+#define PL310_REG15_DEBUG_CTRL_SPNIDEN                                         (0x00000004u)
+#define PL310_REG15_DEBUG_CTRL_SPNIDEN_SHIFT                                   (2u)
+#define PL310_REG15_PREFETCH_CTRL_Prefetchoffset                               (0x0000001Fu)
+#define PL310_REG15_PREFETCH_CTRL_Prefetchoffset_SHIFT                         (0u)
+#define PL310_REG15_PREFETCH_CTRL_NotsameIDonexclusivesequenceenable           (0x00200000u)
+#define PL310_REG15_PREFETCH_CTRL_NotsameIDonexclusivesequenceenable_SHIFT     (21u)
+#define PL310_REG15_PREFETCH_CTRL_IncrdoubleLinefillenable                     (0x00800000u)
+#define PL310_REG15_PREFETCH_CTRL_IncrdoubleLinefillenable_SHIFT               (23u)
+#define PL310_REG15_PREFETCH_CTRL_Prefetchdropenable                           (0x01000000u)
+#define PL310_REG15_PREFETCH_CTRL_Prefetchdropenable_SHIFT                     (24u)
+#define PL310_REG15_PREFETCH_CTRL_DoublelinefillonWRAPreaddisable              (0x08000000u)
+#define PL310_REG15_PREFETCH_CTRL_DoublelinefillonWRAPreaddisable_SHIFT        (27u)
+#define PL310_REG15_PREFETCH_CTRL_Dataprefetchenable                           (0x10000000u)
+#define PL310_REG15_PREFETCH_CTRL_Dataprefetchenable_SHIFT                     (28u)
+#define PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable                    (0x20000000u)
+#define PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable_SHIFT              (29u)
+#define PL310_REG15_PREFETCH_CTRL_Doublelinefillenable                         (0x40000000u)
+#define PL310_REG15_PREFETCH_CTRL_Doublelinefillenable_SHIFT                   (30u)
+#define PL310_REG15_POWER_CTRL_standby_mode_en                                 (0x00000001u)
+#define PL310_REG15_POWER_CTRL_standby_mode_en_SHIFT                           (0u)
+#define PL310_REG15_POWER_CTRL_dynamic_clk_gating_en                           (0x00000002u)
+#define PL310_REG15_POWER_CTRL_dynamic_clk_gating_en_SHIFT                     (1u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pmg_iobitmask.h

@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef PMG_IOBITMASK_H
+#define PMG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define PMG_RRAMKP_RRAMKP0                                                     (0x01u)
+#define PMG_RRAMKP_RRAMKP0_SHIFT                                               (0u)
+#define PMG_RRAMKP_RRAMKP1                                                     (0x02u)
+#define PMG_RRAMKP_RRAMKP1_SHIFT                                               (1u)
+#define PMG_RRAMKP_RRAMKP2                                                     (0x04u)
+#define PMG_RRAMKP_RRAMKP2_SHIFT                                               (2u)
+#define PMG_RRAMKP_RRAMKP3                                                     (0x08u)
+#define PMG_RRAMKP_RRAMKP3_SHIFT                                               (3u)
+#define PMG_DSCTR_RAMBOOT                                                      (0x40u)
+#define PMG_DSCTR_RAMBOOT_SHIFT                                                (6u)
+#define PMG_DSCTR_EBUSKEEPE                                                    (0x80u)
+#define PMG_DSCTR_EBUSKEEPE_SHIFT                                              (7u)
+#define PMG_DSSSR_P3_1                                                         (0x0001u)
+#define PMG_DSSSR_P3_1_SHIFT                                                   (0u)
+#define PMG_DSSSR_P3_3                                                         (0x0002u)
+#define PMG_DSSSR_P3_3_SHIFT                                                   (1u)
+#define PMG_DSSSR_P6_2                                                         (0x0004u)
+#define PMG_DSSSR_P6_2_SHIFT                                                   (2u)
+#define PMG_DSSSR_PE_1                                                         (0x0008u)
+#define PMG_DSSSR_PE_1_SHIFT                                                   (3u)
+#define PMG_DSSSR_PH_1                                                         (0x0010u)
+#define PMG_DSSSR_PH_1_SHIFT                                                   (4u)
+#define PMG_DSSSR_PG_2                                                         (0x0020u)
+#define PMG_DSSSR_PG_2_SHIFT                                                   (5u)
+#define PMG_DSSSR_RTCAR0                                                       (0x0040u)
+#define PMG_DSSSR_RTCAR0_SHIFT                                                 (6u)
+#define PMG_DSSSR_RTCAR1                                                       (0x0080u)
+#define PMG_DSSSR_RTCAR1_SHIFT                                                 (7u)
+#define PMG_DSSSR_NMI                                                          (0x0100u)
+#define PMG_DSSSR_NMI_SHIFT                                                    (8u)
+#define PMG_DSSSR_PG_6                                                         (0x0200u)
+#define PMG_DSSSR_PG_6_SHIFT                                                   (9u)
+#define PMG_DSSSR_PH_0                                                         (0x0400u)
+#define PMG_DSSSR_PH_0_SHIFT                                                   (10u)
+#define PMG_DSSSR_PJ_1                                                         (0x0800u)
+#define PMG_DSSSR_PJ_1_SHIFT                                                   (11u)
+#define PMG_DSSSR_PJ_5                                                         (0x1000u)
+#define PMG_DSSSR_PJ_5_SHIFT                                                   (12u)
+#define PMG_DSSSR_PK_2                                                         (0x2000u)
+#define PMG_DSSSR_PK_2_SHIFT                                                   (13u)
+#define PMG_DSSSR_PK_4                                                         (0x4000u)
+#define PMG_DSSSR_PK_4_SHIFT                                                   (14u)
+#define PMG_DSESR_P3_1E                                                        (0x0001u)
+#define PMG_DSESR_P3_1E_SHIFT                                                  (0u)
+#define PMG_DSESR_P3_3E                                                        (0x0002u)
+#define PMG_DSESR_P3_3E_SHIFT                                                  (1u)
+#define PMG_DSESR_P6_2E                                                        (0x0004u)
+#define PMG_DSESR_P6_2E_SHIFT                                                  (2u)
+#define PMG_DSESR_PE_1E                                                        (0x0008u)
+#define PMG_DSESR_PE_1E_SHIFT                                                  (3u)
+#define PMG_DSESR_PH_1E                                                        (0x0010u)
+#define PMG_DSESR_PH_1E_SHIFT                                                  (4u)
+#define PMG_DSESR_PG_2E                                                        (0x0020u)
+#define PMG_DSESR_PG_2E_SHIFT                                                  (5u)
+#define PMG_DSESR_NMIE                                                         (0x0100u)
+#define PMG_DSESR_NMIE_SHIFT                                                   (8u)
+#define PMG_DSESR_PG_6E                                                        (0x0200u)
+#define PMG_DSESR_PG_6E_SHIFT                                                  (9u)
+#define PMG_DSESR_PH_0E                                                        (0x0400u)
+#define PMG_DSESR_PH_0E_SHIFT                                                  (10u)
+#define PMG_DSESR_PJ_1E                                                        (0x0800u)
+#define PMG_DSESR_PJ_1E_SHIFT                                                  (11u)
+#define PMG_DSESR_PJ_5E                                                        (0x1000u)
+#define PMG_DSESR_PJ_5E_SHIFT                                                  (12u)
+#define PMG_DSESR_PK_2E                                                        (0x2000u)
+#define PMG_DSESR_PK_2E_SHIFT                                                  (13u)
+#define PMG_DSESR_PK_4E                                                        (0x4000u)
+#define PMG_DSESR_PK_4E_SHIFT                                                  (14u)
+#define PMG_DSFR_P3_1F                                                         (0x0001u)
+#define PMG_DSFR_P3_1F_SHIFT                                                   (0u)
+#define PMG_DSFR_P3_3F                                                         (0x0002u)
+#define PMG_DSFR_P3_3F_SHIFT                                                   (1u)
+#define PMG_DSFR_P6_2F                                                         (0x0004u)
+#define PMG_DSFR_P6_2F_SHIFT                                                   (2u)
+#define PMG_DSFR_PE_1F                                                         (0x0008u)
+#define PMG_DSFR_PE_1F_SHIFT                                                   (3u)
+#define PMG_DSFR_PH_1F                                                         (0x0010u)
+#define PMG_DSFR_PH_1F_SHIFT                                                   (4u)
+#define PMG_DSFR_PG_2F                                                         (0x0020u)
+#define PMG_DSFR_PG_2F_SHIFT                                                   (5u)
+#define PMG_DSFR_RTCARF0                                                       (0x0040u)
+#define PMG_DSFR_RTCARF0_SHIFT                                                 (6u)
+#define PMG_DSFR_RTCARF1                                                       (0x0080u)
+#define PMG_DSFR_RTCARF1_SHIFT                                                 (7u)
+#define PMG_DSFR_NMIF                                                          (0x0100u)
+#define PMG_DSFR_NMIF_SHIFT                                                    (8u)
+#define PMG_DSFR_PG_6F                                                         (0x0200u)
+#define PMG_DSFR_PG_6F_SHIFT                                                   (9u)
+#define PMG_DSFR_PH_0F                                                         (0x0400u)
+#define PMG_DSFR_PH_0F_SHIFT                                                   (10u)
+#define PMG_DSFR_PJ_1F                                                         (0x0800u)
+#define PMG_DSFR_PJ_1F_SHIFT                                                   (11u)
+#define PMG_DSFR_PJ_5F                                                         (0x1000u)
+#define PMG_DSFR_PJ_5F_SHIFT                                                   (12u)
+#define PMG_DSFR_PK_2F                                                         (0x2000u)
+#define PMG_DSFR_PK_2F_SHIFT                                                   (13u)
+#define PMG_DSFR_PK_4F                                                         (0x4000u)
+#define PMG_DSFR_PK_4F_SHIFT                                                   (14u)
+#define PMG_DSFR_IOKEEP                                                        (0x8000u)
+#define PMG_DSFR_IOKEEP_SHIFT                                                  (15u)
+#define PMG_DSCNT_CNTD                                                         (0x00FFu)
+#define PMG_DSCNT_CNTD_SHIFT                                                   (0u)
+#define PMG_XTALCTR_GAIN0                                                      (0x01u)
+#define PMG_XTALCTR_GAIN0_SHIFT                                                (0u)
+#define PMG_USBDSSSR_USBDSCE0                                                  (0x01u)
+#define PMG_USBDSSSR_USBDSCE0_SHIFT                                            (0u)
+#define PMG_USBDSSSR_USBDSCE1                                                  (0x02u)
+#define PMG_USBDSSSR_USBDSCE1_SHIFT                                            (1u)
+#define PMG_USBDSSSR_USBDSCE2                                                  (0x04u)
+#define PMG_USBDSSSR_USBDSCE2_SHIFT                                            (2u)
+#define PMG_USBDSSSR_USBDSCE3                                                  (0x08u)
+#define PMG_USBDSSSR_USBDSCE3_SHIFT                                            (3u)
+#define PMG_USBDSFR_USBDSF0                                                    (0x01u)
+#define PMG_USBDSFR_USBDSF0_SHIFT                                              (0u)
+#define PMG_USBDSFR_USBDSF1                                                    (0x02u)
+#define PMG_USBDSFR_USBDSF1_SHIFT                                              (1u)
+#define PMG_USBDSFR_USBDSF2                                                    (0x04u)
+#define PMG_USBDSFR_USBDSF2_SHIFT                                              (2u)
+#define PMG_USBDSFR_USBDSF3                                                    (0x08u)
+#define PMG_USBDSFR_USBDSF3_SHIFT                                              (3u)
+#define PMG_RTCXTALSEL_RTC0XT                                                  (0x0001u)
+#define PMG_RTCXTALSEL_RTC0XT_SHIFT                                            (0u)
+#define PMG_RTCXTALSEL_RTC1XT                                                  (0x0002u)
+#define PMG_RTCXTALSEL_RTC1XT_SHIFT                                            (1u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poe3_iobitmask.h

@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef POE3_IOBITMASK_H
+#define POE3_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define POE3_ICSR1_POE0M                                                       (0x0003u)
+#define POE3_ICSR1_POE0M_SHIFT                                                 (0u)
+#define POE3_ICSR1_PIE1                                                        (0x0100u)
+#define POE3_ICSR1_PIE1_SHIFT                                                  (8u)
+#define POE3_ICSR1_POE0F                                                       (0x1000u)
+#define POE3_ICSR1_POE0F_SHIFT                                                 (12u)
+#define POE3_OCSR1_OIE1                                                        (0x0100u)
+#define POE3_OCSR1_OIE1_SHIFT                                                  (8u)
+#define POE3_OCSR1_OCE1                                                        (0x0200u)
+#define POE3_OCSR1_OCE1_SHIFT                                                  (9u)
+#define POE3_OCSR1_OSF1                                                        (0x8000u)
+#define POE3_OCSR1_OSF1_SHIFT                                                  (15u)
+#define POE3_ICSR2_POE4M                                                       (0x0003u)
+#define POE3_ICSR2_POE4M_SHIFT                                                 (0u)
+#define POE3_ICSR2_PIE2                                                        (0x0100u)
+#define POE3_ICSR2_PIE2_SHIFT                                                  (8u)
+#define POE3_ICSR2_POE4F                                                       (0x1000u)
+#define POE3_ICSR2_POE4F_SHIFT                                                 (12u)
+#define POE3_OCSR2_OIE2                                                        (0x0100u)
+#define POE3_OCSR2_OIE2_SHIFT                                                  (8u)
+#define POE3_OCSR2_OCE2                                                        (0x0200u)
+#define POE3_OCSR2_OCE2_SHIFT                                                  (9u)
+#define POE3_OCSR2_OSF2                                                        (0x8000u)
+#define POE3_OCSR2_OSF2_SHIFT                                                  (15u)
+#define POE3_ICSR3_POE8M                                                       (0x0003u)
+#define POE3_ICSR3_POE8M_SHIFT                                                 (0u)
+#define POE3_ICSR3_PIE3                                                        (0x0100u)
+#define POE3_ICSR3_PIE3_SHIFT                                                  (8u)
+#define POE3_ICSR3_POE8E                                                       (0x0200u)
+#define POE3_ICSR3_POE8E_SHIFT                                                 (9u)
+#define POE3_ICSR3_POE8F                                                       (0x1000u)
+#define POE3_ICSR3_POE8F_SHIFT                                                 (12u)
+#define POE3_SPOER_MTUCH34HIZ                                                  (0x01u)
+#define POE3_SPOER_MTUCH34HIZ_SHIFT                                            (0u)
+#define POE3_SPOER_MTUCH67HIZ                                                  (0x02u)
+#define POE3_SPOER_MTUCH67HIZ_SHIFT                                            (1u)
+#define POE3_SPOER_MTUCH0HIZ                                                   (0x04u)
+#define POE3_SPOER_MTUCH0HIZ_SHIFT                                             (2u)
+#define POE3_POECR1_MTU0AZE                                                    (0x01u)
+#define POE3_POECR1_MTU0AZE_SHIFT                                              (0u)
+#define POE3_POECR1_MTU0BZE                                                    (0x02u)
+#define POE3_POECR1_MTU0BZE_SHIFT                                              (1u)
+#define POE3_POECR1_MTU0CZE                                                    (0x04u)
+#define POE3_POECR1_MTU0CZE_SHIFT                                              (2u)
+#define POE3_POECR1_MTU0DZE                                                    (0x08u)
+#define POE3_POECR1_MTU0DZE_SHIFT                                              (3u)
+#define POE3_POECR2_MTU7BDZE                                                   (0x0001u)
+#define POE3_POECR2_MTU7BDZE_SHIFT                                             (0u)
+#define POE3_POECR2_MTU7ACZE                                                   (0x0002u)
+#define POE3_POECR2_MTU7ACZE_SHIFT                                             (1u)
+#define POE3_POECR2_MTU6BDZE                                                   (0x0004u)
+#define POE3_POECR2_MTU6BDZE_SHIFT                                             (2u)
+#define POE3_POECR2_MTU4BDZE                                                   (0x0100u)
+#define POE3_POECR2_MTU4BDZE_SHIFT                                             (8u)
+#define POE3_POECR2_MTU4ACZE                                                   (0x0200u)
+#define POE3_POECR2_MTU4ACZE_SHIFT                                             (9u)
+#define POE3_POECR2_MTU3BDZE                                                   (0x0400u)
+#define POE3_POECR2_MTU3BDZE_SHIFT                                             (10u)
+#define POE3_POECR4_IC2ADDMT34ZE                                               (0x0004u)
+#define POE3_POECR4_IC2ADDMT34ZE_SHIFT                                         (2u)
+#define POE3_POECR4_IC3ADDMT34ZE                                               (0x0008u)
+#define POE3_POECR4_IC3ADDMT34ZE_SHIFT                                         (3u)
+#define POE3_POECR4_IC4ADDMT34ZE                                               (0x0010u)
+#define POE3_POECR4_IC4ADDMT34ZE_SHIFT                                         (4u)
+#define POE3_POECR4_IC1ADDMT67ZE                                               (0x0200u)
+#define POE3_POECR4_IC1ADDMT67ZE_SHIFT                                         (9u)
+#define POE3_POECR4_IC3ADDMT67ZE                                               (0x0800u)
+#define POE3_POECR4_IC3ADDMT67ZE_SHIFT                                         (11u)
+#define POE3_POECR4_IC4ADDMT67ZE                                               (0x1000u)
+#define POE3_POECR4_IC4ADDMT67ZE_SHIFT                                         (12u)
+#define POE3_POECR5_IC1ADDMT0ZE                                                (0x0002u)
+#define POE3_POECR5_IC1ADDMT0ZE_SHIFT                                          (1u)
+#define POE3_POECR5_IC2ADDMT0ZE                                                (0x0004u)
+#define POE3_POECR5_IC2ADDMT0ZE_SHIFT                                          (2u)
+#define POE3_POECR5_IC4ADDMT0ZE                                                (0x0010u)
+#define POE3_POECR5_IC4ADDMT0ZE_SHIFT                                          (4u)
+#define POE3_ICSR4_POE10M                                                      (0x0003u)
+#define POE3_ICSR4_POE10M_SHIFT                                                (0u)
+#define POE3_ICSR4_PIE4                                                        (0x0100u)
+#define POE3_ICSR4_PIE4_SHIFT                                                  (8u)
+#define POE3_ICSR4_POE10E                                                      (0x0200u)
+#define POE3_ICSR4_POE10E_SHIFT                                                (9u)
+#define POE3_ICSR4_POE10F                                                      (0x1000u)
+#define POE3_ICSR4_POE10F_SHIFT                                                (12u)
+#define POE3_M0SELR1_M0ASEL                                                    (0x0Fu)
+#define POE3_M0SELR1_M0ASEL_SHIFT                                              (0u)
+#define POE3_M0SELR1_M0BSEL                                                    (0xF0u)
+#define POE3_M0SELR1_M0BSEL_SHIFT                                              (4u)
+#define POE3_M0SELR2_M0CSEL                                                    (0x0Fu)
+#define POE3_M0SELR2_M0CSEL_SHIFT                                              (0u)
+#define POE3_M0SELR2_M0DSEL                                                    (0xF0u)
+#define POE3_M0SELR2_M0DSEL_SHIFT                                              (4u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poeg_iobitmask.h

@@ -0,0 +1,122 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef POEG_IOBITMASK_H
+#define POEG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define POEG_POEGGA_PIDF                                                       (0x00000001u)
+#define POEG_POEGGA_PIDF_SHIFT                                                 (0u)
+#define POEG_POEGGA_IOCF                                                       (0x00000002u)
+#define POEG_POEGGA_IOCF_SHIFT                                                 (1u)
+#define POEG_POEGGA_SSF                                                        (0x00000008u)
+#define POEG_POEGGA_SSF_SHIFT                                                  (3u)
+#define POEG_POEGGA_PIDE                                                       (0x00000010u)
+#define POEG_POEGGA_PIDE_SHIFT                                                 (4u)
+#define POEG_POEGGA_IOCE                                                       (0x00000020u)
+#define POEG_POEGGA_IOCE_SHIFT                                                 (5u)
+#define POEG_POEGGA_ST                                                         (0x00010000u)
+#define POEG_POEGGA_ST_SHIFT                                                   (16u)
+#define POEG_POEGGA_INV                                                        (0x10000000u)
+#define POEG_POEGGA_INV_SHIFT                                                  (28u)
+#define POEG_POEGGA_NFEN                                                       (0x20000000u)
+#define POEG_POEGGA_NFEN_SHIFT                                                 (29u)
+#define POEG_POEGGA_NFCS                                                       (0xC0000000u)
+#define POEG_POEGGA_NFCS_SHIFT                                                 (30u)
+#define POEG_POEGGB_PIDF                                                       (0x00000001u)
+#define POEG_POEGGB_PIDF_SHIFT                                                 (0u)
+#define POEG_POEGGB_IOCF                                                       (0x00000002u)
+#define POEG_POEGGB_IOCF_SHIFT                                                 (1u)
+#define POEG_POEGGB_SSF                                                        (0x00000008u)
+#define POEG_POEGGB_SSF_SHIFT                                                  (3u)
+#define POEG_POEGGB_PIDE                                                       (0x00000010u)
+#define POEG_POEGGB_PIDE_SHIFT                                                 (4u)
+#define POEG_POEGGB_IOCE                                                       (0x00000020u)
+#define POEG_POEGGB_IOCE_SHIFT                                                 (5u)
+#define POEG_POEGGB_ST                                                         (0x00010000u)
+#define POEG_POEGGB_ST_SHIFT                                                   (16u)
+#define POEG_POEGGB_INV                                                        (0x10000000u)
+#define POEG_POEGGB_INV_SHIFT                                                  (28u)
+#define POEG_POEGGB_NFEN                                                       (0x20000000u)
+#define POEG_POEGGB_NFEN_SHIFT                                                 (29u)
+#define POEG_POEGGB_NFCS                                                       (0xC0000000u)
+#define POEG_POEGGB_NFCS_SHIFT                                                 (30u)
+#define POEG_POEGGC_PIDF                                                       (0x00000001u)
+#define POEG_POEGGC_PIDF_SHIFT                                                 (0u)
+#define POEG_POEGGC_IOCF                                                       (0x00000002u)
+#define POEG_POEGGC_IOCF_SHIFT                                                 (1u)
+#define POEG_POEGGC_SSF                                                        (0x00000008u)
+#define POEG_POEGGC_SSF_SHIFT                                                  (3u)
+#define POEG_POEGGC_PIDE                                                       (0x00000010u)
+#define POEG_POEGGC_PIDE_SHIFT                                                 (4u)
+#define POEG_POEGGC_IOCE                                                       (0x00000020u)
+#define POEG_POEGGC_IOCE_SHIFT                                                 (5u)
+#define POEG_POEGGC_ST                                                         (0x00010000u)
+#define POEG_POEGGC_ST_SHIFT                                                   (16u)
+#define POEG_POEGGC_INV                                                        (0x10000000u)
+#define POEG_POEGGC_INV_SHIFT                                                  (28u)
+#define POEG_POEGGC_NFEN                                                       (0x20000000u)
+#define POEG_POEGGC_NFEN_SHIFT                                                 (29u)
+#define POEG_POEGGC_NFCS                                                       (0xC0000000u)
+#define POEG_POEGGC_NFCS_SHIFT                                                 (30u)
+#define POEG_POEGGD_PIDF                                                       (0x00000001u)
+#define POEG_POEGGD_PIDF_SHIFT                                                 (0u)
+#define POEG_POEGGD_IOCF                                                       (0x00000002u)
+#define POEG_POEGGD_IOCF_SHIFT                                                 (1u)
+#define POEG_POEGGD_SSF                                                        (0x00000008u)
+#define POEG_POEGGD_SSF_SHIFT                                                  (3u)
+#define POEG_POEGGD_PIDE                                                       (0x00000010u)
+#define POEG_POEGGD_PIDE_SHIFT                                                 (4u)
+#define POEG_POEGGD_IOCE                                                       (0x00000020u)
+#define POEG_POEGGD_IOCE_SHIFT                                                 (5u)
+#define POEG_POEGGD_ST                                                         (0x00010000u)
+#define POEG_POEGGD_ST_SHIFT                                                   (16u)
+#define POEG_POEGGD_INV                                                        (0x10000000u)
+#define POEG_POEGGD_INV_SHIFT                                                  (28u)
+#define POEG_POEGGD_NFEN                                                       (0x20000000u)
+#define POEG_POEGGD_NFEN_SHIFT                                                 (29u)
+#define POEG_POEGGD_NFCS                                                       (0xC0000000u)
+#define POEG_POEGGD_NFCS_SHIFT                                                 (30u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/prr_iobitmask.h

@@ -0,0 +1,344 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef PRR_IOBITMASK_H
+#define PRR_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define PRR_BSID_DID                                                           (0xFFFFFFFFu)
+#define PRR_BSID_DID_SHIFT                                                     (0u)
+#define PRR_AXIBUSCTL0_ETHAXCACHE                                              (0x00000003u)
+#define PRR_AXIBUSCTL0_ETHAXCACHE_SHIFT                                        (0u)
+#define PRR_AXIBUSCTL0_JCUAWCACHE                                              (0x000F0000u)
+#define PRR_AXIBUSCTL0_JCUAWCACHE_SHIFT                                        (16u)
+#define PRR_AXIBUSCTL0_JCUARCACHE                                              (0x0F000000u)
+#define PRR_AXIBUSCTL0_JCUARCACHE_SHIFT                                        (24u)
+#define PRR_AXIBUSCTL1_VINAWCACHE                                              (0x0000000Fu)
+#define PRR_AXIBUSCTL1_VINAWCACHE_SHIFT                                        (0u)
+#define PRR_AXIBUSCTL1_IMR20AWCACHE                                            (0x000F0000u)
+#define PRR_AXIBUSCTL1_IMR20AWCACHE_SHIFT                                      (16u)
+#define PRR_AXIBUSCTL1_IMR20ARCACHE                                            (0x0F000000u)
+#define PRR_AXIBUSCTL1_IMR20ARCACHE_SHIFT                                      (24u)
+#define PRR_AXIBUSCTL2_CEUAWCACHE                                              (0x0000000Fu)
+#define PRR_AXIBUSCTL2_CEUAWCACHE_SHIFT                                        (0u)
+#define PRR_AXIBUSCTL3_SDMMC1AWCACHE                                           (0x0000000Fu)
+#define PRR_AXIBUSCTL3_SDMMC1AWCACHE_SHIFT                                     (0u)
+#define PRR_AXIBUSCTL3_SDMMC1ARCACHE                                           (0x00000F00u)
+#define PRR_AXIBUSCTL3_SDMMC1ARCACHE_SHIFT                                     (8u)
+#define PRR_AXIBUSCTL3_SDMMC0AWCACHE                                           (0x000F0000u)
+#define PRR_AXIBUSCTL3_SDMMC0AWCACHE_SHIFT                                     (16u)
+#define PRR_AXIBUSCTL3_SDMMC0ARCACHE                                           (0x0F000000u)
+#define PRR_AXIBUSCTL3_SDMMC0ARCACHE_SHIFT                                     (24u)
+#define PRR_AXIBUSCTL4_DRPAWCACHE                                              (0x0000000Fu)
+#define PRR_AXIBUSCTL4_DRPAWCACHE_SHIFT                                        (0u)
+#define PRR_AXIBUSCTL4_DRPARCACHE                                              (0x00000F00u)
+#define PRR_AXIBUSCTL4_DRPARCACHE_SHIFT                                        (8u)
+#define PRR_AXIBUSCTL4_NANDAWCACHE                                             (0x000F0000u)
+#define PRR_AXIBUSCTL4_NANDAWCACHE_SHIFT                                       (16u)
+#define PRR_AXIBUSCTL4_NANDARCACHE                                             (0x0F000000u)
+#define PRR_AXIBUSCTL4_NANDARCACHE_SHIFT                                       (24u)
+#define PRR_AXIBUSCTL5_D2D1AXCACHE                                             (0x00000003u)
+#define PRR_AXIBUSCTL5_D2D1AXCACHE_SHIFT                                       (0u)
+#define PRR_AXIBUSCTL5_D2D0AXCACHE                                             (0x00030000u)
+#define PRR_AXIBUSCTL5_D2D0AXCACHE_SHIFT                                       (16u)
+#define PRR_AXIBUSCTL6_VDC602ARCACHE                                           (0x00000F00u)
+#define PRR_AXIBUSCTL6_VDC602ARCACHE_SHIFT                                     (8u)
+#define PRR_AXIBUSCTL6_VDC601AWCACHE                                           (0x000F0000u)
+#define PRR_AXIBUSCTL6_VDC601AWCACHE_SHIFT                                     (16u)
+#define PRR_AXIBUSCTL6_VDC601ARCACHE                                           (0x0F000000u)
+#define PRR_AXIBUSCTL6_VDC601ARCACHE_SHIFT                                     (24u)
+#define PRR_AXIBUSCTL7_VDC604ARCACHE                                           (0x00000F00u)
+#define PRR_AXIBUSCTL7_VDC604ARCACHE_SHIFT                                     (8u)
+#define PRR_AXIRERRCTL0_CEURERREN                                              (0x00000100u)
+#define PRR_AXIRERRCTL0_CEURERREN_SHIFT                                        (8u)
+#define PRR_AXIRERRCTL0_VINRERREN                                              (0x00010000u)
+#define PRR_AXIRERRCTL0_VINRERREN_SHIFT                                        (16u)
+#define PRR_AXIRERRCTL0_IMR20RERREN                                            (0x00100000u)
+#define PRR_AXIRERRCTL0_IMR20RERREN_SHIFT                                      (20u)
+#define PRR_AXIRERRCTL0_JCURERREN                                              (0x10000000u)
+#define PRR_AXIRERRCTL0_JCURERREN_SHIFT                                        (28u)
+#define PRR_AXIRERRCTL1_DRPRERREN                                              (0x00010000u)
+#define PRR_AXIRERRCTL1_DRPRERREN_SHIFT                                        (16u)
+#define PRR_AXIRERRCTL1_NANDRERREN                                             (0x00100000u)
+#define PRR_AXIRERRCTL1_NANDRERREN_SHIFT                                       (20u)
+#define PRR_AXIRERRCTL1_SDMMC1RERREN                                           (0x01000000u)
+#define PRR_AXIRERRCTL1_SDMMC1RERREN_SHIFT                                     (24u)
+#define PRR_AXIRERRCTL1_SDMMC0RERREN                                           (0x10000000u)
+#define PRR_AXIRERRCTL1_SDMMC0RERREN_SHIFT                                     (28u)
+#define PRR_AXIRERRCTL2_VDC604RERREN                                           (0x00010000u)
+#define PRR_AXIRERRCTL2_VDC604RERREN_SHIFT                                     (16u)
+#define PRR_AXIRERRCTL2_VDC602RERREN                                           (0x01000000u)
+#define PRR_AXIRERRCTL2_VDC602RERREN_SHIFT                                     (24u)
+#define PRR_AXIRERRCTL2_VDC601RERREN                                           (0x10000000u)
+#define PRR_AXIRERRCTL2_VDC601RERREN_SHIFT                                     (28u)
+#define PRR_AXIRERRST0_CEUBRESP                                                (0x00000300u)
+#define PRR_AXIRERRST0_CEUBRESP_SHIFT                                          (8u)
+#define PRR_AXIRERRST0_VINBRESP                                                (0x00030000u)
+#define PRR_AXIRERRST0_VINBRESP_SHIFT                                          (16u)
+#define PRR_AXIRERRST0_IMR20BRESP                                              (0x00300000u)
+#define PRR_AXIRERRST0_IMR20BRESP_SHIFT                                        (20u)
+#define PRR_AXIRERRST0_IMR20RRESP                                              (0x00C00000u)
+#define PRR_AXIRERRST0_IMR20RRESP_SHIFT                                        (22u)
+#define PRR_AXIRERRST0_JCUBRESP                                                (0x30000000u)
+#define PRR_AXIRERRST0_JCUBRESP_SHIFT                                          (28u)
+#define PRR_AXIRERRST0_JCURRESP                                                (0xC0000000u)
+#define PRR_AXIRERRST0_JCURRESP_SHIFT                                          (30u)
+#define PRR_AXIRERRST1_DRPBRESP                                                (0x00030000u)
+#define PRR_AXIRERRST1_DRPBRESP_SHIFT                                          (16u)
+#define PRR_AXIRERRST1_DRPRRESP                                                (0x000C0000u)
+#define PRR_AXIRERRST1_DRPRRESP_SHIFT                                          (18u)
+#define PRR_AXIRERRST1_NANDBRESP                                               (0x00300000u)
+#define PRR_AXIRERRST1_NANDBRESP_SHIFT                                         (20u)
+#define PRR_AXIRERRST1_NANDRRESP                                               (0x00C00000u)
+#define PRR_AXIRERRST1_NANDRRESP_SHIFT                                         (22u)
+#define PRR_AXIRERRST1_SDMMC1BRESP                                             (0x03000000u)
+#define PRR_AXIRERRST1_SDMMC1BRESP_SHIFT                                       (24u)
+#define PRR_AXIRERRST1_SDMMC1RRESP                                             (0x0C000000u)
+#define PRR_AXIRERRST1_SDMMC1RRESP_SHIFT                                       (26u)
+#define PRR_AXIRERRST1_SDMMC0BRESP                                             (0x30000000u)
+#define PRR_AXIRERRST1_SDMMC0BRESP_SHIFT                                       (28u)
+#define PRR_AXIRERRST1_SDMMC0RRESP                                             (0xC0000000u)
+#define PRR_AXIRERRST1_SDMMC0RRESP_SHIFT                                       (30u)
+#define PRR_AXIRERRST2_VDC604RRESP                                             (0x000C0000u)
+#define PRR_AXIRERRST2_VDC604RRESP_SHIFT                                       (18u)
+#define PRR_AXIRERRST2_VDC602RRESP                                             (0x0C000000u)
+#define PRR_AXIRERRST2_VDC602RRESP_SHIFT                                       (26u)
+#define PRR_AXIRERRST2_VDC601BRESP                                             (0x30000000u)
+#define PRR_AXIRERRST2_VDC601BRESP_SHIFT                                       (28u)
+#define PRR_AXIRERRST2_VDC601RRESP                                             (0xC0000000u)
+#define PRR_AXIRERRST2_VDC601RRESP_SHIFT                                       (30u)
+#define PRR_AXIRERRCLR0_CEUBRESPCLR                                            (0x00000100u)
+#define PRR_AXIRERRCLR0_CEUBRESPCLR_SHIFT                                      (8u)
+#define PRR_AXIRERRCLR0_SERBRESPCLR                                            (0x00001000u)
+#define PRR_AXIRERRCLR0_SERBRESPCLR_SHIFT                                      (12u)
+#define PRR_AXIRERRCLR0_SERRRESPCLR                                            (0x00004000u)
+#define PRR_AXIRERRCLR0_SERRRESPCLR_SHIFT                                      (14u)
+#define PRR_AXIRERRCLR0_VINBRESPCLR                                            (0x00010000u)
+#define PRR_AXIRERRCLR0_VINBRESPCLR_SHIFT                                      (16u)
+#define PRR_AXIRERRCLR0_IMR20BRESPCLR                                          (0x00100000u)
+#define PRR_AXIRERRCLR0_IMR20BRESPCLR_SHIFT                                    (20u)
+#define PRR_AXIRERRCLR0_IMR20RRESPCLR                                          (0x00400000u)
+#define PRR_AXIRERRCLR0_IMR20RRESPCLR_SHIFT                                    (22u)
+#define PRR_AXIRERRCLR0_JCUBRESPCLR                                            (0x10000000u)
+#define PRR_AXIRERRCLR0_JCUBRESPCLR_SHIFT                                      (28u)
+#define PRR_AXIRERRCLR0_JCURRESPCLR                                            (0x40000000u)
+#define PRR_AXIRERRCLR0_JCURRESPCLR_SHIFT                                      (30u)
+#define PRR_AXIRERRCLR1_DRPBRESPCLR                                            (0x00010000u)
+#define PRR_AXIRERRCLR1_DRPBRESPCLR_SHIFT                                      (16u)
+#define PRR_AXIRERRCLR1_DRPRRESPCLR                                            (0x00040000u)
+#define PRR_AXIRERRCLR1_DRPRRESPCLR_SHIFT                                      (18u)
+#define PRR_AXIRERRCLR1_NANDBRESPCLR                                           (0x00100000u)
+#define PRR_AXIRERRCLR1_NANDBRESPCLR_SHIFT                                     (20u)
+#define PRR_AXIRERRCLR1_NANDRRESPCLR                                           (0x00400000u)
+#define PRR_AXIRERRCLR1_NANDRRESPCLR_SHIFT                                     (22u)
+#define PRR_AXIRERRCLR1_SDMMC1BRESPCLR                                         (0x01000000u)
+#define PRR_AXIRERRCLR1_SDMMC1BRESPCLR_SHIFT                                   (24u)
+#define PRR_AXIRERRCLR1_SDMMC1RRESPCLR                                         (0x04000000u)
+#define PRR_AXIRERRCLR1_SDMMC1RRESPCLR_SHIFT                                   (26u)
+#define PRR_AXIRERRCLR1_SDMMC0BRESPCLR                                         (0x10000000u)
+#define PRR_AXIRERRCLR1_SDMMC0BRESPCLR_SHIFT                                   (28u)
+#define PRR_AXIRERRCLR1_SDMMC0RRESPCLR                                         (0x40000000u)
+#define PRR_AXIRERRCLR1_SDMMC0RRESPCLR_SHIFT                                   (30u)
+#define PRR_AXIRERRCLR2_VDC604RRESPCLR                                         (0x00040000u)
+#define PRR_AXIRERRCLR2_VDC604RRESPCLR_SHIFT                                   (18u)
+#define PRR_AXIRERRCLR2_VDC602RRESPCLR                                         (0x04000000u)
+#define PRR_AXIRERRCLR2_VDC602RRESPCLR_SHIFT                                   (26u)
+#define PRR_AXIRERRCLR2_VDC601BRESPCLR                                         (0x10000000u)
+#define PRR_AXIRERRCLR2_VDC601BRESPCLR_SHIFT                                   (28u)
+#define PRR_AXIRERRCLR2_VDC601RRESPCLR                                         (0x40000000u)
+#define PRR_AXIRERRCLR2_VDC601RRESPCLR_SHIFT                                   (30u)
+#define PRR_MSTACCCTL0_VINAWNS                                                 (0x00000002u)
+#define PRR_MSTACCCTL0_VINAWNS_SHIFT                                           (1u)
+#define PRR_MSTACCCTL0_IMR20AWNS                                               (0x00000200u)
+#define PRR_MSTACCCTL0_IMR20AWNS_SHIFT                                         (9u)
+#define PRR_MSTACCCTL0_IMR20ARNS                                               (0x00002000u)
+#define PRR_MSTACCCTL0_IMR20ARNS_SHIFT                                         (13u)
+#define PRR_MSTACCCTL0_ETHAxNS                                                 (0x00020000u)
+#define PRR_MSTACCCTL0_ETHAxNS_SHIFT                                           (17u)
+#define PRR_MSTACCCTL0_JCUAWNS                                                 (0x02000000u)
+#define PRR_MSTACCCTL0_JCUAWNS_SHIFT                                           (25u)
+#define PRR_MSTACCCTL0_JCUARNS                                                 (0x20000000u)
+#define PRR_MSTACCCTL0_JCUARNS_SHIFT                                           (29u)
+#define PRR_MSTACCCTL1_SDMMC1AWNS                                              (0x00000002u)
+#define PRR_MSTACCCTL1_SDMMC1AWNS_SHIFT                                        (1u)
+#define PRR_MSTACCCTL1_SDMMC1ARNS                                              (0x00000020u)
+#define PRR_MSTACCCTL1_SDMMC1ARNS_SHIFT                                        (5u)
+#define PRR_MSTACCCTL1_SDMMC0AWNS                                              (0x00000200u)
+#define PRR_MSTACCCTL1_SDMMC0AWNS_SHIFT                                        (9u)
+#define PRR_MSTACCCTL1_SDMMC0ARNS                                              (0x00002000u)
+#define PRR_MSTACCCTL1_SDMMC0ARNS_SHIFT                                        (13u)
+#define PRR_MSTACCCTL1_CEUAWNS                                                 (0x00020000u)
+#define PRR_MSTACCCTL1_CEUAWNS_SHIFT                                           (17u)
+#define PRR_MSTACCCTL2_D2D1AxNS                                                (0x00000002u)
+#define PRR_MSTACCCTL2_D2D1AxNS_SHIFT                                          (1u)
+#define PRR_MSTACCCTL2_D2D0AxNS                                                (0x00000200u)
+#define PRR_MSTACCCTL2_D2D0AxNS_SHIFT                                          (9u)
+#define PRR_MSTACCCTL2_DRPAWNS                                                 (0x00020000u)
+#define PRR_MSTACCCTL2_DRPAWNS_SHIFT                                           (17u)
+#define PRR_MSTACCCTL2_DRPARNS                                                 (0x00200000u)
+#define PRR_MSTACCCTL2_DRPARNS_SHIFT                                           (21u)
+#define PRR_MSTACCCTL2_NANDAWNS                                                (0x02000000u)
+#define PRR_MSTACCCTL2_NANDAWNS_SHIFT                                          (25u)
+#define PRR_MSTACCCTL2_NANDARNS                                                (0x20000000u)
+#define PRR_MSTACCCTL2_NANDARNS_SHIFT                                          (29u)
+#define PRR_MSTACCCTL3_VDC604ARNS                                              (0x00000020u)
+#define PRR_MSTACCCTL3_VDC604ARNS_SHIFT                                        (5u)
+#define PRR_MSTACCCTL3_VDC602ARNS                                              (0x00200000u)
+#define PRR_MSTACCCTL3_VDC602ARNS_SHIFT                                        (21u)
+#define PRR_MSTACCCTL3_VDC601AWNS                                              (0x02000000u)
+#define PRR_MSTACCCTL3_VDC601AWNS_SHIFT                                        (25u)
+#define PRR_MSTACCCTL3_VDC601ARNS                                              (0x20000000u)
+#define PRR_MSTACCCTL3_VDC601ARNS_SHIFT                                        (29u)
+#define PRR_MSTACCCTL4_USB11AxNS                                               (0x00000002u)
+#define PRR_MSTACCCTL4_USB11AxNS_SHIFT                                         (1u)
+#define PRR_MSTACCCTL4_USB10AxNS                                               (0x00000200u)
+#define PRR_MSTACCCTL4_USB10AxNS_SHIFT                                         (9u)
+#define PRR_MSTACCCTL4_USB01AxNS                                               (0x00020000u)
+#define PRR_MSTACCCTL4_USB01AxNS_SHIFT                                         (17u)
+#define PRR_MSTACCCTL4_USB00AxNS                                               (0x02000000u)
+#define PRR_MSTACCCTL4_USB00AxNS_SHIFT                                         (25u)
+#define PRR_SLVACCCTL0_WDTNS                                                   (0x00000010u)
+#define PRR_SLVACCCTL0_WDTNS_SHIFT                                             (4u)
+#define PRR_SLVACCCTL0_INTC2NS                                                 (0x00000040u)
+#define PRR_SLVACCCTL0_INTC2NS_SHIFT                                           (6u)
+#define PRR_SLVACCCTL0_POEGNS                                                  (0x00004000u)
+#define PRR_SLVACCCTL0_POEGNS_SHIFT                                            (14u)
+#define PRR_SLVACCCTL0_POE3NS                                                  (0x00010000u)
+#define PRR_SLVACCCTL0_POE3NS_SHIFT                                            (16u)
+#define PRR_SLVACCCTL0_GPTNS                                                   (0x00040000u)
+#define PRR_SLVACCCTL0_GPTNS_SHIFT                                             (18u)
+#define PRR_SLVACCCTL0_MTU3NS                                                  (0x00100000u)
+#define PRR_SLVACCCTL0_MTU3NS_SHIFT                                            (20u)
+#define PRR_SLVACCCTL0_IMR20NS                                                 (0x00400000u)
+#define PRR_SLVACCCTL0_IMR20NS_SHIFT                                           (22u)
+#define PRR_SLVACCCTL0_VDC60NS                                                 (0x01000000u)
+#define PRR_SLVACCCTL0_VDC60NS_SHIFT                                           (24u)
+#define PRR_SLVACCCTL0_SYSNS                                                   (0x40000000u)
+#define PRR_SLVACCCTL0_SYSNS_SHIFT                                             (30u)
+#define PRR_SLVACCCTL1_RSPINS                                                  (0x00000001u)
+#define PRR_SLVACCCTL1_RSPINS_SHIFT                                            (0u)
+#define PRR_SLVACCCTL1_JCUNS                                                   (0x00000004u)
+#define PRR_SLVACCCTL1_JCUNS_SHIFT                                             (2u)
+#define PRR_SLVACCCTL1_SCIFNS                                                  (0x00000010u)
+#define PRR_SLVACCCTL1_SCIFNS_SHIFT                                            (4u)
+#define PRR_SLVACCCTL1_SCINS                                                   (0x00000040u)
+#define PRR_SLVACCCTL1_SCINS_SHIFT                                             (6u)
+#define PRR_SLVACCCTL1_IRDANS                                                  (0x00000100u)
+#define PRR_SLVACCCTL1_IRDANS_SHIFT                                            (8u)
+#define PRR_SLVACCCTL1_ADNS                                                    (0x00000400u)
+#define PRR_SLVACCCTL1_ADNS_SHIFT                                              (10u)
+#define PRR_SLVACCCTL1_SENS                                                    (0x00004000u)
+#define PRR_SLVACCCTL1_SENS_SHIFT                                              (14u)
+#define PRR_SLVACCCTL1_RCANNS                                                  (0x00010000u)
+#define PRR_SLVACCCTL1_RCANNS_SHIFT                                            (16u)
+#define PRR_SLVACCCTL1_SPDIFNS                                                 (0x00040000u)
+#define PRR_SLVACCCTL1_SPDIFNS_SHIFT                                           (18u)
+#define PRR_SLVACCCTL1_SSIFNS                                                  (0x00100000u)
+#define PRR_SLVACCCTL1_SSIFNS_SHIFT                                            (20u)
+#define PRR_SLVACCCTL1_OSTM2NS                                                 (0x00400000u)
+#define PRR_SLVACCCTL1_OSTM2NS_SHIFT                                           (22u)
+#define PRR_SLVACCCTL1_OSTM1NS                                                 (0x01000000u)
+#define PRR_SLVACCCTL1_OSTM1NS_SHIFT                                           (24u)
+#define PRR_SLVACCCTL1_OSTM0NS                                                 (0x04000000u)
+#define PRR_SLVACCCTL1_OSTM0NS_SHIFT                                           (26u)
+#define PRR_SLVACCCTL1_I2CNS                                                   (0x10000000u)
+#define PRR_SLVACCCTL1_I2CNS_SHIFT                                             (28u)
+#define PRR_SLVACCCTL1_GPIONS                                                  (0x40000000u)
+#define PRR_SLVACCCTL1_GPIONS_SHIFT                                            (30u)
+#define PRR_SLVACCCTL2_TSIPNS                                                  (0x00000004u)
+#define PRR_SLVACCCTL2_TSIPNS_SHIFT                                            (2u)
+#define PRR_SLVACCCTL2_DRPNS                                                   (0x00000010u)
+#define PRR_SLVACCCTL2_DRPNS_SHIFT                                             (4u)
+#define PRR_SLVACCCTL2_CEUNS                                                   (0x00000040u)
+#define PRR_SLVACCCTL2_CEUNS_SHIFT                                             (6u)
+#define PRR_SLVACCCTL2_USB11NS                                                 (0x00000100u)
+#define PRR_SLVACCCTL2_USB11NS_SHIFT                                           (8u)
+#define PRR_SLVACCCTL2_USB10NS                                                 (0x00000400u)
+#define PRR_SLVACCCTL2_USB10NS_SHIFT                                           (10u)
+#define PRR_SLVACCCTL2_USB01NS                                                 (0x00001000u)
+#define PRR_SLVACCCTL2_USB01NS_SHIFT                                           (12u)
+#define PRR_SLVACCCTL2_USB00NS                                                 (0x00004000u)
+#define PRR_SLVACCCTL2_USB00NS_SHIFT                                           (14u)
+#define PRR_SLVACCCTL2_VINNS                                                   (0x00400000u)
+#define PRR_SLVACCCTL2_VINNS_SHIFT                                             (22u)
+#define PRR_SLVACCCTL2_MIPINS                                                  (0x01000000u)
+#define PRR_SLVACCCTL2_MIPINS_SHIFT                                            (24u)
+#define PRR_SLVACCCTL2_D2DNS                                                   (0x04000000u)
+#define PRR_SLVACCCTL2_D2DNS_SHIFT                                             (26u)
+#define PRR_SLVACCCTL2_ETHNS                                                   (0x40000000u)
+#define PRR_SLVACCCTL2_ETHNS_SHIFT                                             (30u)
+#define PRR_SLVACCCTL3_CSNS                                                    (0x00100000u)
+#define PRR_SLVACCCTL3_CSNS_SHIFT                                              (20u)
+#define PRR_SLVACCCTL3_NANDNS                                                  (0x01000000u)
+#define PRR_SLVACCCTL3_NANDNS_SHIFT                                            (24u)
+#define PRR_SLVACCCTL3_SDMMC1NS                                                (0x04000000u)
+#define PRR_SLVACCCTL3_SDMMC1NS_SHIFT                                          (26u)
+#define PRR_SLVACCCTL3_SDMMC0NS                                                (0x10000000u)
+#define PRR_SLVACCCTL3_SDMMC0NS_SHIFT                                          (28u)
+#define PRR_SLVACCCTL4_VRAM4NS                                                 (0x00000100u)
+#define PRR_SLVACCCTL4_VRAM4NS_SHIFT                                           (8u)
+#define PRR_SLVACCCTL4_VRAM3NS                                                 (0x00000400u)
+#define PRR_SLVACCCTL4_VRAM3NS_SHIFT                                           (10u)
+#define PRR_SLVACCCTL4_VRAM2NS                                                 (0x00001000u)
+#define PRR_SLVACCCTL4_VRAM2NS_SHIFT                                           (12u)
+#define PRR_SLVACCCTL4_VRAM1NS                                                 (0x00004000u)
+#define PRR_SLVACCCTL4_VRAM1NS_SHIFT                                           (14u)
+#define PRR_SLVACCCTL4_VRAM0NS                                                 (0x00010000u)
+#define PRR_SLVACCCTL4_VRAM0NS_SHIFT                                           (16u)
+#define PRR_SLVACCCTL4_RRAMNS                                                  (0x00040000u)
+#define PRR_SLVACCCTL4_RRAMNS_SHIFT                                            (18u)
+#define PRR_SLVACCCTL4_HYPRNS                                                  (0x00100000u)
+#define PRR_SLVACCCTL4_HYPRNS_SHIFT                                            (20u)
+#define PRR_SLVACCCTL4_HYPNS                                                   (0x00400000u)
+#define PRR_SLVACCCTL4_HYPNS_SHIFT                                             (22u)
+#define PRR_SLVACCCTL4_OCTARNS                                                 (0x01000000u)
+#define PRR_SLVACCCTL4_OCTARNS_SHIFT                                           (24u)
+#define PRR_SLVACCCTL4_OCTANS                                                  (0x04000000u)
+#define PRR_SLVACCCTL4_OCTANS_SHIFT                                            (26u)
+#define PRR_SLVACCCTL4_SPINS                                                   (0x10000000u)
+#define PRR_SLVACCCTL4_SPINS_SHIFT                                             (28u)
+#define PRR_SLVACCCTL4_BSCNS                                                   (0x40000000u)
+#define PRR_SLVACCCTL4_BSCNS_SHIFT                                             (30u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ptpedmac_iobitmask.h

@@ -0,0 +1,148 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef PTPEDMAC_IOBITMASK_H
+#define PTPEDMAC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define PTPEDMAC_EDMR_SWR                                                      (0x00000001u)
+#define PTPEDMAC_EDMR_SWR_SHIFT                                                (0u)
+#define PTPEDMAC_EDMR_DL                                                       (0x00000030u)
+#define PTPEDMAC_EDMR_DL_SHIFT                                                 (4u)
+#define PTPEDMAC_EDMR_DE                                                       (0x00000040u)
+#define PTPEDMAC_EDMR_DE_SHIFT                                                 (6u)
+#define PTPEDMAC_EDTRR_TR                                                      (0x00000001u)
+#define PTPEDMAC_EDTRR_TR_SHIFT                                                (0u)
+#define PTPEDMAC_EDRRR_RR                                                      (0x00000001u)
+#define PTPEDMAC_EDRRR_RR_SHIFT                                                (0u)
+#define PTPEDMAC_TDLAR_TDLAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_TDLAR_TDLAR_SHIFT                                             (0u)
+#define PTPEDMAC_RDLAR_RDLAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_RDLAR_RDLAR_SHIFT                                             (0u)
+#define PTPEDMAC_EESR_TYPE                                                     (0x0000000Fu)
+#define PTPEDMAC_EESR_TYPE_SHIFT                                               (0u)
+#define PTPEDMAC_EESR_PVER                                                     (0x00000010u)
+#define PTPEDMAC_EESR_PVER_SHIFT                                               (4u)
+#define PTPEDMAC_EESR_RPORT                                                    (0x00000080u)
+#define PTPEDMAC_EESR_RPORT_SHIFT                                              (7u)
+#define PTPEDMAC_EESR_MACE                                                     (0x00000100u)
+#define PTPEDMAC_EESR_MACE_SHIFT                                               (8u)
+#define PTPEDMAC_EESR_RFOF                                                     (0x00010000u)
+#define PTPEDMAC_EESR_RFOF_SHIFT                                               (16u)
+#define PTPEDMAC_EESR_RDE                                                      (0x00020000u)
+#define PTPEDMAC_EESR_RDE_SHIFT                                                (17u)
+#define PTPEDMAC_EESR_FR                                                       (0x00040000u)
+#define PTPEDMAC_EESR_FR_SHIFT                                                 (18u)
+#define PTPEDMAC_EESR_TFUF                                                     (0x00080000u)
+#define PTPEDMAC_EESR_TFUF_SHIFT                                               (19u)
+#define PTPEDMAC_EESR_TDE                                                      (0x00100000u)
+#define PTPEDMAC_EESR_TDE_SHIFT                                                (20u)
+#define PTPEDMAC_EESR_TC                                                       (0x00200000u)
+#define PTPEDMAC_EESR_TC_SHIFT                                                 (21u)
+#define PTPEDMAC_EESR_RFCOF                                                    (0x01000000u)
+#define PTPEDMAC_EESR_RFCOF_SHIFT                                              (24u)
+#define PTPEDMAC_EESR_TABT                                                     (0x04000000u)
+#define PTPEDMAC_EESR_TABT_SHIFT                                               (26u)
+#define PTPEDMAC_EESR_TWB                                                      (0x40000000u)
+#define PTPEDMAC_EESR_TWB_SHIFT                                                (30u)
+#define PTPEDMAC_EESIPR_PVERIP                                                 (0x00000010u)
+#define PTPEDMAC_EESIPR_PVERIP_SHIFT                                           (4u)
+#define PTPEDMAC_EESIPR_RPORTIP                                                (0x00000080u)
+#define PTPEDMAC_EESIPR_RPORTIP_SHIFT                                          (7u)
+#define PTPEDMAC_EESIPR_MACEIP                                                 (0x00000100u)
+#define PTPEDMAC_EESIPR_MACEIP_SHIFT                                           (8u)
+#define PTPEDMAC_EESIPR_RFOFIP                                                 (0x00010000u)
+#define PTPEDMAC_EESIPR_RFOFIP_SHIFT                                           (16u)
+#define PTPEDMAC_EESIPR_RDEIP                                                  (0x00020000u)
+#define PTPEDMAC_EESIPR_RDEIP_SHIFT                                            (17u)
+#define PTPEDMAC_EESIPR_FRIP                                                   (0x00040000u)
+#define PTPEDMAC_EESIPR_FRIP_SHIFT                                             (18u)
+#define PTPEDMAC_EESIPR_TFUFIP                                                 (0x00080000u)
+#define PTPEDMAC_EESIPR_TFUFIP_SHIFT                                           (19u)
+#define PTPEDMAC_EESIPR_TDEIP                                                  (0x00100000u)
+#define PTPEDMAC_EESIPR_TDEIP_SHIFT                                            (20u)
+#define PTPEDMAC_EESIPR_TCIP                                                   (0x00200000u)
+#define PTPEDMAC_EESIPR_TCIP_SHIFT                                             (21u)
+#define PTPEDMAC_EESIPR_RFCOFIP                                                (0x01000000u)
+#define PTPEDMAC_EESIPR_RFCOFIP_SHIFT                                          (24u)
+#define PTPEDMAC_EESIPR_TABTIP                                                 (0x04000000u)
+#define PTPEDMAC_EESIPR_TABTIP_SHIFT                                           (26u)
+#define PTPEDMAC_EESIPR_TWBIP                                                  (0x40000000u)
+#define PTPEDMAC_EESIPR_TWBIP_SHIFT                                            (30u)
+#define PTPEDMAC_RMFCR_MFC                                                     (0x0000FFFFu)
+#define PTPEDMAC_RMFCR_MFC_SHIFT                                               (0u)
+#define PTPEDMAC_TFTR_TFT                                                      (0x000007FFu)
+#define PTPEDMAC_TFTR_TFT_SHIFT                                                (0u)
+#define PTPEDMAC_FDR_RFD                                                       (0x0000001Fu)
+#define PTPEDMAC_FDR_RFD_SHIFT                                                 (0u)
+#define PTPEDMAC_FDR_TFD                                                       (0x00001F00u)
+#define PTPEDMAC_FDR_TFD_SHIFT                                                 (8u)
+#define PTPEDMAC_RMCR_RNR                                                      (0x00000001u)
+#define PTPEDMAC_RMCR_RNR_SHIFT                                                (0u)
+#define PTPEDMAC_TFUCR_UNDER                                                   (0x0000FFFFu)
+#define PTPEDMAC_TFUCR_UNDER_SHIFT                                             (0u)
+#define PTPEDMAC_RFOCR_OVER                                                    (0x0000FFFFu)
+#define PTPEDMAC_RFOCR_OVER_SHIFT                                              (0u)
+#define PTPEDMAC_FCFTR_RFDO                                                    (0x00000007u)
+#define PTPEDMAC_FCFTR_RFDO_SHIFT                                              (0u)
+#define PTPEDMAC_FCFTR_RFFO                                                    (0x00070000u)
+#define PTPEDMAC_FCFTR_RFFO_SHIFT                                              (16u)
+#define PTPEDMAC_RPADIR_PADR                                                   (0x0000003Fu)
+#define PTPEDMAC_RPADIR_PADR_SHIFT                                             (0u)
+#define PTPEDMAC_RPADIR_PADS                                                   (0x00030000u)
+#define PTPEDMAC_RPADIR_PADS_SHIFT                                             (16u)
+#define PTPEDMAC_TRIMD_TIS                                                     (0x00000001u)
+#define PTPEDMAC_TRIMD_TIS_SHIFT                                               (0u)
+#define PTPEDMAC_TRIMD_TIM                                                     (0x00000010u)
+#define PTPEDMAC_TRIMD_TIM_SHIFT                                               (4u)
+#define PTPEDMAC_RBWAR_RBWAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_RBWAR_RBWAR_SHIFT                                             (0u)
+#define PTPEDMAC_RDFAR_RDFAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_RDFAR_RDFAR_SHIFT                                             (0u)
+#define PTPEDMAC_TBRAR_TBRAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_TBRAR_TBRAR_SHIFT                                             (0u)
+#define PTPEDMAC_TDFAR_TDFAR                                                   (0xFFFFFFFFu)
+#define PTPEDMAC_TDFAR_TDFAR_SHIFT                                             (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/riic_iobitmask.h

@@ -0,0 +1,206 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef RIIC_IOBITMASK_H
+#define RIIC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define RIIC_ICCR1_SDAI                                                        (0x00000001u)
+#define RIIC_ICCR1_SDAI_SHIFT                                                  (0u)
+#define RIIC_ICCR1_SCLI                                                        (0x00000002u)
+#define RIIC_ICCR1_SCLI_SHIFT                                                  (1u)
+#define RIIC_ICCR1_SDAO                                                        (0x00000004u)
+#define RIIC_ICCR1_SDAO_SHIFT                                                  (2u)
+#define RIIC_ICCR1_SCLO                                                        (0x00000008u)
+#define RIIC_ICCR1_SCLO_SHIFT                                                  (3u)
+#define RIIC_ICCR1_SOWP                                                        (0x00000010u)
+#define RIIC_ICCR1_SOWP_SHIFT                                                  (4u)
+#define RIIC_ICCR1_CLO                                                         (0x00000020u)
+#define RIIC_ICCR1_CLO_SHIFT                                                   (5u)
+#define RIIC_ICCR1_IICRST                                                      (0x00000040u)
+#define RIIC_ICCR1_IICRST_SHIFT                                                (6u)
+#define RIIC_ICCR1_ICE                                                         (0x00000080u)
+#define RIIC_ICCR1_ICE_SHIFT                                                   (7u)
+#define RIIC_ICCR2_ST                                                          (0x00000002u)
+#define RIIC_ICCR2_ST_SHIFT                                                    (1u)
+#define RIIC_ICCR2_RS                                                          (0x00000004u)
+#define RIIC_ICCR2_RS_SHIFT                                                    (2u)
+#define RIIC_ICCR2_SP                                                          (0x00000008u)
+#define RIIC_ICCR2_SP_SHIFT                                                    (3u)
+#define RIIC_ICCR2_TRS                                                         (0x00000020u)
+#define RIIC_ICCR2_TRS_SHIFT                                                   (5u)
+#define RIIC_ICCR2_MST                                                         (0x00000040u)
+#define RIIC_ICCR2_MST_SHIFT                                                   (6u)
+#define RIIC_ICCR2_BBSY                                                        (0x00000080u)
+#define RIIC_ICCR2_BBSY_SHIFT                                                  (7u)
+#define RIIC_ICMR1_BC                                                          (0x00000007u)
+#define RIIC_ICMR1_BC_SHIFT                                                    (0u)
+#define RIIC_ICMR1_BCWP                                                        (0x00000008u)
+#define RIIC_ICMR1_BCWP_SHIFT                                                  (3u)
+#define RIIC_ICMR1_CKS                                                         (0x00000070u)
+#define RIIC_ICMR1_CKS_SHIFT                                                   (4u)
+#define RIIC_ICMR2_TMOS                                                        (0x00000001u)
+#define RIIC_ICMR2_TMOS_SHIFT                                                  (0u)
+#define RIIC_ICMR2_TMOL                                                        (0x00000002u)
+#define RIIC_ICMR2_TMOL_SHIFT                                                  (1u)
+#define RIIC_ICMR2_TMOH                                                        (0x00000004u)
+#define RIIC_ICMR2_TMOH_SHIFT                                                  (2u)
+#define RIIC_ICMR2_SDDL                                                        (0x00000070u)
+#define RIIC_ICMR2_SDDL_SHIFT                                                  (4u)
+#define RIIC_ICMR2_DLCS                                                        (0x00000080u)
+#define RIIC_ICMR2_DLCS_SHIFT                                                  (7u)
+#define RIIC_ICMR3_NF                                                          (0x00000003u)
+#define RIIC_ICMR3_NF_SHIFT                                                    (0u)
+#define RIIC_ICMR3_ACKBR                                                       (0x00000004u)
+#define RIIC_ICMR3_ACKBR_SHIFT                                                 (2u)
+#define RIIC_ICMR3_ACKBT                                                       (0x00000008u)
+#define RIIC_ICMR3_ACKBT_SHIFT                                                 (3u)
+#define RIIC_ICMR3_ACKWP                                                       (0x00000010u)
+#define RIIC_ICMR3_ACKWP_SHIFT                                                 (4u)
+#define RIIC_ICMR3_RDRFS                                                       (0x00000020u)
+#define RIIC_ICMR3_RDRFS_SHIFT                                                 (5u)
+#define RIIC_ICMR3_WAIT                                                        (0x00000040u)
+#define RIIC_ICMR3_WAIT_SHIFT                                                  (6u)
+#define RIIC_ICMR3_SMBE                                                        (0x00000080u)
+#define RIIC_ICMR3_SMBE_SHIFT                                                  (7u)
+#define RIIC_ICFER_TMOE                                                        (0x00000001u)
+#define RIIC_ICFER_TMOE_SHIFT                                                  (0u)
+#define RIIC_ICFER_MALE                                                        (0x00000002u)
+#define RIIC_ICFER_MALE_SHIFT                                                  (1u)
+#define RIIC_ICFER_NALE                                                        (0x00000004u)
+#define RIIC_ICFER_NALE_SHIFT                                                  (2u)
+#define RIIC_ICFER_SALE                                                        (0x00000008u)
+#define RIIC_ICFER_SALE_SHIFT                                                  (3u)
+#define RIIC_ICFER_NACKE                                                       (0x00000010u)
+#define RIIC_ICFER_NACKE_SHIFT                                                 (4u)
+#define RIIC_ICFER_NFE                                                         (0x00000020u)
+#define RIIC_ICFER_NFE_SHIFT                                                   (5u)
+#define RIIC_ICFER_SCLE                                                        (0x00000040u)
+#define RIIC_ICFER_SCLE_SHIFT                                                  (6u)
+#define RIIC_ICFER_FMPE                                                        (0x00000080u)
+#define RIIC_ICFER_FMPE_SHIFT                                                  (7u)
+#define RIIC_ICSER_SAR0                                                        (0x00000001u)
+#define RIIC_ICSER_SAR0_SHIFT                                                  (0u)
+#define RIIC_ICSER_SAR1                                                        (0x00000002u)
+#define RIIC_ICSER_SAR1_SHIFT                                                  (1u)
+#define RIIC_ICSER_SAR2                                                        (0x00000004u)
+#define RIIC_ICSER_SAR2_SHIFT                                                  (2u)
+#define RIIC_ICSER_GCE                                                         (0x00000008u)
+#define RIIC_ICSER_GCE_SHIFT                                                   (3u)
+#define RIIC_ICSER_DIDE                                                        (0x00000020u)
+#define RIIC_ICSER_DIDE_SHIFT                                                  (5u)
+#define RIIC_ICSER_HOAE                                                        (0x00000080u)
+#define RIIC_ICSER_HOAE_SHIFT                                                  (7u)
+#define RIIC_ICIER_TMOIE                                                       (0x00000001u)
+#define RIIC_ICIER_TMOIE_SHIFT                                                 (0u)
+#define RIIC_ICIER_ALIE                                                        (0x00000002u)
+#define RIIC_ICIER_ALIE_SHIFT                                                  (1u)
+#define RIIC_ICIER_STIE                                                        (0x00000004u)
+#define RIIC_ICIER_STIE_SHIFT                                                  (2u)
+#define RIIC_ICIER_SPIE                                                        (0x00000008u)
+#define RIIC_ICIER_SPIE_SHIFT                                                  (3u)
+#define RIIC_ICIER_NAKIE                                                       (0x00000010u)
+#define RIIC_ICIER_NAKIE_SHIFT                                                 (4u)
+#define RIIC_ICIER_RIE                                                         (0x00000020u)
+#define RIIC_ICIER_RIE_SHIFT                                                   (5u)
+#define RIIC_ICIER_TEIE                                                        (0x00000040u)
+#define RIIC_ICIER_TEIE_SHIFT                                                  (6u)
+#define RIIC_ICIER_TIE                                                         (0x00000080u)
+#define RIIC_ICIER_TIE_SHIFT                                                   (7u)
+#define RIIC_ICSR1_AAS0                                                        (0x00000001u)
+#define RIIC_ICSR1_AAS0_SHIFT                                                  (0u)
+#define RIIC_ICSR1_AAS1                                                        (0x00000002u)
+#define RIIC_ICSR1_AAS1_SHIFT                                                  (1u)
+#define RIIC_ICSR1_AAS2                                                        (0x00000004u)
+#define RIIC_ICSR1_AAS2_SHIFT                                                  (2u)
+#define RIIC_ICSR1_GCA                                                         (0x00000008u)
+#define RIIC_ICSR1_GCA_SHIFT                                                   (3u)
+#define RIIC_ICSR1_DID                                                         (0x00000020u)
+#define RIIC_ICSR1_DID_SHIFT                                                   (5u)
+#define RIIC_ICSR1_HOA                                                         (0x00000080u)
+#define RIIC_ICSR1_HOA_SHIFT                                                   (7u)
+#define RIIC_ICSR2_TMOF                                                        (0x00000001u)
+#define RIIC_ICSR2_TMOF_SHIFT                                                  (0u)
+#define RIIC_ICSR2_AL                                                          (0x00000002u)
+#define RIIC_ICSR2_AL_SHIFT                                                    (1u)
+#define RIIC_ICSR2_START                                                       (0x00000004u)
+#define RIIC_ICSR2_START_SHIFT                                                 (2u)
+#define RIIC_ICSR2_STOP                                                        (0x00000008u)
+#define RIIC_ICSR2_STOP_SHIFT                                                  (3u)
+#define RIIC_ICSR2_NACKF                                                       (0x00000010u)
+#define RIIC_ICSR2_NACKF_SHIFT                                                 (4u)
+#define RIIC_ICSR2_RDRF                                                        (0x00000020u)
+#define RIIC_ICSR2_RDRF_SHIFT                                                  (5u)
+#define RIIC_ICSR2_TEND                                                        (0x00000040u)
+#define RIIC_ICSR2_TEND_SHIFT                                                  (6u)
+#define RIIC_ICSR2_TDRE                                                        (0x00000080u)
+#define RIIC_ICSR2_TDRE_SHIFT                                                  (7u)
+#define RIIC_ICSAR0_SVA0                                                       (0x00000001u)
+#define RIIC_ICSAR0_SVA0_SHIFT                                                 (0u)
+#define RIIC_ICSAR0_SVA                                                        (0x000003FCu)
+#define RIIC_ICSAR0_SVA_SHIFT                                                  (1u)
+#define RIIC_ICSAR0_FS0                                                        (0x00008000u)
+#define RIIC_ICSAR0_FS0_SHIFT                                                  (15u)
+#define RIIC_ICSAR1_SVA0                                                       (0x00000001u)
+#define RIIC_ICSAR1_SVA0_SHIFT                                                 (0u)
+#define RIIC_ICSAR1_SVA                                                        (0x000003FCu)
+#define RIIC_ICSAR1_SVA_SHIFT                                                  (1u)
+#define RIIC_ICSAR1_FS1                                                        (0x00008000u)
+#define RIIC_ICSAR1_FS1_SHIFT                                                  (15u)
+#define RIIC_ICSAR2_SVA0                                                       (0x00000001u)
+#define RIIC_ICSAR2_SVA0_SHIFT                                                 (0u)
+#define RIIC_ICSAR2_SVA                                                        (0x000003FCu)
+#define RIIC_ICSAR2_SVA_SHIFT                                                  (1u)
+#define RIIC_ICSAR2_FS2                                                        (0x00008000u)
+#define RIIC_ICSAR2_FS2_SHIFT                                                  (15u)
+#define RIIC_ICBRL_BRL                                                         (0x0000001Fu)
+#define RIIC_ICBRL_BRL_SHIFT                                                   (0u)
+#define RIIC_ICBRH_BRH                                                         (0x0000001Fu)
+#define RIIC_ICBRH_BRH_SHIFT                                                   (0u)
+#define RIIC_ICDRT_DRT                                                         (0x000000FFu)
+#define RIIC_ICDRT_DRT_SHIFT                                                   (0u)
+#define RIIC_ICDRR_DRR                                                         (0x000000FFu)
+#define RIIC_ICDRR_DRR_SHIFT                                                   (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rspi_iobitmask.h

@@ -0,0 +1,308 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef RSPI_IOBITMASK_H
+#define RSPI_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define RSPI_SPCR_MODFEN                                                       (0x04u)
+#define RSPI_SPCR_MODFEN_SHIFT                                                 (2u)
+#define RSPI_SPCR_MSTR                                                         (0x08u)
+#define RSPI_SPCR_MSTR_SHIFT                                                   (3u)
+#define RSPI_SPCR_SPEIE                                                        (0x10u)
+#define RSPI_SPCR_SPEIE_SHIFT                                                  (4u)
+#define RSPI_SPCR_SPTIE                                                        (0x20u)
+#define RSPI_SPCR_SPTIE_SHIFT                                                  (5u)
+#define RSPI_SPCR_SPE                                                          (0x40u)
+#define RSPI_SPCR_SPE_SHIFT                                                    (6u)
+#define RSPI_SPCR_SPRIE                                                        (0x80u)
+#define RSPI_SPCR_SPRIE_SHIFT                                                  (7u)
+#define RSPI_SSLP_SSL0P                                                        (0x01u)
+#define RSPI_SSLP_SSL0P_SHIFT                                                  (0u)
+#define RSPI_SPPCR_SPLP                                                        (0x01u)
+#define RSPI_SPPCR_SPLP_SHIFT                                                  (0u)
+#define RSPI_SPPCR_MOIFV                                                       (0x10u)
+#define RSPI_SPPCR_MOIFV_SHIFT                                                 (4u)
+#define RSPI_SPPCR_MOIFE                                                       (0x20u)
+#define RSPI_SPPCR_MOIFE_SHIFT                                                 (5u)
+#define RSPI_SPSR_OVRF                                                         (0x01u)
+#define RSPI_SPSR_OVRF_SHIFT                                                   (0u)
+#define RSPI_SPSR_MODF                                                         (0x04u)
+#define RSPI_SPSR_MODF_SHIFT                                                   (2u)
+#define RSPI_SPSR_SPTEF                                                        (0x20u)
+#define RSPI_SPSR_SPTEF_SHIFT                                                  (5u)
+#define RSPI_SPSR_TEND                                                         (0x40u)
+#define RSPI_SPSR_TEND_SHIFT                                                   (6u)
+#define RSPI_SPSR_SPRF                                                         (0x80u)
+#define RSPI_SPSR_SPRF_SHIFT                                                   (7u)
+#define RSPI_SPDR_SPD0                                                         (0x00000001u)
+#define RSPI_SPDR_SPD0_SHIFT                                                   (0u)
+#define RSPI_SPDR_SPD1                                                         (0x00000002u)
+#define RSPI_SPDR_SPD1_SHIFT                                                   (1u)
+#define RSPI_SPDR_SPD2                                                         (0x00000004u)
+#define RSPI_SPDR_SPD2_SHIFT                                                   (2u)
+#define RSPI_SPDR_SPD3                                                         (0x00000008u)
+#define RSPI_SPDR_SPD3_SHIFT                                                   (3u)
+#define RSPI_SPDR_SPD4                                                         (0x00000010u)
+#define RSPI_SPDR_SPD4_SHIFT                                                   (4u)
+#define RSPI_SPDR_SPD5                                                         (0x00000020u)
+#define RSPI_SPDR_SPD5_SHIFT                                                   (5u)
+#define RSPI_SPDR_SPD6                                                         (0x00000040u)
+#define RSPI_SPDR_SPD6_SHIFT                                                   (6u)
+#define RSPI_SPDR_SPD7                                                         (0x00000080u)
+#define RSPI_SPDR_SPD7_SHIFT                                                   (7u)
+#define RSPI_SPDR_SPD8                                                         (0x00000100u)
+#define RSPI_SPDR_SPD8_SHIFT                                                   (8u)
+#define RSPI_SPDR_SPD9                                                         (0x00000200u)
+#define RSPI_SPDR_SPD9_SHIFT                                                   (9u)
+#define RSPI_SPDR_SPD10                                                        (0x00000400u)
+#define RSPI_SPDR_SPD10_SHIFT                                                  (10u)
+#define RSPI_SPDR_SPD11                                                        (0x00000800u)
+#define RSPI_SPDR_SPD11_SHIFT                                                  (11u)
+#define RSPI_SPDR_SPD12                                                        (0x00001000u)
+#define RSPI_SPDR_SPD12_SHIFT                                                  (12u)
+#define RSPI_SPDR_SPD13                                                        (0x00002000u)
+#define RSPI_SPDR_SPD13_SHIFT                                                  (13u)
+#define RSPI_SPDR_SPD14                                                        (0x00004000u)
+#define RSPI_SPDR_SPD14_SHIFT                                                  (14u)
+#define RSPI_SPDR_SPD15                                                        (0x00008000u)
+#define RSPI_SPDR_SPD15_SHIFT                                                  (15u)
+#define RSPI_SPDR_SPD16                                                        (0x00010000u)
+#define RSPI_SPDR_SPD16_SHIFT                                                  (16u)
+#define RSPI_SPDR_SPD17                                                        (0x00020000u)
+#define RSPI_SPDR_SPD17_SHIFT                                                  (17u)
+#define RSPI_SPDR_SPD18                                                        (0x00040000u)
+#define RSPI_SPDR_SPD18_SHIFT                                                  (18u)
+#define RSPI_SPDR_SPD19                                                        (0x00080000u)
+#define RSPI_SPDR_SPD19_SHIFT                                                  (19u)
+#define RSPI_SPDR_SPD20                                                        (0x00100000u)
+#define RSPI_SPDR_SPD20_SHIFT                                                  (20u)
+#define RSPI_SPDR_SPD21                                                        (0x00200000u)
+#define RSPI_SPDR_SPD21_SHIFT                                                  (21u)
+#define RSPI_SPDR_SPD22                                                        (0x00400000u)
+#define RSPI_SPDR_SPD22_SHIFT                                                  (22u)
+#define RSPI_SPDR_SPD23                                                        (0x00800000u)
+#define RSPI_SPDR_SPD23_SHIFT                                                  (23u)
+#define RSPI_SPDR_SPD24                                                        (0x01000000u)
+#define RSPI_SPDR_SPD24_SHIFT                                                  (24u)
+#define RSPI_SPDR_SPD25                                                        (0x02000000u)
+#define RSPI_SPDR_SPD25_SHIFT                                                  (25u)
+#define RSPI_SPDR_SPD26                                                        (0x04000000u)
+#define RSPI_SPDR_SPD26_SHIFT                                                  (26u)
+#define RSPI_SPDR_SPD27                                                        (0x08000000u)
+#define RSPI_SPDR_SPD27_SHIFT                                                  (27u)
+#define RSPI_SPDR_SPD28                                                        (0x10000000u)
+#define RSPI_SPDR_SPD28_SHIFT                                                  (28u)
+#define RSPI_SPDR_SPD29                                                        (0x20000000u)
+#define RSPI_SPDR_SPD29_SHIFT                                                  (29u)
+#define RSPI_SPDR_SPD30                                                        (0x40000000u)
+#define RSPI_SPDR_SPD30_SHIFT                                                  (30u)
+#define RSPI_SPDR_SPD31                                                        (0x80000000u)
+#define RSPI_SPDR_SPD31_SHIFT                                                  (31u)
+#define RSPI_SPSCR_SPSLN0                                                      (0x01u)
+#define RSPI_SPSCR_SPSLN0_SHIFT                                                (0u)
+#define RSPI_SPSCR_SPSLN1                                                      (0x02u)
+#define RSPI_SPSCR_SPSLN1_SHIFT                                                (1u)
+#define RSPI_SPSSR_SPCP0                                                       (0x01u)
+#define RSPI_SPSSR_SPCP0_SHIFT                                                 (0u)
+#define RSPI_SPSSR_SPCP1                                                       (0x02u)
+#define RSPI_SPSSR_SPCP1_SHIFT                                                 (1u)
+#define RSPI_SPBR_SPR0                                                         (0x01u)
+#define RSPI_SPBR_SPR0_SHIFT                                                   (0u)
+#define RSPI_SPBR_SPR1                                                         (0x02u)
+#define RSPI_SPBR_SPR1_SHIFT                                                   (1u)
+#define RSPI_SPBR_SPR2                                                         (0x04u)
+#define RSPI_SPBR_SPR2_SHIFT                                                   (2u)
+#define RSPI_SPBR_SPR3                                                         (0x08u)
+#define RSPI_SPBR_SPR3_SHIFT                                                   (3u)
+#define RSPI_SPBR_SPR4                                                         (0x10u)
+#define RSPI_SPBR_SPR4_SHIFT                                                   (4u)
+#define RSPI_SPBR_SPR5                                                         (0x20u)
+#define RSPI_SPBR_SPR5_SHIFT                                                   (5u)
+#define RSPI_SPBR_SPR6                                                         (0x40u)
+#define RSPI_SPBR_SPR6_SHIFT                                                   (6u)
+#define RSPI_SPBR_SPR7                                                         (0x80u)
+#define RSPI_SPBR_SPR7_SHIFT                                                   (7u)
+#define RSPI_SPDCR_SPLW0                                                       (0x20u)
+#define RSPI_SPDCR_SPLW0_SHIFT                                                 (5u)
+#define RSPI_SPDCR_SPLW1                                                       (0x40u)
+#define RSPI_SPDCR_SPLW1_SHIFT                                                 (6u)
+#define RSPI_SPDCR_TXDMY                                                       (0x80u)
+#define RSPI_SPDCR_TXDMY_SHIFT                                                 (7u)
+#define RSPI_SPCKD_SCKDL0                                                      (0x01u)
+#define RSPI_SPCKD_SCKDL0_SHIFT                                                (0u)
+#define RSPI_SPCKD_SCKDL1                                                      (0x02u)
+#define RSPI_SPCKD_SCKDL1_SHIFT                                                (1u)
+#define RSPI_SPCKD_SCKDL2                                                      (0x04u)
+#define RSPI_SPCKD_SCKDL2_SHIFT                                                (2u)
+#define RSPI_SSLND_SLNDL0                                                      (0x01u)
+#define RSPI_SSLND_SLNDL0_SHIFT                                                (0u)
+#define RSPI_SSLND_SLNDL1                                                      (0x02u)
+#define RSPI_SSLND_SLNDL1_SHIFT                                                (1u)
+#define RSPI_SSLND_SLNDL2                                                      (0x04u)
+#define RSPI_SSLND_SLNDL2_SHIFT                                                (2u)
+#define RSPI_SPND_SPNDL0                                                       (0x01u)
+#define RSPI_SPND_SPNDL0_SHIFT                                                 (0u)
+#define RSPI_SPND_SPNDL1                                                       (0x02u)
+#define RSPI_SPND_SPNDL1_SHIFT                                                 (1u)
+#define RSPI_SPND_SPNDL2                                                       (0x04u)
+#define RSPI_SPND_SPNDL2_SHIFT                                                 (2u)
+#define RSPI_SPCMD0_CPHA                                                       (0x0001u)
+#define RSPI_SPCMD0_CPHA_SHIFT                                                 (0u)
+#define RSPI_SPCMD0_CPOL                                                       (0x0002u)
+#define RSPI_SPCMD0_CPOL_SHIFT                                                 (1u)
+#define RSPI_SPCMD0_BRDV0                                                      (0x0004u)
+#define RSPI_SPCMD0_BRDV0_SHIFT                                                (2u)
+#define RSPI_SPCMD0_BRDV1                                                      (0x0008u)
+#define RSPI_SPCMD0_BRDV1_SHIFT                                                (3u)
+#define RSPI_SPCMD0_SSLKP                                                      (0x0080u)
+#define RSPI_SPCMD0_SSLKP_SHIFT                                                (7u)
+#define RSPI_SPCMD0_SPB0                                                       (0x0100u)
+#define RSPI_SPCMD0_SPB0_SHIFT                                                 (8u)
+#define RSPI_SPCMD0_SPB1                                                       (0x0200u)
+#define RSPI_SPCMD0_SPB1_SHIFT                                                 (9u)
+#define RSPI_SPCMD0_SPB2                                                       (0x0400u)
+#define RSPI_SPCMD0_SPB2_SHIFT                                                 (10u)
+#define RSPI_SPCMD0_SPB3                                                       (0x0800u)
+#define RSPI_SPCMD0_SPB3_SHIFT                                                 (11u)
+#define RSPI_SPCMD0_LSBF                                                       (0x1000u)
+#define RSPI_SPCMD0_LSBF_SHIFT                                                 (12u)
+#define RSPI_SPCMD0_SPNDEN                                                     (0x2000u)
+#define RSPI_SPCMD0_SPNDEN_SHIFT                                               (13u)
+#define RSPI_SPCMD0_SLNDEN                                                     (0x4000u)
+#define RSPI_SPCMD0_SLNDEN_SHIFT                                               (14u)
+#define RSPI_SPCMD0_SCKDEN                                                     (0x8000u)
+#define RSPI_SPCMD0_SCKDEN_SHIFT                                               (15u)
+#define RSPI_SPCMD1_CPHA                                                       (0x0001u)
+#define RSPI_SPCMD1_CPHA_SHIFT                                                 (0u)
+#define RSPI_SPCMD1_CPOL                                                       (0x0002u)
+#define RSPI_SPCMD1_CPOL_SHIFT                                                 (1u)
+#define RSPI_SPCMD1_BRDV0                                                      (0x0004u)
+#define RSPI_SPCMD1_BRDV0_SHIFT                                                (2u)
+#define RSPI_SPCMD1_BRDV1                                                      (0x0008u)
+#define RSPI_SPCMD1_BRDV1_SHIFT                                                (3u)
+#define RSPI_SPCMD1_SSLKP                                                      (0x0080u)
+#define RSPI_SPCMD1_SSLKP_SHIFT                                                (7u)
+#define RSPI_SPCMD1_SPB0                                                       (0x0100u)
+#define RSPI_SPCMD1_SPB0_SHIFT                                                 (8u)
+#define RSPI_SPCMD1_SPB1                                                       (0x0200u)
+#define RSPI_SPCMD1_SPB1_SHIFT                                                 (9u)
+#define RSPI_SPCMD1_SPB2                                                       (0x0400u)
+#define RSPI_SPCMD1_SPB2_SHIFT                                                 (10u)
+#define RSPI_SPCMD1_SPB3                                                       (0x0800u)
+#define RSPI_SPCMD1_SPB3_SHIFT                                                 (11u)
+#define RSPI_SPCMD1_LSBF                                                       (0x1000u)
+#define RSPI_SPCMD1_LSBF_SHIFT                                                 (12u)
+#define RSPI_SPCMD1_SPNDEN                                                     (0x2000u)
+#define RSPI_SPCMD1_SPNDEN_SHIFT                                               (13u)
+#define RSPI_SPCMD1_SLNDEN                                                     (0x4000u)
+#define RSPI_SPCMD1_SLNDEN_SHIFT                                               (14u)
+#define RSPI_SPCMD1_SCKDEN                                                     (0x8000u)
+#define RSPI_SPCMD1_SCKDEN_SHIFT                                               (15u)
+#define RSPI_SPCMD2_CPHA                                                       (0x0001u)
+#define RSPI_SPCMD2_CPHA_SHIFT                                                 (0u)
+#define RSPI_SPCMD2_CPOL                                                       (0x0002u)
+#define RSPI_SPCMD2_CPOL_SHIFT                                                 (1u)
+#define RSPI_SPCMD2_BRDV0                                                      (0x0004u)
+#define RSPI_SPCMD2_BRDV0_SHIFT                                                (2u)
+#define RSPI_SPCMD2_BRDV1                                                      (0x0008u)
+#define RSPI_SPCMD2_BRDV1_SHIFT                                                (3u)
+#define RSPI_SPCMD2_SSLKP                                                      (0x0080u)
+#define RSPI_SPCMD2_SSLKP_SHIFT                                                (7u)
+#define RSPI_SPCMD2_SPB0                                                       (0x0100u)
+#define RSPI_SPCMD2_SPB0_SHIFT                                                 (8u)
+#define RSPI_SPCMD2_SPB1                                                       (0x0200u)
+#define RSPI_SPCMD2_SPB1_SHIFT                                                 (9u)
+#define RSPI_SPCMD2_SPB2                                                       (0x0400u)
+#define RSPI_SPCMD2_SPB2_SHIFT                                                 (10u)
+#define RSPI_SPCMD2_SPB3                                                       (0x0800u)
+#define RSPI_SPCMD2_SPB3_SHIFT                                                 (11u)
+#define RSPI_SPCMD2_LSBF                                                       (0x1000u)
+#define RSPI_SPCMD2_LSBF_SHIFT                                                 (12u)
+#define RSPI_SPCMD2_SPNDEN                                                     (0x2000u)
+#define RSPI_SPCMD2_SPNDEN_SHIFT                                               (13u)
+#define RSPI_SPCMD2_SLNDEN                                                     (0x4000u)
+#define RSPI_SPCMD2_SLNDEN_SHIFT                                               (14u)
+#define RSPI_SPCMD2_SCKDEN                                                     (0x8000u)
+#define RSPI_SPCMD2_SCKDEN_SHIFT                                               (15u)
+#define RSPI_SPCMD3_CPHA                                                       (0x0001u)
+#define RSPI_SPCMD3_CPHA_SHIFT                                                 (0u)
+#define RSPI_SPCMD3_CPOL                                                       (0x0002u)
+#define RSPI_SPCMD3_CPOL_SHIFT                                                 (1u)
+#define RSPI_SPCMD3_BRDV0                                                      (0x0004u)
+#define RSPI_SPCMD3_BRDV0_SHIFT                                                (2u)
+#define RSPI_SPCMD3_BRDV1                                                      (0x0008u)
+#define RSPI_SPCMD3_BRDV1_SHIFT                                                (3u)
+#define RSPI_SPCMD3_SSLKP                                                      (0x0080u)
+#define RSPI_SPCMD3_SSLKP_SHIFT                                                (7u)
+#define RSPI_SPCMD3_SPB0                                                       (0x0100u)
+#define RSPI_SPCMD3_SPB0_SHIFT                                                 (8u)
+#define RSPI_SPCMD3_SPB1                                                       (0x0200u)
+#define RSPI_SPCMD3_SPB1_SHIFT                                                 (9u)
+#define RSPI_SPCMD3_SPB2                                                       (0x0400u)
+#define RSPI_SPCMD3_SPB2_SHIFT                                                 (10u)
+#define RSPI_SPCMD3_SPB3                                                       (0x0800u)
+#define RSPI_SPCMD3_SPB3_SHIFT                                                 (11u)
+#define RSPI_SPCMD3_LSBF                                                       (0x1000u)
+#define RSPI_SPCMD3_LSBF_SHIFT                                                 (12u)
+#define RSPI_SPCMD3_SPNDEN                                                     (0x2000u)
+#define RSPI_SPCMD3_SPNDEN_SHIFT                                               (13u)
+#define RSPI_SPCMD3_SLNDEN                                                     (0x4000u)
+#define RSPI_SPCMD3_SLNDEN_SHIFT                                               (14u)
+#define RSPI_SPCMD3_SCKDEN                                                     (0x8000u)
+#define RSPI_SPCMD3_SCKDEN_SHIFT                                               (15u)
+#define RSPI_SPBFCR_RXTRG                                                      (0x07u)
+#define RSPI_SPBFCR_RXTRG_SHIFT                                                (0u)
+#define RSPI_SPBFCR_TXTRG                                                      (0x30u)
+#define RSPI_SPBFCR_TXTRG_SHIFT                                                (4u)
+#define RSPI_SPBFCR_RXRST                                                      (0x40u)
+#define RSPI_SPBFCR_RXRST_SHIFT                                                (6u)
+#define RSPI_SPBFCR_TXRST                                                      (0x80u)
+#define RSPI_SPBFCR_TXRST_SHIFT                                                (7u)
+#define RSPI_SPBFDR_R                                                          (0x003Fu)
+#define RSPI_SPBFDR_R_SHIFT                                                    (0u)
+#define RSPI_SPBFDR_T                                                          (0x0F00u)
+#define RSPI_SPBFDR_T_SHIFT                                                    (8u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rtc_iobitmask.h

@@ -0,0 +1,198 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef RTC_IOBITMASK_H
+#define RTC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define RTC_R64CNT_F64HZ                                                       (0x01u)
+#define RTC_R64CNT_F64HZ_SHIFT                                                 (0u)
+#define RTC_R64CNT_F32HZ                                                       (0x02u)
+#define RTC_R64CNT_F32HZ_SHIFT                                                 (1u)
+#define RTC_R64CNT_F16HZ                                                       (0x04u)
+#define RTC_R64CNT_F16HZ_SHIFT                                                 (2u)
+#define RTC_R64CNT_F8HZ                                                        (0x08u)
+#define RTC_R64CNT_F8HZ_SHIFT                                                  (3u)
+#define RTC_R64CNT_F4HZ                                                        (0x10u)
+#define RTC_R64CNT_F4HZ_SHIFT                                                  (4u)
+#define RTC_R64CNT_F2HZ                                                        (0x20u)
+#define RTC_R64CNT_F2HZ_SHIFT                                                  (5u)
+#define RTC_R64CNT_F1HZ                                                        (0x40u)
+#define RTC_R64CNT_F1HZ_SHIFT                                                  (6u)
+#define RTC_RSECCNT_SEC1                                                       (0x0Fu)
+#define RTC_RSECCNT_SEC1_SHIFT                                                 (0u)
+#define RTC_RSECCNT_SEC10                                                      (0x70u)
+#define RTC_RSECCNT_SEC10_SHIFT                                                (4u)
+#define RTC_RMINCNT_MIN1                                                       (0x0Fu)
+#define RTC_RMINCNT_MIN1_SHIFT                                                 (0u)
+#define RTC_RMINCNT_MIN10                                                      (0x70u)
+#define RTC_RMINCNT_MIN10_SHIFT                                                (4u)
+#define RTC_RHRCNT_HR1                                                         (0x0Fu)
+#define RTC_RHRCNT_HR1_SHIFT                                                   (0u)
+#define RTC_RHRCNT_HR10                                                        (0x30u)
+#define RTC_RHRCNT_HR10_SHIFT                                                  (4u)
+#define RTC_RHRCNT_PM                                                          (0x40u)
+#define RTC_RHRCNT_PM_SHIFT                                                    (6u)
+#define RTC_RWKCNT_DAYW                                                        (0x07u)
+#define RTC_RWKCNT_DAYW_SHIFT                                                  (0u)
+#define RTC_RDAYCNT_DATE1                                                      (0x0Fu)
+#define RTC_RDAYCNT_DATE1_SHIFT                                                (0u)
+#define RTC_RDAYCNT_DATE10                                                     (0x30u)
+#define RTC_RDAYCNT_DATE10_SHIFT                                               (4u)
+#define RTC_RMONCNT_MON1                                                       (0x0Fu)
+#define RTC_RMONCNT_MON1_SHIFT                                                 (0u)
+#define RTC_RMONCNT_MON10                                                      (0x10u)
+#define RTC_RMONCNT_MON10_SHIFT                                                (4u)
+#define RTC_RYRCNT_YR1                                                         (0x000Fu)
+#define RTC_RYRCNT_YR1_SHIFT                                                   (0u)
+#define RTC_RYRCNT_YR10                                                        (0x00F0u)
+#define RTC_RYRCNT_YR10_SHIFT                                                  (4u)
+#define RTC_RSECAR_SEC1                                                        (0x0Fu)
+#define RTC_RSECAR_SEC1_SHIFT                                                  (0u)
+#define RTC_RSECAR_SEC10                                                       (0x70u)
+#define RTC_RSECAR_SEC10_SHIFT                                                 (4u)
+#define RTC_RSECAR_ENB                                                         (0x80u)
+#define RTC_RSECAR_ENB_SHIFT                                                   (7u)
+#define RTC_RMINAR_MIN1                                                        (0x0Fu)
+#define RTC_RMINAR_MIN1_SHIFT                                                  (0u)
+#define RTC_RMINAR_MIN10                                                       (0x70u)
+#define RTC_RMINAR_MIN10_SHIFT                                                 (4u)
+#define RTC_RMINAR_ENB                                                         (0x80u)
+#define RTC_RMINAR_ENB_SHIFT                                                   (7u)
+#define RTC_RHRAR_HR1                                                          (0x0Fu)
+#define RTC_RHRAR_HR1_SHIFT                                                    (0u)
+#define RTC_RHRAR_HR10                                                         (0x30u)
+#define RTC_RHRAR_HR10_SHIFT                                                   (4u)
+#define RTC_RHRAR_PM                                                           (0x40u)
+#define RTC_RHRAR_PM_SHIFT                                                     (6u)
+#define RTC_RHRAR_ENB                                                          (0x80u)
+#define RTC_RHRAR_ENB_SHIFT                                                    (7u)
+#define RTC_RWKAR_DAYW                                                         (0x07u)
+#define RTC_RWKAR_DAYW_SHIFT                                                   (0u)
+#define RTC_RWKAR_ENB                                                          (0x80u)
+#define RTC_RWKAR_ENB_SHIFT                                                    (7u)
+#define RTC_RDAYAR_DATE1                                                       (0x0Fu)
+#define RTC_RDAYAR_DATE1_SHIFT                                                 (0u)
+#define RTC_RDAYAR_DATE10                                                      (0x30u)
+#define RTC_RDAYAR_DATE10_SHIFT                                                (4u)
+#define RTC_RDAYAR_ENB                                                         (0x80u)
+#define RTC_RDAYAR_ENB_SHIFT                                                   (7u)
+#define RTC_RMONAR_MON1                                                        (0x0Fu)
+#define RTC_RMONAR_MON1_SHIFT                                                  (0u)
+#define RTC_RMONAR_MON10                                                       (0x10u)
+#define RTC_RMONAR_MON10_SHIFT                                                 (4u)
+#define RTC_RMONAR_ENB                                                         (0x80u)
+#define RTC_RMONAR_ENB_SHIFT                                                   (7u)
+#define RTC_RYRAR_YR1                                                          (0x000Fu)
+#define RTC_RYRAR_YR1_SHIFT                                                    (0u)
+#define RTC_RYRAR_YR10                                                         (0x00F0u)
+#define RTC_RYRAR_YR10_SHIFT                                                   (4u)
+#define RTC_RYRAREN_ENB                                                        (0x80u)
+#define RTC_RYRAREN_ENB_SHIFT                                                  (7u)
+#define RTC_RSR_AF                                                             (0x01u)
+#define RTC_RSR_AF_SHIFT                                                       (0u)
+#define RTC_RSR_CF                                                             (0x02u)
+#define RTC_RSR_CF_SHIFT                                                       (1u)
+#define RTC_RSR_PF                                                             (0x04u)
+#define RTC_RSR_PF_SHIFT                                                       (2u)
+#define RTC_RCR1_AIE                                                           (0x01u)
+#define RTC_RCR1_AIE_SHIFT                                                     (0u)
+#define RTC_RCR1_CIE                                                           (0x02u)
+#define RTC_RCR1_CIE_SHIFT                                                     (1u)
+#define RTC_RCR1_PIE                                                           (0x04u)
+#define RTC_RCR1_PIE_SHIFT                                                     (2u)
+#define RTC_RCR1_PES                                                           (0xF0u)
+#define RTC_RCR1_PES_SHIFT                                                     (4u)
+#define RTC_RCR2_START                                                         (0x01u)
+#define RTC_RCR2_START_SHIFT                                                   (0u)
+#define RTC_RCR2_RESET                                                         (0x02u)
+#define RTC_RCR2_RESET_SHIFT                                                   (1u)
+#define RTC_RCR2_ADJ30                                                         (0x04u)
+#define RTC_RCR2_ADJ30_SHIFT                                                   (2u)
+#define RTC_RCR2_AADJE                                                         (0x10u)
+#define RTC_RCR2_AADJE_SHIFT                                                   (4u)
+#define RTC_RCR2_AADJP                                                         (0x20u)
+#define RTC_RCR2_AADJP_SHIFT                                                   (5u)
+#define RTC_RCR2_HR24                                                          (0x40u)
+#define RTC_RCR2_HR24_SHIFT                                                    (6u)
+#define RTC_RCR2_CNTMD                                                         (0x80u)
+#define RTC_RCR2_CNTMD_SHIFT                                                   (7u)
+#define RTC_RCR3_RTCEN                                                         (0x01u)
+#define RTC_RCR3_RTCEN_SHIFT                                                   (0u)
+#define RTC_RCR4_RCKSEL                                                        (0x01u)
+#define RTC_RCR4_RCKSEL_SHIFT                                                  (0u)
+#define RTC_RFRH_RFC                                                           (0x0001u)
+#define RTC_RFRH_RFC_SHIFT                                                     (0u)
+#define RTC_RFRL_RFC                                                           (0xFFFFu)
+#define RTC_RFRL_RFC_SHIFT                                                     (0u)
+#define RTC_RADJ_ADJ                                                           (0x3Fu)
+#define RTC_RADJ_ADJ_SHIFT                                                     (0u)
+#define RTC_RADJ_PMADJ                                                         (0xC0u)
+#define RTC_RADJ_PMADJ_SHIFT                                                   (6u)
+#define RTC_BCNT0_BCNT                                                         (0xFFu)
+#define RTC_BCNT0_BCNT_SHIFT                                                   (0u)
+#define RTC_BCNT1_BCNT                                                         (0x00u)
+#define RTC_BCNT1_BCNT_SHIFT                                                   (0u)
+#define RTC_BCNT2_BCNT                                                         (0x00u)
+#define RTC_BCNT2_BCNT_SHIFT                                                   (0u)
+#define RTC_BCNT3_BCNT                                                         (0x00u)
+#define RTC_BCNT3_BCNT_SHIFT                                                   (0u)
+#define RTC_BCNT0AR_BCNTAR                                                     (0xFFu)
+#define RTC_BCNT0AR_BCNTAR_SHIFT                                               (0u)
+#define RTC_BCNT1AR_BCNTAR                                                     (0x00u)
+#define RTC_BCNT1AR_BCNTAR_SHIFT                                               (0u)
+#define RTC_BCNT2AR_BCNTAR                                                     (0x00u)
+#define RTC_BCNT2AR_BCNTAR_SHIFT                                               (0u)
+#define RTC_BCNT3AR_BCNTAR                                                     (0x00u)
+#define RTC_BCNT3AR_BCNTAR_SHIFT                                               (0u)
+#define RTC_BCNT0AER_ENB                                                       (0xFFu)
+#define RTC_BCNT0AER_ENB_SHIFT                                                 (0u)
+#define RTC_BCNT1AER_ENB                                                       (0x00u)
+#define RTC_BCNT1AER_ENB_SHIFT                                                 (0u)
+#define RTC_BCNT2AER_ENB                                                       (0x0000u)
+#define RTC_BCNT2AER_ENB_SHIFT                                                 (0u)
+#define RTC_BCNT3AER_ENB                                                       (0x00u)
+#define RTC_BCNT3AER_ENB_SHIFT                                                 (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scifa_iobitmask.h

@@ -0,0 +1,160 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SCIFA_IOBITMASK_H
+#define SCIFA_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SCIFA_SMR_CKS                                                          (0x0003u)
+#define SCIFA_SMR_CKS_SHIFT                                                    (0u)
+#define SCIFA_SMR_STOP                                                         (0x0008u)
+#define SCIFA_SMR_STOP_SHIFT                                                   (3u)
+#define SCIFA_SMR_PM                                                           (0x0010u)
+#define SCIFA_SMR_PM_SHIFT                                                     (4u)
+#define SCIFA_SMR_PE                                                           (0x0020u)
+#define SCIFA_SMR_PE_SHIFT                                                     (5u)
+#define SCIFA_SMR_CHR                                                          (0x0040u)
+#define SCIFA_SMR_CHR_SHIFT                                                    (6u)
+#define SCIFA_SMR_CM                                                           (0x0080u)
+#define SCIFA_SMR_CM_SHIFT                                                     (7u)
+#define SCIFA_MDDR_MDDR                                                        (0xFFu)
+#define SCIFA_MDDR_MDDR_SHIFT                                                  (0u)
+#define SCIFA_BRR_BRR                                                          (0xFFu)
+#define SCIFA_BRR_BRR_SHIFT                                                    (0u)
+#define SCIFA_SCR_CKE                                                          (0x0003u)
+#define SCIFA_SCR_CKE_SHIFT                                                    (0u)
+#define SCIFA_SCR_TEIE                                                         (0x0004u)
+#define SCIFA_SCR_TEIE_SHIFT                                                   (2u)
+#define SCIFA_SCR_REIE                                                         (0x0008u)
+#define SCIFA_SCR_REIE_SHIFT                                                   (3u)
+#define SCIFA_SCR_RE                                                           (0x0010u)
+#define SCIFA_SCR_RE_SHIFT                                                     (4u)
+#define SCIFA_SCR_TE                                                           (0x0020u)
+#define SCIFA_SCR_TE_SHIFT                                                     (5u)
+#define SCIFA_SCR_RIE                                                          (0x0040u)
+#define SCIFA_SCR_RIE_SHIFT                                                    (6u)
+#define SCIFA_SCR_TIE                                                          (0x0080u)
+#define SCIFA_SCR_TIE_SHIFT                                                    (7u)
+#define SCIFA_FTDR_FTDR                                                        (0xFFu)
+#define SCIFA_FTDR_FTDR_SHIFT                                                  (0u)
+#define SCIFA_FSR_DR                                                           (0x0001u)
+#define SCIFA_FSR_DR_SHIFT                                                     (0u)
+#define SCIFA_FSR_RDF                                                          (0x0002u)
+#define SCIFA_FSR_RDF_SHIFT                                                    (1u)
+#define SCIFA_FSR_PER                                                          (0x0004u)
+#define SCIFA_FSR_PER_SHIFT                                                    (2u)
+#define SCIFA_FSR_FER                                                          (0x0008u)
+#define SCIFA_FSR_FER_SHIFT                                                    (3u)
+#define SCIFA_FSR_BRK                                                          (0x0010u)
+#define SCIFA_FSR_BRK_SHIFT                                                    (4u)
+#define SCIFA_FSR_TDFE                                                         (0x0020u)
+#define SCIFA_FSR_TDFE_SHIFT                                                   (5u)
+#define SCIFA_FSR_TEND                                                         (0x0040u)
+#define SCIFA_FSR_TEND_SHIFT                                                   (6u)
+#define SCIFA_FSR_ER                                                           (0x0080u)
+#define SCIFA_FSR_ER_SHIFT                                                     (7u)
+#define SCIFA_FRDR_FRDR                                                        (0xFFu)
+#define SCIFA_FRDR_FRDR_SHIFT                                                  (0u)
+#define SCIFA_FCR_LOOP                                                         (0x0001u)
+#define SCIFA_FCR_LOOP_SHIFT                                                   (0u)
+#define SCIFA_FCR_RFRST                                                        (0x0002u)
+#define SCIFA_FCR_RFRST_SHIFT                                                  (1u)
+#define SCIFA_FCR_TFRST                                                        (0x0004u)
+#define SCIFA_FCR_TFRST_SHIFT                                                  (2u)
+#define SCIFA_FCR_MCE                                                          (0x0008u)
+#define SCIFA_FCR_MCE_SHIFT                                                    (3u)
+#define SCIFA_FCR_TTRG                                                         (0x0030u)
+#define SCIFA_FCR_TTRG_SHIFT                                                   (4u)
+#define SCIFA_FCR_RTRG                                                         (0x00C0u)
+#define SCIFA_FCR_RTRG_SHIFT                                                   (6u)
+#define SCIFA_FCR_RSTRG                                                        (0x0700u)
+#define SCIFA_FCR_RSTRG_SHIFT                                                  (8u)
+#define SCIFA_FDR_R                                                            (0x001Fu)
+#define SCIFA_FDR_R_SHIFT                                                      (0u)
+#define SCIFA_FDR_T                                                            (0x1F00u)
+#define SCIFA_FDR_T_SHIFT                                                      (8u)
+#define SCIFA_SPTR_SPB2DT                                                      (0x0001u)
+#define SCIFA_SPTR_SPB2DT_SHIFT                                                (0u)
+#define SCIFA_SPTR_SPB2IO                                                      (0x0002u)
+#define SCIFA_SPTR_SPB2IO_SHIFT                                                (1u)
+#define SCIFA_SPTR_SCKDT                                                       (0x0004u)
+#define SCIFA_SPTR_SCKDT_SHIFT                                                 (2u)
+#define SCIFA_SPTR_SCKIO                                                       (0x0008u)
+#define SCIFA_SPTR_SCKIO_SHIFT                                                 (3u)
+#define SCIFA_SPTR_CTS2DT                                                      (0x0010u)
+#define SCIFA_SPTR_CTS2DT_SHIFT                                                (4u)
+#define SCIFA_SPTR_CTS2IO                                                      (0x0020u)
+#define SCIFA_SPTR_CTS2IO_SHIFT                                                (5u)
+#define SCIFA_SPTR_RTS2DT                                                      (0x0040u)
+#define SCIFA_SPTR_RTS2DT_SHIFT                                                (6u)
+#define SCIFA_SPTR_RTS2IO                                                      (0x0080u)
+#define SCIFA_SPTR_RTS2IO_SHIFT                                                (7u)
+#define SCIFA_LSR_ORER                                                         (0x0001u)
+#define SCIFA_LSR_ORER_SHIFT                                                   (0u)
+#define SCIFA_LSR_FER                                                          (0x003Cu)
+#define SCIFA_LSR_FER_SHIFT                                                    (2u)
+#define SCIFA_LSR_PER                                                          (0x0F00u)
+#define SCIFA_LSR_PER_SHIFT                                                    (8u)
+#define SCIFA_SEMR_ABCS0                                                       (0x01u)
+#define SCIFA_SEMR_ABCS0_SHIFT                                                 (0u)
+#define SCIFA_SEMR_NFEN                                                        (0x04u)
+#define SCIFA_SEMR_NFEN_SHIFT                                                  (2u)
+#define SCIFA_SEMR_DIR                                                         (0x08u)
+#define SCIFA_SEMR_DIR_SHIFT                                                   (3u)
+#define SCIFA_SEMR_MDDRS                                                       (0x10u)
+#define SCIFA_SEMR_MDDRS_SHIFT                                                 (4u)
+#define SCIFA_SEMR_BRME                                                        (0x20u)
+#define SCIFA_SEMR_BRME_SHIFT                                                  (5u)
+#define SCIFA_SEMR_BGDM                                                        (0x80u)
+#define SCIFA_SEMR_BGDM_SHIFT                                                  (7u)
+#define SCIFA_FTCR_TFTC                                                        (0x001Fu)
+#define SCIFA_FTCR_TFTC_SHIFT                                                  (0u)
+#define SCIFA_FTCR_TTRGS                                                       (0x0080u)
+#define SCIFA_FTCR_TTRGS_SHIFT                                                 (7u)
+#define SCIFA_FTCR_RFTC                                                        (0x1F00u)
+#define SCIFA_FTCR_RFTC_SHIFT                                                  (8u)
+#define SCIFA_FTCR_RTRGS                                                       (0x8000u)
+#define SCIFA_FTCR_RTRGS_SHIFT                                                 (15u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scim_iobitmask.h

@@ -0,0 +1,140 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SCIM_IOBITMASK_H
+#define SCIM_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SCIM_SMR_CKS                                                           (0x03u)
+#define SCIM_SMR_CKS_SHIFT                                                     (0u)
+#define SCIM_SMR_MP                                                            (0x04u)
+#define SCIM_SMR_MP_SHIFT                                                      (2u)
+#define SCIM_SMR_STOP                                                          (0x08u)
+#define SCIM_SMR_STOP_SHIFT                                                    (3u)
+#define SCIM_SMR_PM                                                            (0x10u)
+#define SCIM_SMR_PM_SHIFT                                                      (4u)
+#define SCIM_SMR_PE                                                            (0x20u)
+#define SCIM_SMR_PE_SHIFT                                                      (5u)
+#define SCIM_SMR_CHR                                                           (0x40u)
+#define SCIM_SMR_CHR_SHIFT                                                     (6u)
+#define SCIM_SMR_CM                                                            (0x80u)
+#define SCIM_SMR_CM_SHIFT                                                      (7u)
+#define SCIM_BRR_BRR                                                           (0xFFu)
+#define SCIM_BRR_BRR_SHIFT                                                     (0u)
+#define SCIM_SCR_CKE                                                           (0x03u)
+#define SCIM_SCR_CKE_SHIFT                                                     (0u)
+#define SCIM_SCR_TEIE                                                          (0x04u)
+#define SCIM_SCR_TEIE_SHIFT                                                    (2u)
+#define SCIM_SCR_MPIE                                                          (0x08u)
+#define SCIM_SCR_MPIE_SHIFT                                                    (3u)
+#define SCIM_SCR_RE                                                            (0x10u)
+#define SCIM_SCR_RE_SHIFT                                                      (4u)
+#define SCIM_SCR_TE                                                            (0x20u)
+#define SCIM_SCR_TE_SHIFT                                                      (5u)
+#define SCIM_SCR_RIE                                                           (0x40u)
+#define SCIM_SCR_RIE_SHIFT                                                     (6u)
+#define SCIM_SCR_TIE                                                           (0x80u)
+#define SCIM_SCR_TIE_SHIFT                                                     (7u)
+#define SCIM_TDR_TDR                                                           (0xFFu)
+#define SCIM_TDR_TDR_SHIFT                                                     (0u)
+#define SCIM_SSR_MPBT                                                          (0x01u)
+#define SCIM_SSR_MPBT_SHIFT                                                    (0u)
+#define SCIM_SSR_MPB                                                           (0x02u)
+#define SCIM_SSR_MPB_SHIFT                                                     (1u)
+#define SCIM_SSR_TEND                                                          (0x04u)
+#define SCIM_SSR_TEND_SHIFT                                                    (2u)
+#define SCIM_SSR_PER                                                           (0x08u)
+#define SCIM_SSR_PER_SHIFT                                                     (3u)
+#define SCIM_SSR_FER                                                           (0x10u)
+#define SCIM_SSR_FER_SHIFT                                                     (4u)
+#define SCIM_SSR_ORER                                                          (0x20u)
+#define SCIM_SSR_ORER_SHIFT                                                    (5u)
+#define SCIM_SSR_RDRF                                                          (0x40u)
+#define SCIM_SSR_RDRF_SHIFT                                                    (6u)
+#define SCIM_SSR_TDRE                                                          (0x80u)
+#define SCIM_SSR_TDRE_SHIFT                                                    (7u)
+#define SCIM_RDR_RDR                                                           (0xFFu)
+#define SCIM_RDR_RDR_SHIFT                                                     (0u)
+#define SCIM_SCMR_SMIF                                                         (0x01u)
+#define SCIM_SCMR_SMIF_SHIFT                                                   (0u)
+#define SCIM_SCMR_SINV                                                         (0x04u)
+#define SCIM_SCMR_SINV_SHIFT                                                   (2u)
+#define SCIM_SCMR_SDIR                                                         (0x08u)
+#define SCIM_SCMR_SDIR_SHIFT                                                   (3u)
+#define SCIM_SCMR_CHR1                                                         (0x10u)
+#define SCIM_SCMR_CHR1_SHIFT                                                   (4u)
+#define SCIM_SCMR_BCP2                                                         (0x80u)
+#define SCIM_SCMR_BCP2_SHIFT                                                   (7u)
+#define SCIM_SEMR_ACS0                                                         (0x01u)
+#define SCIM_SEMR_ACS0_SHIFT                                                   (0u)
+#define SCIM_SEMR_BRME                                                         (0x04u)
+#define SCIM_SEMR_BRME_SHIFT                                                   (2u)
+#define SCIM_SEMR_ABCS                                                         (0x10u)
+#define SCIM_SEMR_ABCS_SHIFT                                                   (4u)
+#define SCIM_SEMR_NFEN                                                         (0x20u)
+#define SCIM_SEMR_NFEN_SHIFT                                                   (5u)
+#define SCIM_SEMR_BGDM                                                         (0x40u)
+#define SCIM_SEMR_BGDM_SHIFT                                                   (6u)
+#define SCIM_SEMR_RXDESEL                                                      (0x80u)
+#define SCIM_SEMR_RXDESEL_SHIFT                                                (7u)
+#define SCIM_SNFR_NFCS                                                         (0x07u)
+#define SCIM_SNFR_NFCS_SHIFT                                                   (0u)
+#define SCIM_SECR_CTSE                                                         (0x02u)
+#define SCIM_SECR_CTSE_SHIFT                                                   (1u)
+#define SCIM_TDRHL_TDRHL                                                       (0xFFFFu)
+#define SCIM_TDRHL_TDRHL_SHIFT                                                 (0u)
+#define SCIM_TDRH_TDRH                                                         (0xFFu)
+#define SCIM_TDRH_TDRH_SHIFT                                                   (0u)
+#define SCIM_TDRL_TDRL                                                         (0xFFu)
+#define SCIM_TDRL_TDRL_SHIFT                                                   (0u)
+#define SCIM_RDRHL_RDRHL                                                       (0xFFFFu)
+#define SCIM_RDRHL_RDRHL_SHIFT                                                 (0u)
+#define SCIM_RDRH_RDRH                                                         (0xFFu)
+#define SCIM_RDRH_RDRH_SHIFT                                                   (0u)
+#define SCIM_RDRL_RDRL                                                         (0xFFu)
+#define SCIM_RDRL_RDRL_SHIFT                                                   (0u)
+#define SCIM_MDDR_MDDR                                                         (0xFFu)
+#define SCIM_MDDR_MDDR_SHIFT                                                   (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sdmmc_iobitmask.h

@@ -0,0 +1,362 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SDMMC_IOBITMASK_H
+#define SDMMC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SDMMC_SCC_DTCNTL_TAPEN                                                 (0x00000001u)
+#define SDMMC_SCC_DTCNTL_TAPEN_SHIFT                                           (0u)
+#define SDMMC_SCC_DTCNTL_TAPNUM                                                (0x00000000u)
+#define SDMMC_SCC_DTCNTL_TAPNUM_SHIFT                                          (16u)
+#define SDMMC_SCC_TAPSET_TAPSET                                                (0x000000FFu)
+#define SDMMC_SCC_TAPSET_TAPSET_SHIFT                                          (0u)
+#define SDMMC_SCC_DT2FF_DT2NSSET                                               (0x000000FFu)
+#define SDMMC_SCC_DT2FF_DT2NSSET_SHIFT                                         (0u)
+#define SDMMC_SCC_DT2FF_DT2NESET                                               (0x0000FF00u)
+#define SDMMC_SCC_DT2FF_DT2NESET_SHIFT                                         (8u)
+#define SDMMC_SCC_CKSEL_DTSEL                                                  (0x00000001u)
+#define SDMMC_SCC_CKSEL_DTSEL_SHIFT                                            (0u)
+#define SDMMC_SCC_RVSCNTL_RVSEN                                                (0x00000001u)
+#define SDMMC_SCC_RVSCNTL_RVSEN_SHIFT                                          (0u)
+#define SDMMC_SCC_RVSCNTL_RVSW                                                 (0x00000002u)
+#define SDMMC_SCC_RVSCNTL_RVSW_SHIFT                                           (1u)
+#define SDMMC_SCC_RVSCNTL_TAPSEL                                               (0x0000FF00u)
+#define SDMMC_SCC_RVSCNTL_TAPSEL_SHIFT                                         (8u)
+#define SDMMC_SCC_RVSREQ_REQTAPDWN                                             (0x00000001u)
+#define SDMMC_SCC_RVSREQ_REQTAPDWN_SHIFT                                       (0u)
+#define SDMMC_SCC_RVSREQ_REQTAPUP                                              (0x00000002u)
+#define SDMMC_SCC_RVSREQ_REQTAPUP_SHIFT                                        (1u)
+#define SDMMC_SCC_RVSREQ_RVSERR                                                (0x00000004u)
+#define SDMMC_SCC_RVSREQ_RVSERR_SHIFT                                          (2u)
+#define SDMMC_SCC_SMPCMP_CMPNGD                                                (0x000001FFu)
+#define SDMMC_SCC_SMPCMP_CMPNGD_SHIFT                                          (0u)
+#define SDMMC_SCC_SMPCMP_CMPNGU                                                (0x01FF0000u)
+#define SDMMC_SCC_SMPCMP_CMPNGU_SHIFT                                          (16u)
+#define SDMMC_SD_CMD_CF                                                        (0x0000000000000000u)
+#define SDMMC_SD_CMD_CF_SHIFT                                                  (0u)
+#define SDMMC_SD_CMD_C0                                                        (0x0000000000000040u)
+#define SDMMC_SD_CMD_C0_SHIFT                                                  (6u)
+#define SDMMC_SD_CMD_C1                                                        (0x0000000000000080u)
+#define SDMMC_SD_CMD_C1_SHIFT                                                  (7u)
+#define SDMMC_SD_CMD_MD0                                                       (0x0000000000000100u)
+#define SDMMC_SD_CMD_MD0_SHIFT                                                 (8u)
+#define SDMMC_SD_CMD_MD1                                                       (0x0000000000000200u)
+#define SDMMC_SD_CMD_MD1_SHIFT                                                 (9u)
+#define SDMMC_SD_CMD_MD2                                                       (0x0000000000000400u)
+#define SDMMC_SD_CMD_MD2_SHIFT                                                 (10u)
+#define SDMMC_SD_CMD_MD3                                                       (0x0000000000000800u)
+#define SDMMC_SD_CMD_MD3_SHIFT                                                 (11u)
+#define SDMMC_SD_CMD_MD4                                                       (0x0000000000001000u)
+#define SDMMC_SD_CMD_MD4_SHIFT                                                 (12u)
+#define SDMMC_SD_CMD_MD5                                                       (0x0000000000002000u)
+#define SDMMC_SD_CMD_MD5_SHIFT                                                 (13u)
+#define SDMMC_SD_CMD_MD6                                                       (0x0000000000004000u)
+#define SDMMC_SD_CMD_MD6_SHIFT                                                 (14u)
+#define SDMMC_SD_CMD_MD7                                                       (0x0000000000008000u)
+#define SDMMC_SD_CMD_MD7_SHIFT                                                 (15u)
+#define SDMMC_SD_ARG_CF                                                        (0x00000000FFFFFF00u)
+#define SDMMC_SD_ARG_CF_SHIFT                                                  (0u)
+#define SDMMC_SD_ARG1_CF                                                       (0x0000000000000000u)
+#define SDMMC_SD_ARG1_CF_SHIFT                                                 (0u)
+#define SDMMC_SD_STOP_STP                                                      (0x0000000000000001u)
+#define SDMMC_SD_STOP_STP_SHIFT                                                (0u)
+#define SDMMC_SD_STOP_SEC                                                      (0x0000000000000100u)
+#define SDMMC_SD_STOP_SEC_SHIFT                                                (8u)
+#define SDMMC_SD_STOP_HPICMD                                                   (0x0000000000010000u)
+#define SDMMC_SD_STOP_HPICMD_SHIFT                                             (16u)
+#define SDMMC_SD_STOP_HPIMODE                                                  (0x0000000000020000u)
+#define SDMMC_SD_STOP_HPIMODE_SHIFT                                            (17u)
+#define SDMMC_SD_SECCNT_CNT                                                    (0x00000000FFFFFFFFu)
+#define SDMMC_SD_SECCNT_CNT_SHIFT                                              (0u)
+#define SDMMC_SD_RSP10_R                                                       (0xFFFFFFFFFFFFFF00u)
+#define SDMMC_SD_RSP10_R_SHIFT                                                 (0u)
+#define SDMMC_SD_RSP1_R                                                        (0x0000000000000000u)
+#define SDMMC_SD_RSP1_R_SHIFT                                                  (0u)
+#define SDMMC_SD_RSP32_R                                                       (0x0000000000000000u)
+#define SDMMC_SD_RSP32_R_SHIFT                                                 (0u)
+#define SDMMC_SD_RSP3_R                                                        (0x0000000000000000u)
+#define SDMMC_SD_RSP3_R_SHIFT                                                  (0u)
+#define SDMMC_SD_RSP54_R                                                       (0x0000000000000000u)
+#define SDMMC_SD_RSP54_R_SHIFT                                                 (0u)
+#define SDMMC_SD_RSP5_R                                                        (0x0000000000000000u)
+#define SDMMC_SD_RSP5_R_SHIFT                                                  (0u)
+#define SDMMC_SD_RSP76_R                                                       (0x0000000000000000u)
+#define SDMMC_SD_RSP76_R_SHIFT                                                 (0u)
+#define SDMMC_SD_RSP7_R                                                        (0x0000000000000000u)
+#define SDMMC_SD_RSP7_R_SHIFT                                                  (0u)
+#define SDMMC_SD_INFO1_INFO0                                                   (0x0000000000000001u)
+#define SDMMC_SD_INFO1_INFO0_SHIFT                                             (0u)
+#define SDMMC_SD_INFO1_INFO2                                                   (0x0000000000000004u)
+#define SDMMC_SD_INFO1_INFO2_SHIFT                                             (2u)
+#define SDMMC_SD_INFO1_INFO3                                                   (0x0000000000000008u)
+#define SDMMC_SD_INFO1_INFO3_SHIFT                                             (3u)
+#define SDMMC_SD_INFO1_INFO4                                                   (0x0000000000000010u)
+#define SDMMC_SD_INFO1_INFO4_SHIFT                                             (4u)
+#define SDMMC_SD_INFO1_INFO5                                                   (0x0000000000000020u)
+#define SDMMC_SD_INFO1_INFO5_SHIFT                                             (5u)
+#define SDMMC_SD_INFO1_INFO7                                                   (0x0000000000000080u)
+#define SDMMC_SD_INFO1_INFO7_SHIFT                                             (7u)
+#define SDMMC_SD_INFO1_INFO8                                                   (0x0000000000000100u)
+#define SDMMC_SD_INFO1_INFO8_SHIFT                                             (8u)
+#define SDMMC_SD_INFO1_INFO9                                                   (0x0000000000000200u)
+#define SDMMC_SD_INFO1_INFO9_SHIFT                                             (9u)
+#define SDMMC_SD_INFO1_INFO10                                                  (0x0000000000000400u)
+#define SDMMC_SD_INFO1_INFO10_SHIFT                                            (10u)
+#define SDMMC_SD_INFO1_HPIRES                                                  (0x0000000000010000u)
+#define SDMMC_SD_INFO1_HPIRES_SHIFT                                            (16u)
+#define SDMMC_SD_INFO2_ERR0                                                    (0x0000000000000001u)
+#define SDMMC_SD_INFO2_ERR0_SHIFT                                              (0u)
+#define SDMMC_SD_INFO2_ERR1                                                    (0x0000000000000002u)
+#define SDMMC_SD_INFO2_ERR1_SHIFT                                              (1u)
+#define SDMMC_SD_INFO2_ERR2                                                    (0x0000000000000004u)
+#define SDMMC_SD_INFO2_ERR2_SHIFT                                              (2u)
+#define SDMMC_SD_INFO2_ERR3                                                    (0x0000000000000008u)
+#define SDMMC_SD_INFO2_ERR3_SHIFT                                              (3u)
+#define SDMMC_SD_INFO2_ERR4                                                    (0x0000000000000010u)
+#define SDMMC_SD_INFO2_ERR4_SHIFT                                              (4u)
+#define SDMMC_SD_INFO2_ERR5                                                    (0x0000000000000020u)
+#define SDMMC_SD_INFO2_ERR5_SHIFT                                              (5u)
+#define SDMMC_SD_INFO2_ERR6                                                    (0x0000000000000040u)
+#define SDMMC_SD_INFO2_ERR6_SHIFT                                              (6u)
+#define SDMMC_SD_INFO2_DAT0                                                    (0x0000000000000080u)
+#define SDMMC_SD_INFO2_DAT0_SHIFT                                              (7u)
+#define SDMMC_SD_INFO2_BRE                                                     (0x0000000000000100u)
+#define SDMMC_SD_INFO2_BRE_SHIFT                                               (8u)
+#define SDMMC_SD_INFO2_BWE                                                     (0x0000000000000200u)
+#define SDMMC_SD_INFO2_BWE_SHIFT                                               (9u)
+#define SDMMC_SD_INFO2_SCLKDIVEN                                               (0x0000000000002000u)
+#define SDMMC_SD_INFO2_SCLKDIVEN_SHIFT                                         (13u)
+#define SDMMC_SD_INFO2_CBSY                                                    (0x0000000000004000u)
+#define SDMMC_SD_INFO2_CBSY_SHIFT                                              (14u)
+#define SDMMC_SD_INFO2_ILA                                                     (0x0000000000008000u)
+#define SDMMC_SD_INFO2_ILA_SHIFT                                               (15u)
+#define SDMMC_SD_INFO1_MASK_IMASK0                                             (0x0000000000000001u)
+#define SDMMC_SD_INFO1_MASK_IMASK0_SHIFT                                       (0u)
+#define SDMMC_SD_INFO1_MASK_IMASK2                                             (0x0000000000000004u)
+#define SDMMC_SD_INFO1_MASK_IMASK2_SHIFT                                       (2u)
+#define SDMMC_SD_INFO1_MASK_IMASK3                                             (0x0000000000000008u)
+#define SDMMC_SD_INFO1_MASK_IMASK3_SHIFT                                       (3u)
+#define SDMMC_SD_INFO1_MASK_IMASK4                                             (0x0000000000000010u)
+#define SDMMC_SD_INFO1_MASK_IMASK4_SHIFT                                       (4u)
+#define SDMMC_SD_INFO1_MASK_IMASK8                                             (0x0000000000000100u)
+#define SDMMC_SD_INFO1_MASK_IMASK8_SHIFT                                       (8u)
+#define SDMMC_SD_INFO1_MASK_IMASK9                                             (0x0000000000000200u)
+#define SDMMC_SD_INFO1_MASK_IMASK9_SHIFT                                       (9u)
+#define SDMMC_SD_INFO1_MASK_IMASK16                                            (0x0000000000010000u)
+#define SDMMC_SD_INFO1_MASK_IMASK16_SHIFT                                      (16u)
+#define SDMMC_SD_INFO2_MASK_EMASK0                                             (0x0000000000000001u)
+#define SDMMC_SD_INFO2_MASK_EMASK0_SHIFT                                       (0u)
+#define SDMMC_SD_INFO2_MASK_EMASK1                                             (0x0000000000000002u)
+#define SDMMC_SD_INFO2_MASK_EMASK1_SHIFT                                       (1u)
+#define SDMMC_SD_INFO2_MASK_EMASK2                                             (0x0000000000000004u)
+#define SDMMC_SD_INFO2_MASK_EMASK2_SHIFT                                       (2u)
+#define SDMMC_SD_INFO2_MASK_EMASK3                                             (0x0000000000000008u)
+#define SDMMC_SD_INFO2_MASK_EMASK3_SHIFT                                       (3u)
+#define SDMMC_SD_INFO2_MASK_EMASK4                                             (0x0000000000000010u)
+#define SDMMC_SD_INFO2_MASK_EMASK4_SHIFT                                       (4u)
+#define SDMMC_SD_INFO2_MASK_EMASK5                                             (0x0000000000000020u)
+#define SDMMC_SD_INFO2_MASK_EMASK5_SHIFT                                       (5u)
+#define SDMMC_SD_INFO2_MASK_EMASK6                                             (0x0000000000000040u)
+#define SDMMC_SD_INFO2_MASK_EMASK6_SHIFT                                       (6u)
+#define SDMMC_SD_INFO2_MASK_BMASK0                                             (0x0000000000000100u)
+#define SDMMC_SD_INFO2_MASK_BMASK0_SHIFT                                       (8u)
+#define SDMMC_SD_INFO2_MASK_BMASK1                                             (0x0000000000000200u)
+#define SDMMC_SD_INFO2_MASK_BMASK1_SHIFT                                       (9u)
+#define SDMMC_SD_INFO2_MASK_IMASK                                              (0x0000000000008000u)
+#define SDMMC_SD_INFO2_MASK_IMASK_SHIFT                                        (15u)
+#define SDMMC_SD_CLK_CTRL_DIV                                                  (0x00000000000000FFu)
+#define SDMMC_SD_CLK_CTRL_DIV_SHIFT                                            (0u)
+#define SDMMC_SD_CLK_CTRL_SCLKEN                                               (0x0000000000000100u)
+#define SDMMC_SD_CLK_CTRL_SCLKEN_SHIFT                                         (8u)
+#define SDMMC_SD_CLK_CTRL_SDCLKOFFEN                                           (0x0000000000000200u)
+#define SDMMC_SD_CLK_CTRL_SDCLKOFFEN_SHIFT                                     (9u)
+#define SDMMC_SD_SIZE_LEN                                                      (0x00000000000003FFu)
+#define SDMMC_SD_SIZE_LEN_SHIFT                                                (0u)
+#define SDMMC_SD_OPTION_CTOP21                                                 (0x0000000000000001u)
+#define SDMMC_SD_OPTION_CTOP21_SHIFT                                           (0u)
+#define SDMMC_SD_OPTION_CTOP22                                                 (0x0000000000000002u)
+#define SDMMC_SD_OPTION_CTOP22_SHIFT                                           (1u)
+#define SDMMC_SD_OPTION_CTOP23                                                 (0x0000000000000004u)
+#define SDMMC_SD_OPTION_CTOP23_SHIFT                                           (2u)
+#define SDMMC_SD_OPTION_CTOP24                                                 (0x0000000000000008u)
+#define SDMMC_SD_OPTION_CTOP24_SHIFT                                           (3u)
+#define SDMMC_SD_OPTION_TOP24                                                  (0x0000000000000010u)
+#define SDMMC_SD_OPTION_TOP24_SHIFT                                            (4u)
+#define SDMMC_SD_OPTION_TOP25                                                  (0x0000000000000020u)
+#define SDMMC_SD_OPTION_TOP25_SHIFT                                            (5u)
+#define SDMMC_SD_OPTION_TOP26                                                  (0x0000000000000040u)
+#define SDMMC_SD_OPTION_TOP26_SHIFT                                            (6u)
+#define SDMMC_SD_OPTION_TOP27                                                  (0x0000000000000080u)
+#define SDMMC_SD_OPTION_TOP27_SHIFT                                            (7u)
+#define SDMMC_SD_OPTION_TOUTMASK                                               (0x0000000000000100u)
+#define SDMMC_SD_OPTION_TOUTMASK_SHIFT                                         (8u)
+#define SDMMC_SD_OPTION_EXTOP                                                  (0x0000000000000200u)
+#define SDMMC_SD_OPTION_EXTOP_SHIFT                                            (9u)
+#define SDMMC_SD_OPTION_WIDTH8                                                 (0x0000000000002000u)
+#define SDMMC_SD_OPTION_WIDTH8_SHIFT                                           (13u)
+#define SDMMC_SD_OPTION_WIDTH                                                  (0x0000000000008000u)
+#define SDMMC_SD_OPTION_WIDTH_SHIFT                                            (15u)
+#define SDMMC_SD_ERR_STS1_E0                                                   (0x0000000000000001u)
+#define SDMMC_SD_ERR_STS1_E0_SHIFT                                             (0u)
+#define SDMMC_SD_ERR_STS1_E1                                                   (0x0000000000000002u)
+#define SDMMC_SD_ERR_STS1_E1_SHIFT                                             (1u)
+#define SDMMC_SD_ERR_STS1_E2                                                   (0x0000000000000004u)
+#define SDMMC_SD_ERR_STS1_E2_SHIFT                                             (2u)
+#define SDMMC_SD_ERR_STS1_E3                                                   (0x0000000000000008u)
+#define SDMMC_SD_ERR_STS1_E3_SHIFT                                             (3u)
+#define SDMMC_SD_ERR_STS1_E4                                                   (0x0000000000000010u)
+#define SDMMC_SD_ERR_STS1_E4_SHIFT                                             (4u)
+#define SDMMC_SD_ERR_STS1_E5                                                   (0x0000000000000020u)
+#define SDMMC_SD_ERR_STS1_E5_SHIFT                                             (5u)
+#define SDMMC_SD_ERR_STS1_E8                                                   (0x0000000000000100u)
+#define SDMMC_SD_ERR_STS1_E8_SHIFT                                             (8u)
+#define SDMMC_SD_ERR_STS1_E9                                                   (0x0000000000000200u)
+#define SDMMC_SD_ERR_STS1_E9_SHIFT                                             (9u)
+#define SDMMC_SD_ERR_STS1_E10                                                  (0x0000000000000400u)
+#define SDMMC_SD_ERR_STS1_E10_SHIFT                                            (10u)
+#define SDMMC_SD_ERR_STS1_E11                                                  (0x0000000000000800u)
+#define SDMMC_SD_ERR_STS1_E11_SHIFT                                            (11u)
+#define SDMMC_SD_ERR_STS1_E12                                                  (0x0000000000001000u)
+#define SDMMC_SD_ERR_STS1_E12_SHIFT                                            (12u)
+#define SDMMC_SD_ERR_STS1_E13                                                  (0x0000000000002000u)
+#define SDMMC_SD_ERR_STS1_E13_SHIFT                                            (13u)
+#define SDMMC_SD_ERR_STS1_E14                                                  (0x0000000000004000u)
+#define SDMMC_SD_ERR_STS1_E14_SHIFT                                            (14u)
+#define SDMMC_SD_ERR_STS2_E0                                                   (0x0000000000000001u)
+#define SDMMC_SD_ERR_STS2_E0_SHIFT                                             (0u)
+#define SDMMC_SD_ERR_STS2_E1                                                   (0x0000000000000002u)
+#define SDMMC_SD_ERR_STS2_E1_SHIFT                                             (1u)
+#define SDMMC_SD_ERR_STS2_E2                                                   (0x0000000000000004u)
+#define SDMMC_SD_ERR_STS2_E2_SHIFT                                             (2u)
+#define SDMMC_SD_ERR_STS2_E3                                                   (0x0000000000000008u)
+#define SDMMC_SD_ERR_STS2_E3_SHIFT                                             (3u)
+#define SDMMC_SD_ERR_STS2_E4                                                   (0x0000000000000010u)
+#define SDMMC_SD_ERR_STS2_E4_SHIFT                                             (4u)
+#define SDMMC_SD_ERR_STS2_E5                                                   (0x0000000000000020u)
+#define SDMMC_SD_ERR_STS2_E5_SHIFT                                             (5u)
+#define SDMMC_SD_ERR_STS2_E6                                                   (0x0000000000000040u)
+#define SDMMC_SD_ERR_STS2_E6_SHIFT                                             (6u)
+#define SDMMC_SD_BUF0_BUF                                                      (0xFFFFFFFFFFFFFFFFu)
+#define SDMMC_SD_BUF0_BUF_SHIFT                                                (0u)
+#define SDMMC_SDIO_MODE_IOMOD                                                  (0x0000000000000001u)
+#define SDMMC_SDIO_MODE_IOMOD_SHIFT                                            (0u)
+#define SDMMC_SDIO_MODE_RWREQ                                                  (0x0000000000000004u)
+#define SDMMC_SDIO_MODE_RWREQ_SHIFT                                            (2u)
+#define SDMMC_SDIO_MODE_IOABT                                                  (0x0000000000000100u)
+#define SDMMC_SDIO_MODE_IOABT_SHIFT                                            (8u)
+#define SDMMC_SDIO_MODE_C52PUB                                                 (0x0000000000000200u)
+#define SDMMC_SDIO_MODE_C52PUB_SHIFT                                           (9u)
+#define SDMMC_SDIO_INFO1_IOIRQ                                                 (0x0000000000000001u)
+#define SDMMC_SDIO_INFO1_IOIRQ_SHIFT                                           (0u)
+#define SDMMC_SDIO_INFO1_EXPUB52                                               (0x0000000000004000u)
+#define SDMMC_SDIO_INFO1_EXPUB52_SHIFT                                         (14u)
+#define SDMMC_SDIO_INFO1_EXWT                                                  (0x0000000000008000u)
+#define SDMMC_SDIO_INFO1_EXWT_SHIFT                                            (15u)
+#define SDMMC_SDIO_INFO1_MASK_IOMSK                                            (0x0000000000000001u)
+#define SDMMC_SDIO_INFO1_MASK_IOMSK_SHIFT                                      (0u)
+#define SDMMC_SDIO_INFO1_MASK_MEXPUB52                                         (0x0000000000004000u)
+#define SDMMC_SDIO_INFO1_MASK_MEXPUB52_SHIFT                                   (14u)
+#define SDMMC_SDIO_INFO1_MASK_MEXWT                                            (0x0000000000008000u)
+#define SDMMC_SDIO_INFO1_MASK_MEXWT_SHIFT                                      (15u)
+#define SDMMC_CC_EXT_MODE_DMASDRW                                              (0x0000000000000002u)
+#define SDMMC_CC_EXT_MODE_DMASDRW_SHIFT                                        (1u)
+#define SDMMC_SOFT_RST_SDRST                                                   (0x0000000000000001u)
+#define SDMMC_SOFT_RST_SDRST_SHIFT                                             (0u)
+#define SDMMC_VERSION_IP                                                       (0x00000000000000FFu)
+#define SDMMC_VERSION_IP_SHIFT                                                 (0u)
+#define SDMMC_VERSION_UR                                                       (0x000000000000FF00u)
+#define SDMMC_VERSION_UR_SHIFT                                                 (8u)
+#define SDMMC_HOST_MODE_WMODE                                                  (0x0000000000000001u)
+#define SDMMC_HOST_MODE_WMODE_SHIFT                                            (0u)
+#define SDMMC_HOST_MODE_ENDIAN                                                 (0x0000000000000002u)
+#define SDMMC_HOST_MODE_ENDIAN_SHIFT                                           (1u)
+#define SDMMC_HOST_MODE_BUSWIDTH                                               (0x0000000000000100u)
+#define SDMMC_HOST_MODE_BUSWIDTH_SHIFT                                         (8u)
+#define SDMMC_SDIF_MODE_DDR                                                    (0x0000000000000001u)
+#define SDMMC_SDIF_MODE_DDR_SHIFT                                              (0u)
+#define SDMMC_SDIF_MODE_NOCHKCR                                                (0x0000000000000100u)
+#define SDMMC_SDIF_MODE_NOCHKCR_SHIFT                                          (8u)
+#define SDMMC_SD_STATUS_SD_RST                                                 (0x0000000000000002u)
+#define SDMMC_SD_STATUS_SD_RST_SHIFT                                           (1u)
+#define SDMMC_DM_CM_DTRAN_MODE_BUS_WIDTH                                       (0x0000000000000030u)
+#define SDMMC_DM_CM_DTRAN_MODE_BUS_WIDTH_SHIFT                                 (4u)
+#define SDMMC_DM_CM_DTRAN_MODE_CH_NUM                                          (0x0000000000030000u)
+#define SDMMC_DM_CM_DTRAN_MODE_CH_NUM_SHIFT                                    (16u)
+#define SDMMC_DM_CM_DTRAN_CTRL_DM_START                                        (0x0000000000000001u)
+#define SDMMC_DM_CM_DTRAN_CTRL_DM_START_SHIFT                                  (0u)
+#define SDMMC_DM_CM_RST_SEQRST                                                 (0x0000000000000001u)
+#define SDMMC_DM_CM_RST_SEQRST_SHIFT                                           (0u)
+#define SDMMC_DM_CM_RST_DTRANRST0                                              (0x0000000000000100u)
+#define SDMMC_DM_CM_RST_DTRANRST0_SHIFT                                        (8u)
+#define SDMMC_DM_CM_RST_DTRANRST1                                              (0x0000000000000200u)
+#define SDMMC_DM_CM_RST_DTRANRST1_SHIFT                                        (9u)
+#define SDMMC_DM_CM_INFO1_SEQEND                                               (0x0000000000000001u)
+#define SDMMC_DM_CM_INFO1_SEQEND_SHIFT                                         (0u)
+#define SDMMC_DM_CM_INFO1_DTRANEND0                                            (0x0000000000010000u)
+#define SDMMC_DM_CM_INFO1_DTRANEND0_SHIFT                                      (16u)
+#define SDMMC_DM_CM_INFO1_DTRANEND1                                            (0x0000000000100000u)
+#define SDMMC_DM_CM_INFO1_DTRANEND1_SHIFT                                      (20u)
+#define SDMMC_DM_CM_INFO1_MASK_SEQEND_MASK                                     (0x0000000000000001u)
+#define SDMMC_DM_CM_INFO1_MASK_SEQEND_MASK_SHIFT                               (0u)
+#define SDMMC_DM_CM_INFO1_MASK_DTRANEND0_MASK                                  (0x0000000000010000u)
+#define SDMMC_DM_CM_INFO1_MASK_DTRANEND0_MASK_SHIFT                            (16u)
+#define SDMMC_DM_CM_INFO1_MASK_DTRANEND1_MASK                                  (0x0000000000100000u)
+#define SDMMC_DM_CM_INFO1_MASK_DTRANEND1_MASK_SHIFT                            (20u)
+#define SDMMC_DM_CM_INFO2_SEQERR                                               (0x0000000000000001u)
+#define SDMMC_DM_CM_INFO2_SEQERR_SHIFT                                         (0u)
+#define SDMMC_DM_CM_INFO2_DTRANERR0                                            (0x0000000000010000u)
+#define SDMMC_DM_CM_INFO2_DTRANERR0_SHIFT                                      (16u)
+#define SDMMC_DM_CM_INFO2_DTRANERR1                                            (0x0000000000020000u)
+#define SDMMC_DM_CM_INFO2_DTRANERR1_SHIFT                                      (17u)
+#define SDMMC_DM_CM_INFO2_MASK_SEQERR_MASK                                     (0x0000000000000001u)
+#define SDMMC_DM_CM_INFO2_MASK_SEQERR_MASK_SHIFT                               (0u)
+#define SDMMC_DM_CM_INFO2_MASK_DTRANERR0_MASK                                  (0x0000000000010000u)
+#define SDMMC_DM_CM_INFO2_MASK_DTRANERR0_MASK_SHIFT                            (16u)
+#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK                                  (0x0000000000020000u)
+#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK_SHIFT                            (17u)
+#define SDMMC_DM_DTRAN_ADDR_DADDR                                              (0x00000000FFFFFFC0u)
+#define SDMMC_DM_DTRAN_ADDR_DADDR_SHIFT                                        (3u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spdif_iobitmask.h

@@ -0,0 +1,200 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SPDIF_IOBITMASK_H
+#define SPDIF_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SPDIF_TLCA_TLCA                                                        (0x00FFFFFFu)
+#define SPDIF_TLCA_TLCA_SHIFT                                                  (0u)
+#define SPDIF_TRCA_TRCA                                                        (0x00FFFFFFu)
+#define SPDIF_TRCA_TRCA_SHIFT                                                  (0u)
+#define SPDIF_TLCS_CTL                                                         (0x0000003Eu)
+#define SPDIF_TLCS_CTL_SHIFT                                                   (1u)
+#define SPDIF_TLCS_CATCD                                                       (0x0000FF00u)
+#define SPDIF_TLCS_CATCD_SHIFT                                                 (8u)
+#define SPDIF_TLCS_SRCNO                                                       (0x000F0000u)
+#define SPDIF_TLCS_SRCNO_SHIFT                                                 (16u)
+#define SPDIF_TLCS_CHNO                                                        (0x00F00000u)
+#define SPDIF_TLCS_CHNO_SHIFT                                                  (20u)
+#define SPDIF_TLCS_FS                                                          (0x0F000000u)
+#define SPDIF_TLCS_FS_SHIFT                                                    (24u)
+#define SPDIF_TLCS_CLAC                                                        (0x30000000u)
+#define SPDIF_TLCS_CLAC_SHIFT                                                  (28u)
+#define SPDIF_TRCS_CTL                                                         (0x0000003Eu)
+#define SPDIF_TRCS_CTL_SHIFT                                                   (1u)
+#define SPDIF_TRCS_CATCD                                                       (0x0000FF00u)
+#define SPDIF_TRCS_CATCD_SHIFT                                                 (8u)
+#define SPDIF_TRCS_SRCNO                                                       (0x000F0000u)
+#define SPDIF_TRCS_SRCNO_SHIFT                                                 (16u)
+#define SPDIF_TRCS_CHNO                                                        (0x00F00000u)
+#define SPDIF_TRCS_CHNO_SHIFT                                                  (20u)
+#define SPDIF_TRCS_FS                                                          (0x0F000000u)
+#define SPDIF_TRCS_FS_SHIFT                                                    (24u)
+#define SPDIF_TRCS_CLAC                                                        (0x30000000u)
+#define SPDIF_TRCS_CLAC_SHIFT                                                  (28u)
+#define SPDIF_TUI_TUI                                                          (0xFFFFFFFFu)
+#define SPDIF_TUI_TUI_SHIFT                                                    (0u)
+#define SPDIF_RLCA_RLCA                                                        (0x00FFFFFFu)
+#define SPDIF_RLCA_RLCA_SHIFT                                                  (0u)
+#define SPDIF_RRCA_RRCA                                                        (0x00FFFFFFu)
+#define SPDIF_RRCA_RRCA_SHIFT                                                  (0u)
+#define SPDIF_RLCS_CTL                                                         (0x0000003Eu)
+#define SPDIF_RLCS_CTL_SHIFT                                                   (1u)
+#define SPDIF_RLCS_CATCD                                                       (0x0000FF00u)
+#define SPDIF_RLCS_CATCD_SHIFT                                                 (8u)
+#define SPDIF_RLCS_SRCNO                                                       (0x000F0000u)
+#define SPDIF_RLCS_SRCNO_SHIFT                                                 (16u)
+#define SPDIF_RLCS_CHNO                                                        (0x00F00000u)
+#define SPDIF_RLCS_CHNO_SHIFT                                                  (20u)
+#define SPDIF_RLCS_FS                                                          (0x0F000000u)
+#define SPDIF_RLCS_FS_SHIFT                                                    (24u)
+#define SPDIF_RLCS_CLAC                                                        (0x30000000u)
+#define SPDIF_RLCS_CLAC_SHIFT                                                  (28u)
+#define SPDIF_RRCS_CTL                                                         (0x0000003Eu)
+#define SPDIF_RRCS_CTL_SHIFT                                                   (1u)
+#define SPDIF_RRCS_CATCD                                                       (0x0000FF00u)
+#define SPDIF_RRCS_CATCD_SHIFT                                                 (8u)
+#define SPDIF_RRCS_SRCNO                                                       (0x000F0000u)
+#define SPDIF_RRCS_SRCNO_SHIFT                                                 (16u)
+#define SPDIF_RRCS_CHNO                                                        (0x00F00000u)
+#define SPDIF_RRCS_CHNO_SHIFT                                                  (20u)
+#define SPDIF_RRCS_FS                                                          (0x0F000000u)
+#define SPDIF_RRCS_FS_SHIFT                                                    (24u)
+#define SPDIF_RRCS_CLAC                                                        (0x30000000u)
+#define SPDIF_RRCS_CLAC_SHIFT                                                  (28u)
+#define SPDIF_RUI_RUI                                                          (0xFFFFFFFFu)
+#define SPDIF_RUI_RUI_SHIFT                                                    (0u)
+#define SPDIF_CTRL_TCBI                                                        (0x00000001u)
+#define SPDIF_CTRL_TCBI_SHIFT                                                  (0u)
+#define SPDIF_CTRL_TCSI                                                        (0x00000002u)
+#define SPDIF_CTRL_TCSI_SHIFT                                                  (1u)
+#define SPDIF_CTRL_RCBI                                                        (0x00000004u)
+#define SPDIF_CTRL_RCBI_SHIFT                                                  (2u)
+#define SPDIF_CTRL_RCSI                                                        (0x00000008u)
+#define SPDIF_CTRL_RCSI_SHIFT                                                  (3u)
+#define SPDIF_CTRL_TUII                                                        (0x00000010u)
+#define SPDIF_CTRL_TUII_SHIFT                                                  (4u)
+#define SPDIF_CTRL_RUII                                                        (0x00000020u)
+#define SPDIF_CTRL_RUII_SHIFT                                                  (5u)
+#define SPDIF_CTRL_ABUI                                                        (0x00000040u)
+#define SPDIF_CTRL_ABUI_SHIFT                                                  (6u)
+#define SPDIF_CTRL_ABOI                                                        (0x00000080u)
+#define SPDIF_CTRL_ABOI_SHIFT                                                  (7u)
+#define SPDIF_CTRL_CSEI                                                        (0x00000100u)
+#define SPDIF_CTRL_CSEI_SHIFT                                                  (8u)
+#define SPDIF_CTRL_PREI                                                        (0x00000200u)
+#define SPDIF_CTRL_PREI_SHIFT                                                  (9u)
+#define SPDIF_CTRL_PAEI                                                        (0x00000400u)
+#define SPDIF_CTRL_PAEI_SHIFT                                                  (10u)
+#define SPDIF_CTRL_CREI                                                        (0x00000800u)
+#define SPDIF_CTRL_CREI_SHIFT                                                  (11u)
+#define SPDIF_CTRL_UBUI                                                        (0x00001000u)
+#define SPDIF_CTRL_UBUI_SHIFT                                                  (12u)
+#define SPDIF_CTRL_UBOI                                                        (0x00002000u)
+#define SPDIF_CTRL_UBOI_SHIFT                                                  (13u)
+#define SPDIF_CTRL_TEIE                                                        (0x00004000u)
+#define SPDIF_CTRL_TEIE_SHIFT                                                  (14u)
+#define SPDIF_CTRL_REIE                                                        (0x00008000u)
+#define SPDIF_CTRL_REIE_SHIFT                                                  (15u)
+#define SPDIF_CTRL_TME                                                         (0x00010000u)
+#define SPDIF_CTRL_TME_SHIFT                                                   (16u)
+#define SPDIF_CTRL_RME                                                         (0x00020000u)
+#define SPDIF_CTRL_RME_SHIFT                                                   (17u)
+#define SPDIF_CTRL_AOS                                                         (0x00040000u)
+#define SPDIF_CTRL_AOS_SHIFT                                                   (18u)
+#define SPDIF_CTRL_NCSI                                                        (0x00080000u)
+#define SPDIF_CTRL_NCSI_SHIFT                                                  (19u)
+#define SPDIF_CTRL_TDE                                                         (0x00100000u)
+#define SPDIF_CTRL_TDE_SHIFT                                                   (20u)
+#define SPDIF_CTRL_RDE                                                         (0x00200000u)
+#define SPDIF_CTRL_RDE_SHIFT                                                   (21u)
+#define SPDIF_CTRL_TASS                                                        (0x00C00000u)
+#define SPDIF_CTRL_TASS_SHIFT                                                  (22u)
+#define SPDIF_CTRL_RASS                                                        (0x03000000u)
+#define SPDIF_CTRL_RASS_SHIFT                                                  (24u)
+#define SPDIF_CTRL_PB                                                          (0x04000000u)
+#define SPDIF_CTRL_PB_SHIFT                                                    (26u)
+#define SPDIF_CTRL_CKS                                                         (0x10000000u)
+#define SPDIF_CTRL_CKS_SHIFT                                                   (28u)
+#define SPDIF_STAT_CBTX                                                        (0x00000001u)
+#define SPDIF_STAT_CBTX_SHIFT                                                  (0u)
+#define SPDIF_STAT_CSTX                                                        (0x00000002u)
+#define SPDIF_STAT_CSTX_SHIFT                                                  (1u)
+#define SPDIF_STAT_CBRX                                                        (0x00000004u)
+#define SPDIF_STAT_CBRX_SHIFT                                                  (2u)
+#define SPDIF_STAT_CSRX                                                        (0x00000008u)
+#define SPDIF_STAT_CSRX_SHIFT                                                  (3u)
+#define SPDIF_STAT_TUIR                                                        (0x00000010u)
+#define SPDIF_STAT_TUIR_SHIFT                                                  (4u)
+#define SPDIF_STAT_RUIR                                                        (0x00000020u)
+#define SPDIF_STAT_RUIR_SHIFT                                                  (5u)
+#define SPDIF_STAT_ABU                                                         (0x00000040u)
+#define SPDIF_STAT_ABU_SHIFT                                                   (6u)
+#define SPDIF_STAT_ABO                                                         (0x00000080u)
+#define SPDIF_STAT_ABO_SHIFT                                                   (7u)
+#define SPDIF_STAT_CSE                                                         (0x00000100u)
+#define SPDIF_STAT_CSE_SHIFT                                                   (8u)
+#define SPDIF_STAT_PREE                                                        (0x00000200u)
+#define SPDIF_STAT_PREE_SHIFT                                                  (9u)
+#define SPDIF_STAT_PARE                                                        (0x00000400u)
+#define SPDIF_STAT_PARE_SHIFT                                                  (10u)
+#define SPDIF_STAT_CE                                                          (0x00000800u)
+#define SPDIF_STAT_CE_SHIFT                                                    (11u)
+#define SPDIF_STAT_UBU                                                         (0x00001000u)
+#define SPDIF_STAT_UBU_SHIFT                                                   (12u)
+#define SPDIF_STAT_UBO                                                         (0x00002000u)
+#define SPDIF_STAT_UBO_SHIFT                                                   (13u)
+#define SPDIF_STAT_TIS                                                         (0x00004000u)
+#define SPDIF_STAT_TIS_SHIFT                                                   (14u)
+#define SPDIF_STAT_RIS                                                         (0x00008000u)
+#define SPDIF_STAT_RIS_SHIFT                                                   (15u)
+#define SPDIF_STAT_CMD                                                         (0x00010000u)
+#define SPDIF_STAT_CMD_SHIFT                                                   (16u)
+#define SPDIF_TDAD_TDAD                                                        (0x00FFFFFFu)
+#define SPDIF_TDAD_TDAD_SHIFT                                                  (0u)
+#define SPDIF_RDAD_RDAD                                                        (0x00FFFFFFu)
+#define SPDIF_RDAD_RDAD_SHIFT                                                  (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spibsc_iobitmask.h

@@ -0,0 +1,236 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SPIBSC_IOBITMASK_H
+#define SPIBSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SPIBSC_CMNCR_BSZ                                                       (0x00000003u)
+#define SPIBSC_CMNCR_BSZ_SHIFT                                                 (0u)
+#define SPIBSC_CMNCR_IO0FV                                                     (0x00000300u)
+#define SPIBSC_CMNCR_IO0FV_SHIFT                                               (8u)
+#define SPIBSC_CMNCR_IO2FV                                                     (0x00003000u)
+#define SPIBSC_CMNCR_IO2FV_SHIFT                                               (12u)
+#define SPIBSC_CMNCR_IO3FV                                                     (0x0000C000u)
+#define SPIBSC_CMNCR_IO3FV_SHIFT                                               (14u)
+#define SPIBSC_CMNCR_MOIIO0                                                    (0x00030000u)
+#define SPIBSC_CMNCR_MOIIO0_SHIFT                                              (16u)
+#define SPIBSC_CMNCR_MOIIO1                                                    (0x000C0000u)
+#define SPIBSC_CMNCR_MOIIO1_SHIFT                                              (18u)
+#define SPIBSC_CMNCR_MOIIO2                                                    (0x00300000u)
+#define SPIBSC_CMNCR_MOIIO2_SHIFT                                              (20u)
+#define SPIBSC_CMNCR_MOIIO3                                                    (0x00C00000u)
+#define SPIBSC_CMNCR_MOIIO3_SHIFT                                              (22u)
+#define SPIBSC_CMNCR_MD                                                        (0x80000000u)
+#define SPIBSC_CMNCR_MD_SHIFT                                                  (31u)
+#define SPIBSC_SSLDR_SCKDL                                                     (0x00000007u)
+#define SPIBSC_SSLDR_SCKDL_SHIFT                                               (0u)
+#define SPIBSC_SSLDR_SLNDL                                                     (0x00000700u)
+#define SPIBSC_SSLDR_SLNDL_SHIFT                                               (8u)
+#define SPIBSC_SSLDR_SPNDL                                                     (0x00070000u)
+#define SPIBSC_SSLDR_SPNDL_SHIFT                                               (16u)
+#define SPIBSC_DRCR_SSLE                                                       (0x00000001u)
+#define SPIBSC_DRCR_SSLE_SHIFT                                                 (0u)
+#define SPIBSC_DRCR_RBE                                                        (0x00000100u)
+#define SPIBSC_DRCR_RBE_SHIFT                                                  (8u)
+#define SPIBSC_DRCR_RCF                                                        (0x00000200u)
+#define SPIBSC_DRCR_RCF_SHIFT                                                  (9u)
+#define SPIBSC_DRCR_RBURST                                                     (0x001F0000u)
+#define SPIBSC_DRCR_RBURST_SHIFT                                               (16u)
+#define SPIBSC_DRCR_SSLN                                                       (0x01000000u)
+#define SPIBSC_DRCR_SSLN_SHIFT                                                 (24u)
+#define SPIBSC_DRCMR_OCMD                                                      (0x000000FFu)
+#define SPIBSC_DRCMR_OCMD_SHIFT                                                (0u)
+#define SPIBSC_DRCMR_CMD                                                       (0x00FF0000u)
+#define SPIBSC_DRCMR_CMD_SHIFT                                                 (16u)
+#define SPIBSC_DREAR_EAC                                                       (0x00000007u)
+#define SPIBSC_DREAR_EAC_SHIFT                                                 (0u)
+#define SPIBSC_DREAR_EAV                                                       (0x00FF0000u)
+#define SPIBSC_DREAR_EAV_SHIFT                                                 (16u)
+#define SPIBSC_DROPR_OPD0                                                      (0x000000FFu)
+#define SPIBSC_DROPR_OPD0_SHIFT                                                (0u)
+#define SPIBSC_DROPR_OPD1                                                      (0x0000FF00u)
+#define SPIBSC_DROPR_OPD1_SHIFT                                                (8u)
+#define SPIBSC_DROPR_OPD2                                                      (0x00FF0000u)
+#define SPIBSC_DROPR_OPD2_SHIFT                                                (16u)
+#define SPIBSC_DROPR_OPD3                                                      (0xFF000000u)
+#define SPIBSC_DROPR_OPD3_SHIFT                                                (24u)
+#define SPIBSC_DRENR_OPDE                                                      (0x000000F0u)
+#define SPIBSC_DRENR_OPDE_SHIFT                                                (4u)
+#define SPIBSC_DRENR_ADE                                                       (0x00000F00u)
+#define SPIBSC_DRENR_ADE_SHIFT                                                 (8u)
+#define SPIBSC_DRENR_OCDE                                                      (0x00001000u)
+#define SPIBSC_DRENR_OCDE_SHIFT                                                (12u)
+#define SPIBSC_DRENR_CDE                                                       (0x00004000u)
+#define SPIBSC_DRENR_CDE_SHIFT                                                 (14u)
+#define SPIBSC_DRENR_DME                                                       (0x00008000u)
+#define SPIBSC_DRENR_DME_SHIFT                                                 (15u)
+#define SPIBSC_DRENR_DRDB                                                      (0x00030000u)
+#define SPIBSC_DRENR_DRDB_SHIFT                                                (16u)
+#define SPIBSC_DRENR_OPDB                                                      (0x00300000u)
+#define SPIBSC_DRENR_OPDB_SHIFT                                                (20u)
+#define SPIBSC_DRENR_ADB                                                       (0x03000000u)
+#define SPIBSC_DRENR_ADB_SHIFT                                                 (24u)
+#define SPIBSC_DRENR_OCDB                                                      (0x30000000u)
+#define SPIBSC_DRENR_OCDB_SHIFT                                                (28u)
+#define SPIBSC_DRENR_CDB                                                       (0xC0000000u)
+#define SPIBSC_DRENR_CDB_SHIFT                                                 (30u)
+#define SPIBSC_SMCR_SPIE                                                       (0x00000001u)
+#define SPIBSC_SMCR_SPIE_SHIFT                                                 (0u)
+#define SPIBSC_SMCR_SPIWE                                                      (0x00000002u)
+#define SPIBSC_SMCR_SPIWE_SHIFT                                                (1u)
+#define SPIBSC_SMCR_SPIRE                                                      (0x00000004u)
+#define SPIBSC_SMCR_SPIRE_SHIFT                                                (2u)
+#define SPIBSC_SMCR_SSLKP                                                      (0x00000100u)
+#define SPIBSC_SMCR_SSLKP_SHIFT                                                (8u)
+#define SPIBSC_SMCMR_OCMD                                                      (0x000000FFu)
+#define SPIBSC_SMCMR_OCMD_SHIFT                                                (0u)
+#define SPIBSC_SMCMR_CMD                                                       (0x00FF0000u)
+#define SPIBSC_SMCMR_CMD_SHIFT                                                 (16u)
+#define SPIBSC_SMADR_ADR                                                       (0xFFFFFFFFu)
+#define SPIBSC_SMADR_ADR_SHIFT                                                 (0u)
+#define SPIBSC_SMOPR_OPD0                                                      (0x000000FFu)
+#define SPIBSC_SMOPR_OPD0_SHIFT                                                (0u)
+#define SPIBSC_SMOPR_OPD1                                                      (0x0000FF00u)
+#define SPIBSC_SMOPR_OPD1_SHIFT                                                (8u)
+#define SPIBSC_SMOPR_OPD2                                                      (0x00FF0000u)
+#define SPIBSC_SMOPR_OPD2_SHIFT                                                (16u)
+#define SPIBSC_SMOPR_OPD3                                                      (0xFF000000u)
+#define SPIBSC_SMOPR_OPD3_SHIFT                                                (24u)
+#define SPIBSC_SMENR_SPIDE                                                     (0x0000000Fu)
+#define SPIBSC_SMENR_SPIDE_SHIFT                                               (0u)
+#define SPIBSC_SMENR_OPDE                                                      (0x000000F0u)
+#define SPIBSC_SMENR_OPDE_SHIFT                                                (4u)
+#define SPIBSC_SMENR_ADE                                                       (0x00000F00u)
+#define SPIBSC_SMENR_ADE_SHIFT                                                 (8u)
+#define SPIBSC_SMENR_OCDE                                                      (0x00001000u)
+#define SPIBSC_SMENR_OCDE_SHIFT                                                (12u)
+#define SPIBSC_SMENR_CDE                                                       (0x00004000u)
+#define SPIBSC_SMENR_CDE_SHIFT                                                 (14u)
+#define SPIBSC_SMENR_DME                                                       (0x00008000u)
+#define SPIBSC_SMENR_DME_SHIFT                                                 (15u)
+#define SPIBSC_SMENR_SPIDB                                                     (0x00030000u)
+#define SPIBSC_SMENR_SPIDB_SHIFT                                               (16u)
+#define SPIBSC_SMENR_OPDB                                                      (0x00300000u)
+#define SPIBSC_SMENR_OPDB_SHIFT                                                (20u)
+#define SPIBSC_SMENR_ADB                                                       (0x03000000u)
+#define SPIBSC_SMENR_ADB_SHIFT                                                 (24u)
+#define SPIBSC_SMENR_OCDB                                                      (0x30000000u)
+#define SPIBSC_SMENR_OCDB_SHIFT                                                (28u)
+#define SPIBSC_SMENR_CDB                                                       (0xC0000000u)
+#define SPIBSC_SMENR_CDB_SHIFT                                                 (30u)
+#define SPIBSC_SMRDR0_RDATA0                                                   (0xFFFFFFFFu)
+#define SPIBSC_SMRDR0_RDATA0_SHIFT                                             (0u)
+#define SPIBSC_SMRDR1_RDATA1                                                   (0xFFFFFFFFu)
+#define SPIBSC_SMRDR1_RDATA1_SHIFT                                             (0u)
+#define SPIBSC_SMWDR0_WDATA0                                                   (0xFFFFFFFFu)
+#define SPIBSC_SMWDR0_WDATA0_SHIFT                                             (0u)
+#define SPIBSC_SMWDR1_WDATA1                                                   (0xFFFFFFFFu)
+#define SPIBSC_SMWDR1_WDATA1_SHIFT                                             (0u)
+#define SPIBSC_CMNSR_TEND                                                      (0x00000001u)
+#define SPIBSC_CMNSR_TEND_SHIFT                                                (0u)
+#define SPIBSC_CMNSR_SSLF                                                      (0x00000002u)
+#define SPIBSC_CMNSR_SSLF_SHIFT                                                (1u)
+#define SPIBSC_DRDMCR_DMCYC                                                    (0x0000001Fu)
+#define SPIBSC_DRDMCR_DMCYC_SHIFT                                              (0u)
+#define SPIBSC_DRDRENR_DRDRE                                                   (0x00000001u)
+#define SPIBSC_DRDRENR_DRDRE_SHIFT                                             (0u)
+#define SPIBSC_DRDRENR_OPDRE                                                   (0x00000010u)
+#define SPIBSC_DRDRENR_OPDRE_SHIFT                                             (4u)
+#define SPIBSC_DRDRENR_ADDRE                                                   (0x00000100u)
+#define SPIBSC_DRDRENR_ADDRE_SHIFT                                             (8u)
+#define SPIBSC_DRDRENR_HYPE                                                    (0x00007000u)
+#define SPIBSC_DRDRENR_HYPE_SHIFT                                              (12u)
+#define SPIBSC_SMDMCR_DMCYC                                                    (0x0000001Fu)
+#define SPIBSC_SMDMCR_DMCYC_SHIFT                                              (0u)
+#define SPIBSC_SMDRENR_SPIDRE                                                  (0x00000001u)
+#define SPIBSC_SMDRENR_SPIDRE_SHIFT                                            (0u)
+#define SPIBSC_SMDRENR_OPDRE                                                   (0x00000010u)
+#define SPIBSC_SMDRENR_OPDRE_SHIFT                                             (4u)
+#define SPIBSC_SMDRENR_ADDRE                                                   (0x00000100u)
+#define SPIBSC_SMDRENR_ADDRE_SHIFT                                             (8u)
+#define SPIBSC_SMDRENR_HYPE                                                    (0x00007000u)
+#define SPIBSC_SMDRENR_HYPE_SHIFT                                              (12u)
+#define SPIBSC_PHYADJ1_ADJ1                                                    (0xFFFFFFFFu)
+#define SPIBSC_PHYADJ1_ADJ1_SHIFT                                              (0u)
+#define SPIBSC_PHYADJ2_ADJ2                                                    (0xFFFFFFFFu)
+#define SPIBSC_PHYADJ2_ADJ2_SHIFT                                              (0u)
+#define SPIBSC_PHYCNT_PHYMEM                                                   (0x00000003u)
+#define SPIBSC_PHYCNT_PHYMEM_SHIFT                                             (0u)
+#define SPIBSC_PHYCNT_WBUF                                                     (0x00000004u)
+#define SPIBSC_PHYCNT_WBUF_SHIFT                                               (2u)
+#define SPIBSC_PHYCNT_WBUF2                                                    (0x00000010u)
+#define SPIBSC_PHYCNT_WBUF2_SHIFT                                              (4u)
+#define SPIBSC_PHYCNT_CKSEL                                                    (0x00030000u)
+#define SPIBSC_PHYCNT_CKSEL_SHIFT                                              (16u)
+#define SPIBSC_PHYCNT_HS                                                       (0x00040000u)
+#define SPIBSC_PHYCNT_HS_SHIFT                                                 (18u)
+#define SPIBSC_PHYCNT_OCT                                                      (0x00100000u)
+#define SPIBSC_PHYCNT_OCT_SHIFT                                                (20u)
+#define SPIBSC_PHYCNT_EXDS                                                     (0x00200000u)
+#define SPIBSC_PHYCNT_EXDS_SHIFT                                               (21u)
+#define SPIBSC_PHYCNT_OCTA_1_0                                                 (0x00C00000u)
+#define SPIBSC_PHYCNT_OCTA_1_0_SHIFT                                           (22u)
+#define SPIBSC_PHYCNT_ALT_ALIGN                                                (0x40000000u)
+#define SPIBSC_PHYCNT_ALT_ALIGN_SHIFT                                          (30u)
+#define SPIBSC_PHYCNT_CAL                                                      (0x80000000u)
+#define SPIBSC_PHYCNT_CAL_SHIFT                                                (31u)
+#define SPIBSC_PHYOFFSET1_DDRTMG                                               (0x30000000u)
+#define SPIBSC_PHYOFFSET1_DDRTMG_SHIFT                                         (28u)
+#define SPIBSC_PHYOFFSET2_OCTTMG                                               (0x00000700u)
+#define SPIBSC_PHYOFFSET2_OCTTMG_SHIFT                                         (8u)
+#define SPIBSC_PHYINT_INT                                                      (0x00000001u)
+#define SPIBSC_PHYINT_INT_SHIFT                                                (0u)
+#define SPIBSC_PHYINT_WPVAL                                                    (0x00000002u)
+#define SPIBSC_PHYINT_WPVAL_SHIFT                                              (1u)
+#define SPIBSC_PHYINT_RSTVAL                                                   (0x00000004u)
+#define SPIBSC_PHYINT_RSTVAL_SHIFT                                             (2u)
+#define SPIBSC_PHYINT_INTEN                                                    (0x01000000u)
+#define SPIBSC_PHYINT_INTEN_SHIFT                                              (24u)
+#define SPIBSC_PHYINT_WPEN                                                     (0x02000000u)
+#define SPIBSC_PHYINT_WPEN_SHIFT                                               (25u)
+#define SPIBSC_PHYINT_RSTEN                                                    (0x04000000u)
+#define SPIBSC_PHYINT_RSTEN_SHIFT                                              (26u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sprite_iobitmask.h

@@ -0,0 +1,516 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SPRITE_IOBITMASK_H
+#define SPRITE_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SPRITE_SPEA0RLSL_SPEA0RBUSSEL                                          (0x00000001u)
+#define SPRITE_SPEA0RLSL_SPEA0RBUSSEL_SHIFT                                    (0u)
+#define SPRITE_SPEA0STA0_SPEA0RSTA0                                            (0xFFFFFFFFu)
+#define SPRITE_SPEA0STA0_SPEA0RSTA0_SHIFT                                      (0u)
+#define SPRITE_SPEA0PHA0_SPEA0RPHA0                                            (0xFFFFFFFFu)
+#define SPRITE_SPEA0PHA0_SPEA0RPHA0_SHIFT                                      (0u)
+#define SPRITE_SPEA0RCM0_SPEA0RCM0                                             (0x00000003u)
+#define SPRITE_SPEA0RCM0_SPEA0RCM0_SHIFT                                       (0u)
+#define SPRITE_SPEA0RUP_SPEA0RUP0                                              (0x00000001u)
+#define SPRITE_SPEA0RUP_SPEA0RUP0_SHIFT                                        (0u)
+#define SPRITE_SPEA0RCFG_SPEA0RDTH                                             (0x00000007u)
+#define SPRITE_SPEA0RCFG_SPEA0RDTH_SHIFT                                       (0u)
+#define SPRITE_SPEA0RCFG_SPEA0RLEN                                             (0x00000070u)
+#define SPRITE_SPEA0RCFG_SPEA0RLEN_SHIFT                                       (4u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN0                                            (0x00000001u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN1                                            (0x00000002u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN1_SHIFT                                      (1u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN2                                            (0x00000004u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN2_SHIFT                                      (2u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN3                                            (0x00000008u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN3_SHIFT                                      (3u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN4                                            (0x00000010u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN4_SHIFT                                      (4u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN5                                            (0x00000020u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN5_SHIFT                                      (5u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN6                                            (0x00000040u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN6_SHIFT                                      (6u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN7                                            (0x00000080u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN7_SHIFT                                      (7u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN8                                            (0x00000100u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN8_SHIFT                                      (8u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN9                                            (0x00000200u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN9_SHIFT                                      (9u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN10                                           (0x00000400u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN10_SHIFT                                     (10u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN11                                           (0x00000800u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN11_SHIFT                                     (11u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN12                                           (0x00001000u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN12_SHIFT                                     (12u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN13                                           (0x00002000u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN13_SHIFT                                     (13u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN14                                           (0x00004000u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN14_SHIFT                                     (14u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN15                                           (0x00008000u)
+#define SPRITE_SPEA0S0EN_SPEA0S0EN15_SHIFT                                     (15u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS0                                            (0x00000001u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS1                                            (0x00000002u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS1_SHIFT                                      (1u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS2                                            (0x00000004u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS2_SHIFT                                      (2u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS3                                            (0x00000008u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS3_SHIFT                                      (3u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS4                                            (0x00000010u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS4_SHIFT                                      (4u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS5                                            (0x00000020u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS5_SHIFT                                      (5u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS6                                            (0x00000040u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS6_SHIFT                                      (6u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS7                                            (0x00000080u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS7_SHIFT                                      (7u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS8                                            (0x00000100u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS8_SHIFT                                      (8u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS9                                            (0x00000200u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS9_SHIFT                                      (9u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS10                                           (0x00000400u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS10_SHIFT                                     (10u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS11                                           (0x00000800u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS11_SHIFT                                     (11u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS12                                           (0x00001000u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS12_SHIFT                                     (12u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS13                                           (0x00002000u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS13_SHIFT                                     (13u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS14                                           (0x00004000u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS14_SHIFT                                     (14u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS15                                           (0x00008000u)
+#define SPRITE_SPEA0S0DS_SPEA0S0DS15_SHIFT                                     (15u)
+#define SPRITE_SPEA0S0UP_SPEA0S0UP0                                            (0x00000001u)
+#define SPRITE_SPEA0S0UP_SPEA0S0UP0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN0                                            (0x00000001u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN1                                            (0x00000002u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN1_SHIFT                                      (1u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN2                                            (0x00000004u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN2_SHIFT                                      (2u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN3                                            (0x00000008u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN3_SHIFT                                      (3u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN4                                            (0x00000010u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN4_SHIFT                                      (4u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN5                                            (0x00000020u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN5_SHIFT                                      (5u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN6                                            (0x00000040u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN6_SHIFT                                      (6u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN7                                            (0x00000080u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN7_SHIFT                                      (7u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN8                                            (0x00000100u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN8_SHIFT                                      (8u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN9                                            (0x00000200u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN9_SHIFT                                      (9u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN10                                           (0x00000400u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN10_SHIFT                                     (10u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN11                                           (0x00000800u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN11_SHIFT                                     (11u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN12                                           (0x00001000u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN12_SHIFT                                     (12u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN13                                           (0x00002000u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN13_SHIFT                                     (13u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN14                                           (0x00004000u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN14_SHIFT                                     (14u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN15                                           (0x00008000u)
+#define SPRITE_SPEA0S1EN_SPEA0S1EN15_SHIFT                                     (15u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS0                                            (0x00000001u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS1                                            (0x00000002u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS1_SHIFT                                      (1u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS2                                            (0x00000004u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS2_SHIFT                                      (2u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS3                                            (0x00000008u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS3_SHIFT                                      (3u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS4                                            (0x00000010u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS4_SHIFT                                      (4u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS5                                            (0x00000020u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS5_SHIFT                                      (5u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS6                                            (0x00000040u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS6_SHIFT                                      (6u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS7                                            (0x00000080u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS7_SHIFT                                      (7u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS8                                            (0x00000100u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS8_SHIFT                                      (8u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS9                                            (0x00000200u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS9_SHIFT                                      (9u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS10                                           (0x00000400u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS10_SHIFT                                     (10u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS11                                           (0x00000800u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS11_SHIFT                                     (11u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS12                                           (0x00001000u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS12_SHIFT                                     (12u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS13                                           (0x00002000u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS13_SHIFT                                     (13u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS14                                           (0x00004000u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS14_SHIFT                                     (14u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS15                                           (0x00008000u)
+#define SPRITE_SPEA0S1DS_SPEA0S1DS15_SHIFT                                     (15u)
+#define SPRITE_SPEA0S1UP_SPEA0S1UP0                                            (0x00000001u)
+#define SPRITE_SPEA0S1UP_SPEA0S1UP0_SHIFT                                      (0u)
+#define SPRITE_SPEA0S0DA0_SPEA0S0DA0                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA0_SPEA0S0DA0_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY0_SPEA0S0LYH0                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY0_SPEA0S0LYH0_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY0_SPEA0S0LYW0                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY0_SPEA0S0LYW0_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS0_SPEA0S0PSY0                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS0_SPEA0S0PSY0_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS0_SPEA0S0PSX0                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS0_SPEA0S0PSX0_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA1_SPEA0S0DA1                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA1_SPEA0S0DA1_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY1_SPEA0S0LYH1                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY1_SPEA0S0LYH1_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY1_SPEA0S0LYW1                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY1_SPEA0S0LYW1_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS1_SPEA0S0PSY1                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS1_SPEA0S0PSY1_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS1_SPEA0S0PSX1                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS1_SPEA0S0PSX1_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA2_SPEA0S0DA2                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA2_SPEA0S0DA2_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY2_SPEA0S0LYH2                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY2_SPEA0S0LYH2_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY2_SPEA0S0LYW2                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY2_SPEA0S0LYW2_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS2_SPEA0S0PSY2                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS2_SPEA0S0PSY2_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS2_SPEA0S0PSX2                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS2_SPEA0S0PSX2_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA3_SPEA0S0DA3                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA3_SPEA0S0DA3_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY3_SPEA0S0LYH3                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY3_SPEA0S0LYH3_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY3_SPEA0S0LYW3                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY3_SPEA0S0LYW3_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS3_SPEA0S0PSY3                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS3_SPEA0S0PSY3_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS3_SPEA0S0PSX3                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS3_SPEA0S0PSX3_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA4_SPEA0S0DA4                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA4_SPEA0S0DA4_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY4_SPEA0S0LYH4                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY4_SPEA0S0LYH4_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY4_SPEA0S0LYW4                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY4_SPEA0S0LYW4_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS4_SPEA0S0PSY4                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS4_SPEA0S0PSY4_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS4_SPEA0S0PSX4                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS4_SPEA0S0PSX4_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA5_SPEA0S0DA5                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA5_SPEA0S0DA5_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY5_SPEA0S0LYH5                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY5_SPEA0S0LYH5_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY5_SPEA0S0LYW5                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY5_SPEA0S0LYW5_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS5_SPEA0S0PSY5                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS5_SPEA0S0PSY5_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS5_SPEA0S0PSX5                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS5_SPEA0S0PSX5_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA6_SPEA0S0DA6                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA6_SPEA0S0DA6_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY6_SPEA0S0LYH6                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY6_SPEA0S0LYH6_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY6_SPEA0S0LYW6                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY6_SPEA0S0LYW6_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS6_SPEA0S0PSY6                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS6_SPEA0S0PSY6_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS6_SPEA0S0PSX6                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS6_SPEA0S0PSX6_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA7_SPEA0S0DA7                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA7_SPEA0S0DA7_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY7_SPEA0S0LYH7                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY7_SPEA0S0LYH7_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY7_SPEA0S0LYW7                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY7_SPEA0S0LYW7_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS7_SPEA0S0PSY7                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS7_SPEA0S0PSY7_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS7_SPEA0S0PSX7                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS7_SPEA0S0PSX7_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA8_SPEA0S0DA8                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA8_SPEA0S0DA8_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY8_SPEA0S0LYH8                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY8_SPEA0S0LYH8_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY8_SPEA0S0LYW8                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY8_SPEA0S0LYW8_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS8_SPEA0S0PSY8                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS8_SPEA0S0PSY8_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS8_SPEA0S0PSX8                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS8_SPEA0S0PSX8_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA9_SPEA0S0DA9                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA9_SPEA0S0DA9_SHIFT                                     (0u)
+#define SPRITE_SPEA0S0LY9_SPEA0S0LYH9                                          (0x000007FFu)
+#define SPRITE_SPEA0S0LY9_SPEA0S0LYH9_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0LY9_SPEA0S0LYW9                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0LY9_SPEA0S0LYW9_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0PS9_SPEA0S0PSY9                                          (0x00001FFFu)
+#define SPRITE_SPEA0S0PS9_SPEA0S0PSY9_SHIFT                                    (0u)
+#define SPRITE_SPEA0S0PS9_SPEA0S0PSX9                                          (0x07FE0000u)
+#define SPRITE_SPEA0S0PS9_SPEA0S0PSX9_SHIFT                                    (17u)
+#define SPRITE_SPEA0S0DA10_SPEA0S0DA10                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA10_SPEA0S0DA10_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY10_SPEA0S0LYH10                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY10_SPEA0S0LYH10_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY10_SPEA0S0LYW10                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY10_SPEA0S0LYW10_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS10_SPEA0S0PSY10                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS10_SPEA0S0PSY10_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS10_SPEA0S0PSX10                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS10_SPEA0S0PSX10_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0DA11_SPEA0S0DA11                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA11_SPEA0S0DA11_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY11_SPEA0S0LYH11                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY11_SPEA0S0LYH11_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY11_SPEA0S0LYW11                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY11_SPEA0S0LYW11_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS11_SPEA0S0PSY11                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS11_SPEA0S0PSY11_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS11_SPEA0S0PSX11                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS11_SPEA0S0PSX11_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0DA12_SPEA0S0DA12                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA12_SPEA0S0DA12_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY12_SPEA0S0LYH12                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY12_SPEA0S0LYH12_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY12_SPEA0S0LYW12                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY12_SPEA0S0LYW12_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS12_SPEA0S0PSY12                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS12_SPEA0S0PSY12_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS12_SPEA0S0PSX12                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS12_SPEA0S0PSX12_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0DA13_SPEA0S0DA13                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA13_SPEA0S0DA13_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY13_SPEA0S0LYH13                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY13_SPEA0S0LYH13_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY13_SPEA0S0LYW13                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY13_SPEA0S0LYW13_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS13_SPEA0S0PSY13                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS13_SPEA0S0PSY13_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS13_SPEA0S0PSX13                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS13_SPEA0S0PSX13_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0DA14_SPEA0S0DA14                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA14_SPEA0S0DA14_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY14_SPEA0S0LYH14                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY14_SPEA0S0LYH14_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY14_SPEA0S0LYW14                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY14_SPEA0S0LYW14_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS14_SPEA0S0PSY14                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS14_SPEA0S0PSY14_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS14_SPEA0S0PSX14                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS14_SPEA0S0PSX14_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0DA15_SPEA0S0DA15                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S0DA15_SPEA0S0DA15_SHIFT                                   (0u)
+#define SPRITE_SPEA0S0LY15_SPEA0S0LYH15                                        (0x000007FFu)
+#define SPRITE_SPEA0S0LY15_SPEA0S0LYH15_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0LY15_SPEA0S0LYW15                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0LY15_SPEA0S0LYW15_SHIFT                                  (17u)
+#define SPRITE_SPEA0S0PS15_SPEA0S0PSY15                                        (0x00001FFFu)
+#define SPRITE_SPEA0S0PS15_SPEA0S0PSY15_SHIFT                                  (0u)
+#define SPRITE_SPEA0S0PS15_SPEA0S0PSX15                                        (0x07FE0000u)
+#define SPRITE_SPEA0S0PS15_SPEA0S0PSX15_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA0_SPEA0S1DA0                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA0_SPEA0S1DA0_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY0_SPEA0S1LYH0                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY0_SPEA0S1LYH0_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY0_SPEA0S1LYW0                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY0_SPEA0S1LYW0_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS0_SPEA0S1PSY0                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS0_SPEA0S1PSY0_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS0_SPEA0S1PSX0                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS0_SPEA0S1PSX0_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA1_SPEA0S1DA1                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA1_SPEA0S1DA1_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY1_SPEA0S1LYH1                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY1_SPEA0S1LYH1_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY1_SPEA0S1LYW1                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY1_SPEA0S1LYW1_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS1_SPEA0S1PSY1                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS1_SPEA0S1PSY1_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS1_SPEA0S1PSX1                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS1_SPEA0S1PSX1_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA2_SPEA0S1DA2                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA2_SPEA0S1DA2_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY2_SPEA0S1LYH2                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY2_SPEA0S1LYH2_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY2_SPEA0S1LYW2                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY2_SPEA0S1LYW2_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS2_SPEA0S1PSY2                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS2_SPEA0S1PSY2_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS2_SPEA0S1PSX2                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS2_SPEA0S1PSX2_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA3_SPEA0S1DA3                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA3_SPEA0S1DA3_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY3_SPEA0S1LYH3                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY3_SPEA0S1LYH3_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY3_SPEA0S1LYW3                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY3_SPEA0S1LYW3_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS3_SPEA0S1PSY3                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS3_SPEA0S1PSY3_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS3_SPEA0S1PSX3                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS3_SPEA0S1PSX3_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA4_SPEA0S1DA4                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA4_SPEA0S1DA4_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY4_SPEA0S1LYH4                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY4_SPEA0S1LYH4_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY4_SPEA0S1LYW4                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY4_SPEA0S1LYW4_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS4_SPEA0S1PSY4                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS4_SPEA0S1PSY4_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS4_SPEA0S1PSX4                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS4_SPEA0S1PSX4_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA5_SPEA0S1DA5                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA5_SPEA0S1DA5_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY5_SPEA0S1LYH5                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY5_SPEA0S1LYH5_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY5_SPEA0S1LYW5                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY5_SPEA0S1LYW5_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS5_SPEA0S1PSY5                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS5_SPEA0S1PSY5_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS5_SPEA0S1PSX5                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS5_SPEA0S1PSX5_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA6_SPEA0S1DA6                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA6_SPEA0S1DA6_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY6_SPEA0S1LYH6                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY6_SPEA0S1LYH6_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY6_SPEA0S1LYW6                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY6_SPEA0S1LYW6_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS6_SPEA0S1PSY6                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS6_SPEA0S1PSY6_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS6_SPEA0S1PSX6                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS6_SPEA0S1PSX6_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA7_SPEA0S1DA7                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA7_SPEA0S1DA7_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY7_SPEA0S1LYH7                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY7_SPEA0S1LYH7_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY7_SPEA0S1LYW7                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY7_SPEA0S1LYW7_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS7_SPEA0S1PSY7                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS7_SPEA0S1PSY7_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS7_SPEA0S1PSX7                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS7_SPEA0S1PSX7_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA8_SPEA0S1DA8                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA8_SPEA0S1DA8_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY8_SPEA0S1LYH8                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY8_SPEA0S1LYH8_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY8_SPEA0S1LYW8                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY8_SPEA0S1LYW8_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS8_SPEA0S1PSY8                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS8_SPEA0S1PSY8_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS8_SPEA0S1PSX8                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS8_SPEA0S1PSX8_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA9_SPEA0S1DA9                                           (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA9_SPEA0S1DA9_SHIFT                                     (0u)
+#define SPRITE_SPEA0S1LY9_SPEA0S1LYH9                                          (0x000007FFu)
+#define SPRITE_SPEA0S1LY9_SPEA0S1LYH9_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1LY9_SPEA0S1LYW9                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1LY9_SPEA0S1LYW9_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1PS9_SPEA0S1PSY9                                          (0x00001FFFu)
+#define SPRITE_SPEA0S1PS9_SPEA0S1PSY9_SHIFT                                    (0u)
+#define SPRITE_SPEA0S1PS9_SPEA0S1PSX9                                          (0x07FE0000u)
+#define SPRITE_SPEA0S1PS9_SPEA0S1PSX9_SHIFT                                    (17u)
+#define SPRITE_SPEA0S1DA10_SPEA0S1DA10                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA10_SPEA0S1DA10_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY10_SPEA0S1LYH10                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY10_SPEA0S1LYH10_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY10_SPEA0S1LYW10                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY10_SPEA0S1LYW10_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS10_SPEA0S1PSY10                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS10_SPEA0S1PSY10_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS10_SPEA0S1PSX10                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS10_SPEA0S1PSX10_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA11_SPEA0S1DA11                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA11_SPEA0S1DA11_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY11_SPEA0S1LYH11                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY11_SPEA0S1LYH11_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY11_SPEA0S1LYW11                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY11_SPEA0S1LYW11_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS11_SPEA0S1PSY11                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS11_SPEA0S1PSY11_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS11_SPEA0S1PSX11                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS11_SPEA0S1PSX11_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA12_SPEA0S1DA12                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA12_SPEA0S1DA12_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY12_SPEA0S1LYH12                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY12_SPEA0S1LYH12_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY12_SPEA0S1LYW12                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY12_SPEA0S1LYW12_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS12_SPEA0S1PSY12                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS12_SPEA0S1PSY12_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS12_SPEA0S1PSX12                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS12_SPEA0S1PSX12_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA13_SPEA0S1DA13                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA13_SPEA0S1DA13_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY13_SPEA0S1LYH13                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY13_SPEA0S1LYH13_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY13_SPEA0S1LYW13                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY13_SPEA0S1LYW13_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS13_SPEA0S1PSY13                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS13_SPEA0S1PSY13_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS13_SPEA0S1PSX13                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS13_SPEA0S1PSX13_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA14_SPEA0S1DA14                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA14_SPEA0S1DA14_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY14_SPEA0S1LYH14                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY14_SPEA0S1LYH14_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY14_SPEA0S1LYW14                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY14_SPEA0S1LYW14_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS14_SPEA0S1PSY14                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS14_SPEA0S1PSY14_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS14_SPEA0S1PSX14                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS14_SPEA0S1PSX14_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1DA15_SPEA0S1DA15                                         (0xFFFFFFFFu)
+#define SPRITE_SPEA0S1DA15_SPEA0S1DA15_SHIFT                                   (0u)
+#define SPRITE_SPEA0S1LY15_SPEA0S1LYH15                                        (0x000007FFu)
+#define SPRITE_SPEA0S1LY15_SPEA0S1LYH15_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1LY15_SPEA0S1LYW15                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1LY15_SPEA0S1LYW15_SHIFT                                  (17u)
+#define SPRITE_SPEA0S1PS15_SPEA0S1PSY15                                        (0x00001FFFu)
+#define SPRITE_SPEA0S1PS15_SPEA0S1PSY15_SHIFT                                  (0u)
+#define SPRITE_SPEA0S1PS15_SPEA0S1PSX15                                        (0x07FE0000u)
+#define SPRITE_SPEA0S1PS15_SPEA0S1PSX15_SHIFT                                  (17u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ssif_iobitmask.h

@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef SSIF_IOBITMASK_H
+#define SSIF_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define SSIF_SSICR_REN                                                         (0x00000001u)
+#define SSIF_SSICR_REN_SHIFT                                                   (0u)
+#define SSIF_SSICR_TEN                                                         (0x00000002u)
+#define SSIF_SSICR_TEN_SHIFT                                                   (1u)
+#define SSIF_SSICR_MUEN                                                        (0x00000008u)
+#define SSIF_SSICR_MUEN_SHIFT                                                  (3u)
+#define SSIF_SSICR_CKDV                                                        (0x000000F0u)
+#define SSIF_SSICR_CKDV_SHIFT                                                  (4u)
+#define SSIF_SSICR_DEL                                                         (0x00000100u)
+#define SSIF_SSICR_DEL_SHIFT                                                   (8u)
+#define SSIF_SSICR_PDTA                                                        (0x00000200u)
+#define SSIF_SSICR_PDTA_SHIFT                                                  (9u)
+#define SSIF_SSICR_SDTA                                                        (0x00000400u)
+#define SSIF_SSICR_SDTA_SHIFT                                                  (10u)
+#define SSIF_SSICR_SPDP                                                        (0x00000800u)
+#define SSIF_SSICR_SPDP_SHIFT                                                  (11u)
+#define SSIF_SSICR_LRCKP                                                       (0x00001000u)
+#define SSIF_SSICR_LRCKP_SHIFT                                                 (12u)
+#define SSIF_SSICR_BCKP                                                        (0x00002000u)
+#define SSIF_SSICR_BCKP_SHIFT                                                  (13u)
+#define SSIF_SSICR_MST                                                         (0x00004000u)
+#define SSIF_SSICR_MST_SHIFT                                                   (14u)
+#define SSIF_SSICR_SWL                                                         (0x00070000u)
+#define SSIF_SSICR_SWL_SHIFT                                                   (16u)
+#define SSIF_SSICR_DWL                                                         (0x00380000u)
+#define SSIF_SSICR_DWL_SHIFT                                                   (19u)
+#define SSIF_SSICR_FRM                                                         (0x00C00000u)
+#define SSIF_SSICR_FRM_SHIFT                                                   (22u)
+#define SSIF_SSICR_IIEN                                                        (0x02000000u)
+#define SSIF_SSICR_IIEN_SHIFT                                                  (25u)
+#define SSIF_SSICR_ROIEN                                                       (0x04000000u)
+#define SSIF_SSICR_ROIEN_SHIFT                                                 (26u)
+#define SSIF_SSICR_RUIEN                                                       (0x08000000u)
+#define SSIF_SSICR_RUIEN_SHIFT                                                 (27u)
+#define SSIF_SSICR_TOIEN                                                       (0x10000000u)
+#define SSIF_SSICR_TOIEN_SHIFT                                                 (28u)
+#define SSIF_SSICR_TUIEN                                                       (0x20000000u)
+#define SSIF_SSICR_TUIEN_SHIFT                                                 (29u)
+#define SSIF_SSICR_CKS                                                         (0x40000000u)
+#define SSIF_SSICR_CKS_SHIFT                                                   (30u)
+#define SSIF_SSISR_IIRQ                                                        (0x02000000u)
+#define SSIF_SSISR_IIRQ_SHIFT                                                  (25u)
+#define SSIF_SSISR_ROIRQ                                                       (0x04000000u)
+#define SSIF_SSISR_ROIRQ_SHIFT                                                 (26u)
+#define SSIF_SSISR_RUIRQ                                                       (0x08000000u)
+#define SSIF_SSISR_RUIRQ_SHIFT                                                 (27u)
+#define SSIF_SSISR_TOIRQ                                                       (0x10000000u)
+#define SSIF_SSISR_TOIRQ_SHIFT                                                 (28u)
+#define SSIF_SSISR_TUIRQ                                                       (0x20000000u)
+#define SSIF_SSISR_TUIRQ_SHIFT                                                 (29u)
+#define SSIF_SSIFCR_RFRST                                                      (0x00000001u)
+#define SSIF_SSIFCR_RFRST_SHIFT                                                (0u)
+#define SSIF_SSIFCR_TFRST                                                      (0x00000002u)
+#define SSIF_SSIFCR_TFRST_SHIFT                                                (1u)
+#define SSIF_SSIFCR_RIE                                                        (0x00000004u)
+#define SSIF_SSIFCR_RIE_SHIFT                                                  (2u)
+#define SSIF_SSIFCR_TIE                                                        (0x00000008u)
+#define SSIF_SSIFCR_TIE_SHIFT                                                  (3u)
+#define SSIF_SSIFCR_RXDNCE                                                     (0x00000100u)
+#define SSIF_SSIFCR_RXDNCE_SHIFT                                               (8u)
+#define SSIF_SSIFCR_LRCKNCE                                                    (0x00000200u)
+#define SSIF_SSIFCR_LRCKNCE_SHIFT                                              (9u)
+#define SSIF_SSIFCR_BCKNCE                                                     (0x00000400u)
+#define SSIF_SSIFCR_BCKNCE_SHIFT                                               (10u)
+#define SSIF_SSIFCR_BSW                                                        (0x00000800u)
+#define SSIF_SSIFCR_BSW_SHIFT                                                  (11u)
+#define SSIF_SSIFCR_SSIRST                                                     (0x00010000u)
+#define SSIF_SSIFCR_SSIRST_SHIFT                                               (16u)
+#define SSIF_SSIFCR_AUCKE                                                      (0x80000000u)
+#define SSIF_SSIFCR_AUCKE_SHIFT                                                (31u)
+#define SSIF_SSIFSR_RDF                                                        (0x00000001u)
+#define SSIF_SSIFSR_RDF_SHIFT                                                  (0u)
+#define SSIF_SSIFSR_RDC                                                        (0x00003F00u)
+#define SSIF_SSIFSR_RDC_SHIFT                                                  (8u)
+#define SSIF_SSIFSR_TDE                                                        (0x00010000u)
+#define SSIF_SSIFSR_TDE_SHIFT                                                  (16u)
+#define SSIF_SSIFSR_TDC                                                        (0x3F000000u)
+#define SSIF_SSIFSR_TDC_SHIFT                                                  (24u)
+#define SSIF_SSIFTDR_SSIFTDR                                                   (0xFFFFFFFFu)
+#define SSIF_SSIFTDR_SSIFTDR_SHIFT                                             (0u)
+#define SSIF_SSIFRDR_SSIFRDR                                                   (0xFFFFFFFFu)
+#define SSIF_SSIFRDR_SSIFRDR_SHIFT                                             (0u)
+#define SSIF_SSIOFR_OMOD                                                       (0x00000003u)
+#define SSIF_SSIOFR_OMOD_SHIFT                                                 (0u)
+#define SSIF_SSIOFR_LRCONT                                                     (0x00000100u)
+#define SSIF_SSIOFR_LRCONT_SHIFT                                               (8u)
+#define SSIF_SSIOFR_BCKASTP                                                    (0x00000200u)
+#define SSIF_SSIOFR_BCKASTP_SHIFT                                              (9u)
+#define SSIF_SSISCR_RDFS                                                       (0x0000001Fu)
+#define SSIF_SSISCR_RDFS_SHIFT                                                 (0u)
+#define SSIF_SSISCR_TDES                                                       (0x00001F00u)
+#define SSIF_SSISCR_TDES_SHIFT                                                 (8u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vin_iobitmask.h

@@ -0,0 +1,272 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef VIN_IOBITMASK_H
+#define VIN_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define VIN_V0MC_ME                                                            (0x00000001u)
+#define VIN_V0MC_ME_SHIFT                                                      (0u)
+#define VIN_V0MC_BPS                                                           (0x00000002u)
+#define VIN_V0MC_BPS_SHIFT                                                     (1u)
+#define VIN_V0MC_IM                                                            (0x00000018u)
+#define VIN_V0MC_IM_SHIFT                                                      (3u)
+#define VIN_V0MC_EN                                                            (0x00000040u)
+#define VIN_V0MC_EN_SHIFT                                                      (6u)
+#define VIN_V0MC_DC                                                            (0x0000C000u)
+#define VIN_V0MC_DC_SHIFT                                                      (14u)
+#define VIN_V0MC_INF                                                           (0x00070000u)
+#define VIN_V0MC_INF_SHIFT                                                     (16u)
+#define VIN_V0MC_YCAL                                                          (0x00080000u)
+#define VIN_V0MC_YCAL_SHIFT                                                    (19u)
+#define VIN_V0MC_LUTE                                                          (0x00100000u)
+#define VIN_V0MC_LUTE_SHIFT                                                    (20u)
+#define VIN_V0MC_SCLE                                                          (0x04000000u)
+#define VIN_V0MC_SCLE_SHIFT                                                    (26u)
+#define VIN_V0MC_CLP                                                           (0x30000000u)
+#define VIN_V0MC_CLP_SHIFT                                                     (28u)
+#define VIN_V0MS_CA                                                            (0x00000001u)
+#define VIN_V0MS_CA_SHIFT                                                      (0u)
+#define VIN_V0MS_AV                                                            (0x00000002u)
+#define VIN_V0MS_AV_SHIFT                                                      (1u)
+#define VIN_V0MS_FS                                                            (0x00000004u)
+#define VIN_V0MS_FS_SHIFT                                                      (2u)
+#define VIN_V0MS_FBS                                                           (0x00000018u)
+#define VIN_V0MS_FBS_SHIFT                                                     (3u)
+#define VIN_V0FC_SC                                                            (0x00000001u)
+#define VIN_V0FC_SC_SHIFT                                                      (0u)
+#define VIN_V0FC_CC                                                            (0x00000002u)
+#define VIN_V0FC_CC_SHIFT                                                      (1u)
+#define VIN_V0SLPrC_SLPrC                                                      (0x000007FFu)
+#define VIN_V0SLPrC_SLPrC_SHIFT                                                (0u)
+#define VIN_V0ELPrC_ELPrC                                                      (0x000007FFu)
+#define VIN_V0ELPrC_ELPrC_SHIFT                                                (0u)
+#define VIN_V0SPPrC_SPPrC                                                      (0x000007FFu)
+#define VIN_V0SPPrC_SPPrC_SHIFT                                                (0u)
+#define VIN_V0EPPrC_EPPrC                                                      (0x000007FFu)
+#define VIN_V0EPPrC_EPPrC_SHIFT                                                (0u)
+#define VIN_V0CSI_IFMD_DES0                                                    (0x02000000u)
+#define VIN_V0CSI_IFMD_DES0_SHIFT                                              (25u)
+#define VIN_V0IS_IS                                                            (0x00001FF0u)
+#define VIN_V0IS_IS_SHIFT                                                      (4u)
+#define VIN_V0MB1_MB1                                                          (0xFFFFFF80u)
+#define VIN_V0MB1_MB1_SHIFT                                                    (7u)
+#define VIN_V0MB2_MB2                                                          (0xFFFFFF80u)
+#define VIN_V0MB2_MB2_SHIFT                                                    (7u)
+#define VIN_V0MB3_MB3                                                          (0xFFFFFF80u)
+#define VIN_V0MB3_MB3_SHIFT                                                    (7u)
+#define VIN_V0LC_LC                                                            (0x00000FFFu)
+#define VIN_V0LC_LC_SHIFT                                                      (0u)
+#define VIN_V0IE_FOE                                                           (0x00000001u)
+#define VIN_V0IE_FOE_SHIFT                                                     (0u)
+#define VIN_V0IE_EFE                                                           (0x00000002u)
+#define VIN_V0IE_EFE_SHIFT                                                     (1u)
+#define VIN_V0IE_SIE                                                           (0x00000004u)
+#define VIN_V0IE_SIE_SHIFT                                                     (2u)
+#define VIN_V0IE_FIE                                                           (0x00000010u)
+#define VIN_V0IE_FIE_SHIFT                                                     (4u)
+#define VIN_V0IE_VRE                                                           (0x00010000u)
+#define VIN_V0IE_VRE_SHIFT                                                     (16u)
+#define VIN_V0IE_VFE                                                           (0x00020000u)
+#define VIN_V0IE_VFE_SHIFT                                                     (17u)
+#define VIN_V0IE_FIE2                                                          (0x80000000u)
+#define VIN_V0IE_FIE2_SHIFT                                                    (31u)
+#define VIN_V0INTS_FOS                                                         (0x00000001u)
+#define VIN_V0INTS_FOS_SHIFT                                                   (0u)
+#define VIN_V0INTS_EFS                                                         (0x00000002u)
+#define VIN_V0INTS_EFS_SHIFT                                                   (1u)
+#define VIN_V0INTS_SIS                                                         (0x00000004u)
+#define VIN_V0INTS_SIS_SHIFT                                                   (2u)
+#define VIN_V0INTS_FIS                                                         (0x00000010u)
+#define VIN_V0INTS_FIS_SHIFT                                                   (4u)
+#define VIN_V0INTS_VRS                                                         (0x00010000u)
+#define VIN_V0INTS_VRS_SHIFT                                                   (16u)
+#define VIN_V0INTS_VFS                                                         (0x00020000u)
+#define VIN_V0INTS_VFS_SHIFT                                                   (17u)
+#define VIN_V0INTS_FIS2                                                        (0x80000000u)
+#define VIN_V0INTS_FIS2_SHIFT                                                  (31u)
+#define VIN_V0SI_SI                                                            (0x000007FFu)
+#define VIN_V0SI_SI_SHIFT                                                      (0u)
+#define VIN_V0DMR_DTMD                                                         (0x00000003u)
+#define VIN_V0DMR_DTMD_SHIFT                                                   (0u)
+#define VIN_V0DMR_ABIT                                                         (0x00000004u)
+#define VIN_V0DMR_ABIT_SHIFT                                                   (2u)
+#define VIN_V0DMR_BPSM                                                         (0x00000010u)
+#define VIN_V0DMR_BPSM_SHIFT                                                   (4u)
+#define VIN_V0DMR_EXRGB                                                        (0x00000100u)
+#define VIN_V0DMR_EXRGB_SHIFT                                                  (8u)
+#define VIN_V0DMR_YC_THR                                                       (0x00000800u)
+#define VIN_V0DMR_YC_THR_SHIFT                                                 (11u)
+#define VIN_V0DMR_YMODE                                                        (0x00007000u)
+#define VIN_V0DMR_YMODE_SHIFT                                                  (12u)
+#define VIN_V0DMR_EVA                                                          (0x00010000u)
+#define VIN_V0DMR_EVA_SHIFT                                                    (16u)
+#define VIN_V0DMR_A8BIT                                                        (0xFF000000u)
+#define VIN_V0DMR_A8BIT_SHIFT                                                  (24u)
+#define VIN_V0DMR2_HLV                                                         (0x000007FFu)
+#define VIN_V0DMR2_HLV_SHIFT                                                   (0u)
+#define VIN_V0DMR2_VLV                                                         (0x0000F000u)
+#define VIN_V0DMR2_VLV_SHIFT                                                   (12u)
+#define VIN_V0DMR2_FTEH                                                        (0x00010000u)
+#define VIN_V0DMR2_FTEH_SHIFT                                                  (16u)
+#define VIN_V0DMR2_FTEV                                                        (0x00020000u)
+#define VIN_V0DMR2_FTEV_SHIFT                                                  (17u)
+#define VIN_V0UVAOF_UVAOF                                                      (0xFFFFFF80u)
+#define VIN_V0UVAOF_UVAOF_SHIFT                                                (7u)
+#define VIN_V0CSCC1_CSUB                                                       (0x000000FFu)
+#define VIN_V0CSCC1_CSUB_SHIFT                                                 (0u)
+#define VIN_V0CSCC1_YSUB                                                       (0x0000FF00u)
+#define VIN_V0CSCC1_YSUB_SHIFT                                                 (8u)
+#define VIN_V0CSCC1_YMUL                                                       (0x03FF0000u)
+#define VIN_V0CSCC1_YMUL_SHIFT                                                 (16u)
+#define VIN_V0CSCC2_GCRMUL                                                     (0x000003FFu)
+#define VIN_V0CSCC2_GCRMUL_SHIFT                                               (0u)
+#define VIN_V0CSCC2_RCRMUL                                                     (0x03FF0000u)
+#define VIN_V0CSCC2_RCRMUL_SHIFT                                               (16u)
+#define VIN_V0CSCC3_BCBMUL                                                     (0x000003FFu)
+#define VIN_V0CSCC3_BCBMUL_SHIFT                                               (0u)
+#define VIN_V0CSCC3_GCBMUL                                                     (0x03FF0000u)
+#define VIN_V0CSCC3_GCBMUL_SHIFT                                               (16u)
+#define VIN_V0UDS_CTRL_NE_BCB                                                  (0x00010000u)
+#define VIN_V0UDS_CTRL_NE_BCB_SHIFT                                            (16u)
+#define VIN_V0UDS_CTRL_NE_GY                                                   (0x00020000u)
+#define VIN_V0UDS_CTRL_NE_GY_SHIFT                                             (17u)
+#define VIN_V0UDS_CTRL_NE_RCR                                                  (0x00040000u)
+#define VIN_V0UDS_CTRL_NE_RCR_SHIFT                                            (18u)
+#define VIN_V0UDS_CTRL_BC                                                      (0x00100000u)
+#define VIN_V0UDS_CTRL_BC_SHIFT                                                (20u)
+#define VIN_V0UDS_CTRL_AMD                                                     (0x40000000u)
+#define VIN_V0UDS_CTRL_AMD_SHIFT                                               (30u)
+#define VIN_V0UDS_SCALE_VFRAC                                                  (0x00000FFFu)
+#define VIN_V0UDS_SCALE_VFRAC_SHIFT                                            (0u)
+#define VIN_V0UDS_SCALE_VMANT                                                  (0x0000F000u)
+#define VIN_V0UDS_SCALE_VMANT_SHIFT                                            (12u)
+#define VIN_V0UDS_SCALE_HFRAC                                                  (0x0FFF0000u)
+#define VIN_V0UDS_SCALE_HFRAC_SHIFT                                            (16u)
+#define VIN_V0UDS_SCALE_HMANT                                                  (0xF0000000u)
+#define VIN_V0UDS_SCALE_HMANT_SHIFT                                            (28u)
+#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_V                                         (0x0000007Fu)
+#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_V_SHIFT                                   (0u)
+#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_H                                         (0x007F0000u)
+#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_H_SHIFT                                   (16u)
+#define VIN_V0UDS_CLIP_SIZE_CL_VSIZE                                           (0x00000FFFu)
+#define VIN_V0UDS_CLIP_SIZE_CL_VSIZE_SHIFT                                     (0u)
+#define VIN_V0UDS_CLIP_SIZE_CL_HSIZE                                           (0x0FFF0000u)
+#define VIN_V0UDS_CLIP_SIZE_CL_HSIZE_SHIFT                                     (16u)
+#define VIN_V0LUTP_LTCRPR                                                      (0x000003FFu)
+#define VIN_V0LUTP_LTCRPR_SHIFT                                                (0u)
+#define VIN_V0LUTP_LTCBPR                                                      (0x000FFC00u)
+#define VIN_V0LUTP_LTCBPR_SHIFT                                                (10u)
+#define VIN_V0LUTP_LTYPR                                                       (0x3FF00000u)
+#define VIN_V0LUTP_LTYPR_SHIFT                                                 (20u)
+#define VIN_V0LUTD_LTCRDT                                                      (0x000000FFu)
+#define VIN_V0LUTD_LTCRDT_SHIFT                                                (0u)
+#define VIN_V0LUTD_LTCBDT                                                      (0x0000FF00u)
+#define VIN_V0LUTD_LTCBDT_SHIFT                                                (8u)
+#define VIN_V0LUTD_LTYDT                                                       (0x00FF0000u)
+#define VIN_V0LUTD_LTYDT_SHIFT                                                 (16u)
+#define VIN_V0YCCR1_YCLRP                                                      (0x00001FFFu)
+#define VIN_V0YCCR1_YCLRP_SHIFT                                                (0u)
+#define VIN_V0YCCR2_YCLGP                                                      (0x00001FFFu)
+#define VIN_V0YCCR2_YCLGP_SHIFT                                                (0u)
+#define VIN_V0YCCR2_YCLBP                                                      (0x1FFF0000u)
+#define VIN_V0YCCR2_YCLBP_SHIFT                                                (16u)
+#define VIN_V0YCCR3_YCLAP                                                      (0x00000FFFu)
+#define VIN_V0YCCR3_YCLAP_SHIFT                                                (0u)
+#define VIN_V0YCCR3_YCLCEN                                                     (0x00010000u)
+#define VIN_V0YCCR3_YCLCEN_SHIFT                                               (16u)
+#define VIN_V0YCCR3_YCLHEN                                                     (0x00800000u)
+#define VIN_V0YCCR3_YCLHEN_SHIFT                                               (23u)
+#define VIN_V0YCCR3_YCLSFT                                                     (0x1F000000u)
+#define VIN_V0YCCR3_YCLSFT_SHIFT                                               (24u)
+#define VIN_V0YCCR3_YEXPEN                                                     (0x80000000u)
+#define VIN_V0YCCR3_YEXPEN_SHIFT                                               (31u)
+#define VIN_V0CBCCR1_CBCLRP                                                    (0x00001FFFu)
+#define VIN_V0CBCCR1_CBCLRP_SHIFT                                              (0u)
+#define VIN_V0CBCCR2_CBCLGP                                                    (0x00001FFFu)
+#define VIN_V0CBCCR2_CBCLGP_SHIFT                                              (0u)
+#define VIN_V0CBCCR2_CBCLBP                                                    (0x1FFF0000u)
+#define VIN_V0CBCCR2_CBCLBP_SHIFT                                              (16u)
+#define VIN_V0CBCCR3_CBCLAP                                                    (0x00000FFFu)
+#define VIN_V0CBCCR3_CBCLAP_SHIFT                                              (0u)
+#define VIN_V0CBCCR3_CBCLCEN                                                   (0x00010000u)
+#define VIN_V0CBCCR3_CBCLCEN_SHIFT                                             (16u)
+#define VIN_V0CBCCR3_CBCLHEN                                                   (0x00800000u)
+#define VIN_V0CBCCR3_CBCLHEN_SHIFT                                             (23u)
+#define VIN_V0CBCCR3_CBCLSFT                                                   (0x1F000000u)
+#define VIN_V0CBCCR3_CBCLSFT_SHIFT                                             (24u)
+#define VIN_V0CBCCR3_CBEXPEN                                                   (0x80000000u)
+#define VIN_V0CBCCR3_CBEXPEN_SHIFT                                             (31u)
+#define VIN_V0CRCCR1_CRCLRP                                                    (0x00001FFFu)
+#define VIN_V0CRCCR1_CRCLRP_SHIFT                                              (0u)
+#define VIN_V0CRCCR2_CRCLGP                                                    (0x00001FFFu)
+#define VIN_V0CRCCR2_CRCLGP_SHIFT                                              (0u)
+#define VIN_V0CRCCR2_CRCLBP                                                    (0x1FFF0000u)
+#define VIN_V0CRCCR2_CRCLBP_SHIFT                                              (16u)
+#define VIN_V0CRCCR3_CRCLAP                                                    (0x00000FFFu)
+#define VIN_V0CRCCR3_CRCLAP_SHIFT                                              (0u)
+#define VIN_V0CRCCR3_CRCLCEN                                                   (0x00010000u)
+#define VIN_V0CRCCR3_CRCLCEN_SHIFT                                             (16u)
+#define VIN_V0CRCCR3_CRCLHEN                                                   (0x00800000u)
+#define VIN_V0CRCCR3_CRCLHEN_SHIFT                                             (23u)
+#define VIN_V0CRCCR3_CRCLSFT                                                   (0x1F000000u)
+#define VIN_V0CRCCR3_CRCLSFT_SHIFT                                             (24u)
+#define VIN_V0CRCCR3_CREXPEN                                                   (0x80000000u)
+#define VIN_V0CRCCR3_CREXPEN_SHIFT                                             (31u)
+#define VIN_V0CSCE1_YMUL2                                                      (0x00003FFFu)
+#define VIN_V0CSCE1_YMUL2_SHIFT                                                (0u)
+#define VIN_V0CSCE2_CSUB2                                                      (0x00000FFFu)
+#define VIN_V0CSCE2_CSUB2_SHIFT                                                (0u)
+#define VIN_V0CSCE2_YSUB2                                                      (0x0FFF0000u)
+#define VIN_V0CSCE2_YSUB2_SHIFT                                                (16u)
+#define VIN_V0CSCE3_GCRMUL2                                                    (0x00003FFFu)
+#define VIN_V0CSCE3_GCRMUL2_SHIFT                                              (0u)
+#define VIN_V0CSCE3_RCRMUL2                                                    (0x3FFF0000u)
+#define VIN_V0CSCE3_RCRMUL2_SHIFT                                              (16u)
+#define VIN_V0CSCE4_BCBMUL2                                                    (0x00003FFFu)
+#define VIN_V0CSCE4_BCBMUL2_SHIFT                                              (0u)
+#define VIN_V0CSCE4_GCBMUL2                                                    (0x3FFF0000u)
+#define VIN_V0CSCE4_GCBMUL2_SHIFT                                              (16u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/wdt_iobitmask.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO bitmask header
+*******************************************************************************/
+
+#ifndef WDT_IOBITMASK_H
+#define WDT_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define WDT_WTCSR_CKS                                                          (0x000Fu)
+#define WDT_WTCSR_CKS_SHIFT                                                    (0u)
+#define WDT_WTCSR_TME                                                          (0x0020u)
+#define WDT_WTCSR_TME_SHIFT                                                    (5u)
+#define WDT_WTCSR_WTIT                                                         (0x0040u)
+#define WDT_WTCSR_WTIT_SHIFT                                                   (6u)
+#define WDT_WTCSR_IOVF                                                         (0x0080u)
+#define WDT_WTCSR_IOVF_SHIFT                                                   (7u)
+#define WDT_WTCNT_WTCNT                                                        (0x00FFu)
+#define WDT_WTCNT_WTCNT_SHIFT                                                  (0u)
+#define WDT_WRCSR_RSTE                                                         (0x0040u)
+#define WDT_WRCSR_RSTE_SHIFT                                                   (6u)
+#define WDT_WRCSR_WOVF                                                         (0x0080u)
+#define WDT_WRCSR_WOVF_SHIFT                                                   (7u)
+#define WDT_PEER_PEE                                                           (0x00FFu)
+#define WDT_PEER_PEE_SHIFT                                                     (0u)
+#define WDT_PECR_PERIE                                                         (0x00FFu)
+#define WDT_PECR_PERIE_SHIFT                                                   (0u)
+#define WDT_PESR_PEF                                                           (0x00FFu)
+#define WDT_PESR_PEF_SHIFT                                                     (0u)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefine.h

@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef __RZA2M___IODEFINE_HEADER__
+#define __RZA2M___IODEFINE_HEADER__
+
+#include "iodefines/adc_iodefine.h"
+#include "iodefines/bsc_iodefine.h"
+#include "iodefines/ceu_iodefine.h"
+#include "iodefines/cpg_iodefine.h"
+#include "iodefines/csi2link_iodefine.h"
+#include "iodefines/dmac_iodefine.h"
+#include "iodefines/drpk_iodefine.h"
+#include "iodefines/drw_iodefine.h"
+#include "iodefines/edmac_iodefine.h"
+#include "iodefines/eptpc_iodefine.h"
+#include "iodefines/etherc_iodefine.h"
+#include "iodefines/gpio_iodefine.h"
+#include "iodefines/gpt_iodefine.h"
+#include "iodefines/hyper_iodefine.h"
+#include "iodefines/imr_iodefine.h"
+#include "iodefines/intc_iodefine.h"
+#include "iodefines/irda_iodefine.h"
+#include "iodefines/jcu_iodefine.h"
+#include "iodefines/lvds_iodefine.h"
+#include "iodefines/mtu_iodefine.h"
+#include "iodefines/nandc_iodefine.h"
+#include "iodefines/octa_iodefine.h"
+#include "iodefines/ostm_iodefine.h"
+#include "iodefines/pl_iodefine.h"
+#include "iodefines/pmg_iodefine.h"
+#include "iodefines/poeg_iodefine.h"
+#include "iodefines/poe_iodefine.h"
+#include "iodefines/prr_iodefine.h"
+#include "iodefines/ptpedmac_iodefine.h"
+#include "iodefines/rcanfd_iodefine.h"
+#include "iodefines/rcan_iodefine.h"
+#include "iodefines/riic_iodefine.h"
+#include "iodefines/rspi_iodefine.h"
+#include "iodefines/rtc_iodefine.h"
+#include "iodefines/scifa_iodefine.h"
+#include "iodefines/scim_iodefine.h"
+#include "iodefines/sdmmc_iodefine.h"
+#include "iodefines/spdif_iodefine.h"
+#include "iodefines/spibsc_iodefine.h"
+#include "iodefines/sprite_iodefine.h"
+#include "iodefines/ssif_iodefine.h"
+#include "iodefines/usb_iodefine.h"
+#include "iodefines/vdc_iodefine.h"
+#include "iodefines/vin_iodefine.h"
+#include "iodefines/wdt_iodefine.h"
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/adc_iodefine.h

@@ -0,0 +1,470 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef ADC_IODEFINE_H
+#define ADC_IODEFINE_H
+
+struct st_adc {
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short DBLANS: 5;
+            unsigned short : 1;
+            unsigned short GBADIE: 1;
+            unsigned short DBLE: 1;
+            unsigned short EXTRG: 1;
+            unsigned short TRGE: 1;
+            unsigned short : 1;
+            unsigned short : 1;
+            unsigned short ADIE: 1;
+            unsigned short ADCS: 2;
+            unsigned short ADST: 1;
+        } BIT;
+    } ADCSR;
+    char           wk0[1];
+    char           wk1[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short ANSA0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADANSA0;
+    char           wk2[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short ADS0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADADS0;
+    char           wk3[2];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char ADC_2_0: 3;
+            unsigned char : 4;
+            unsigned char AVEE: 1;
+        } BIT;
+    } ADADC;
+    char           wk4[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short : 1;
+            unsigned short ADPRC: 2;
+            unsigned short : 1;
+            unsigned short : 1;
+            unsigned short ACE: 1;
+            unsigned short : 2;
+            unsigned short DIAGVAL: 2;
+            unsigned short DIAGLD: 1;
+            unsigned short DIAGM: 1;
+            unsigned short : 3;
+            unsigned short ADRFMT: 1;
+        } BIT;
+    } ADCER;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short TRSB: 6;
+            unsigned short : 2;
+            unsigned short TRSA: 6;
+            unsigned short : 2;
+        } BIT;
+    } ADSTRGR;
+    char           wk5[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short ANSB0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADANSB0;
+    char           wk6[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDBLDR;
+    char           wk7[2];
+    char           wk8[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADRD;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR0;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR1;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR2;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR3;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR4;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR5;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR6;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDR7;
+    char           wk9[2];
+    char           wk10[2];
+    char           wk11[2];
+    char           wk12[2];
+    char           wk13[2];
+    char           wk14[2];
+    char           wk15[2];
+    char           wk16[2];
+    char           wk17[2];
+    char           wk18[2];
+    char           wk19[2];
+    char           wk20[2];
+    char           wk21[2];
+    char           wk22[2];
+    char           wk23[2];
+    char           wk24[2];
+    char           wk25[2];
+    char           wk26[2];
+    char           wk27[2];
+    char           wk28[2];
+    char           wk29[2];
+    char           wk30[2];
+    char           wk31[2];
+    char           wk32[2];
+    char           wk33[2];
+    char           wk34[1];
+    char           wk35[1];
+    char           wk36[2];
+    char           wk37[2];
+    char           wk38[2];
+    char           wk39[2];
+    char           wk40[2];
+    char           wk41[2];
+    char           wk42[2];
+    char           wk43[2];
+    char           wk44[2];
+    char           wk45[2];
+    char           wk46[2];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char ADNDIS: 5;
+            unsigned char : 3;
+        } BIT;
+    } ADDISCR;
+    char           wk47[1];
+    char           wk48[1];
+    char           wk49[1];
+    char           wk50[1];
+    char           wk51[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short PGS: 1;
+            unsigned short GBRSCN: 1;
+            unsigned short : 6;
+            unsigned short : 1;
+            unsigned short : 5;
+            unsigned short LGRRS: 1;
+            unsigned short GBRP: 1;
+        } BIT;
+    } ADGSPCR;
+    char           wk52[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDBLDRA;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short AD: 16;
+        } BIT;
+    } ADDBLDRB;
+    char           wk53[1];
+    char           wk54[1];
+    char           wk55[1];
+    char           wk56[1];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MONCOMB: 1;
+            unsigned char : 3;
+            unsigned char MONCMPA: 1;
+            unsigned char MONCMPB: 1;
+            unsigned char : 2;
+        } BIT;
+    } ADWINMON;
+    char           wk57[3];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short : 2;
+            unsigned short : 7;
+            unsigned short CMPBE: 1;
+            unsigned short : 1;
+            unsigned short CMPAE: 1;
+            unsigned short : 1;
+            unsigned short CMPBIE: 1;
+            unsigned short WCMPE: 1;
+            unsigned short CMPAIE: 1;
+        } BIT;
+    } ADCMPCR;
+    char           wk58[1];
+    char           wk59[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPCHA0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADCMPANSR0;
+    char           wk60[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPLCHA0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADCMPLR0;
+    char           wk61[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPD0: 16;
+        } BIT;
+    } ADCMPDR0;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPD1: 16;
+        } BIT;
+    } ADCMPDR1;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPSTCHA0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADCMPSR0;
+    char           wk62[2];
+    char           wk63[1];
+    char           wk64[1];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char CMPCHB: 6;
+            unsigned char : 1;
+            unsigned char CMPLB: 1;
+        } BIT;
+    } ADCMPBNSR;
+    char           wk65[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPLLB: 16;
+        } BIT;
+    } ADWINLLB;
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CMPULB: 16;
+        } BIT;
+    } ADWINULB;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char CMPSTB: 1;
+            unsigned char : 7;
+        } BIT;
+    } ADCMPBSR;
+    char           wk66[3];
+    char           wk67[2];
+    char           wk68[2];
+    char           wk69[2];
+    char           wk70[2];
+    char           wk71[2];
+    char           wk72[2];
+    char           wk73[2];
+    char           wk74[2];
+    char           wk75[2];
+    char           wk76[2];
+    char           wk77[2];
+    char           wk78[2];
+    char           wk79[2];
+    char           wk80[2];
+    char           wk81[2];
+    char           wk82[2];
+    char           wk83[1];
+    char           wk84[1];
+    char           wk85[1];
+    char           wk86[1];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short ANSC0: 8;
+            unsigned short : 8;
+        } BIT;
+    } ADANSC0;
+    char           wk87[2];
+    char           wk88[1];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char TRSC: 6;
+            unsigned char GCADIE: 1;
+            unsigned char GRCE: 1;
+        } BIT;
+    } ADGCTRGR;
+    char           wk89[3];
+    char           wk90[1];
+    char           wk91[1];
+    char           wk92[1];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR0;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR1;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR2;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR3;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR4;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR5;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR6;
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SST: 8;
+        } BIT;
+    } ADSSTR7;
+    char           wk93[1];
+    char           wk94[1];
+    char           wk95[1];
+    char           wk96[1];
+    char           wk97[1];
+    char           wk98[1];
+    char           wk99[1];
+    char           wk100[1];
+    char           wk101[176];
+    char           wk102[2];
+    char           wk103[2];
+    char           wk104[12];
+    char           wk105[2];
+    char           wk106[2];
+    char           wk107[1];
+    char           wk108[1];
+    char           wk109[42];
+    char           wk110[1];
+};
+
+#define ADC       (*(volatile struct st_adc       *)0xE8005800)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/bsc_iodefine.h

@@ -0,0 +1,402 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef BSC_IODEFINE_H
+#define BSC_IODEFINE_H
+
+struct st_bsc {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HIZCNT: 1;
+            unsigned long HIZMEM: 1;
+            unsigned long : 7;
+            unsigned long DPRTY: 2;
+            unsigned long : 13;
+            unsigned long AL0: 1;
+            unsigned long : 3;
+            unsigned long TL0: 1;
+            unsigned long : 3;
+        } BIT;
+    } CMNCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS0BCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS1BCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS2BCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS3BCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS4BCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 9;
+            unsigned long BSZ: 2;
+            unsigned long : 1;
+            unsigned long TYPE: 3;
+            unsigned long : 1;
+            unsigned long IWRRS: 3;
+            unsigned long IWRRD: 3;
+            unsigned long IWRWS: 3;
+            unsigned long IWRWD: 3;
+            unsigned long IWW: 3;
+            unsigned long : 1;
+        } BIT;
+    } CS5BCR;
+    char           wk0[4];
+    char           wk1[4];
+    char           wk2[4];
+    union {
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long HW: 2;
+                unsigned long : 4;
+                unsigned long WM: 1;
+                unsigned long WR: 4;
+                unsigned long SW: 2;
+                unsigned long : 7;
+                unsigned long BAS: 1;
+                unsigned long : 11;
+            } BIT;
+        } CS0WCR_0;
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long : 6;
+                unsigned long WM: 1;
+                unsigned long W: 4;
+                unsigned long : 5;
+                unsigned long BW: 2;
+                unsigned long : 2;
+                unsigned long BST: 2;
+                unsigned long : 10;
+            } BIT;
+        } CS0WCR_1;
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long : 6;
+                unsigned long WM: 1;
+                unsigned long W: 4;
+                unsigned long : 5;
+                unsigned long BW: 2;
+                unsigned long : 14;
+            } BIT;
+        } CS0WCR_2;
+    } CS0WCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HW: 2;
+            unsigned long : 4;
+            unsigned long WM: 1;
+            unsigned long WR: 4;
+            unsigned long SW: 2;
+            unsigned long : 3;
+            unsigned long WW: 3;
+            unsigned long : 1;
+            unsigned long BAS: 1;
+            unsigned long : 11;
+        } BIT;
+    } CS1WCR_0;
+    union {
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long : 6;
+                unsigned long WM: 1;
+                unsigned long WR: 4;
+                unsigned long : 9;
+                unsigned long BAS: 1;
+                unsigned long : 11;
+            } BIT;
+        } CS2WCR_0;
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long : 7;
+                unsigned long A2CL: 2;
+                unsigned long : 23;
+            } BIT;
+        } CS2WCR_1;
+    } CS2WCR;
+    union {
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long WTRC: 2;
+                unsigned long : 1;
+                unsigned long TRWL: 2;
+                unsigned long : 2;
+                unsigned long A3CL: 2;
+                unsigned long : 1;
+                unsigned long WTRCD: 2;
+                unsigned long : 1;
+                unsigned long WTRP: 2;
+                unsigned long : 17;
+            } BIT;
+        } CS3WCR_1;
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long : 6;
+                unsigned long WM: 1;
+                unsigned long WR: 4;
+                unsigned long : 9;
+                unsigned long BAS: 1;
+                unsigned long : 11;
+            } BIT;
+        } CS3WCR_0;
+    } CS3WCR;
+    union {
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long HW: 2;
+                unsigned long : 4;
+                unsigned long WM: 1;
+                unsigned long WR: 4;
+                unsigned long SW: 2;
+                unsigned long : 3;
+                unsigned long WW: 3;
+                unsigned long : 1;
+                unsigned long BAS: 1;
+                unsigned long : 11;
+            } BIT;
+        } CS4WCR_0;
+        union {
+            unsigned long LONG;
+            struct {
+                unsigned long HW: 2;
+                unsigned long : 4;
+                unsigned long WM: 1;
+                unsigned long W: 4;
+                unsigned long SW: 2;
+                unsigned long : 3;
+                unsigned long BW: 2;
+                unsigned long : 2;
+                unsigned long BST: 2;
+                unsigned long : 10;
+            } BIT;
+        } CS4WCR_1;
+    } CS4WCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HW: 2;
+            unsigned long : 4;
+            unsigned long WM: 1;
+            unsigned long WR: 4;
+            unsigned long SW: 2;
+            unsigned long : 3;
+            unsigned long WW: 3;
+            unsigned long : 1;
+            unsigned long MPXWBAS: 1;
+            unsigned long SZSEL: 1;
+            unsigned long : 10;
+        } BIT;
+    } CS5WCR_0;
+    char           wk3[4];
+    char           wk4[4];
+    char           wk5[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long A3COL: 2;
+            unsigned long : 1;
+            unsigned long A3ROW: 2;
+            unsigned long : 3;
+            unsigned long BACTV: 1;
+            unsigned long PDOWN: 1;
+            unsigned long RMODE: 1;
+            unsigned long RFSH: 1;
+            unsigned long : 1;
+            unsigned long DEEP: 1;
+            unsigned long : 2;
+            unsigned long A2COL: 2;
+            unsigned long : 1;
+            unsigned long A2ROW: 2;
+            unsigned long : 11;
+        } BIT;
+    } SDCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RRC: 3;
+            unsigned long CKS: 3;
+            unsigned long CMIE: 1;
+            unsigned long CMF: 1;
+            unsigned long : 24;
+        } BIT;
+    } RTCSR;
+    unsigned long  RTCNT;
+    unsigned long  RTCOR;
+    char           wk6[4];
+    unsigned long  TOSCOR0;
+    unsigned long  TOSCOR1;
+    unsigned long  TOSCOR2;
+    unsigned long  TOSCOR3;
+    unsigned long  TOSCOR4;
+    unsigned long  TOSCOR5;
+    char           wk7[4];
+    char           wk8[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CS0TOSTF: 1;
+            unsigned long CS1TOSTF: 1;
+            unsigned long CS2TOSTF: 1;
+            unsigned long CS3TOSTF: 1;
+            unsigned long CS4TOSTF: 1;
+            unsigned long CS5TOSTF: 1;
+            unsigned long : 26;
+        } BIT;
+    } TOSTR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CS0TOEN: 1;
+            unsigned long CS1TOEN: 1;
+            unsigned long CS2TOEN: 1;
+            unsigned long CS3TOEN: 1;
+            unsigned long CS4TOEN: 1;
+            unsigned long CS5TOEN: 1;
+            unsigned long : 26;
+        } BIT;
+    } TOENR;
+    char           wk9[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SDRIDLY: 4;
+            unsigned long : 12;
+            unsigned long SDRODLY: 4;
+            unsigned long : 12;
+        } BIT;
+    } ACADJ;
+    char           wk10[2924];
+    char           wk11[4];
+    char           wk12[4];
+    char           wk13[4];
+    char           wk14[4];
+    char           wk15[4];
+    char           wk16[4];
+    char           wk17[228];
+    char           wk18[1];
+};
+
+#define BSC       (*(volatile struct st_bsc       *)0x1F000000)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ceu_iodefine.h

@@ -0,0 +1,594 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef CEU_IODEFINE_H
+#define CEU_IODEFINE_H
+
+struct st_ceu {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CE: 1;
+            unsigned long : 15;
+            unsigned long CPKIL: 1;
+            unsigned long : 15;
+        } BIT;
+    } CAPSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 16;
+            unsigned long CTNCP: 1;
+            unsigned long : 3;
+            unsigned long MTCM: 2;
+            unsigned long : 2;
+            unsigned long FDRP: 8;
+        } BIT;
+    } CAPCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HDPOL: 1;
+            unsigned long VDPOL: 1;
+            unsigned long : 2;
+            unsigned long JPG: 2;
+            unsigned long : 2;
+            unsigned long DTARY: 2;
+            unsigned long : 2;
+            unsigned long DTIF: 1;
+            unsigned long : 3;
+            unsigned long FLDPOL: 1;
+            unsigned long : 7;
+            unsigned long DSEL: 1;
+            unsigned long FLDSEL: 1;
+            unsigned long HDSEL: 1;
+            unsigned long VDSEL: 1;
+            unsigned long : 4;
+        } BIT;
+    } CAMCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HCYL: 14;
+            unsigned long : 2;
+            unsigned long VCYL: 14;
+            unsigned long : 2;
+        } BIT;
+    } CMCYR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HOFST: 13;
+            unsigned long : 3;
+            unsigned long VOFST: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAMOR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HWDTH: 13;
+            unsigned long : 3;
+            unsigned long VWDTH: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAPWR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long FCI: 2;
+            unsigned long : 2;
+            unsigned long CIM: 1;
+            unsigned long : 3;
+            unsigned long IFS: 1;
+            unsigned long : 23;
+        } BIT;
+    } CAIFR;
+    char           wk0[4];
+    char           wk1[4];
+    char           wk2[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RC: 1;
+            unsigned long RS: 1;
+            unsigned long : 2;
+            unsigned long RVS: 1;
+            unsigned long : 27;
+        } BIT;
+    } CRCNTR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RA: 1;
+            unsigned long : 31;
+        } BIT;
+    } CRCMPR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFRAC: 12;
+            unsigned long HMANT: 4;
+            unsigned long VFRAC: 12;
+            unsigned long VMANT: 4;
+        } BIT;
+    } CFLCR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFCLP: 12;
+            unsigned long : 4;
+            unsigned long VFCLP: 12;
+            unsigned long : 4;
+        } BIT;
+    } CFSZR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CHDW: 13;
+            unsigned long : 19;
+        } BIT;
+    } CDWDR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR: 32;
+        } BIT;
+    } CDAYR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR: 32;
+        } BIT;
+    } CDACR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR: 32;
+        } BIT;
+    } CDBYR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR: 32;
+        } BIT;
+    } CDBCR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBVS: 23;
+            unsigned long : 9;
+        } BIT;
+    } CBDSR_A;
+    char           wk3[12];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long FWE: 1;
+            unsigned long : 4;
+            unsigned long FWV: 27;
+        } BIT;
+    } CFWCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LPF: 1;
+            unsigned long : 31;
+        } BIT;
+    } CLFCR_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COBS: 1;
+            unsigned long COWS: 1;
+            unsigned long COLS: 1;
+            unsigned long : 1;
+            unsigned long CDS: 1;
+            unsigned long : 3;
+            unsigned long : 1;
+            unsigned long : 7;
+            unsigned long CBE: 1;
+            unsigned long : 15;
+        } BIT;
+    } CDOCR_A;
+    char           wk4[4];
+    char           wk5[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CPEIE: 1;
+            unsigned long CFEIE: 1;
+            unsigned long : 2;
+            unsigned long IGRWIE: 1;
+            unsigned long : 3;
+            unsigned long HDIE: 1;
+            unsigned long VDIE: 1;
+            unsigned long : 2;
+            unsigned long CPBE1IE: 1;
+            unsigned long CPBE2IE: 1;
+            unsigned long CPBE3IE: 1;
+            unsigned long CPBE4IE: 1;
+            unsigned long CDTOFIE: 1;
+            unsigned long IGHSIE: 1;
+            unsigned long IGVSIE: 1;
+            unsigned long : 1;
+            unsigned long VBPIE: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long FWFIE: 1;
+            unsigned long NHDIE: 1;
+            unsigned long NVDIE: 1;
+            unsigned long : 6;
+        } BIT;
+    } CEIER;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CPE: 1;
+            unsigned long CFE: 1;
+            unsigned long : 2;
+            unsigned long IGRW: 1;
+            unsigned long : 3;
+            unsigned long HD: 1;
+            unsigned long VD: 1;
+            unsigned long : 2;
+            unsigned long CPBE1: 1;
+            unsigned long CPBE2: 1;
+            unsigned long CPBE3: 1;
+            unsigned long CPBE4: 1;
+            unsigned long CDTOF: 1;
+            unsigned long IGHS: 1;
+            unsigned long IGVS: 1;
+            unsigned long : 1;
+            unsigned long VBP: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long FWF: 1;
+            unsigned long NHD: 1;
+            unsigned long NVD: 1;
+            unsigned long : 6;
+        } BIT;
+    } CETCR;
+    char           wk6[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CPTON: 1;
+            unsigned long : 7;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 6;
+            unsigned long CPFLD: 1;
+            unsigned long : 7;
+            unsigned long CRST: 1;
+            unsigned long : 7;
+        } BIT;
+    } CSTSR;
+    char           wk7[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CDSS: 32;
+        } BIT;
+    } CDSSR;
+    char           wk8[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR2: 32;
+        } BIT;
+    } CDAYR2_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR2: 32;
+        } BIT;
+    } CDACR2_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR2: 32;
+        } BIT;
+    } CDBYR2_A;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR2: 32;
+        } BIT;
+    } CDBCR2_A;
+    char           wk9[3952];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HOFST: 13;
+            unsigned long : 3;
+            unsigned long VOFST: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAMOR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HWDTH: 13;
+            unsigned long : 3;
+            unsigned long VWDTH: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAPWR_B;
+    char           wk10[24];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFRAC: 12;
+            unsigned long HMANT: 4;
+            unsigned long VFRAC: 12;
+            unsigned long VMANT: 4;
+        } BIT;
+    } CFLCR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFCLP: 12;
+            unsigned long : 4;
+            unsigned long VFCLP: 12;
+            unsigned long : 4;
+        } BIT;
+    } CFSZR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CHDW: 13;
+            unsigned long : 19;
+        } BIT;
+    } CDWDR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR: 32;
+        } BIT;
+    } CDAYR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR: 32;
+        } BIT;
+    } CDACR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR: 32;
+        } BIT;
+    } CDBYR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR: 32;
+        } BIT;
+    } CDBCR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBVS: 23;
+            unsigned long : 9;
+        } BIT;
+    } CBDSR_B;
+    char           wk11[16];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LPF: 1;
+            unsigned long : 31;
+        } BIT;
+    } CLFCR_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COBS: 1;
+            unsigned long COWS: 1;
+            unsigned long COLS: 1;
+            unsigned long : 1;
+            unsigned long CDS: 1;
+            unsigned long : 3;
+            unsigned long : 1;
+            unsigned long : 7;
+            unsigned long CBE: 1;
+            unsigned long : 15;
+        } BIT;
+    } CDOCR_B;
+    char           wk12[4];
+    char           wk13[4];
+    char           wk14[32];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR2: 32;
+        } BIT;
+    } CDAYR2_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR2: 32;
+        } BIT;
+    } CDACR2_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR2: 32;
+        } BIT;
+    } CDBYR2_B;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR2: 32;
+        } BIT;
+    } CDBCR2_B;
+    char           wk15[3952];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HOFST: 13;
+            unsigned long : 3;
+            unsigned long VOFST: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAMOR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HWDTH: 13;
+            unsigned long : 3;
+            unsigned long VWDTH: 12;
+            unsigned long : 4;
+        } BIT;
+    } CAPWR_M;
+    char           wk16[24];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFRAC: 12;
+            unsigned long HMANT: 4;
+            unsigned long VFRAC: 12;
+            unsigned long VMANT: 4;
+        } BIT;
+    } CFLCR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long HFCLP: 12;
+            unsigned long : 4;
+            unsigned long VFCLP: 12;
+            unsigned long : 4;
+        } BIT;
+    } CFSZR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CHDW: 13;
+            unsigned long : 19;
+        } BIT;
+    } CDWDR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR: 32;
+        } BIT;
+    } CDAYR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR: 32;
+        } BIT;
+    } CDACR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR: 32;
+        } BIT;
+    } CDBYR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR: 32;
+        } BIT;
+    } CDBCR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBVS: 23;
+            unsigned long : 9;
+        } BIT;
+    } CBDSR_M;
+    char           wk17[16];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LPF: 1;
+            unsigned long : 31;
+        } BIT;
+    } CLFCR_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COBS: 1;
+            unsigned long COWS: 1;
+            unsigned long COLS: 1;
+            unsigned long : 1;
+            unsigned long CDS: 1;
+            unsigned long : 3;
+            unsigned long : 1;
+            unsigned long : 7;
+            unsigned long CBE: 1;
+            unsigned long : 15;
+        } BIT;
+    } CDOCR_M;
+    char           wk18[4];
+    char           wk19[4];
+    char           wk20[32];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAYR2: 32;
+        } BIT;
+    } CDAYR2_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CACR2: 32;
+        } BIT;
+    } CDACR2_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBYR2: 32;
+        } BIT;
+    } CDBYR2_M;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CBCR2: 32;
+        } BIT;
+    } CDBCR2_M;
+};
+
+#define CEU       (*(volatile struct st_ceu       *)0xE8210000)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/cpg_iodefine.h

@@ -0,0 +1,369 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef CPG_IODEFINE_H
+#define CPG_IODEFINE_H
+
+struct st_cpg {
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short PFC: 2;
+            unsigned short : 1;
+            unsigned short : 1;
+            unsigned short BFC: 2;
+            unsigned short : 2;
+            unsigned short IFC: 2;
+            unsigned short : 2;
+            unsigned short CKOEN: 2;
+            unsigned short CKOEN2: 1;
+            unsigned short : 1;
+        } BIT;
+    } FRQCR;
+    char           wk0[6];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 1;
+            unsigned char : 1;
+            unsigned char : 2;
+            unsigned char ISBUSY: 1;
+            unsigned char : 3;
+        } BIT;
+    } CPUSTS;
+    char           wk1[7];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 6;
+            unsigned char DEEP: 1;
+            unsigned char STBY: 1;
+        } BIT;
+    } STBCR1;
+    char           wk2[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP20: 1;
+            unsigned char : 6;
+            unsigned char HIZ: 1;
+        } BIT;
+    } STBCR2;
+    char           wk3[11];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBRQ10: 1;
+            unsigned char STBRQ11: 1;
+            unsigned char STBRQ12: 1;
+            unsigned char STBRQ13: 1;
+            unsigned char : 1;
+            unsigned char STBRQ15: 1;
+            unsigned char : 1;
+            unsigned char : 1;
+        } BIT;
+    } STBREQ1;
+    char           wk4[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBRQ20: 1;
+            unsigned char STBRQ21: 1;
+            unsigned char STBRQ22: 1;
+            unsigned char STBRQ23: 1;
+            unsigned char STBRQ24: 1;
+            unsigned char STBRQ25: 1;
+            unsigned char STBRQ26: 1;
+            unsigned char STBRQ27: 1;
+        } BIT;
+    } STBREQ2;
+    char           wk5[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBRQ30: 1;
+            unsigned char STBRQ31: 1;
+            unsigned char STBRQ32: 1;
+            unsigned char STBRQ33: 1;
+            unsigned char : 4;
+        } BIT;
+    } STBREQ3;
+    char           wk6[7];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBAK10: 1;
+            unsigned char STBAK11: 1;
+            unsigned char STBAK12: 1;
+            unsigned char STBAK13: 1;
+            unsigned char : 1;
+            unsigned char STBAK15: 1;
+            unsigned char : 1;
+            unsigned char : 1;
+        } BIT;
+    } STBACK1;
+    char           wk7[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBAK20: 1;
+            unsigned char STBAK21: 1;
+            unsigned char STBAK22: 1;
+            unsigned char STBAK23: 1;
+            unsigned char STBAK24: 1;
+            unsigned char STBAK25: 1;
+            unsigned char STBAK26: 1;
+            unsigned char STBAK27: 1;
+        } BIT;
+    } STBACK2;
+    char           wk8[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char STBAK30: 1;
+            unsigned char STBAK31: 1;
+            unsigned char STBAK32: 1;
+            unsigned char STBAK33: 1;
+            unsigned char : 4;
+        } BIT;
+    } STBACK3;
+    char           wk9[183];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short CKIOSEL: 2;
+            unsigned short : 14;
+        } BIT;
+    } CKIOSEL;
+    char           wk10[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short SPICR: 2;
+            unsigned short : 2;
+            unsigned short HYMCR: 2;
+            unsigned short : 2;
+            unsigned short OCTCR: 2;
+            unsigned short : 6;
+        } BIT;
+    } SCLKSEL;
+    char           wk11[762];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char VRAME0: 1;
+            unsigned char VRAME1: 1;
+            unsigned char VRAME2: 1;
+            unsigned char VRAME3: 1;
+            unsigned char VRAME4: 1;
+            unsigned char : 3;
+        } BIT;
+    } SYSCR1;
+    char           wk12[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char VRAMWE0: 1;
+            unsigned char VRAMWE1: 1;
+            unsigned char VRAMWE2: 1;
+            unsigned char VRAMWE3: 1;
+            unsigned char VRAMWE4: 1;
+            unsigned char : 3;
+        } BIT;
+    } SYSCR2;
+    char           wk13[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char RRAMWE0: 1;
+            unsigned char RRAMWE1: 1;
+            unsigned char RRAMWE2: 1;
+            unsigned char RRAMWE3: 1;
+            unsigned char : 4;
+        } BIT;
+    } SYSCR3;
+    char           wk14[23];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP30: 1;
+            unsigned char MSTP31: 1;
+            unsigned char MSTP32: 1;
+            unsigned char MSTP33: 1;
+            unsigned char MSTP34: 1;
+            unsigned char MSTP35: 1;
+            unsigned char MSTP36: 1;
+            unsigned char : 1;
+        } BIT;
+    } STBCR3;
+    char           wk15[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP40: 1;
+            unsigned char MSTP41: 1;
+            unsigned char MSTP42: 1;
+            unsigned char MSTP43: 1;
+            unsigned char MSTP44: 1;
+            unsigned char MSTP45: 1;
+            unsigned char MSTP46: 1;
+            unsigned char MSTP47: 1;
+        } BIT;
+    } STBCR4;
+    char           wk16[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 1;
+            unsigned char MSTP51: 1;
+            unsigned char MSTP52: 1;
+            unsigned char MSTP53: 1;
+            unsigned char : 2;
+            unsigned char MSTP56: 1;
+            unsigned char MSTP57: 1;
+        } BIT;
+    } STBCR5;
+    char           wk17[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP60: 1;
+            unsigned char MSTP61: 1;
+            unsigned char MSTP62: 1;
+            unsigned char MSTP63: 1;
+            unsigned char MSTP64: 1;
+            unsigned char MSTP65: 1;
+            unsigned char MSTP66: 1;
+            unsigned char : 1;
+        } BIT;
+    } STBCR6;
+    char           wk18[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP70: 1;
+            unsigned char MSTP71: 1;
+            unsigned char MSTP72: 1;
+            unsigned char MSTP73: 1;
+            unsigned char : 1;
+            unsigned char MSTP75: 1;
+            unsigned char MSTP76: 1;
+            unsigned char MSTP77: 1;
+        } BIT;
+    } STBCR7;
+    char           wk19[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 1;
+            unsigned char MSTP81: 1;
+            unsigned char : 1;
+            unsigned char MSTP83: 1;
+            unsigned char MSTP84: 1;
+            unsigned char MSTP85: 1;
+            unsigned char MSTP86: 1;
+            unsigned char MSTP87: 1;
+        } BIT;
+    } STBCR8;
+    char           wk20[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP90: 1;
+            unsigned char MSTP91: 1;
+            unsigned char MSTP92: 1;
+            unsigned char MSTP93: 1;
+            unsigned char : 1;
+            unsigned char MSTP95: 1;
+            unsigned char MSTP96: 1;
+            unsigned char MSTP97: 1;
+        } BIT;
+    } STBCR9;
+    char           wk21[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char MSTP100: 1;
+            unsigned char MSTP101: 1;
+            unsigned char MSTP102: 1;
+            unsigned char MSTP103: 1;
+            unsigned char MSTP104: 1;
+            unsigned char : 1;
+            unsigned char : 1;
+            unsigned char MSTP107: 1;
+        } BIT;
+    } STBCR10;
+    char           wk22[3];
+    char           wk23[1];
+    char           wk24[31];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char SRST10: 1;
+            unsigned char SRST11: 1;
+            unsigned char SRST12: 1;
+            unsigned char SRST13: 1;
+            unsigned char : 1;
+            unsigned char : 1;
+            unsigned char : 1;
+            unsigned char AXTALE: 1;
+        } BIT;
+    } SWRSTCR1;
+    char           wk25[3];
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 1;
+            unsigned char SRST21: 1;
+            unsigned char SRST22: 1;
+            unsigned char SRST23: 1;
+            unsigned char SRST24: 1;
+            unsigned char SRST25: 1;
+            unsigned char SRST26: 1;
+            unsigned char : 1;
+        } BIT;
+    } SWRSTCR2;
+};
+
+#define CPG       (*(volatile struct st_cpg       *)0xFCFE0010)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/csi2link_iodefine.h

@@ -0,0 +1,630 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef CSI2LINK_IODEFINE_H
+#define CSI2LINK_IODEFINE_H
+
+struct st_csi2link {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TREF: 1;
+            unsigned long : 31;
+        } BIT;
+    } TREF;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SRST: 1;
+            unsigned long : 31;
+        } BIT;
+    } SRST;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ENABLE_0: 1;
+            unsigned long ENABLE_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long ENABLECLK: 1;
+            unsigned long : 11;
+            unsigned long RSTZ: 1;
+            unsigned long SHUTDOWNZ: 1;
+            unsigned long : 14;
+        } BIT;
+    } PHYCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CRC_EN: 1;
+            unsigned long ECC_EN: 1;
+            unsigned long : 30;
+        } BIT;
+    } CHKSUM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SEL_DT: 6;
+            unsigned long SEL_DT_ON: 1;
+            unsigned long : 1;
+            unsigned long SEL_VC: 2;
+            unsigned long : 5;
+            unsigned long VCDT_EN: 1;
+            unsigned long : 6;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 2;
+            unsigned long : 5;
+            unsigned long : 1;
+        } BIT;
+    } VCDT;
+    char           wk0[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 16;
+            unsigned long DT_FE: 6;
+            unsigned long : 2;
+            unsigned long DT_FS: 6;
+            unsigned long : 2;
+        } BIT;
+    } FRDT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long FLD_EN: 1;
+            unsigned long : 3;
+            unsigned long FLD_DET_SEL: 2;
+            unsigned long : 10;
+            unsigned long FLD_NUM: 16;
+        } BIT;
+    } FLD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long AUTO_STANDBY_EN: 5;
+            unsigned long VD_MSK_EN: 1;
+            unsigned long : 2;
+            unsigned long VD_MSK_CYCLE: 6;
+            unsigned long : 18;
+        } BIT;
+    } ASTBY;
+    char           wk1[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LNGDT0: 32;
+        } BIT;
+    } LNGDT0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LNGDT1: 32;
+        } BIT;
+    } LNGDT1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long IEN: 32;
+        } BIT;
+    } INTEN;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ICL: 32;
+        } BIT;
+    } INTCLOSE;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long IST: 32;
+        } BIT;
+    } INTSTATE;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long IEST: 16;
+            unsigned long : 16;
+        } BIT;
+    } INTERRSTATE;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long DATA: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } SHPDAT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long NUM: 4;
+            unsigned long : 12;
+            unsigned long OVF: 1;
+            unsigned long : 15;
+        } BIT;
+    } SHPCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 24;
+            unsigned long : 1;
+            unsigned long REG_MONI_PACT_EN: 1;
+            unsigned long : 5;
+            unsigned long MONITOR_EN: 1;
+        } BIT;
+    } LINKCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long L0SEL: 2;
+            unsigned long L1SEL: 2;
+            unsigned long : 2;
+            unsigned long : 2;
+            unsigned long : 24;
+        } BIT;
+    } LSWAP;
+    char           wk2[4];
+    char           wk3[4];
+    char           wk4[4];
+    char           wk5[12];
+    char           wk6[4];
+    char           wk7[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ERRCONTROL_0: 1;
+            unsigned long ERRCONTROL_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 4;
+            unsigned long ERRESC_0: 1;
+            unsigned long ERRESC_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long CL_ERRCONTROL: 1;
+            unsigned long : 19;
+        } BIT;
+    } PHEERM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long STOPSTATECLK: 1;
+            unsigned long RXCLKACTIVEHS: 1;
+            unsigned long RXULPSCLKNOT: 1;
+            unsigned long ULPSACTIVENOTCLK: 1;
+            unsigned long : 28;
+        } BIT;
+    } PHCLM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long STOPSTATEDATA_0: 1;
+            unsigned long STOPSTATEDATA_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 4;
+            unsigned long RXULPSESC_0: 1;
+            unsigned long RXULPSESC_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long ULPSACTIVENOT_0: 1;
+            unsigned long ULPSACTIVENOT_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 16;
+        } BIT;
+    } PHDLM;
+    char           wk8[112];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long : 8;
+        } BIT;
+    } PH0M0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PH_CNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } PH0M1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long : 8;
+        } BIT;
+    } PH1M0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PH_CNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } PH1M1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long : 8;
+        } BIT;
+    } PH2M0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PH_CNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } PH2M1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long : 8;
+        } BIT;
+    } PH3M0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PH_CNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } PH3M1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHRM0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHRM1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHRM2;
+    char           wk9[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long CAL_PARITY: 8;
+        } BIT;
+    } PHCM0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long CAL_PARITY: 8;
+        } BIT;
+    } PHCM1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAL_CRC: 16;
+            unsigned long CRC: 16;
+        } BIT;
+    } CRCM0;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CAL_CRC: 16;
+            unsigned long CRC: 16;
+        } BIT;
+    } CRCM1;
+    char           wk10[16];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ERRSOTHS_CNT: 8;
+            unsigned long : 24;
+        } BIT;
+    } SERRCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ERRSOTSYNCHS: 4;
+            unsigned long : 28;
+        } BIT;
+    } SSERRCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ECC_CRCT_CNT: 8;
+            unsigned long : 24;
+        } BIT;
+    } ECCCM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ECC_ERR_CNT: 8;
+            unsigned long : 24;
+        } BIT;
+    } ECECM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CRC_ERR_CNT: 8;
+            unsigned long : 24;
+        } BIT;
+    } CRCECM;
+    char           wk11[12];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LINE_CNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } LCNT;
+    char           wk12[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MONI_LINECNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } LCNTM;
+    char           wk13[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MONI_FCOUNT: 16;
+            unsigned long : 16;
+        } BIT;
+    } FCNTM;
+    char           wk14[4];
+    char           wk15[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RXDATAHS_0: 8;
+            unsigned long RXDATAHS_1: 8;
+            unsigned long : 8;
+            unsigned long : 8;
+        } BIT;
+    } PHYDIM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RXSYNCHS_0_CNT: 4;
+            unsigned long RXSYNCHS_1_CNT: 4;
+            unsigned long : 4;
+            unsigned long : 4;
+            unsigned long RXACTIVEHS_0: 1;
+            unsigned long RXACTIVEHS_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long RXVALIDHS_0: 1;
+            unsigned long RXVALIDHS_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 7;
+            unsigned long RXCLK_CNT: 1;
+        } BIT;
+    } PHYIM;
+    char           wk16[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSIR_DAT: 32;
+        } BIT;
+    } VINDM;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSIR_HD_CNT: 12;
+            unsigned long CSIR_VD_CNT: 4;
+            unsigned long : 12;
+            unsigned long : 4;
+        } BIT;
+    } VINSM1;
+    char           wk17[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSIR_PE: 1;
+            unsigned long : 3;
+            unsigned long CSIR_PEB: 4;
+            unsigned long CSIR_FLD: 4;
+            unsigned long CSIR_TAG: 2;
+            unsigned long CSIR_ERRC: 1;
+            unsigned long CSIR_ERRE: 1;
+            unsigned long : 16;
+        } BIT;
+    } VINSM3;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ENABLE_0: 1;
+            unsigned long ENABLE_1: 1;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long ENABLECLK: 1;
+            unsigned long : 27;
+        } BIT;
+    } PHYOM;
+    char           wk18[32];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM2;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM3;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM4;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM5;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM6;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM7;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DT: 6;
+            unsigned long VC: 2;
+            unsigned long WC: 16;
+            unsigned long ECC: 8;
+        } BIT;
+    } PHM8;
+    char           wk19[4];
+    char           wk20[4];
+    char           wk21[4];
+    char           wk22[4];
+    char           wk23[4];
+    char           wk24[4];
+    char           wk25[4];
+    char           wk26[4];
+    char           wk27[84];
+    char           wk28[4];
+    char           wk29[12];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long T_INIT_SLAVE: 16;
+            unsigned long : 16;
+        } BIT;
+    } PHYTIM1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TCLK_PREPARE: 5;
+            unsigned long : 3;
+            unsigned long TCLK_SETTLE: 6;
+            unsigned long : 2;
+            unsigned long TCLK_MISS: 5;
+            unsigned long : 11;
+        } BIT;
+    } PHYTIM2;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long THS_PREPARE: 6;
+            unsigned long : 2;
+            unsigned long THS_SETTLE: 6;
+            unsigned long : 18;
+        } BIT;
+    } PHYTIM3;
+    char           wk30[4];
+};
+
+#define CSI2LINK  (*(volatile struct st_csi2link  *)0xE8209000)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drpk_iodefine.h

@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef DRPK_IODEFINE_H
+#define DRPK_IODEFINE_H
+
+struct st_drpk {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA0;
+    char           wk0[508];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA1;
+    char           wk1[508];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA2;
+    char           wk2[508];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA3;
+    char           wk3[508];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA4;
+    char           wk4[508];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned short L;
+            unsigned short H;
+        } WORD;
+        struct {
+            unsigned long FIFODATA: 32;
+        } BIT;
+    } FIFODATA5;
+};
+
+#define DRPK      (*(volatile struct st_drpk      *)0xEAFD3000)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drw_iodefine.h

@@ -0,0 +1,432 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef DRW_IODEFINE_H
+#define DRW_IODEFINE_H
+
+struct st_drw {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LIM1ENABLE: 1;
+            unsigned long LIM2ENABLE: 1;
+            unsigned long LIM3ENABLE: 1;
+            unsigned long LIM4ENABLE: 1;
+            unsigned long LIM5ENABLE: 1;
+            unsigned long LIM6ENABLE: 1;
+            unsigned long QUAD1ENABLE: 1;
+            unsigned long QUAD2ENABLE: 1;
+            unsigned long QUAD3ENABLE: 1;
+            unsigned long LIM1THRESHOLD: 1;
+            unsigned long LIM2THRESHOLD: 1;
+            unsigned long LIM3THRESHOLD: 1;
+            unsigned long LIM4THRESHOLD: 1;
+            unsigned long LIM5THRESHOLD: 1;
+            unsigned long LIM6THRESHOLD: 1;
+            unsigned long BAND1ENABLE: 1;
+            unsigned long BAND2ENABLE: 1;
+            unsigned long UNION12: 1;
+            unsigned long UNION34: 1;
+            unsigned long UNION56: 1;
+            unsigned long UNIONAB: 1;
+            unsigned long UNIONCD: 1;
+            unsigned long SPANABORT: 1;
+            unsigned long SPANSTORE: 1;
+            unsigned long : 8;
+        } BIT;
+    } CONTROL;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PATTERNENABLE: 1;
+            unsigned long TEXTUREENABLE: 1;
+            unsigned long PATTERNSOURCEL5: 1;
+            unsigned long USEACB: 1;
+            unsigned long READFORMAT_3_2: 2;
+            unsigned long BSFA: 1;
+            unsigned long BDFA: 1;
+            unsigned long WRITEFORMAT_2: 1;
+            unsigned long BSF: 1;
+            unsigned long BDF: 1;
+            unsigned long BSI: 1;
+            unsigned long BDI: 1;
+            unsigned long BC2: 1;
+            unsigned long TEXTURECLAMPX: 1;
+            unsigned long TEXTURECLAMPY: 1;
+            unsigned long TEXTUREFILTERX: 1;
+            unsigned long TEXTUREFILTERY: 1;
+            unsigned long READFORMAT_1_0: 2;
+            unsigned long WRITEFORMAT_1_0: 2;
+            unsigned long WRITEALPHA: 2;
+            unsigned long RLEENABLE: 1;
+            unsigned long CLUTENABLE: 1;
+            unsigned long COLKEYENABLE: 1;
+            unsigned long CLUTFORMAT: 1;
+            unsigned long BSIA: 1;
+            unsigned long BDIA: 1;
+            unsigned long RLEPIXELWIDTH: 2;
+        } BIT;
+    } CONTROL2;
+    char           wk0[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L1START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L2START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L3START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L4START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L5START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LSTART: 32;
+        } BIT;
+    } L6START;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L1XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L2XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L3XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L4XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L5XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LXADD: 32;
+        } BIT;
+    } L6XADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L1YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L2YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L3YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L4YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L5YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LYADD: 32;
+        } BIT;
+    } L6YADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LBAND: 32;
+        } BIT;
+    } L1BAND;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LBAND: 32;
+        } BIT;
+    } L2BAND;
+    char           wk1[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COLOR1B: 8;
+            unsigned long COLOR1G: 8;
+            unsigned long COLOR1R: 8;
+            unsigned long COLOR1A: 8;
+        } BIT;
+    } COLOR1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COLOR2B: 8;
+            unsigned long COLOR2G: 8;
+            unsigned long COLOR2R: 8;
+            unsigned long COLOR2A: 8;
+        } BIT;
+    } COLOR2;
+    char           wk2[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PATTERN: 8;
+            unsigned long : 24;
+        } BIT;
+    } PATTERN;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SIZEX: 16;
+            unsigned long SIZEY: 16;
+        } BIT;
+    } SIZE;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PITCH: 16;
+            unsigned long SSD: 16;
+        } BIT;
+    } PITCH;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ORIGIN: 32;
+        } BIT;
+    } ORIGIN;
+    char           wk3[12];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LUSTART: 32;
+        } BIT;
+    } LUSTART;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LUXADD: 32;
+        } BIT;
+    } LUXADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LUYADD: 32;
+        } BIT;
+    } LUYADD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LVSTARTI: 32;
+        } BIT;
+    } LVSTARTI;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LVSTARTF: 16;
+            unsigned long : 16;
+        } BIT;
+    } LVSTARTF;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LVXADDI: 32;
+        } BIT;
+    } LVXADDI;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LVYADDI: 32;
+        } BIT;
+    } LVYADDI;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LVXADDF: 16;
+            unsigned long LVYADDF: 16;
+        } BIT;
+    } LVYXADDF;
+    char           wk4[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TEXPITCH: 11;
+            unsigned long : 21;
+        } BIT;
+    } TEXPITCH;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TEXUMASK: 11;
+            unsigned long TEXVMASK: 21;
+        } BIT;
+    } TEXMASK;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TEXORIGIN: 32;
+        } BIT;
+    } TEXORIGIN;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ENUMIRQEN: 1;
+            unsigned long DLISTIRQEN: 1;
+            unsigned long ENUMIRQCLR: 1;
+            unsigned long DLISTIRQCLR: 1;
+            unsigned long BUSIRQEN: 1;
+            unsigned long BUSIRQCLR: 1;
+            unsigned long : 26;
+        } BIT;
+    } IRQCTL;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CENABLEFX: 1;
+            unsigned long CFLUSHFX: 1;
+            unsigned long CENABLETX: 1;
+            unsigned long CFLUSHTX: 1;
+            unsigned long : 28;
+        } BIT;
+    } CACHECTL;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DLISTSTART: 32;
+        } BIT;
+    } DLISTSTART;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PERFCOUNT: 32;
+        } BIT;
+    } PERFCOUNT1;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PERFCOUNT: 32;
+        } BIT;
+    } PERFCOUNT2;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PERFTRIGGER1: 5;
+            unsigned long : 11;
+            unsigned long PERFTRIGGER2: 5;
+            unsigned long : 11;
+        } BIT;
+    } PERFTRIGGER;
+    char           wk5[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CLADDR: 8;
+            unsigned long : 24;
+        } BIT;
+    } TEXCLADDR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CLDATA: 32;
+        } BIT;
+    } TEXCLDATA;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CLOFFSET: 8;
+            unsigned long : 24;
+        } BIT;
+    } TEXCLOFFSET;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long COLKEYB: 8;
+            unsigned long COLKEYG: 8;
+            unsigned long COLKEYR: 8;
+            unsigned long : 8;
+        } BIT;
+    } COLKEY;
+};
+
+#define DRW       (*(volatile struct st_drw       *)0xE820A000)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/edmac_iodefine.h

@@ -0,0 +1,277 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef EDMAC_IODEFINE_H
+#define EDMAC_IODEFINE_H
+
+struct st_edmac {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SWR: 1;
+            unsigned long : 3;
+            unsigned long DL: 2;
+            unsigned long DE: 1;
+            unsigned long : 25;
+        } BIT;
+    } EDMR;
+    char           wk0[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TR: 1;
+            unsigned long : 31;
+        } BIT;
+    } EDTRR;
+    char           wk1[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RR: 1;
+            unsigned long : 31;
+        } BIT;
+    } EDRRR;
+    char           wk2[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TDLAR: 32;
+        } BIT;
+    } TDLAR;
+    char           wk3[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RDLAR: 32;
+        } BIT;
+    } RDLAR;
+    char           wk4[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CERF: 1;
+            unsigned long PRE: 1;
+            unsigned long RTSF: 1;
+            unsigned long RTLF: 1;
+            unsigned long RRF: 1;
+            unsigned long : 2;
+            unsigned long RMAF: 1;
+            unsigned long TRO: 1;
+            unsigned long CD: 1;
+            unsigned long DLC: 1;
+            unsigned long CND: 1;
+            unsigned long : 4;
+            unsigned long RFOF: 1;
+            unsigned long RDE: 1;
+            unsigned long FR: 1;
+            unsigned long TFUF: 1;
+            unsigned long TDE: 1;
+            unsigned long TC: 1;
+            unsigned long ECI: 1;
+            unsigned long : 1;
+            unsigned long RFCOF: 1;
+            unsigned long RABT: 1;
+            unsigned long TABT: 1;
+            unsigned long : 3;
+            unsigned long TWB: 1;
+            unsigned long : 1;
+        } BIT;
+    } EESR;
+    char           wk5[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CERFIP: 1;
+            unsigned long PREIP: 1;
+            unsigned long RTSFIP: 1;
+            unsigned long RTLFIP: 1;
+            unsigned long RRFIP: 1;
+            unsigned long : 2;
+            unsigned long RMAFIP: 1;
+            unsigned long TROIP: 1;
+            unsigned long CDIP: 1;
+            unsigned long DLCIP: 1;
+            unsigned long CNDIP: 1;
+            unsigned long : 4;
+            unsigned long RFOFIP: 1;
+            unsigned long RDEIP: 1;
+            unsigned long FRIP: 1;
+            unsigned long TFUFIP: 1;
+            unsigned long TDEIP: 1;
+            unsigned long TCIP: 1;
+            unsigned long ECIIP: 1;
+            unsigned long : 1;
+            unsigned long RFCOFIP: 1;
+            unsigned long RABTIP: 1;
+            unsigned long TABTIP: 1;
+            unsigned long : 3;
+            unsigned long TWBIP: 1;
+            unsigned long : 1;
+        } BIT;
+    } EESIPR;
+    char           wk6[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long : 4;
+            unsigned long RRFCE: 1;
+            unsigned long : 2;
+            unsigned long RMAFCE: 1;
+            unsigned long : 24;
+        } BIT;
+    } TRSCER;
+    char           wk7[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MFC: 16;
+            unsigned long : 16;
+        } BIT;
+    } RMFCR;
+    char           wk8[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TFT: 11;
+            unsigned long : 21;
+        } BIT;
+    } TFTR;
+    char           wk9[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RFD: 5;
+            unsigned long : 3;
+            unsigned long TFD: 5;
+            unsigned long : 19;
+        } BIT;
+    } FDR;
+    char           wk10[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RNR: 1;
+            unsigned long : 31;
+        } BIT;
+    } RMCR;
+    char           wk11[8];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long UNDER: 16;
+            unsigned long : 16;
+        } BIT;
+    } TFUCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long OVER: 16;
+            unsigned long : 16;
+        } BIT;
+    } RFOCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ELB: 1;
+            unsigned long : 31;
+        } BIT;
+    } IOSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RFDO: 3;
+            unsigned long : 13;
+            unsigned long RFFO: 3;
+            unsigned long : 13;
+        } BIT;
+    } FCFTR;
+    char           wk12[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PADR: 6;
+            unsigned long : 10;
+            unsigned long PADS: 2;
+            unsigned long : 14;
+        } BIT;
+    } RPADIR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TIS: 1;
+            unsigned long : 3;
+            unsigned long TIM: 1;
+            unsigned long : 27;
+        } BIT;
+    } TRIMD;
+    char           wk13[72];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RBWAR: 32;
+        } BIT;
+    } RBWAR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RDFAR: 32;
+        } BIT;
+    } RDFAR;
+    char           wk14[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TBRAR: 32;
+        } BIT;
+    } TBRAR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TDFAR: 32;
+        } BIT;
+    } TDFAR;
+};
+
+#define EDMAC0    (*(volatile struct st_edmac     *)0xE8204000)
+#define EDMAC1    (*(volatile struct st_edmac     *)0xE8204200)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/etherc_iodefine.h

@@ -0,0 +1,264 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef ETHERC_IODEFINE_H
+#define ETHERC_IODEFINE_H
+
+struct st_etherc {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PRM: 1;
+            unsigned long DM: 1;
+            unsigned long RTM: 1;
+            unsigned long ILB: 1;
+            unsigned long : 1;
+            unsigned long TE: 1;
+            unsigned long RE: 1;
+            unsigned long : 2;
+            unsigned long MPDE: 1;
+            unsigned long : 2;
+            unsigned long PRCEF: 1;
+            unsigned long : 3;
+            unsigned long TXF: 1;
+            unsigned long RXF: 1;
+            unsigned long PFR: 1;
+            unsigned long ZPF: 1;
+            unsigned long TPC: 1;
+            unsigned long : 11;
+        } BIT;
+    } ECMR;
+    char           wk0[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RFL: 12;
+            unsigned long : 20;
+        } BIT;
+    } RFLR;
+    char           wk1[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ICD: 1;
+            unsigned long MPD: 1;
+            unsigned long LCHNG: 1;
+            unsigned long : 1;
+            unsigned long PSRTO: 1;
+            unsigned long BFR: 1;
+            unsigned long : 26;
+        } BIT;
+    } ECSR;
+    char           wk2[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ICDIP: 1;
+            unsigned long MPDIP: 1;
+            unsigned long LCHNGIP: 1;
+            unsigned long : 1;
+            unsigned long PSRTOIP: 1;
+            unsigned long BFSIPR: 1;
+            unsigned long : 26;
+        } BIT;
+    } ECSIPR;
+    char           wk3[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MDC: 1;
+            unsigned long MMD: 1;
+            unsigned long MDO: 1;
+            unsigned long MDI: 1;
+            unsigned long : 28;
+        } BIT;
+    } PIR;
+    char           wk4[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LMON: 1;
+            unsigned long : 31;
+        } BIT;
+    } PSR;
+    char           wk5[20];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RMD: 20;
+            unsigned long : 12;
+        } BIT;
+    } RDMLR;
+    char           wk6[12];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long IPG: 5;
+            unsigned long : 27;
+        } BIT;
+    } IPGR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long AP: 16;
+            unsigned long : 16;
+        } BIT;
+    } APR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MP: 16;
+            unsigned long : 16;
+        } BIT;
+    } MPR;
+    char           wk7[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RPAUSE: 8;
+            unsigned long : 24;
+        } BIT;
+    } RFCF;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TPAUSE: 16;
+            unsigned long : 16;
+        } BIT;
+    } TPAUSER;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TXP: 8;
+            unsigned long : 24;
+        } BIT;
+    } TPAUSECR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long BCF: 16;
+            unsigned long : 16;
+        } BIT;
+    } BCFRR;
+    char           wk8[80];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MAHR: 32;
+        } BIT;
+    } MAHR;
+    char           wk9[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MALR: 16;
+            unsigned long : 16;
+        } BIT;
+    } MALR;
+    char           wk10[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TROCR: 32;
+        } BIT;
+    } TROCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CDCR: 32;
+        } BIT;
+    } CDCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long LCCR: 32;
+        } BIT;
+    } LCCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CNDCR: 32;
+        } BIT;
+    } CNDCR;
+    char           wk11[4];
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CEFCR: 32;
+        } BIT;
+    } CEFCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long FRECR: 32;
+        } BIT;
+    } FRECR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TSFRCR: 32;
+        } BIT;
+    } TSFRCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TLFRCR: 32;
+        } BIT;
+    } TLFRCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long RFCR: 32;
+        } BIT;
+    } RFCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long MAFCR: 32;
+        } BIT;
+    } MAFCR;
+};
+
+#define ETHERC0   (*(volatile struct st_etherc    *)0xE8204100)
+#define ETHERC1   (*(volatile struct st_etherc    *)0xE8204300)
+
+#endif

targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpt_iodefine.h

@@ -0,0 +1,687 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*******************************************************************************
+* Rev: 2.00
+* Description : IO define header
+*******************************************************************************/
+
+#ifndef GPT_IODEFINE_H
+#define GPT_IODEFINE_H
+
+struct st_gpt {
+    union {
+        unsigned char BYTE;
+        struct {
+            unsigned char : 7;
+            unsigned char EVCON: 1;
+        } BIT;
+    } GTECR;
+    char           wk0[15];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR0;
+    char           wk1[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR1;
+    char           wk2[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR2;
+    char           wk3[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR3;
+    char           wk4[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR4;
+    char           wk5[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR5;
+    char           wk6[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR6;
+    char           wk7[2];
+    union {
+        unsigned short WORD;
+        struct {
+            unsigned short EVS: 7;
+            unsigned short : 9;
+        } BIT;
+    } GTESR7;
+};
+
+struct st_gpt32e {
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long WP: 1;
+            unsigned long : 7;
+            unsigned long PRKEY: 8;
+            unsigned long : 16;
+        } BIT;
+    } GTWP;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSTRT0: 1;
+            unsigned long CSTRT1: 1;
+            unsigned long CSTRT2: 1;
+            unsigned long CSTRT3: 1;
+            unsigned long CSTRT4: 1;
+            unsigned long CSTRT5: 1;
+            unsigned long CSTRT6: 1;
+            unsigned long CSTRT7: 1;
+            unsigned long : 24;
+        } BIT;
+    } GTSTR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSTOP0: 1;
+            unsigned long CSTOP1: 1;
+            unsigned long CSTOP2: 1;
+            unsigned long CSTOP3: 1;
+            unsigned long CSTOP4: 1;
+            unsigned long CSTOP5: 1;
+            unsigned long CSTOP6: 1;
+            unsigned long CSTOP7: 1;
+            unsigned long : 24;
+        } BIT;
+    } GTSTP;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CCLR0: 1;
+            unsigned long CCLR1: 1;
+            unsigned long CCLR2: 1;
+            unsigned long CCLR3: 1;
+            unsigned long CCLR4: 1;
+            unsigned long CCLR5: 1;
+            unsigned long CCLR6: 1;
+            unsigned long CCLR7: 1;
+            unsigned long : 24;
+        } BIT;
+    } GTCLR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SSGTRGAR: 1;
+            unsigned long SSGTRGAF: 1;
+            unsigned long SSGTRGBR: 1;
+            unsigned long SSGTRGBF: 1;
+            unsigned long SSGTRGCR: 1;
+            unsigned long SSGTRGCF: 1;
+            unsigned long SSGTRGDR: 1;
+            unsigned long SSGTRGDF: 1;
+            unsigned long SSCARBL: 1;
+            unsigned long SSCARBH: 1;
+            unsigned long SSCAFBL: 1;
+            unsigned long SSCAFBH: 1;
+            unsigned long SSCBRAL: 1;
+            unsigned long SSCBRAH: 1;
+            unsigned long SSCBFAL: 1;
+            unsigned long SSCBFAH: 1;
+            unsigned long SSEVTA: 1;
+            unsigned long SSEVTB: 1;
+            unsigned long SSEVTC: 1;
+            unsigned long SSEVTD: 1;
+            unsigned long SSEVTE: 1;
+            unsigned long SSEVTF: 1;
+            unsigned long SSEVTG: 1;
+            unsigned long SSEVTH: 1;
+            unsigned long : 7;
+            unsigned long CSTRT: 1;
+        } BIT;
+    } GTSSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long PSGTRGAR: 1;
+            unsigned long PSGTRGAF: 1;
+            unsigned long PSGTRGBR: 1;
+            unsigned long PSGTRGBF: 1;
+            unsigned long PSGTRGCR: 1;
+            unsigned long PSGTRGCF: 1;
+            unsigned long PSGTRGDR: 1;
+            unsigned long PSGTRGDF: 1;
+            unsigned long PSCARBL: 1;
+            unsigned long PSCARBH: 1;
+            unsigned long PSCAFBL: 1;
+            unsigned long PSCAFBH: 1;
+            unsigned long PSCBRAL: 1;
+            unsigned long PSCBRAH: 1;
+            unsigned long PSCBFAL: 1;
+            unsigned long PSCBFAH: 1;
+            unsigned long PSEVTA: 1;
+            unsigned long PSEVTB: 1;
+            unsigned long PSEVTC: 1;
+            unsigned long PSEVTD: 1;
+            unsigned long PSEVTE: 1;
+            unsigned long PSEVTF: 1;
+            unsigned long PSEVTG: 1;
+            unsigned long PSEVTH: 1;
+            unsigned long : 7;
+            unsigned long CSTOP: 1;
+        } BIT;
+    } GTPSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CSGTRGAR: 1;
+            unsigned long CSGTRGAF: 1;
+            unsigned long CSGTRGBR: 1;
+            unsigned long CSGTRGBF: 1;
+            unsigned long CSGTRGCR: 1;
+            unsigned long CSGTRGCF: 1;
+            unsigned long CSGTRGDR: 1;
+            unsigned long CSGTRGDF: 1;
+            unsigned long CSCARBL: 1;
+            unsigned long CSCARBH: 1;
+            unsigned long CSCAFBL: 1;
+            unsigned long CSCAFBH: 1;
+            unsigned long CSCBRAL: 1;
+            unsigned long CSCBRAH: 1;
+            unsigned long CSCBFAL: 1;
+            unsigned long CSCBFAH: 1;
+            unsigned long CSEVTA: 1;
+            unsigned long CSEVTB: 1;
+            unsigned long CSEVTC: 1;
+            unsigned long CSEVTD: 1;
+            unsigned long CSEVTE: 1;
+            unsigned long CSEVTF: 1;
+            unsigned long CSEVTG: 1;
+            unsigned long CSEVTH: 1;
+            unsigned long : 7;
+            unsigned long CCLR: 1;
+        } BIT;
+    } GTCSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long USGTRGAR: 1;
+            unsigned long USGTRGAF: 1;
+            unsigned long USGTRGBR: 1;
+            unsigned long USGTRGBF: 1;
+            unsigned long USGTRGCR: 1;
+            unsigned long USGTRGCF: 1;
+            unsigned long USGTRGDR: 1;
+            unsigned long USGTRGDF: 1;
+            unsigned long USCARBL: 1;
+            unsigned long USCARBH: 1;
+            unsigned long USCAFBL: 1;
+            unsigned long USCAFBH: 1;
+            unsigned long USCBRAL: 1;
+            unsigned long USCBRAH: 1;
+            unsigned long USCBFAL: 1;
+            unsigned long USCBFAH: 1;
+            unsigned long USEVTA: 1;
+            unsigned long USEVTB: 1;
+            unsigned long USEVTC: 1;
+            unsigned long USEVTD: 1;
+            unsigned long USEVTE: 1;
+            unsigned long USEVTF: 1;
+            unsigned long USEVTG: 1;
+            unsigned long USEVTH: 1;
+            unsigned long : 8;
+        } BIT;
+    } GTUPSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long DSGTRGAR: 1;
+            unsigned long DSGTRGAF: 1;
+            unsigned long DSGTRGBR: 1;
+            unsigned long DSGTRGBF: 1;
+            unsigned long DSGTRGCR: 1;
+            unsigned long DSGTRGCF: 1;
+            unsigned long DSGTRGDR: 1;
+            unsigned long DSGTRGDF: 1;
+            unsigned long DSCARBL: 1;
+            unsigned long DSCARBH: 1;
+            unsigned long DSCAFBL: 1;
+            unsigned long DSCAFBH: 1;
+            unsigned long DSCBRAL: 1;
+            unsigned long DSCBRAH: 1;
+            unsigned long DSCBFAL: 1;
+            unsigned long DSCBFAH: 1;
+            unsigned long DSEVTA: 1;
+            unsigned long DSEVTB: 1;
+            unsigned long DSEVTC: 1;
+            unsigned long DSEVTD: 1;
+            unsigned long DSEVTE: 1;
+            unsigned long DSEVTF: 1;
+            unsigned long DSEVTG: 1;
+            unsigned long DSEVTH: 1;
+            unsigned long : 8;
+        } BIT;
+    } GTDNSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ASGTRGAR: 1;
+            unsigned long ASGTRGAF: 1;
+            unsigned long ASGTRGBR: 1;
+            unsigned long ASGTRGBF: 1;
+            unsigned long ASGTRGCR: 1;
+            unsigned long ASGTRGCF: 1;
+            unsigned long ASGTRGDR: 1;
+            unsigned long ASGTRGDF: 1;
+            unsigned long ASCARBL: 1;
+            unsigned long ASCARBH: 1;
+            unsigned long ASCAFBL: 1;
+            unsigned long ASCAFBH: 1;
+            unsigned long ASCBRAL: 1;
+            unsigned long ASCBRAH: 1;
+            unsigned long ASCBFAL: 1;
+            unsigned long ASCBFAH: 1;
+            unsigned long ASEVTA: 1;
+            unsigned long ASEVTB: 1;
+            unsigned long ASEVTC: 1;
+            unsigned long ASEVTD: 1;
+            unsigned long ASEVTE: 1;
+            unsigned long ASEVTF: 1;
+            unsigned long ASEVTG: 1;
+            unsigned long ASEVTH: 1;
+            unsigned long : 8;
+        } BIT;
+    } GTICASR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long BSGTRGAR: 1;
+            unsigned long BSGTRGAF: 1;
+            unsigned long BSGTRGBR: 1;
+            unsigned long BSGTRGBF: 1;
+            unsigned long BSGTRGCR: 1;
+            unsigned long BSGTRGCF: 1;
+            unsigned long BSGTRGDR: 1;
+            unsigned long BSGTRGDF: 1;
+            unsigned long BSCARBL: 1;
+            unsigned long BSCARBH: 1;
+            unsigned long BSCAFBL: 1;
+            unsigned long BSCAFBH: 1;
+            unsigned long BSCBRAL: 1;
+            unsigned long BSCBRAH: 1;
+            unsigned long BSCBFAL: 1;
+            unsigned long BSCBFAH: 1;
+            unsigned long BSEVTA: 1;
+            unsigned long BSEVTB: 1;
+            unsigned long BSEVTC: 1;
+            unsigned long BSEVTD: 1;
+            unsigned long BSEVTE: 1;
+            unsigned long BSEVTF: 1;
+            unsigned long BSEVTG: 1;
+            unsigned long BSEVTH: 1;
+            unsigned long : 8;
+        } BIT;
+    } GTICBSR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long CST: 1;
+            unsigned long : 7;
+            unsigned long : 1;
+            unsigned long : 5;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long MD: 3;
+            unsigned long : 5;
+            unsigned long TPCS: 3;
+            unsigned long : 5;
+        } BIT;
+    } GTCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long UD: 1;
+            unsigned long UDF: 1;
+            unsigned long : 14;
+            unsigned long OADTY: 2;
+            unsigned long OADTYF: 1;
+            unsigned long OADTYR: 1;
+            unsigned long : 4;
+            unsigned long OBDTY: 2;
+            unsigned long OBDTYF: 1;
+            unsigned long OBDTYR: 1;
+            unsigned long : 4;
+        } BIT;
+    } GTUDDTYC;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTIOA: 5;
+            unsigned long : 1;
+            unsigned long OADFLT: 1;
+            unsigned long OAHLD: 1;
+            unsigned long OAE: 1;
+            unsigned long OADF: 2;
+            unsigned long : 2;
+            unsigned long NFAEN: 1;
+            unsigned long NFCSA: 2;
+            unsigned long GTIOB: 5;
+            unsigned long : 1;
+            unsigned long OBDFLT: 1;
+            unsigned long OBHLD: 1;
+            unsigned long OBE: 1;
+            unsigned long OBDF: 2;
+            unsigned long : 2;
+            unsigned long NFBEN: 1;
+            unsigned long NFCSB: 2;
+        } BIT;
+    } GTIOR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTINTA: 1;
+            unsigned long GTINTB: 1;
+            unsigned long GTINTC: 1;
+            unsigned long GTINTD: 1;
+            unsigned long GTINTE: 1;
+            unsigned long GTINTF: 1;
+            unsigned long GTINTPR: 2;
+            unsigned long : 8;
+            unsigned long ADTRAUEN: 1;
+            unsigned long ADTRADEN: 1;
+            unsigned long ADTRBUEN: 1;
+            unsigned long ADTRBDEN: 1;
+            unsigned long : 4;
+            unsigned long GRP: 2;
+            unsigned long : 2;
+            unsigned long GRPDTE: 1;
+            unsigned long GRPABH: 1;
+            unsigned long GRPABL: 1;
+            unsigned long : 1;
+        } BIT;
+    } GTINTAD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TCFA: 1;
+            unsigned long TCFB: 1;
+            unsigned long TCFC: 1;
+            unsigned long TCFD: 1;
+            unsigned long TCFE: 1;
+            unsigned long TCFF: 1;
+            unsigned long TCFPO: 1;
+            unsigned long TCFPU: 1;
+            unsigned long ITCNT: 3;
+            unsigned long : 4;
+            unsigned long TUCF: 1;
+            unsigned long ADTRAUF: 1;
+            unsigned long ADTRADF: 1;
+            unsigned long ADTRBUF: 1;
+            unsigned long ADTRBDF: 1;
+            unsigned long : 4;
+            unsigned long ODF: 1;
+            unsigned long : 3;
+            unsigned long DTEF: 1;
+            unsigned long OABHF: 1;
+            unsigned long OABLF: 1;
+            unsigned long : 1;
+        } BIT;
+    } GTST;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long BD: 4;
+            unsigned long : 12;
+            unsigned long CCRA: 2;
+            unsigned long CCRB: 2;
+            unsigned long PR: 2;
+            unsigned long CCRSWT: 1;
+            unsigned long : 1;
+            unsigned long ADTTA: 2;
+            unsigned long ADTDA: 1;
+            unsigned long : 1;
+            unsigned long ADTTB: 2;
+            unsigned long ADTDB: 1;
+            unsigned long : 1;
+        } BIT;
+    } GTBER;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long ITLA: 1;
+            unsigned long ITLB: 1;
+            unsigned long ITLC: 1;
+            unsigned long ITLD: 1;
+            unsigned long ITLE: 1;
+            unsigned long ITLF: 1;
+            unsigned long IVTC: 2;
+            unsigned long IVTT: 3;
+            unsigned long : 1;
+            unsigned long ADTAL: 1;
+            unsigned long : 1;
+            unsigned long ADTBL: 1;
+            unsigned long : 17;
+        } BIT;
+    } GTITC;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCNT: 32;
+        } BIT;
+    } GTCNT;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRA: 32;
+        } BIT;
+    } GTCCRA;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRB: 32;
+        } BIT;
+    } GTCCRB;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRC: 32;
+        } BIT;
+    } GTCCRC;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRE: 32;
+        } BIT;
+    } GTCCRE;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRD: 32;
+        } BIT;
+    } GTCCRD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTCCRF: 32;
+        } BIT;
+    } GTCCRF;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTPR: 32;
+        } BIT;
+    } GTPR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTPBR: 32;
+        } BIT;
+    } GTPBR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTPDBR: 32;
+        } BIT;
+    } GTPDBR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTRA: 32;
+        } BIT;
+    } GTADTRA;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTBRA: 32;
+        } BIT;
+    } GTADTBRA;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTDBRA: 32;
+        } BIT;
+    } GTADTDBRA;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTRB: 32;
+        } BIT;
+    } GTADTRB;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTBRB: 32;
+        } BIT;
+    } GTADTBRB;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTADTDBRB: 32;
+        } BIT;
+    } GTADTDBRB;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long TDE: 1;
+            unsigned long : 3;
+            unsigned long TDBUE: 1;
+            unsigned long TDBDE: 1;
+            unsigned long : 2;
+            unsigned long TDFER: 1;
+            unsigned long : 23;
+        } BIT;
+    } GTDTCR;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTDVU: 32;
+        } BIT;
+    } GTDVU;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTDVD: 32;
+        } BIT;
+    } GTDVD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTDBU: 32;
+        } BIT;
+    } GTDBU;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long GTDBD: 32;
+        } BIT;
+    } GTDBD;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SOS: 2;
+            unsigned long : 6;
+            unsigned long : 1;
+            unsigned long : 1;
+            unsigned long : 22;
+        } BIT;
+    } GTSOS;
+    union {
+        unsigned long LONG;
+        struct {
+            unsigned long SOTR: 1;
+            unsigned long : 31;
+        } BIT;
+    } GTSOTR;
+};
+
+#define GPT       (*(volatile struct st_gpt       *)0xE8043800)
+#define GPT32E0   (*(volatile struct st_gpt32e    *)0xE8043000)
+#define GPT32E1   (*(volatile struct st_gpt32e    *)0xE8043100)
+#define GPT32E2   (*(volatile struct st_gpt32e    *)0xE8043200)
+#define GPT32E3   (*(volatile struct st_gpt32e    *)0xE8043300)
+#define GPT32E4   (*(volatile struct st_gpt32e    *)0xE8043400)
+#define GPT32E5   (*(volatile struct st_gpt32e    *)0xE8043500)
+#define GPT32E6   (*(volatile struct st_gpt32e    *)0xE8043600)
+#define GPT32E7   (*(volatile struct st_gpt32e    *)0xE8043700)
+
+#endif