ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update psoc6pdl to 1.6.0.4266-rc3

pull/13122/head
Roman Okhrimenko 2020-06-18 10:13:35 +03:00
parent bcc8c2cdae
commit 7a862d2059
21 changed files with 2480 additions and 2393 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md
View File

@ -1,4 +1,4 @@
# PSoC 6 Peripheral Driver Library v1.5.2
# PSoC 6 Peripheral Driver Library v1.6.0
Please refer to the [README.md](./README.md) and the
[PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
@ -6,18 +6,76 @@ for a complete description of the Peripheral Driver Library.
## New Features
* No new features
* Added support for the PSoC 64 Secure MCU devices.
Limitations for the secure devices are described as a part of the [PRA](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html) driver.
## Updated Personalities
* WiFi - Fix build warning in the generated code
* Power - Added possibility to select the Normal/Minimum Current for the both LDO and BUCK Core regulators.
## Personalities with patch version updates
Minor updates to support the PSoC 64 Secure MCU devices
* Wco
* TimerClk
* TickClk
* SysClock
* SlowClk
* PumpClk
* Pll
* Pin
* Pilo
* PeriClk
* PathMux
* LfClk
* HvIlo
* HfClk
* Fll
* FastClk
* ExtClk
* Eco
* BakClk
* AltHf_BleEco
## Added Drivers
* [PRA 1.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html)
## Updated Drivers
* [SD Host 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sd__host.html)
* [Startup 2.80](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html)
* [WDT 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html)
* [SysTick 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__arm__system__timer.html)
* [SysPm 5.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html)
* [SysLib 2.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html)
* [SysClk 2.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html)
* [SCB 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__scb.html)
* [LVD 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__lvd.html)
* [Flash 3.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html)
* [CTB 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ctb.html)
### Drivers with patch version updates
Minor documentation changes:
* USBFS 2.20.1
* TrigMux 1.20.2
* Tcpwm 1.10.2
* SysInt 1.30.1
* SysAnalog 1.10.1
* SMIF 1.50.1
* Smart I/O 1.0.1
* Sd_host 1.50.1
* Sar 1.20.3
* Rtc 2.30.1
* Prot 1.30.3
* Profiler 1.20.1
## Known Issues
None
[SysClk](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html)
driver.
## Defect Fixes

21
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file cy_csd.h
* \version 1.10
* \version 1.10.1
*
* The header file of the CSD driver.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -254,22 +254,22 @@
* * <a href="http://www.cypress.com/trm218176"><b>Technical Reference Manual (TRM)</b></a>
*
* * <a href="https://github.com/cypresssemiconductorco/capsense">
* <b>Cypress CapSense Middleware Library</b></a>
* <b>CapSense Middleware Library</b></a>
*
* * <a href="https://cypresssemiconductorco.github.io/capsense/capsense_api_reference_manual/html/index.html">
* <b>Cypress CapSense Middleware API Reference Guide</b></a>
* <b>CapSense Middleware API Reference Guide</b></a>
*
* * <a href="https://github.com/cypresssemiconductorco/csdadc">
* <b>Cypress CSDADC Middleware Library</b></a>
* <b>CSDADC Middleware Library</b></a>
*
* * <a href="https://cypresssemiconductorco.github.io/csdadc/csdadc_api_reference_manual/html/index.html">
* <b>Cypress CSDADC Middleware API Reference Guide</b></a>
* <b>CSDADC Middleware API Reference Guide</b></a>
*
* * <a href="https://github.com/cypresssemiconductorco/csdidac">
* <b>Cypress CSDIDAC Middleware Library</b></a>
* <b>CSDIDAC Middleware Library</b></a>
*
* * <a href="https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html">
* <b>Cypress CSDIDAC Middleware API Reference Guide</b></a>
* <b>CSDIDAC Middleware API Reference Guide</b></a>
*
* * \ref page_getting_started "Getting Started with the PDL"
*
@ -312,6 +312,11 @@
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.10.1</td>
* <td>Documentation updates</td>
* <td>Update middleware references</td>
* </tr>
* <tr>
* <td rowspan="2">1.10</td>
* <td>The CSD driver sources are enclosed with the conditional compilation
* to ensure a successful compilation for non-CapSense-capable devices

7
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctb.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy_ctb.h
* \version 1.10.3
* \version 1.20
*
* Header file for the CTB driver
*
@ -287,6 +287,11 @@
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.20</td>
* <td>Fixed the \ref Cy_CTB_OpampInit function to do not affect another OpAmp instance.</td>
* <td>Bug fixing.</td>
* </tr>
* <tr>
* <td>1.10.3</td>
* <td>Minor documentation updates.</td>
* <td>Documentation enhancement.</td>

374
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h
View File

@ -2,7 +2,8 @@
* \file cy_pra.h
* \version 1.0
*
* \brief The header file of the PRA driver.
* \brief The header file of the PRA driver. The API is not intended to
* be used directly by the user application.
*
********************************************************************************
* \copyright
@ -26,23 +27,100 @@
/**
* \addtogroup group_pra
* \{
* The Protected Register Access (PRA) driver used to provice access to the
* protected registers to a non-secure application on PSoC 64 devices.
* \note The Protection Register Access (PRA) driver is intended for the PSoC 64
* devices only and provides other PDL drivers access to the registers that have
* secure access restrictions. It is not intended to be used directly by user
* application.
*
* The PRA PDL driver is only intended for the PSoC 64 devices as it provides
* access only to the registers that have PSoC 64 access restrictions. Refer to
* device technical reference manual (TRM) for the list of the protected
* registers.
* The PRA driver is used to protect the system from invalid configurations that
* could potentially cause the system to be unstable or indirectly allow access
* to registers and memory that are protected. This is done using several
* methods:
* * Allow only valid register settings.
* * Force a specified sequence of operations when writing to a register.
* * Totally block access to registers that are deemed critical to security.
* * Allow only known, well defined system configurations.
* * Allow access to non-critical registers that are protected by a fixed PPU.
*
* The driver is not expected to be used directly, instead the PDL functions
* affected by PSoC 64 access restrictions are updated to access registers with
* PRA API.
* On PSoC 64 devices, secure firmware protects entire regions of registers
* with the fixed PPUs, however there are some registers within that regions
* that should not be protected but, are protected due to fixed PPU
* granularity.
*
* The list of the registers that can be accessed by PRA driver directly is
* defined in the cy_pra.h file with the CY_PRA_INDX_ prefix.
*
* Most PDL drivers are not affected or use the PRA driver. Only the following
* PDL drivers are affected by this driver:
* * \ref group_lvd
* * \ref group_syslib
* * \ref group_sysclk
* * \ref group_syspm
* * \ref group_arm_system_timer
* * \ref group_wdt
* * \ref group_flash
*
* The execution time of the functions that access the protected registers is
* increased on the PSoC 64 devices because the access is performed on Cortex-M0+
* via the IPC command:
* * The access to the protected register may take around by 20 times longer compared
* to unprotected one.
* * The initial device configuration based on the device configuration depends on
* actual configuration, but may take up to 40 times longer.
* * The transition Active to DeepSleep to Active may take 2 times longer.
*
* \section group_pra_basic_operation Basic Operation
* The PRA driver uses an IPC channel to transfer register data between the user
* application running on the Cortex-CM4 and the secure Cortex-CM0+ CPU. The
* secure processor performs the data validation and correct register write
* sequence to ensure proper stable operation of the system. Function status and
* requested data is also returned via the IPC channel.
*
* The PDL driver that accesses protected registers, generates request to the
* PRA driver and it passes request over the IPC to secure Cortex-M0+, where
* request is validated and executed, and, then, reports result back to the
* driver on Cortex-M4 side.
*
* \image html pra_high_level_diagram.png
*
* \section group_pra_device_config Device Configuration
* For PSoC 64 device, device configuration (like system clock settings and
* power modes) is applied on the secure Cortex-M0+. The device configuration
* structure \ref cy_stc_pra_system_config_t is initialized with Device
* Configurator and passed to the secure Cortex-M0+ for validation and
* register the update in the cybsp_init() function.
*
* \warning The external clocks (ECO, ALTHF, WCO, and EXTCLK) are not
* allowed to source CLK_HF0 (clocks both Cortex-M0+ and Cortex-M4 CPUs)
* in order to prevent clock tampering. The external clock support for
* CLK_HF0 feature is planned to be added and validated via secure policy
* statements in the future releases.
*
* \note The internal low-frequency clocks (ILO and PILO) are not allowed to
* source the CLK_HF0 directly and through PLL or FLL.
*
* \note The clock source for Cortex-M4 SysTick cannot be configured with
* the Device Configurator. Enabling CLK_ALT_SYS_TICK will result in a
* compilation error. SysTick still can be configured in run-time with
* some limitations. For more details, refer to \ref Cy_SysTick_GetClockSource()
* in \ref group_arm_system_timer.
*
* \section group_pra_standalone Using without BSPs
* If PDL is used in Standalone mode without Board Support Package (BSP),
* do the following:
* * 1) Call the \ref Cy_PRA_Init function prior to executing
* API of any of the drivers listed above. By default, this function is
* called from \ref SystemInit on both CPU cores.
* * 2) Call the \ref Cy_PRA_SystemConfig function with the initial
* device configuration passed as a parameter. Refer to Section "Function Usage"
* of the \ref Cy_PRA_SystemConfig function for more details.
*
* \section group_pra_more_information More Information
* See the device technical reference manual (TRM).
* See the device technical reference manual (TRM) reference manual (TRM) for
* the list of the protected registers.
*
* \section group_pra_MISRA MISRA-C Compliance
* The LVD driver has the following specific deviations:
* The LVD driver specific deviations:
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
@ -53,37 +131,37 @@
* <tr>
* <td>13.7</td>
* <td>R</td>
* <td>Boolean operations whose results are invariant shall not be permitted.</td>
* <td>False positive. The Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared
* variable that is modified by Cortex-M0+ application, but the analysis tool
* <td>Boolean operations with invariant results are not permitted.</td>
* <td>False positive. Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared
* variable, which is modified by the Cortex-M0+ application, but the analysis tool
* is not aware of this fact.</td>
* </tr>
* <tr>
* <td>14.1</td>
* <td>R</td>
* <td>There shall be no unreachable code.</td>
* <td>False positive. The Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared
* variable that is modified by Cortex-M0+ application and used in a condition
* <td>No unreachable code.</td>
* <td>False positive. Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared
* variable, which is modified by the Cortex-M0+ application and used in a condition
* statement, but the analysis tool is not aware of this fact.</td>
* </tr>
* <tr>
* <td>14.7</td>
* <td>R</td>
* <td>A function shall have a single point of exit at the end of the function.</td>
* <td>There are few functions with multiple points of exit implemented to
* <td>A function has a single exit point at the end of the function.</td>
* <td>There are a few functions with multiple exit points implemented to
* simplify functions design.</td>
* </tr>
* <tr>
* <td>19.13</td>
* <td>A</td>
* <td>The # and ## operators should not be used.</td>
* <td>Do not use the # and ## operators.</td>
* <td>The ## preprocessor operator is used in macros to form the field mask.</td>
* </tr>
* <tr>
* <td>20.3</td>
* <td>R</td>
* <td>The validity of values passed to library functions shall be checked.</td>
* <td>The additional check to eliminate possibility of accessing beyond array in Cy_PRA_ProcessCmd().</td>
* <td>Check the validity of values passed to library functions.</td>
* <td>The additional check to eliminate the possibility of accessing the beyond array in Cy_PRA_ProcessCmd().</td>
* </tr>
* </table>
*
@ -100,7 +178,6 @@
* \defgroup group_pra_macros Macros
* \defgroup group_pra_functions Functions
* \defgroup group_pra_enums Enumerated Types
* \defgroup group_pra_data_structures_cfg Data Structures
*/
#if !defined(CY_PRA_H)
@ -146,7 +223,7 @@ extern "C" {
#define CY_PRA_INDX_SRSS_SRSS_INTR_MASK (3U)
#define CY_PRA_INDX_SRSS_SRSS_INTR_CFG (4U)
#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_1 (5U)
/* Do not change index below as it is used in flash loaders */
/* Do not change the index below abecause it is used in flash loaders */
#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_2 (6U)
#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_3 (7U)
#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_4 (8U)
@ -228,109 +305,109 @@ extern "C" {
* \addtogroup group_pra_enums
* \{
*/
/** The PRA function return value status definitions. */
/** Status definitions of the PRA function return values. */
typedef enum
{
CY_PRA_STATUS_SUCCESS = 0x0U, /**< Returned successful */
CY_PRA_STATUS_ACCESS_DENIED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFFU,
CY_PRA_STATUS_INVALID_PARAM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFEU,
CY_PRA_STATUS_ERROR_PROCESSING = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFDU,
CY_PRA_STATUS_REQUEST_SENT = CY_PRA_ID | CY_PDL_STATUS_INFO | 0xFFCU,
CY_PRA_STATUS_ERROR_SYSPM_FAIL = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFBU,
CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFAU,
/* Reserve 0xFFFD - 0xFFF0*/
CY_PRA_STATUS_SUCCESS = 0x0U, /**< Returns success */
CY_PRA_STATUS_ACCESS_DENIED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFFU, /**< Access denied - PRA does not allow a call from Non-Secure */
CY_PRA_STATUS_INVALID_PARAM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFEU, /**< Invalid parameter */
CY_PRA_STATUS_ERROR_PROCESSING = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFDU, /**< An error while applying the device configuration */
CY_PRA_STATUS_REQUEST_SENT = CY_PRA_ID | CY_PDL_STATUS_INFO | 0xFFCU, /**< The IPC message status when sent from Non-Secure to Secure */
CY_PRA_STATUS_ERROR_SYSPM_FAIL = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFBU, /**< SysPM failure */
CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFAU, /**< SysPM operation timeout */
/* Reserve 0xFF9 - 0xFF0 */
CY_PRA_STATUS_INVALID_PARAM_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEFU,
CY_PRA_STATUS_INVALID_PARAM_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEEU,
CY_PRA_STATUS_INVALID_PARAM_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEDU,
CY_PRA_STATUS_INVALID_PARAM_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFECU,
CY_PRA_STATUS_INVALID_PARAM_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEBU,
CY_PRA_STATUS_INVALID_PARAM_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEAU,
/* Reserve for other source clocks 0xFFE9 - 0xFFE0 */
CY_PRA_STATUS_INVALID_PARAM_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEFU, /**< Returns Error while validating the ECO parameters */
CY_PRA_STATUS_INVALID_PARAM_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEEU, /**< Returns Error while validating the CLK_EXT parameters */
CY_PRA_STATUS_INVALID_PARAM_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEDU, /**< Returns Error while validating the CLK_ALTHF parameters */
CY_PRA_STATUS_INVALID_PARAM_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFECU, /**< Returns Error while validating the CLK_ILO parameters */
CY_PRA_STATUS_INVALID_PARAM_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEBU, /**< Returns Error while validating the CLK_PILO parameters */
CY_PRA_STATUS_INVALID_PARAM_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEAU, /**< Returns Error while validating the CLK_WCO parameters */
/* Reserve for other source clocks 0xFE9 - 0xFE0 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDFU,
CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDEU,
CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDDU,
CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDCU,
CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDBU,
CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDAU,
/* Reserve for other path-mux 0xFFD9 - 0xFFD0 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDFU, /**< Returns Error while validating PATH_MUX0 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDEU, /**< Returns Error while validating PATH_MUX1 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDDU, /**< Returns Error while validating PATH_MUX2 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDCU, /**< Returns Error while validating PATH_MUX3 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDBU, /**< Returns Error while validating PATH_MUX4 */
CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDAU, /**< Returns Error while validating PATH_MUX5 */
/* Reserve for other path-mux 0xFD9 - 0xFD0 */
CY_PRA_STATUS_INVALID_PARAM_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFCFU,
/* Reserve for other FLLs 0xFFCE - 0xFFC0 */
CY_PRA_STATUS_INVALID_PARAM_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFCFU, /**< Returns Error while validating FLL */
/* Reserve for other FLLs 0xFCE - 0xFC0 */
CY_PRA_STATUS_INVALID_PARAM_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBFU,
CY_PRA_STATUS_INVALID_PARAM_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBEU,
CY_PRA_STATUS_INVALID_PARAM_PLL_NUM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBDU,
/* Reserve for other PLLs 0xFFBD - 0xFFB0 */
CY_PRA_STATUS_INVALID_PARAM_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBFU, /**< Returns Error while validating PLL0 */
CY_PRA_STATUS_INVALID_PARAM_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBEU, /**< Returns Error while validating PLL1 */
CY_PRA_STATUS_INVALID_PARAM_PLL_NUM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBDU, /**< Returns Error for the invalid PLL number */
/* Reserve for other PLLs 0xFBC - 0xFB0 */
CY_PRA_STATUS_INVALID_PARAM_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFAFU,
/* Reserve for other clocks 0xFFAE - 0xFFA0 */
CY_PRA_STATUS_INVALID_PARAM_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFAFU, /**< Returns Error while validating CLK_LF */
/* Reserve for other clocks 0xFAE - 0xFA0 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9FU,
CY_PRA_STATUS_INVALID_PARAM_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9EU,
CY_PRA_STATUS_INVALID_PARAM_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9DU,
CY_PRA_STATUS_INVALID_PARAM_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9CU,
CY_PRA_STATUS_INVALID_PARAM_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9BU,
CY_PRA_STATUS_INVALID_PARAM_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9AU,
/* Reserve for other HF clocks 0xFF99 - 0xFF90 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9FU, /**< Returns Error while validating CLK_HF0 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9EU, /**< Returns Error while validating CLK_HF1 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9DU, /**< Returns Error while validating CLK_HF2 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9CU, /**< Returns Error while validating CLK_HF3 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9BU, /**< Returns Error while validating CLK_HF4 */
CY_PRA_STATUS_INVALID_PARAM_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9AU, /**< Returns Error while validating CLK_HF5 */
/* Reserve for other HF clocks 0xF99 - 0xF90 */
CY_PRA_STATUS_INVALID_PARAM_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8FU,
CY_PRA_STATUS_INVALID_PARAM_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8EU,
CY_PRA_STATUS_INVALID_PARAM_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8DU,
CY_PRA_STATUS_INVALID_PARAM_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8CU,
CY_PRA_STATUS_INVALID_PARAM_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8BU,
CY_PRA_STATUS_INVALID_PARAM_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8AU,
CY_PRA_STATUS_INVALID_PARAM_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF89U,
/* Reserve for other HF clocks 0xFF88 - 0xFF80 */
CY_PRA_STATUS_INVALID_PARAM_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8FU, /**< Returns Error while validating CLK_PUMP */
CY_PRA_STATUS_INVALID_PARAM_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8EU, /**< Returns Error while validating CLK_BAK */
CY_PRA_STATUS_INVALID_PARAM_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8DU, /**< Returns Error while validating CLK_FAST */
CY_PRA_STATUS_INVALID_PARAM_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8CU, /**< Returns Error while validating CLK_PERI */
CY_PRA_STATUS_INVALID_PARAM_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8BU, /**< Returns Error while validating CLK_SLOW */
CY_PRA_STATUS_INVALID_PARAM_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8AU, /**< Returns Error while validating CLK_ALT_SYS_TICK */
CY_PRA_STATUS_INVALID_PARAM_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF89U, /**< Returns Error while validating CLK_TIMER */
/* Reserve for other HF clocks 0xF88 - 0xF70 */
CY_PRA_STATUS_ERROR_PROCESSING_PWR = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF6FU,
/* Reserve 0xFF6E - 0xFF60*/
CY_PRA_STATUS_ERROR_PROCESSING_PWR = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF6FU, /**< Returns Error while initializing power */
/* Reserve 0xF6E - 0xF60*/
CY_PRA_STATUS_ERROR_PROCESSING_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5FU,
CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5EU,
CY_PRA_STATUS_ERROR_PROCESSING_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5DU,
CY_PRA_STATUS_ERROR_PROCESSING_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5CU,
CY_PRA_STATUS_ERROR_PROCESSING_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5BU,
CY_PRA_STATUS_ERROR_PROCESSING_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5AU,
CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF59U,
/* Reserve for other source clocks 0xF59 - 0xFF50 */
CY_PRA_STATUS_ERROR_PROCESSING_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5FU, /**< Returns Error while initializing ECO */
CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5EU, /**< Returns Error while enabling CLK_EXT */
CY_PRA_STATUS_ERROR_PROCESSING_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5DU, /**< Returns Error while enabling CLK_ALTHF */
CY_PRA_STATUS_ERROR_PROCESSING_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5CU, /**< Returns Error while enabling/disabling CLK_ILO */
CY_PRA_STATUS_ERROR_PROCESSING_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5BU, /**< Returns Error while enabling/disabling CLK_ALTHF */
CY_PRA_STATUS_ERROR_PROCESSING_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5AU, /**< Returns Error while enabling/disabling CLK_WCO */
CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF59U, /**< Returns Error while enabling CLK_ECO */
/* Reserve for other source clocks 0xF58 - 0xF50 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4FU,
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4EU,
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4DU,
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4CU,
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4BU,
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4AU,
/* Reserve for other path-mux 0xFF49 - 0xFF40 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4FU, /**< Returns Error while setting PATH_MUX0 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4EU, /**< Returns Error while setting PATH_MUX1 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4DU, /**< Returns Error while setting PATH_MUX2 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4CU, /**< Returns Error while setting PATH_MUX3 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4BU, /**< Returns Error while setting PATH_MUX4 */
CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4AU, /**< Returns Error while setting PATH_MUX5 */
/* Reserve for other path-mux 0xF49 - 0xF40 */
CY_PRA_STATUS_ERROR_PROCESSING_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3FU,
CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3EU,
/* Reserve for other FLLs 0xFF3E - 0xFF30 */
CY_PRA_STATUS_ERROR_PROCESSING_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3FU, /**< Returns Error while enabling/disabling FLL */
CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3EU, /**< Returns Error while trying to enable an already enabled FLL */
/* Reserve for other FLLs 0xF3D - 0xF30 */
CY_PRA_STATUS_ERROR_PROCESSING_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2FU,
CY_PRA_STATUS_ERROR_PROCESSING_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2EU,
CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2DU,
/* Reserve for other PLLs 0xFF2D - 0xFF20 */
CY_PRA_STATUS_ERROR_PROCESSING_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2FU, /**< Returns Error while enabling/disabling PLL0 */
CY_PRA_STATUS_ERROR_PROCESSING_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2EU, /**< Returns Error while enabling/disabling PLL1 */
CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2DU, /**< Returns Error while trying to enable an already enabled PLL */
/* Reserve for other PLLs 0xF2C - 0xF20 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF1FU,
/* Reserve for other clocks 0xFF1E - 0xFF10 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF1FU, /**< Returns Error while enabling/disabling CLK_LF */
/* Reserve for other clocks 0xF1E - 0xF10 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0FU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0EU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0DU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0CU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0BU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0AU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0FU, /**< Returns Error while enabling/disabling CLK_HF0 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0EU, /**< Returns Error while enabling/disabling CLK_HF1 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0DU, /**< Returns Error while enabling/disabling CLK_HF2 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0CU, /**< Returns Error while enabling/disabling CLK_HF3 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0BU, /**< Returns Error while enabling/disabling CLK_HF4 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0AU, /**< Returns Error while enabling/disabling CLK_HF5 */
/* Reserve for other HF clocks 0xFF09 - 0xFF00 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFFU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFEU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFDU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFCU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFBU,
CY_PRA_STATUS_ERROR_PROCESSING_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFAU,
CY_PRA_STATUS_ERROR_PROCESSING_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEF9U,
/* Reserve for other HF clocks 0xF09 - 0xF00 */
CY_PRA_STATUS_ERROR_PROCESSING_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFFU, /**< Returns Error while enabling/disabling CLK_PUMP */
CY_PRA_STATUS_ERROR_PROCESSING_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFEU, /**< Returns Error while enabling/disabling CLK_BAK */
CY_PRA_STATUS_ERROR_PROCESSING_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFDU, /**< Returns Error while enabling/disabling CLK_FAST */
CY_PRA_STATUS_ERROR_PROCESSING_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFCU, /**< Returns Error while enabling/disabling CLK_PERI */
CY_PRA_STATUS_ERROR_PROCESSING_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFBU, /**< Returns Error while enabling/disabling CLK_SLOW */
CY_PRA_STATUS_ERROR_PROCESSING_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFAU, /**< Returns Error while enabling/disabling CLK_ALT_SYS_TICK */
CY_PRA_STATUS_ERROR_PROCESSING_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEF9U, /**< Returns Error while enabling/disabling CLK_TIMER */
} cy_en_pra_status_t;
/** \} group_pra_enums */
@ -339,30 +416,27 @@ typedef enum
* Data Structures
******************************************************************************/
/**
* \addtogroup group_pra_data_structures
* \{
*/
/** \cond INTERNAL */
/** PRA register access */
typedef struct
{
volatile uint32_t * addr; /**< Register address */
uint32_t writeMask; /**< Write mask. Zero grants access, one - no access */
volatile uint32_t * addr; /**< A protected register address */
uint32_t writeMask; /**< The write mask. Zero grants access, one - no access. */
} cy_stc_pra_reg_policy_t;
/** Message used for communication */
typedef struct
{
uint16_t praCommand; /**< Message Type */
uint16_t praIndex; /**< Register index */
cy_en_pra_status_t praStatus; /**< Status */
uint32_t praData1; /**< First data word */
uint32_t praData2; /**< Second data word */
uint16_t praCommand; /**< The message type. Refer to \ref group_pra_macros. */
uint16_t praIndex; /**< The register or function index. */
cy_en_pra_status_t praStatus; /**< The status */
uint32_t praData1; /**< The first data word. The usage depends on \ref group_pra_macros. */
uint32_t praData2; /**< The second data word. The usage depends on \ref group_pra_macros. */
} cy_stc_pra_msg_t;
/** \} group_pra_data_structures */
/** \endcond */
/** \cond INTERNAL */
/* Public for testing purposes */
extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT];
/** \endcond */
@ -377,17 +451,18 @@ extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT];
*/
void Cy_PRA_Init(void);
/** \cond INTERNAL */
#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
void Cy_PRA_CloseSrssMain2(void);
void Cy_PRA_OpenSrssMain2(void);
#endif /* (CY_CPU_CORTEX_M0P) */
/** \endcond */
#if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN)
cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask);
/** \} group_pra_functions */
/**
* \addtogroup group_pra_macros
* \{
@ -400,6 +475,11 @@ void Cy_PRA_Init(void);
* Provides get-clear-modify-write operations with a name field and value and
* writes a resulting value to the 32-bit register.
*
* \note An attempt to access not-supported registers (not secure and
* not listed in the TRM) results in an error. The list of the registers that
* can be accessed by the PRA driver directly is defined in the cy_pra.h file
* with the CY_PRA_INDX_ prefix.
*
*******************************************************************************/
#define CY_PRA_REG32_CLR_SET(regIndex, field, value) \
(void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_CLR_SET, \
@ -415,6 +495,11 @@ void Cy_PRA_Init(void);
*
* Writes the 32-bit value to the specified register.
*
* \note An attempt to access not-supported registers (not secure and
* not listed in the TRM) results in an error. The list of the registers that
* can be accessed by the PRA driver directly is defined in the cy_pra.h file
* with the CY_PRA_INDX_ prefix.
*
* \param regIndex The register address index.
*
* \param value The value to write.
@ -430,6 +515,11 @@ void Cy_PRA_Init(void);
*
* Reads the 32-bit value from the specified register.
*
* \note An attempt to access not-supported registers (not secure and
* not listed in the TRM) results in an error. The list of the registers that
* can be accessed by the PRA driver directly is defined in the cy_pra.h file
* with the CY_PRA_INDX_ prefix.
*
* \param regIndex The register address index.
*
* \return The read value.
@ -443,7 +533,7 @@ void Cy_PRA_Init(void);
* Macro Name: CY_PRA_CM0_WAKEUP()
****************************************************************************//**
*
* A simple request to wake up Cortex-M0+ core.
* The request to wake up the Cortex-M0+ core.
*
*******************************************************************************/
#define CY_PRA_CM0_WAKEUP() \
@ -454,16 +544,16 @@ void Cy_PRA_Init(void);
* Macro Name: CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param)
****************************************************************************//**
*
* Calls the specified function with the provided parameter and return the
* Calls the specified function with the provided parameter and returns the
* execution status.
*
* \param msgType Function type.
* \param msgType The function type.
*
* \param funcIndex Function reference.
* \param funcIndex The function reference.
*
* \param param Pointer to the function parameter.
* \param param The pointer to the function parameter.
*
* \return Function execution status.
* \return The function execution status.
*
*******************************************************************************/
#define CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) \
@ -474,13 +564,13 @@ void Cy_PRA_Init(void);
* Macro Name: CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex)
****************************************************************************//**
*
* Calls the specified function without parameter and return void.
* Calls the specified function without a parameter and returns void.
*
* \param msgType Function type.
* \param msgType The function type.
*
* \param funcIndex Function reference.
* \param funcIndex The function reference.
*
* \return Function execution status.
* \return The function execution status.
*
*******************************************************************************/
#define CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) \
@ -491,13 +581,13 @@ void Cy_PRA_Init(void);
* Macro Name: CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param)
****************************************************************************//**
*
* Calls the specified function with the provided parameter and return void.
* Calls the specified function with the provided parameter and returns void.
*
* \param msgType Function type.
* \param msgType The function type.
*
* \param funcIndex Function reference.
* \param funcIndex The function reference.
*
* \param param Pointer to the function parameter.
* \param param The pointer to the function parameter.
*
*******************************************************************************/
#define CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) \
@ -508,11 +598,11 @@ void Cy_PRA_Init(void);
* Macro Name: CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex)
****************************************************************************//**
*
* Calls the specified function without parameter and return void.
* Calls the specified function without a parameter and returns void.
*
* \param msgType Function type.
* \param msgType The function type.
*
* \param funcIndex Function reference.
* \param funcIndex The function reference.
*
*******************************************************************************/
#define CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) \

21
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra_cfg.h
View File

@ -2,7 +2,8 @@
* \file cy_pra_cfg.h
* \version 1.0
*
* \brief The header file of the PRA driver.
* \brief The header file of the PRA driver. The API is not intended to
* be used directly by the user application.
*
********************************************************************************
* \copyright
@ -140,12 +141,12 @@ typedef struct
bool fllEnable; /**< FLL Enable */
bool pll0Enable; /**< PLL0 Enable */
bool pll1Enable; /**< PLL1 Enable */
bool path0Enable; /**< CLKPATH0 Enable */
bool path1Enable; /**< CLKPATH1 Enable */
bool path2Enable; /**< CLKPATH2 Enable */
bool path3Enable; /**< CLKPATH3 Enable */
bool path4Enable; /**< CLKPATH4 Enable */
bool path5Enable; /**< CLKPATH5 Enable */
bool path0Enable; /**< PATH_MUX0 Enable */
bool path1Enable; /**< PATH_MUX1 Enable */
bool path2Enable; /**< PATH_MUX2 Enable */
bool path3Enable; /**< PATH_MUX3 Enable */
bool path4Enable; /**< PATH_MUX4 Enable */
bool path5Enable; /**< PATH_MUX5 Enable */
bool clkFastEnable; /**< CLKFAST Enable */
bool clkPeriEnable; /**< CLKPERI Enable */
bool clkSlowEnable; /**< CLKSLOW Enable */
@ -228,8 +229,8 @@ typedef struct
bool pll1LfMode; /**< PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit */
cy_en_fll_pll_output_mode_t pll1OutputMode; /**< PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits */
/* Number of clock Path available for device is defined in CY_SRSS_NUM_CLKPATH.
* Max 6 clock path are defined */
/* The number of clock paths available for the device is defined in CY_SRSS_NUM_CLKPATH.
* Max 6 clock paths are defined */
/* Clock Paths Configuration */
cy_en_clkpath_in_sources_t path0Src; /**< Input multiplexer0 clock source */
@ -244,7 +245,7 @@ typedef struct
uint8_t clkPeriDiv; /**< Peri clock divider. User has to pass actual divider-1 */
uint8_t clkSlowDiv; /**< Slow clock divider. User has to pass actual divider-1 */
/* Number of HF clocks are defined in device specific header CY_SRSS_NUM_HFROOT
/* The number of HF clocks is defined in the device specific header CY_SRSS_NUM_HFROOT
* Max 6 HFs are defined */
/* HF Configurations */
cy_en_clkhf_in_sources_t hf0Source; /**< HF0 Source Clock Path */

23
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h
View File

@ -102,11 +102,22 @@
* </tr>
* </table>
*
* \section group_sysclk_errata Known Issues
* <table class="doxtable">
* <tr><th>Issue</th><th>Workaround</th></tr>
* <tr>
* <td>The CLKLF does not work if after transition to the new clock
* source the previous one is immediately disabled.
* </td>
* <td>Wait 4 clock cycles of previous CLKLF clock source before disabling it.</td>
* </tr>
* </table>
*
* \section group_sysclk_changelog Changelog
* <table class="doxtable">
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td rowspan="2">3.0</td>
* <td rowspan="3">2.10</td>
* <td>Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return
* PRA driver status value.</td>
* <td>The SysClk driver uses the PRA driver to change the protected registers.
@ -115,15 +126,13 @@
* refer to PRA return statuses. Refer to functions description for details.</td>
* </tr>
* <tr>
* <td>Minor documentation updates.</td>
* <td>Documentation enhancement.</td>
* </tr>
* <tr>
* <td>2.10</td>
* <td>Updated the code of \ref Cy_SysClk_ClkPathGetFrequency function.</td>
* <td>Make the code more error-resistant to user errors for some corner cases.</td>
* </tr>
* <tr>
* <td>Minor documentation updates.</td>
* <td>Documentation enhancement.</td>
* </tr>
* <tr>
* <td>2.0</td>
* <td>Updated the ECO trimming values calculation algorithm in the \ref Cy_SysClk_EcoConfigure implementation. \n

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy_csd.c
* \version 1.10
* \version 1.10.1
*
* The source file of the CSD driver.
*

9
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctb.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy_ctb.c
* \version 1.10.3
* \version 1.20
*
* \brief
* Provides the public functions for the CTB driver.
@ -307,7 +307,7 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp
CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass));
CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst));
CTBM_CTB_CTRL(base) = (uint32_t) config->deepSleep;
CY_REG32_CLR_SET(CTBM_CTB_CTRL(base), CTBM_CTB_CTRL_DEEPSLEEP_ON, (CY_CTB_DEEPSLEEP_DISABLE != config->deepSleep) ? 1UL : 0UL);
/* The two opamp control registers are symmetrical */
oaResCtrl = (uint32_t) config->oaPower \
@ -415,7 +415,10 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
* - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
* - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV
* - .oaCompIntrEn = true
*
* \note This function call disables a whole CTB block,
* call \ref Cy_CTB_Enable after this function call.
*
* \param base
* Pointer to structure describing registers
*

378
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c
View File

File diff suppressed because it is too large Load Diff

776
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c
View File

File diff suppressed because it is too large Load Diff

735
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality
View File

File diff suppressed because it is too large Load Diff

735
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality
View File

File diff suppressed because it is too large Load Diff

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml
View File

@ -1 +1 @@
<version>1.6.0.4172</version>
<version>1.6.0.4266</version>