mirror of https://github.com/ARMmbed/mbed-os.git
Implementation of SLEEP feature for Renesas mbed boards
I implemented the SLEEP feature for Rnesas mbed boards. The mainly changing is here. - hal_sleep() To satisfy the mbed specificationm, I implemented this function newly by using "sleep" that is one of low power mode that is incorporated in our hardware(RZ_A1). In the "sleep", peripheral and memory state are maintained, and the peripherals continue to work and can generate interrupts. - hal_deepsleep() To satisfy the mbed specificationm, I implemented this function newly by combined using "sleep" and "module standby" that is the low power mode that is incorporated in our hardware(RZ_A1). The "module standby" is peripheral module's powerdown. Also in case of our "module standby", it need to read register as dummy when access to each register.pull/7009/head
TomoYamanaka
Bartek Szatkowski
parent
785e5d30a2
commit
7a48ee89e3
targets
TARGET_RENESAS/TARGET_RZ_A1XX
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@ -0,0 +1,198 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "sleep_api.h"
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#include "cmsis.h"
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#include "mbed_interface.h"
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#include "mbed_critical.h"
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#include "iodefine.h"
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#if DEVICE_SLEEP
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static volatile uint8_t wk_CPGSTBCR3;
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static volatile uint8_t wk_CPGSTBCR4;
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static volatile uint8_t wk_CPGSTBCR5;
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static volatile uint8_t wk_CPGSTBCR6;
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static volatile uint8_t wk_CPGSTBCR7;
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static volatile uint8_t wk_CPGSTBCR8;
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static volatile uint8_t wk_CPGSTBCR9;
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static volatile uint8_t wk_CPGSTBCR10;
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static volatile uint8_t wk_CPGSTBCR11;
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static volatile uint8_t wk_CPGSTBCR12;
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#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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static volatile uint8_t wk_CPGSTBCR13;
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#endif
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static volatile uint8_t wk_CPGSTBREQ1;
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static volatile uint8_t wk_CPGSTBREQ2;
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typedef struct {
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volatile uint8_t * p_wk_stbcr;
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volatile uint8_t * p_stbcr;
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volatile uint8_t * p_stbreq;
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volatile uint8_t * p_stback;
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uint8_t mstp;
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uint8_t stbrq;
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} module_stanby_t;
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static const module_stanby_t module_stanby[] = {
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{&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_BIT_MSTP61, CPG_STBREQ1_BIT_STBRQ13}, /* JCU */
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{&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_BIT_MSTP66, CPG_STBREQ1_BIT_STBRQ10}, /* CEU */
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{&wk_CPGSTBCR6, &CPGSTBCR8, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR8_BIT_MSTP82, CPG_STBREQ1_BIT_STBRQ12}, /* EthernetAVB */
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{&wk_CPGSTBCR7, &CPGSTBCR7, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_BIT_MSTP74, CPG_STBREQ2_BIT_STBRQ26}, /* Ethernet */
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{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP83, CPG_STBREQ2_BIT_STBRQ27}, /* MediaLB */
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{&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_BIT_MSTP91, CPG_STBREQ2_BIT_STBRQ25}, /* VDC5_0 */
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#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP85, CPG_STBREQ2_BIT_STBRQ21}, /* IMR-LSD */
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{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP86, CPG_STBREQ2_BIT_STBRQ22}, /* IMR-LS2_1 */
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{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP87, CPG_STBREQ2_BIT_STBRQ23}, /* IMR-LS2_0 */
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{&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_BIT_MSTP90, CPG_STBREQ2_BIT_STBRQ24}, /* VDC5_1 */
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{&wk_CPGSTBCR10, &CPGSTBCR10, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR10_BIT_MSTP100, CPG_STBREQ2_BIT_STBRQ20}, /* OpenVG */
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#endif
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{0, 0, 0, 0, 0} /* None */
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};
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static void module_standby_in(void) {
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volatile uint32_t cnt;
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volatile uint8_t dummy_8;
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const module_stanby_t * p_module = &module_stanby[0];
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while (p_module->p_wk_stbcr != 0) {
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if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
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*p_module->p_stbreq |= p_module->stbrq;
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dummy_8 = *p_module->p_stbreq;
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for (cnt = 0; cnt < 1000; cnt++) { // wait time
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if ((*p_module->p_stback & p_module->stbrq) != 0) {
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break;
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}
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}
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*p_module->p_stbcr |= p_module->mstp;
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dummy_8 = *p_module->p_stbcr;
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}
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p_module++;
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}
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(void)dummy_8;
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}
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static void module_standby_out(void) {
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volatile uint32_t cnt;
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volatile uint8_t dummy_8;
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const module_stanby_t * p_module = &module_stanby[0];
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while (p_module->p_wk_stbcr != 0) {
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if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
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*p_module->p_stbreq &= ~(p_module->stbrq);
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dummy_8 = *p_module->p_stbreq;
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for (cnt = 0; cnt < 1000; cnt++) {
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if ((*p_module->p_stback & p_module->stbrq) == 0) {
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break;
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}
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}
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}
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p_module++;
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}
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(void)dummy_8;
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}
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void hal_sleep(void) {
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// Transition to Sleep Mode
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__WFI();
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}
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void hal_deepsleep(void) {
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volatile uint8_t dummy_8;
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core_util_critical_section_enter();
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/* For powerdown the peripheral module, save current standby control register values(just in case) */
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wk_CPGSTBCR3 = CPGSTBCR3;
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wk_CPGSTBCR4 = CPGSTBCR4;
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wk_CPGSTBCR5 = CPGSTBCR5;
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wk_CPGSTBCR6 = CPGSTBCR6;
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wk_CPGSTBCR7 = CPGSTBCR7;
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wk_CPGSTBCR8 = CPGSTBCR8;
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wk_CPGSTBCR9 = CPGSTBCR9;
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wk_CPGSTBCR10 = CPGSTBCR10;
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wk_CPGSTBCR11 = CPGSTBCR11;
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wk_CPGSTBCR12 = CPGSTBCR12;
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#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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wk_CPGSTBCR13 = CPGSTBCR13;
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#endif
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/* MTU2 (for low power ticker) */
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CPGSTBCR3 |= ~(CPG_STBCR3_BIT_MSTP33);
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dummy_8 = CPGSTBCR3;
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CPGSTBCR4 = 0xFF;
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dummy_8 = CPGSTBCR4;
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CPGSTBCR5 = 0xFF;
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dummy_8 = CPGSTBCR5;
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/* Realtime Clock, JCU, CEU */
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CPGSTBCR6 |= ~(CPG_STBCR6_BIT_MSTP60 | CPG_STBCR6_BIT_MSTP61 | CPG_STBCR6_BIT_MSTP66);
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dummy_8 = CPGSTBCR6;
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/* Video Decoder0, Video Decoder1, Ethernet */
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CPGSTBCR7 |= ~(CPG_STBCR7_BIT_MSTP77 | CPG_STBCR7_BIT_MSTP76 | CPG_STBCR7_BIT_MSTP74);
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dummy_8 = CPGSTBCR7;
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/* EthernetAVB, MediaLB, IMR-LSD, IMR-LS2_1, IMR-LS2_0 */
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CPGSTBCR8 |= ~(CPG_STBCR8_BIT_MSTP82 | CPG_STBCR8_BIT_MSTP83 | CPG_STBCR8_BIT_MSTP85 | CPG_STBCR8_BIT_MSTP86 | CPG_STBCR8_BIT_MSTP87);
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dummy_8 = CPGSTBCR8;
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/* VDC5_1, SPI Multi I/O Bus Controller0 */
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CPGSTBCR9 |= ~(CPG_STBCR9_BIT_MSTP90 | CPG_STBCR9_BIT_MSTP93);
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dummy_8 = CPGSTBCR9;
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/* OpenVG */
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CPGSTBCR10 |= ~(CPG_STBCR10_BIT_MSTP100);
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dummy_8 = CPGSTBCR10;
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CPGSTBCR11 = 0xFF;
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dummy_8 = CPGSTBCR11;
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CPGSTBCR12 = 0xFF;
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dummy_8 = CPGSTBCR12;
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#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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CPGSTBCR13 = 0xFF;
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dummy_8 = CPGSTBCR13;
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#endif
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module_standby_in();
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// Transition to Sleep Mode
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__WFI();
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/* Revert standby control register values */
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CPGSTBCR3 = wk_CPGSTBCR3;
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dummy_8 = CPGSTBCR3;
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CPGSTBCR4 = wk_CPGSTBCR4;
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dummy_8 = CPGSTBCR4;
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CPGSTBCR5 = wk_CPGSTBCR5;
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dummy_8 = CPGSTBCR5;
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CPGSTBCR6 = wk_CPGSTBCR6;
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dummy_8 = CPGSTBCR6;
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CPGSTBCR7 = wk_CPGSTBCR7;
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dummy_8 = CPGSTBCR7;
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CPGSTBCR8 = wk_CPGSTBCR8;
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dummy_8 = CPGSTBCR8;
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CPGSTBCR9 = wk_CPGSTBCR9;
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dummy_8 = CPGSTBCR9;
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CPGSTBCR10 = wk_CPGSTBCR10;
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dummy_8 = CPGSTBCR10;
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CPGSTBCR11 = wk_CPGSTBCR11;
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dummy_8 = CPGSTBCR11;
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CPGSTBCR12 = wk_CPGSTBCR12;
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dummy_8 = CPGSTBCR12;
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#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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CPGSTBCR13 = wk_CPGSTBCR13;
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dummy_8 = CPGSTBCR13;
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#endif
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module_standby_out();
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core_util_critical_section_exit();
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(void)dummy_8;
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}
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#endif
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@ -2774,7 +2774,7 @@
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"core": "Cortex-A9",
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"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
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"extra_labels": ["RENESAS", "RZ_A1XX"],
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"device_has": ["USTICKER", "ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"device_has": ["SLEEP", "USTICKER", "ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"features": ["LWIP"],
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"program_cycle_s": 2,
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"overrides": {
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