Merge pull request #1138 from stevew817/master

Silicon Labs - Initial test framework pin definitions for EFM32 platforms
pull/1121/head
Martin Kojtal 2015-06-01 10:53:17 +01:00
commit 7a1d25e3df
11 changed files with 158 additions and 2 deletions

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@ -139,7 +139,7 @@ void pwmout_write(pwmout_t *obj, float value)
value = 1; value = 1;
} }
float pulse_period_in_s = obj->period_cycles / (float) pwm_clockfreq; float pulse_period_in_s = obj->period_cycles / ((float) (pwm_clockfreq >> pwm_prescaler_div));
pwmout_pulsewidth(obj, value * pulse_period_in_s); pwmout_pulsewidth(obj, value * pulse_period_in_s);
} }
@ -192,7 +192,7 @@ void pwmout_period_us(pwmout_t *obj, int us)
void pwmout_pulsewidth(pwmout_t *obj, float seconds) void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{ {
obj->width_cycles = pwm_clockfreq * seconds; obj->width_cycles = (uint32_t) (((float) (pwm_clockfreq >> pwm_prescaler_div)) * seconds);
TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles); TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles);
} }

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@ -46,6 +46,18 @@ DigitalIn in(TP4);
DigitalOut out(P1_0); DigitalOut out(P1_0);
DigitalIn in(P4_7); DigitalIn in(P4_7);
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
DigitalOut out(PD0);
DigitalIn in(PC3);
#elif defined(TARGET_EFM32ZG_STK3200)
DigitalOut out(PD7);
DigitalIn in(PC1);
#elif defined(TARGET_EFM32HG_STK3400)
DigitalOut out(PE10);
DigitalIn in(PC1);
#else #else
DigitalOut out(p5); DigitalOut out(p5);
DigitalIn in(p25); DigitalIn in(p25);

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@ -46,6 +46,18 @@ DigitalInOut d2(TP4);
DigitalInOut d1(P1_0); DigitalInOut d1(P1_0);
DigitalInOut d2(P4_7); DigitalInOut d2(P4_7);
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
DigitalInOut d1(PD0);
DigitalInOut d2(PC3);
#elif defined(TARGET_EFM32ZG_STK3200)
DigitalInOut d1(PD7);
DigitalInOut d2(PC1);
#elif defined(TARGET_EFM32HG_STK3400)
DigitalInOut d1(PE10);
DigitalInOut d2(PC1);
#else #else
DigitalInOut d1(p5); DigitalInOut d1(p5);
DigitalInOut d2(p25); DigitalInOut d2(p25);

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@ -10,6 +10,18 @@ I2C i2c(PTE0, PTE1);
I2C i2c(p22,p20); I2C i2c(p22,p20);
#elif defined(TARGET_FF_ARDUINO) || defined(TARGET_MAXWSNENV) #elif defined(TARGET_FF_ARDUINO) || defined(TARGET_MAXWSNENV)
I2C i2c(I2C_SDA, I2C_SCL); I2C i2c(I2C_SDA, I2C_SCL);
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define TEST_SDA_PIN PD6
#define TEST_SCL_PIN PD7
I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN);
#elif defined(TARGET_EFM32ZG_STK3200)
#define TEST_SDA_PIN PE12
#define TEST_SCL_PIN PE13
I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN);
#elif defined(TARGET_EFM32HG_STK3400)
#define TEST_SDA_PIN PD6
#define TEST_SCL_PIN PD7
I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN);
#else #else
I2C i2c(p28, p27); I2C i2c(p28, p27);
#endif #endif

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@ -75,6 +75,18 @@ void in_handler() {
#define PIN_OUT P1_0 #define PIN_OUT P1_0
#define PIN_IN P4_7 #define PIN_IN P4_7
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define PIN_OUT PD0
#define PIN_IN PC3
#elif defined(TARGET_EFM32ZG_STK3200)
#define PIN_OUT PD7
#define PIN_IN PC1
#elif defined(TARGET_EFM32HG_STK3400)
#define PIN_OUT PE10
#define PIN_IN PC1
#else #else
#define PIN_IN (p5) #define PIN_IN (p5)
#define PIN_OUT (p25) #define PIN_OUT (p25)

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@ -101,6 +101,34 @@
#define P2_1 (1 << 8) // PB_8 #define P2_1 (1 << 8) // PB_8
#define P2_2 (1 << 9) // PB_9 #define P2_2 (1 << 9) // PB_9
#define PORT_2 PortB #define PORT_2 PortB
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define P1_1 (1 << 0) // PD0
#define P1_2 (1 << 1) // PD1
#define PORT_1 PortD
#define P2_1 (1 << 3) // PC3
#define P2_2 (1 << 4) // PC4
#define PORT_2 PortC
#elif defined(TARGET_EFM32ZG_STK3200)
#define P1_1 (1 << 7) // PD7
#define P1_2 (1 << 6) // PD6
#define PORT_1 PortD
#define P2_1 (1 << 1) // PC1
#define P2_2 (1 << 2) // PC2
#define PORT_2 PortC
#elif defined(TARGET_EFM32HG_STK3400)
#define P1_1 (1 << 10) // PE10
#define P1_2 (1 << 11) // PE11
#define PORT_1 PortE
#define P2_1 (1 << 1) // PC1
#define P2_2 (1 << 2) // PC2
#define PORT_2 PortC
#endif #endif
#define MASK_1 (P1_1 | P1_2) #define MASK_1 (P1_1 | P1_2)

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@ -101,6 +101,34 @@
#define P2_1 (1 << 8) // PB_8 #define P2_1 (1 << 8) // PB_8
#define P2_2 (1 << 9) // PB_9 #define P2_2 (1 << 9) // PB_9
#define PORT_2 PortB #define PORT_2 PortB
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define P1_1 (1 << 0) // PD0
#define P1_2 (1 << 1) // PD1
#define PORT_1 PortD
#define P2_1 (1 << 3) // PC3
#define P2_2 (1 << 4) // PC4
#define PORT_2 PortC
#elif defined(TARGET_EFM32ZG_STK3200)
#define P1_1 (1 << 7) // PD7
#define P1_2 (1 << 6) // PD6
#define PORT_1 PortD
#define P2_1 (1 << 1) // PC1
#define P2_2 (1 << 2) // PC2
#define PORT_2 PortC
#elif defined(TARGET_EFM32HG_STK3400)
#define P1_1 (1 << 10) // PE10
#define P1_2 (1 << 11) // PE11
#define PORT_1 PortE
#define P2_1 (1 << 1) // PC1
#define P2_2 (1 << 2) // PC2
#define PORT_2 PortC
#endif #endif
#define MASK_1 (P1_1 | P1_2) #define MASK_1 (P1_1 | P1_2)

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@ -13,6 +13,15 @@ DigitalOut cs(PTA13);
#elif defined(TARGET_FF_ARDUINO) #elif defined(TARGET_FF_ARDUINO)
SPI spi(D11, D12, D13); // mosi, miso, sclk SPI spi(D11, D12, D13); // mosi, miso, sclk
DigitalOut cs(D10); DigitalOut cs(D10);
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
SPI spi(PD0, PD1, PD2); // mosi, miso, sclk
DigitalOut cs(PD3);
#elif defined(TARGET_EFM32ZG_STK3200)
SPI spi(PD7, PD6, PC15); // mosi, miso, sclk
DigitalOut cs(PC14);
#elif defined(TARGET_EFM32HG_STK3400)
SPI spi(PE10, PE11, PE12); // mosi, miso, sclk
DigitalOut cs(PE13);
#else #else
SPI spi(p5, p6, p7); // mosi, miso, sclk SPI spi(p5, p6, p7); // mosi, miso, sclk
DigitalOut cs(p8); DigitalOut cs(p8);

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@ -27,6 +27,19 @@
#if defined(TARGET_K64F) #if defined(TARGET_K64F)
#define TEST_SDA_PIN PTE25 #define TEST_SDA_PIN PTE25
#define TEST_SCL_PIN PTE24 #define TEST_SCL_PIN PTE24
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define TEST_SDA_PIN PD6
#define TEST_SCL_PIN PD7
#elif defined(TARGET_EFM32ZG_STK3200)
#define TEST_SDA_PIN PE12
#define TEST_SCL_PIN PE13
#elif defined(TARGET_EFM32HG_STK3400)
#define TEST_SDA_PIN PD6
#define TEST_SCL_PIN PD7
#else #else
#error Target not supported #error Target not supported
#endif #endif

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@ -28,6 +28,17 @@
#define TEST_SERIAL_ONE_TX_PIN PTC17 // uart3 #define TEST_SERIAL_ONE_TX_PIN PTC17 // uart3
#define TEST_SERIAL_TWO_RX_PIN PTD2 // uart2 #define TEST_SERIAL_TWO_RX_PIN PTD2 // uart2
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define TEST_SERIAL_ONE_TX_PIN PD0 // usart1
#define TEST_SERIAL_TWO_RX_PIN PC3 // usart2
#elif defined(TARGET_EFM32ZG_STK3200)
#error "Target not supported (only 2 serial ports available, need 3)"
#elif defined(TARGET_EFM32HG_STK3400)
#define TEST_SERIAL_ONE_TX_PIN PE10 // usart0
#define TEST_SERIAL_TWO_RX_PIN PC1 // usart1
#else #else
#error Target not supported #error Target not supported

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@ -39,6 +39,25 @@
#define TEST_MISO_PIN PTD3 #define TEST_MISO_PIN PTD3
#define TEST_SCLK_PIN PTD1 #define TEST_SCLK_PIN PTD1
#define TEST_CS_PIN PTD0 #define TEST_CS_PIN PTD0
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define TEST_MOSI_PIN PD0
#define TEST_MISO_PIN PD1
#define TEST_SCLK_PIN PD2
#define TEST_CS_PIN PD3
#elif defined(TARGET_EFM32ZG_STK3200)
#define TEST_MOSI_PIN PD7
#define TEST_MISO_PIN PD6
#define TEST_SCLK_PIN PC15
#define TEST_CS_PIN PC14
#elif defined(TARGET_EFM32HG_STK3400)
#define TEST_MOSI_PIN PE10
#define TEST_MISO_PIN PE11
#define TEST_SCLK_PIN PE12
#define TEST_CS_PIN PE13
#else #else
#error Target not supported #error Target not supported
#endif #endif