diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
index fb0d2dac63..2b50515c1c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
@@ -665,29 +665,30 @@ Notes for STM32F0xx HAL Drivers
Update History V1.1.0
-/ 03-Oct-2014 Main
+V1.2.0
+/ 11-December-2014 Main
Changes
-HAL generic updateminor corrections for Pdf/Chm UM generation Correction for MISRA [F098xx] Remove PVD IT line wrapper FLAG&IT assert macros to be removed Bad macro name in stm32F0xx_hal.c/.h files uint32_t Alignement in HAL driver HAL Cortex update
HAL DMA update
Bit definition name error for HAL_DMA1_CH2 remap on Stingray 256K minor update HAL_DMA_PollForTransfer updated HAL GPIO update
rework GPIO_GET_SOURCE
BSRR regsiter should not be split in BSRRH/BSRRL HAL I2S update
HAL IRDA update
HAL IWDG update
HAL PWR update
HAL SPI update
HAL TIM update
Missed/Unused assert param to be added/removed Trigger interrupt should be activated when working with a slave mode Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4 missing assert in HAL_TIMEx_ConfigBreakDeadTime Add URS_ENABLE/ URS_DISABLE macros HAL UART/USART update
Change UART TX-IT implementation to remove WaitOnFlag in ISR HAL USB update
HAL WWDG update
V1.1.0RC2
-/ 01-Aug-2014 Main
+HAL generic Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . HandleTypeDef.ErrorCode must be typed uint32_t Update HAL drivers to ensure compliancy w/ C++ Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h Case mismatch between #include typo and effective file name generating compiler errors under Linux Correct various issues for documentation generation (group name, doxygen tags, etc..) Missing support of I2C_PAx_FMP of F04xx devices HAL ADC
Improve HAL ADC comments Correct issue observed with ADC start simultaneous commands Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices. HAL CAN ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issueHAL CEC
HAL COMP State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issuechange HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue HAL CRC
HAL DAC
HAL DMA
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . DMA channel remap register renamed for compatibility with other STM32 devices. Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description HAL FLASH Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issuechange HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue Clean the error context to FLASH_ERROR_NONE before starting new Flash operation Put all the clear flags in the FLASH_SetSerrorCode() Stop the programming procedure in case of error detected in HAL_FLASH_Program() Check error before doing new procedure in HAL_FLASH_IRQhandler() HAL GPIO
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . correct Typo in 'How to use this driver' section & update comments Add assert on GPIO PIN in HAL_GPIO_DeInit() Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX() Reset Interrupt mode registers only in HAL_GPIO_DeInit() HAL I2C Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issueHAL I2S
ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.Change HAL_I2S_GetError () type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue. Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO . Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation) HAL IRDA
ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issueMissing doxygen tags for IRDA_HandleTypeDef fields description HAL PWR
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register: HAL_PWR_DisableSleepOnExit() HAL_PWR_EnableSleepOnExit() HAL_PWR_EnableSEVOnPend() HAL_PWR_DisableSEVOnPend() Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode() HAL RCC
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_ rcc_ex.h since this feature is not supported on all F0 devices Change HAL_RCCEx_CRSWaitSynchronization () type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue HAL RTC
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . Enhance @note describing the use of HAL RTC APIs HAL SMARTCARD ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issueHAL SMBUS ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issueChange HAL_SMBUS_GetState () type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue HAL SPI
ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issueAdd use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO . Add DMA circular mode support on SPI HAL driver. Internal
+fucntion renaming: HAL_SPI_DMATransmitCplt(),
+HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() &
+HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError(). Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype uint32_t driver alignment for compatibility with other STM32 devices Add new API HAL_SPI_GetError (), which was missing on STM32F0xx family HAL UART/USART
Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC . structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices. ErrorCode field is now declared as uint32 instead of enum HAL_U(S)ART_ErrorTypeDef to fix C++ compilation issueunused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h Add missing API HAL_StatusTypeDef HAL_LIN_SendBreak () correct wrong USART_IT_CM value correct issue with Lin mode data length Add new value for Stop bit definition: UART_STOPBITS_1_5 HAL USB
Add support of new STM32F0 value line devices STM32F070xB/x6 Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description Correct _HAL_PCD_CLEAR_FLAG() macros definition HAL WWDG
V1.1.0
+/ 03-October-2014 Main
Changes
-
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s
new file mode 100644
index 0000000000..0814fae074
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s
@@ -0,0 +1,239 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD 0 ; Reserved
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct
new file mode 100644
index 0000000000..d6531bd026
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F070RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 0000000000..bb665909b9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s
new file mode 100644
index 0000000000..29a68407e0
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s
@@ -0,0 +1,212 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD 0 ; Reserved
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct
new file mode 100644
index 0000000000..d6531bd026
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F070RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..bb665909b9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld
new file mode 100644
index 0000000000..137d809714
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 16k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s
new file mode 100644
index 0000000000..288a5bda86
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f070xb.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word 0 /* Reserved */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word 0 /* Reserved */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word 0 /* Reserved */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_4_IRQHandler /* USART3 and USART4 */
+ .word 0 /* Reserved */
+ .word USB_IRQHandler /* USB */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_5_IRQHandler
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_4_IRQHandler
+ .thumb_set USART3_4_IRQHandler,Default_Handler
+
+ .weak USB_IRQHandler
+ .thumb_set USB_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s
new file mode 100644
index 0000000000..7fcd91c9e4
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s
@@ -0,0 +1,305 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070xB devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address,
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* © COPYRIGHT(c) 2014 STMicroelectronics © COPYRIGHT 2014 STMicroelectronics © COPYRIGHT(c) 2014 STMicroelectronics © COPYRIGHT(c) 2014 STMicroelectronics
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+#define STM32F070xB /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
new file mode 100644
index 0000000000..fe0f8d4ba0
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
@@ -0,0 +1,467 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics © COPYRIGHT(c) 2014 STMicroelectronics State = HAL_DAC_STATE_READY;
@@ -823,7 +823,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel;
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY;
@@ -1066,17 +1066,18 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/**
* @}
*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F071xB STM32F072xB STM32F078xx */
/* STM32F091xC STM32F098xx */
#endif /* HAL_DAC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
index 3519b3cf7b..b38d32f373 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
index d8944779dc..62bb2973bc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_def.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@@ -70,8 +70,8 @@ typedef enum
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
-#ifndef HAL_NULL
- #define HAL_NULL (void *) 0
+#ifndef NULL
+ #define NULL 0
#endif
#define HAL_MAX_DELAY 0xFFFFFFFF
@@ -85,6 +85,8 @@ typedef enum
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0)
+#define UNUSED(x) ((void)(x))
+
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
@@ -154,6 +156,23 @@ typedef enum
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
index 21c082f76d..64123ec361 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
uint32_t tmp = 0;
/* Check the DMA handle allocation */
- if(hdma == HAL_NULL)
+ if(hdma == NULL)
{
return HAL_ERROR;
}
@@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
- if(hdma == HAL_NULL)
+ if(hdma == NULL)
{
return HAL_ERROR;
}
@@ -535,7 +535,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
- if (hdma->XferErrorCallback != HAL_NULL)
+ if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
@@ -560,7 +560,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF;
- if(hdma->XferHalfCpltCallback != HAL_NULL)
+ if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
@@ -590,7 +590,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
- if(hdma->XferCpltCallback != HAL_NULL)
+ if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
index 2f53e61eda..07bed3c233 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -288,34 +288,34 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
-#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
/**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
index d018ae4dc5..fd85710b2f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of DMA HAL Extension module.
******************************************************************************
* @attention
@@ -56,201 +56,229 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
-#define DMA1_CHANNEL1_RMP 0x00000000
-#define DMA1_CHANNEL2_RMP 0x10000000
-#define DMA1_CHANNEL3_RMP 0x20000000
-#define DMA1_CHANNEL4_RMP 0x30000000
-#define DMA1_CHANNEL5_RMP 0x40000000
-#define DMA1_CHANNEL6_RMP 0x50000000
-#define DMA1_CHANNEL7_RMP 0x60000000
-#define DMA2_CHANNEL1_RMP 0x00000000
-#define DMA2_CHANNEL2_RMP 0x10000000
-#define DMA2_CHANNEL3_RMP 0x20000000
-#define DMA2_CHANNEL4_RMP 0x30000000
-#define DMA2_CHANNEL5_RMP 0x40000000
+#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#if !defined(STM32F030xC)
+#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#endif /* !defined(STM32F030xC) */
/****************** DMA1 remap bit field definition********************/
/* DMA1 - Channel 1 */
-#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
-#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
-#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
+#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
+#endif /* !defined(STM32F030xC) */
+
/* DMA1 - Channel 2 */
-#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
-#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
-#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
-#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
+#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
+#endif /* !defined(STM32F030xC) */
+
/* DMA1 - Channel 3 */
-#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
-#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
-#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
-#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
-#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
-#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+
/* DMA1 - Channel 4 */
-#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
-#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+
/* DMA1 - Channel 5 */
-#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
+#endif /* !defined(STM32F030xC) */
+
+#if !defined(STM32F030xC)
/* DMA1 - Channel 6 */
-#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
/* DMA1 - Channel 7 */
-#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
-#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
-#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
-#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
/****************** DMA2 remap bit field definition********************/
/* DMA2 - Channel 1 */
-#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
/* DMA2 - Channel 2 */
-#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
/* DMA2 - Channel 3 */
-#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
-#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
-#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
+#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
/* DMA2 - Channel 4 */
-#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
-#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
-#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
+#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
/* DMA2 - Channel 5 */
-#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
+#endif /* !defined(STM32F030xC) */
-#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
@@ -413,10 +441,76 @@
((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030xC)
+#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
+#endif /* STM32F030xC */
+
/**
* @}
*/
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/* Exported macros -----------------------------------------------------------*/
@@ -473,9 +567,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -487,9 +581,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
@@ -558,9 +652,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -574,9 +668,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval None
*/
@@ -584,7 +678,7 @@
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
-#else /* STM32F030x8_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx Product devices */
+#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle
@@ -626,9 +720,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_5 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -640,9 +734,9 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_5 to select the DMA Channel flag.
* @retval None
*/
@@ -651,20 +745,22 @@
#endif
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __HAL_DMA1_REMAP(__REQUEST__) \
do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
- DMA1->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
- DMA1->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
+ DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
+ DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
}while(0)
+#if defined(STM32F091xC) || defined(STM32F098xx)
#define __HAL_DMA2_REMAP(__REQUEST__) \
do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
- DMA2->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
- DMA2->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
+ DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
+ DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
}while(0)
+#endif /* STM32F091xC || STM32F098xx */
- #endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
index 647795b853..64232f81bb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -14,8 +14,7 @@
@verbatim
==============================================================================
##### FLASH peripheral features #####
- ==============================================================================
-
+ ==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
@@ -40,7 +39,7 @@
functions to erase and program the main memory:
(++) Lock and Unlock the FLASH interface
(++) Erase function: Erase page, erase all pages
- (++) Program functions: half word and word
+ (++) Program functions: half word, word and doubleword
(#) Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
@@ -113,9 +112,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Defines FLASH Private Define
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
@@ -126,7 +139,6 @@ FLASH_ProcessTypeDef pFlash;
*/
/* Private function prototypes -----------------------------------------------*/
-
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
@@ -143,8 +155,7 @@ static void FLASH_SetErrorCode(void);
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-
+/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
@@ -172,6 +183,9 @@ static void FLASH_SetErrorCode(void);
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
* @param TypeProgram: Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address: Specifies the address to be programmed.
@@ -220,15 +234,14 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
}
}
@@ -301,9 +314,21 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
*/
void HAL_FLASH_IRQHandler(void)
{
- uint32_t addresstmp;
- /* If the operation is completed, disable the PG, PER and MER Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(pFlash.Address);
+
+ /* Reset address and stop the procedure ongoing*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
@@ -311,6 +336,9 @@ void HAL_FLASH_IRQHandler(void)
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/* Nb of pages to erased can be decreased */
@@ -325,6 +353,10 @@ void HAL_FLASH_IRQHandler(void)
/* Increment page address to next page */
pFlash.Address += FLASH_PAGE_SIZE;
addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
FLASH_PageErase(addresstmp);
}
else
@@ -338,6 +370,9 @@ void HAL_FLASH_IRQHandler(void)
}
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
/*MassErase ended. Return the selected bank*/
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(0);
@@ -360,6 +395,9 @@ void HAL_FLASH_IRQHandler(void)
/* Shift to have next 16-bit data */
pFlash.Data = (pFlash.Data >> 16);
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
}
@@ -385,27 +423,14 @@ void HAL_FLASH_IRQHandler(void)
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
- }
-
- /* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR))
- {
- /*Save the Error code*/
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(pFlash.Address);
-
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
- /* Reset address and stop the procedure ongoing*/
- pFlash.Address = 0xFFFFFFFF;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
/* Disable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
@@ -535,6 +560,9 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
@@ -566,11 +594,10 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
* @arg FLASH_ERROR_PG: FLASH Programming error flag
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
*/
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
+uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
-}
-
+}
/**
* @}
*/
@@ -591,8 +618,8 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
*/
void FLASH_PageErase(uint32_t PageAddress)
{
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
@@ -608,9 +635,9 @@ void FLASH_PageErase(uint32_t PageAddress)
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
@@ -641,6 +668,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
}
}
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
/*Save the error code*/
@@ -648,7 +682,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
return HAL_ERROR;
}
- /* If there is an error flag set */
+ /* If there is no error flag set */
return HAL_OK;
}
@@ -658,16 +692,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
* @retval None
*/
static void FLASH_SetErrorCode(void)
-{
+{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
- pFlash.ErrorCode = FLASH_ERROR_WRP;
+ pFlash.ErrorCode |= FLASH_ERROR_WRP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
pFlash.ErrorCode |= FLASH_ERROR_PG;
}
-}
+
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+}
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
index efb7564cd0..29b37cecc3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@@ -60,15 +60,6 @@
* @{
*/
-/**
- * @brief FLASH Error source
- */
-typedef enum
-{
- FLASH_ERROR_PG = 0x01,
- FLASH_ERROR_WRP = 0x02
-} FLASH_ErrorTypeDef;
-
/**
* @brief FLASH Erase structure definition
*/
@@ -134,17 +125,18 @@ typedef enum
*/
typedef struct
{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
- __IO uint32_t DataRemaining; /* Internal variable to save the remaining pages to erase or half-word to program in IT context */
+ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
- __IO uint32_t Address; /* Internal variable to save address selected for program or erase */
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
- __IO uint64_t Data; /* Internal variable to save data to be programmed */
+ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
- HAL_LockTypeDef Lock; /* FLASH locking object */
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
- __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+ __IO uint32_t ErrorCode; /*!< FLASH error code
+ This parameter can be a value of @ref FLASH_Error */
} FLASH_ProcessTypeDef;
@@ -158,6 +150,16 @@ typedef struct
* @{
*/
+/** @defgroup FLASH_Error FLASH Error
+ * @{
+ */
+#define FLASH_ERROR_NONE ((uint32_t)0x00000000)
+#define FLASH_ERROR_PG ((uint32_t)0x00000001)
+#define FLASH_ERROR_WRP ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
/** @defgroup FLASH_Type_Erase FLASH Type Erase
* @{
*/
@@ -204,7 +206,7 @@ typedef struct
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!CR, FLASH_CR_MER);
}
@@ -209,14 +202,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
+
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
@@ -252,6 +238,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
/* Process Locked */
__HAL_LOCK(&pFlash);
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
@@ -327,11 +319,11 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
- {
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* If the previous operation is completed, proceed to erase the option bytes */
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
@@ -450,9 +442,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
*/
static void FLASH_MassErase(void)
{
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
+
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Proceed to erase all sectors */
SET_BIT(FLASH->CR, FLASH_CR_MER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
@@ -471,33 +464,33 @@ static void FLASH_MassErase(void)
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
uint16_t WRP0_Data = 0xFFFF;
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
uint16_t WRP1_Data = 0xFFFF;
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
WriteProtectPage = (uint32_t)(~WriteProtectPage);
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
@@ -507,16 +500,16 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
#if defined(STM32F091xC) || defined(STM32F098xx)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
#endif /* STM32F091xC || STM32F098xx */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
- {
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
if(WRP0_Data != 0xFF)
@@ -528,8 +521,8 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
}
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
if((status == HAL_OK) && (WRP1_Data != 0xFF))
{
OB->WRP1 &= WRP1_Data;
@@ -537,11 +530,11 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
}
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB ||
- STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
+ STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
if((status == HAL_OK) && (WRP2_Data != 0xFF))
{
OB->WRP2 &= WRP2_Data;
@@ -557,14 +550,13 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
}
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC*/
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
return status;
-
}
/**
@@ -580,32 +572,32 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
uint16_t WRP0_Data = 0xFFFF;
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
uint16_t WRP1_Data = 0xFFFF;
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || STM32F070x6 || \
defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
@@ -615,16 +607,16 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(STM32F091xC) || defined(STM32F098xx)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
#endif /* STM32F091xC || STM32F098xx */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
- {
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
if(WRP0_Data != 0xFF)
@@ -636,8 +628,8 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
}
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
if((status == HAL_OK) && (WRP1_Data != 0xFF))
{
OB->WRP1 |= WRP1_Data;
@@ -645,11 +637,11 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
}
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB ||
- STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
+ STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
if((status == HAL_OK) && (WRP2_Data != 0xFF))
{
OB->WRP2 |= WRP2_Data;
@@ -665,12 +657,11 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
}
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
-
+ }
return status;
}
@@ -696,11 +687,11 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
@@ -734,27 +725,27 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_RAM_PARITY_CHECK_RESET)));
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
OB->USER = UserConfig;
#else
OB->USER = (UserConfig | 0x88);
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
@@ -788,11 +779,11 @@ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-
if(status == HAL_OK)
{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
/* Enables the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
*(__IO uint16_t*)Address = Data;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
index f7a0371895..69d52579c2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@@ -62,21 +62,21 @@
/** @defgroup FLASHEx_Address FLASHEx Address
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) || defined(STM32F070x6)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF))
-#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB*/
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC*/
/**
* @}
*/
@@ -85,14 +85,14 @@
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define FLASH_PAGE_SIZE 0x400
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define FLASH_PAGE_SIZE 0x800
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
@@ -101,21 +101,21 @@
/** @defgroup FLASHEx_Nb_Pages FLASHEx Nb Pages
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF)
-#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF)
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
*/
@@ -124,7 +124,7 @@
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
@@ -149,17 +149,17 @@
#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
#define OB_WRP_ALLPAGES ((uint32_t)0x000000FF) /*!< Write protection of all pages */
-#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
@@ -191,32 +191,32 @@
#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define OB_WRP_PAGES62TO63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define OB_WRP_PAGES48TO63MASK ((uint32_t)0xFF000000)
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
/**
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx OB BOOT SEL
* @{
*/
@@ -236,7 +236,7 @@
/**
* @}
*/
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
index e8096e42a2..cca2d3b5ac 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -47,11 +47,11 @@
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
[..]
- The external interrupt/event controller consists of up to 23 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
+ The external interrupt/event controller consists of up to 28 edge detectors
+ (depending on products 16 lines are connected to GPIO) for generating event/interrupt
+ requests (each input line can be independently configured to select the type
+ (interrupt or event) and the corresponding trigger event (rising or falling or both).
+ Each line can also be masked independently.
##### How to use this driver #####
==============================================================================
@@ -64,7 +64,7 @@
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure,
- the speed is configurable: 2 MHz, 10 MHz and 50 MHz.
+ the speed is configurable: Low, Medium and High.
(++) If alternate mode is selected, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure
(++) Analog mode is required when a pin is to be used as ADC channel
@@ -77,6 +77,11 @@
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
+ (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
+ recommended to use it to unconfigure pin which was used as an external interrupt
+ or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
+ registers.
+
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
@@ -192,8 +197,7 @@
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- uint32_t position;
- uint32_t ioposition = 0x00;
+ uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t temp = 0x00;
@@ -204,21 +208,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
- for (position = 0; position < GPIO_NUMBER; position++)
+ while ((GPIO_Init->Pin) >> position)
{
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
- if (iocurrent == ioposition)
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1 << position);
+
+ if(iocurrent)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
- /* Check the Alternate function parameter */
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
@@ -266,7 +270,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp = SYSCFG->EXTICR[position >> 2];
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- temp |= (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
@@ -303,26 +307,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
}
EXTI->FTSR = temp;
}
- else
- {
- temp = SYSCFG->EXTICR[position >> 2];
- temp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
- if(temp == (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03))))
- {
- /* Configure the External Interrupt or event for the current IO */
- temp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~temp;
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
- }
- }
}
+
+ position++;
}
}
@@ -337,23 +324,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
- uint32_t position;
- uint32_t ioposition = 0x00;
+ uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
- for (position = 0; position < GPIO_NUMBER; position++)
+ while (GPIO_Pin >> position)
{
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (GPIO_Pin) & ioposition;
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1 << position);
- if (iocurrent == ioposition)
+ if (iocurrent)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
@@ -376,7 +361,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
- if(tmp == (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03))))
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
{
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
@@ -390,6 +375,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
EXTI->FTSR &= ~((uint32_t)iocurrent);
}
}
+
+ position++;
}
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
index 07f6753caa..9fcbe451bd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
index a0825f1c0a..b737e4e5fd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@@ -431,6 +431,71 @@
#endif /* STM32F091xC || STM32F098xx */
+#if defined(STM32F030xC)
+/*--------------------------- STM32F030xC ----------------------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USART5 ((uint8_t)0x02) /*!< AF2: USART5 Alternate Function mapping */
+#define GPIO_AF2_USART6 ((uint8_t)0x02) /*!< AF2: USART6 Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART5 ((uint8_t)0x04) /*!< AF4: USART5 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_USART6 ((uint8_t)0x05) /*!< AF5: USART6 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F030xC */
+
#if defined (STM32F072xB) || defined (STM32F078xx)
/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/
/* AF 0 */
@@ -510,6 +575,65 @@
#endif /* STM32F072xB || STM32F078xx */
+#if defined (STM32F070xB)
+/*---------------------------------- STM32F070xB ---------------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART4 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F070xB */
+
#if defined (STM32F042x6) || defined (STM32F048xx)
/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/
/* AF 0 */
@@ -569,6 +693,56 @@
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined (STM32F070x6)
+/*--------------------------------------- STM32F070x6 ----------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_I2C1 ((uint8_t)0x05) /*!< AF5: I2C1 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_USB ((uint8_t)0x05) /*!< AF5: USB Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F070x6 */
/**
* @}
*/
@@ -587,24 +761,24 @@
*/
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U : 5U)
#endif
-#if defined (STM32F030x6) || defined (STM32F030x8) || \
+#if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F070xB) || defined (STM32F030xC) || \
defined (STM32F051x8) || defined (STM32F058xx)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U : 5U)
#endif
#if defined (STM32F031x6) || defined (STM32F038xx) || \
- defined (STM32F042x6) || defined (STM32F048xx)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U : 5U)
#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
index 9de795a717..0b386ad15f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -293,7 +293,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == HAL_NULL)
+ if(hi2c == NULL)
{
return HAL_ERROR;
}
@@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == HAL_NULL)
+ if(hi2c == NULL)
{
return HAL_ERROR;
}
@@ -503,7 +503,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -623,7 +623,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -734,7 +734,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -975,7 +975,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1047,7 +1047,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1117,7 +1117,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1167,7 +1167,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1218,7 +1218,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1309,7 +1309,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1475,7 +1475,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1555,7 +1555,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1698,7 +1698,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1833,7 +1833,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1926,7 +1926,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -2018,7 +2018,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -2127,7 +2127,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
index 7b6a14121a..80fbdfcb80 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -117,27 +117,6 @@ typedef enum
}HAL_I2C_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup I2C_Error_Code_structure_definition I2C Error Code structure definition
- * @brief I2C Error Code structure definition
- * @{
- */
-
-typedef enum
-{
- HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
- HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
- HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
- HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
- HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */
- HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */
-}HAL_I2C_ErrorTypeDef;
-
/**
* @}
*/
@@ -167,7 +146,8 @@ typedef struct
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
- __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
+ __IO uint32_t ErrorCode; /*!< I2C Error code
+ This parameter can be a value of @ref I2C_Error */
}I2C_HandleTypeDef;
/**
@@ -183,6 +163,25 @@ typedef struct
* @{
*/
+/** @defgroup I2C_Error I2C Error
+ * @brief I2C Error
+ * @{
+ */
+
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
+
+/**
+ * @}
+ */
+
+
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
index 78bcbc8476..6026fff2c0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief I2C Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C extension peripheral:
@@ -194,6 +194,7 @@ HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32
return HAL_OK;
}
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/**
* @brief Enables I2C wakeup from stop mode.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
@@ -270,7 +271,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
return HAL_OK;
}
-
+#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
index b3547525d2..1452a42e57 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
@@ -100,8 +100,10 @@
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
+#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
index 9096535745..c1a03a8b25 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -93,7 +93,7 @@
*** I2S HAL driver macros list ***
=============================================
[..]
- Below the list of most used macros in USART HAL driver.
+ Below the list of most used macros in I2S HAL driver.
(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
@@ -138,6 +138,14 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -147,19 +155,14 @@
* @{
*/
-#ifdef HAL_I2S_MODULE_ENABLED
-
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
@@ -168,8 +171,11 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
@@ -216,7 +222,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
uint32_t tmp = 0, i2sclk = 0;
/* Check the I2S handle allocation */
- if(hi2s == HAL_NULL)
+ if(hi2s == NULL)
{
return HAL_ERROR;
}
@@ -329,7 +335,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
- if(hi2s == HAL_NULL)
+ if(hi2s == NULL)
{
return HAL_ERROR;
}
@@ -443,7 +449,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -533,7 +539,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -611,7 +617,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -678,7 +684,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -743,7 +749,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -824,7 +830,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -981,12 +987,12 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
__HAL_DMA_DISABLE(hi2s->hdmarx);
/* Abort the I2S DMA tx channel */
- if(hi2s->hdmatx != HAL_NULL)
+ if(hi2s->hdmatx != NULL)
{
HAL_DMA_Abort(hi2s->hdmatx);
}
/* Abort the I2S DMA rx channel */
- if(hi2s->hdmarx != HAL_NULL)
+ if(hi2s->hdmarx != NULL)
{
HAL_DMA_Abort(hi2s->hdmarx);
}
@@ -1157,7 +1163,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval I2S Error Code
*/
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}
@@ -1169,8 +1175,7 @@ HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
* @}
*/
-
-/** @defgroup I2S_Private_Functions I2S Private Functions
+/** @addtogroup I2S_Private_Functions I2S Private Functions
* @{
*/
/**
@@ -1361,6 +1366,14 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
return HAL_OK;
}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1372,12 +1385,5 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
/* defined(STM32F091xC) || defined(STM32F098xx) */
#endif /* HAL_I2S_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
index 04f8711fea..38e7841ee0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@@ -103,54 +103,42 @@ typedef enum
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
}HAL_I2S_StateTypeDef;
-/**
- * @brief HAL I2S Error Code structure definition
- */
-typedef enum
-{
- HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2S_ERROR_TIMEOUT = 0x01, /*!< Timeout error */
- HAL_I2S_ERROR_OVR = 0x02, /*!< OVR error */
- HAL_I2S_ERROR_UDR = 0x04, /*!< UDR error */
- HAL_I2S_ERROR_DMA = 0x08, /*!< DMA transfer error */
- HAL_I2S_ERROR_UNKNOW = 0x10 /*!< Unknow Error error */
-}HAL_I2S_ErrorTypeDef;
-
/**
* @brief I2S handle Structure definition
*/
typedef struct
{
- SPI_TypeDef *Instance; /* I2S registers base address */
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
- I2S_InitTypeDef Init; /* I2S communication parameters */
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
- uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
- __IO uint16_t TxXferSize; /* I2S Tx transfer size */
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
- __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
- uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
- __IO uint16_t RxXferSize; /* I2S Rx transfer size */
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
- __IO uint16_t RxXferCount; /* I2S Rx transfer counter
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
- DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
- DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
- __IO HAL_LockTypeDef Lock; /* I2S locking object */
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
- __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
- __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
}I2S_HandleTypeDef;
/**
@@ -161,6 +149,18 @@ typedef struct
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */
+/**
+ * @}
+ */
/** @defgroup I2S_Mode I2S Mode
* @{
@@ -348,13 +348,21 @@ typedef struct
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
- tmpreg = (__HANDLE__)->Instance->SR;}while(0)
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0)
/**
* @}
*/
@@ -412,7 +420,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
index d97855e9e1..3bb9b44478 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -131,6 +131,10 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -139,16 +143,13 @@
* @brief HAL IRDA module driver
* @{
*/
-#ifdef HAL_IRDA_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define TEACK_REACK_TIMEOUT 1000
+#define TEACK_REACK_TIMEOUT 1000
#define IRDA_TXDMA_TIMEOUTVALUE 22000
#define IRDA_TIMEOUT_VALUE 22000
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
@@ -238,7 +239,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == HAL_NULL)
+ if(hirda == NULL)
{
return HAL_ERROR;
}
@@ -287,7 +288,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == HAL_NULL)
+ if(hirda == NULL)
{
return HAL_ERROR;
}
@@ -407,7 +408,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -487,7 +488,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -565,7 +566,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
{
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -615,7 +616,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
{
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -674,7 +675,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -737,7 +738,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1305,7 +1306,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
- hirda->State= HAL_IRDA_STATE_TIMEOUT;
+ hirda->State= HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -1330,7 +1331,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
- hirda->State= HAL_IRDA_STATE_TIMEOUT;
+ hirda->State= HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -1347,15 +1348,16 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
index d05f3612d5..1dd71b5091 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief This file contains all the functions prototypes for the IRDA
* firmware library.
******************************************************************************
@@ -44,7 +44,7 @@
extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -107,19 +107,6 @@ typedef enum
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
}HAL_IRDA_StateTypeDef;
-/**
- * @brief HAL IRDA Error Code structure definition
- */
-typedef enum
-{
- HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
- HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
- HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
- HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
- HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_IRDA_ErrorTypeDef;
-
/**
* @brief IRDA clock sources definition
*/
@@ -137,34 +124,35 @@ typedef enum
*/
typedef struct
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- IRDA_InitTypeDef Init; /* IRDA communication parameters */
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
- uint16_t TxXferSize; /* IRDA Tx Transfer size */
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
- uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
- uint16_t RxXferSize; /* IRDA Rx Transfer size */
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
- uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
- uint16_t Mask; /* USART RX RDR register mask */
+ uint16_t Mask; /*!< USART RX RDR register mask */
- DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_IRDA_StateTypeDef State; /* IRDA communication state */
-
- HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
+ HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
+ __IO uint32_t ErrorCode; /*!< IRDA Error code
+ This parameter can be a value of @ref IRDA_Error */
+
}IRDA_HandleTypeDef;
/**
@@ -189,6 +177,19 @@ typedef enum
* @{
*/
+/** @defgroup IRDA_Error IRDA Error
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
@@ -551,7 +552,7 @@ typedef enum
* @}
*/
-/* Include IRDA HAL Extension module */
+/* Include IRDA HAL Extended module */
#include "stm32f0xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
@@ -618,7 +619,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
index 0b78a679b4..56cffaafed 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -103,7 +103,7 @@
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
+#if defined(STM32F031x6) || defined(STM32F038xx)
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
@@ -125,8 +125,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F030x8) || \
- defined (STM32F042x6) || defined (STM32F048xx) || \
+#elif defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -310,7 +309,7 @@
} \
} while(0)
-#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
+#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
/** @brief Computes the mask to apply to retrieve the received data
@@ -404,7 +403,7 @@
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
index faf91285c0..d8ade7223c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
@@ -2,11 +2,11 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the IWDG peripheral:
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
* + Peripheral State functions
@@ -37,7 +37,6 @@
can be used to have an IWDG timeout with an acceptable accuracy.
For more information, please refer to the STM32F0x Reference manual.
- ===============================================================================
##### How to use this driver #####
===============================================================================
[..]
@@ -171,7 +170,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
uint32_t tickstart = 0;
/* Check the IWDG handle allocation */
- if(hiwdg == HAL_NULL)
+ if(hiwdg == NULL)
{
return HAL_ERROR;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
index 0f50618b3c..0607b4122a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
index 9bc3b51545..ecec1e265b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -76,7 +76,7 @@
#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
@@ -142,7 +142,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
uint32_t wInterrupt_Mask = 0;
/* Check the PCD handle allocation */
- if(hpcd == HAL_NULL)
+ if(hpcd == NULL)
{
return HAL_ERROR;
}
@@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
- if(hpcd == HAL_NULL)
+ if(hpcd == NULL)
{
return HAL_ERROR;
}
@@ -768,7 +768,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Connect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -784,7 +784,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Disconnect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -1353,7 +1353,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
/**
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
#endif /* HAL_PCD_MODULE_ENABLED */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
index 8163fe1341..47fc4318a3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -98,13 +98,13 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Core_Speed */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS */
+ This parameter can be any value of @ref PCD_EP0_MPS */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
This parameter can be set to ENABLE or DISABLE */
@@ -132,7 +132,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
+ This parameter can be any value of @ref PCD_EP_Type */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
@@ -190,7 +190,7 @@ typedef struct
* @{
*/
-/** @defgroup USB_Core_Speed USB Core Speed
+/** @defgroup PCD_Core_Speed PCD Core Speed
* @{
*/
#define PCD_SPEED_HIGH 0 /* Not Supported */
@@ -199,7 +199,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_PHY USB Core PHY
+ /** @defgroup PCD_Core_PHY PCD Core PHY
* @{
*/
#define PCD_PHY_EMBEDDED 2
@@ -207,7 +207,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP0_MPS USB EP0 MPS
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
@@ -223,7 +223,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP_Type USB EP Type
+/** @defgroup PCD_EP_Type PCD EP Type
* @{
*/
#define PCD_EP_TYPE_CTRL 0
@@ -234,7 +234,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_ENDP USB ENDP
+/** @defgroup PCD_ENDP_Type PCD_ENDP_Type
* @{
*/
@@ -267,7 +267,7 @@ typedef struct
* @{
*/
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) = ~(__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
@@ -770,7 +770,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
index 4488294c76..b25c170dee 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -44,7 +44,7 @@
#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
@@ -65,7 +65,7 @@
* @{
*/
-/** @defgroup PCDEx_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup PCDEx_Exported_Functions_Group2 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -146,7 +146,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
#endif /* HAL_PCD_MODULE_ENABLED */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
index 9134967d5b..167070957d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -65,8 +65,8 @@
/** @addtogroup PCDEx_Exported_Functions
* @{
*/
-/** @addtogroup PCDEx_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+
+/** @addtogroup PCDEx_Exported_Functions_Group2
* @{
*/
@@ -90,7 +90,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
index d9ab29c089..a651527631 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -271,9 +271,9 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
* @brief Enters Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Specifies the regulator state in SLEEP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+ * On STM32F0 devices, this parameter is a dummy value and it is ignored
+ * as regulator can't be modified in this mode. Parameter is kept for platform
+ * compatibility.
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
* When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
@@ -284,24 +284,10 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
- uint32_t tmpreg = 0;
-
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
- /* Select the regulator state in SLEEP mode ---------------------------------*/
- tmpreg = PWR->CR;
-
- /* Clear PDDS and LPDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
-
- /* Set LPDS bit according to Regulator value */
- tmpreg |= Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
/* Clear SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
@@ -410,6 +396,60 @@ void HAL_PWR_EnterSTANDBYMode(void)
__WFI();
}
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
index 3c0becf87d..5725323644 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
@@ -175,6 +175,11 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
index 52fbbe8d4e..55dd4a3831 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -217,7 +217,6 @@ __weak void HAL_PWR_PVDCallback(void)
defined (STM32F091xC) || defined (STM32F098xx)
/**
* @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection.
- * @param None
* @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint,
an interrupt is generated Irq line 1.
NVIS has to be enable by user.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
index 6526c5d4d3..43e482263a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
@@ -92,8 +92,8 @@ typedef struct
/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
* @{
*/
-#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
#define PWR_WAKEUP_PIN3 ((uint32_t)0x02)
@@ -117,8 +117,8 @@ typedef struct
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2))
-#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || */
- /* defined (STM32F091xC) || defined (STM32F098xx) */
+#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || */
+ /* defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
@@ -142,9 +142,9 @@ typedef struct
#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)0x80000000) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
/**
* @}
*/
@@ -204,6 +204,10 @@ typedef struct
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#else
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
@@ -339,7 +343,7 @@ typedef struct
#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
index dc7d02c19f..34315ac045 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization/de-initialization function
- * + Peripheral Control function
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
*
@verbatim
==============================================================================
@@ -23,9 +23,7 @@
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
+ [..] Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
@@ -33,7 +31,27 @@
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
- @endverbatim
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registeres.
+ (+) This delay depends on the peripheral mapping.
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ after the clock enable bit is set on the hardware register
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ after the clock enable bit is set on the hardware register
+
+ [..]
+ Possible Workarounds:
+ (#) Enable the peripheral clock sometimes before the peripheral read/write
+ register is required.
+ (#) For AHB peripheral, insert two dummy read to the peripheral register.
+ (#) For APB peripheral, insert a dummy read to the peripheral register.
+
+@endverbatim
******************************************************************************
* @attention
*
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
index 048a5bddab..7b9785c515 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -105,7 +105,7 @@ typedef struct
uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
- uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x and STM32F0x2 devices).
+ uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
This parameter can be a value of @ref RCCEx_HSI48_Config */
uint32_t LSIState; /*!< The new state of the LSI.
@@ -963,32 +963,6 @@ typedef struct
* @}
*/
-/** @addtogroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
- * @{
- */
-/** @brief Macro to configure the USART2 clock (USART2CLK).
- * @param __USART2CLKSource__: specifies the USART2 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
- */
-#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
-
-/** @brief Macro to get the USART2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
- */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
-/**
- * @}
- */
-
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
index 754128b3a0..00a4cc1238 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Extended RCC HAL module driver
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -952,16 +952,17 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (HSI_VALUE/prediv) * pllmul;
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (HSI_VALUE >> 1) * pllmul;
-#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB
+ STM32F091xC || STM32F098xx || STM32F030xC */
}
sysclockfreq = pllclk;
break;
@@ -1100,7 +1101,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
}
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
/*------------------------------ USB Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
{
@@ -1110,7 +1111,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
}
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
@@ -1167,11 +1168,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
/* Get the USB clock source ---------------------------------------------*/
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
@@ -1271,7 +1272,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
{
/* Check the parameter */
- assert_param(pSynchroInfo != HAL_NULL);
+ assert_param(pSynchroInfo != NULL);
/* Get the reload value */
pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
@@ -1303,9 +1304,9 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo
* @arg RCC_CRS_SYNCMISS
* @arg RCC_CRS_TRIMOV
*/
-RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{
- RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE;
+ uint32_t crsstatus = RCC_CRS_NONE;
uint32_t tickstart = 0;
/* Get timeout */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
index 8d9a1489c4..c070dcb62e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -63,7 +63,8 @@
/**
* @brief RCC extended clocks structure definition
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F030xC)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -79,7 +80,29 @@ typedef struct
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
typedef struct
@@ -205,23 +228,9 @@ typedef struct
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F091xC || STM32F098xx */
-
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
-/**
- * @brief RCC CRS Status structures definition
- */
-typedef enum
-{
- RCC_CRS_NONE = 0x00,
- RCC_CRS_TIMEOUT = 0x01,
- RCC_CRS_SYNCOK = 0x02,
- RCC_CRS_SYNCWARM = 0x04,
- RCC_CRS_SYNCERR = 0x08,
- RCC_CRS_SYNCMISS = 0x10,
- RCC_CRS_TRIMOV = 0x20
-} RCC_CRSStatusTypeDef;
/**
* @brief RCC_CRS Init structure definition
@@ -271,7 +280,7 @@ typedef struct
}RCC_CRSSynchroInfoTypeDef;
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
@@ -285,17 +294,51 @@ typedef struct
* @{
*/
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define RCC_CRS_NONE ((uint32_t)0x00000000)
+#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
+#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
+#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
+#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
+#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
+#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
+
+#endif /* STM32F042x6 || STM32F048xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F030xC)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC))
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
@@ -365,7 +408,7 @@ typedef struct
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
@@ -379,7 +422,7 @@ typedef struct
((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCOSOURCE_HSI14))
-#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
@@ -442,6 +485,20 @@ typedef struct
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
+ * @{
+ */
+#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+#endif /* STM32F070x6 || STM32F070xB */
+
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -554,12 +611,16 @@ typedef struct
/**
* @}
*/
-
#else
/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
* @{
*/
+
+#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#else
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
+#endif
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
@@ -608,10 +669,10 @@ typedef struct
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
@@ -628,8 +689,8 @@ typedef struct
((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
@@ -760,14 +821,14 @@ typedef struct
* @}
*/
-/**
- * @}
- */
-
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/* Exported macros ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
@@ -780,29 +841,29 @@ typedef struct
* using it.
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
+#if defined(STM32F030x6) || defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
-#endif /* STM32F030x6 || STM32F030x8 || */
- /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx |[ */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F030x6 || STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || STM32F070xB || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
@@ -834,8 +895,8 @@ typedef struct
#if defined(STM32F030x8) || \
defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
@@ -845,8 +906,8 @@ typedef struct
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F031x6) || defined(STM32F038xx) || \
defined(STM32F042x6) || defined(STM32F048xx) || \
@@ -866,8 +927,8 @@ typedef struct
#if defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
@@ -877,8 +938,8 @@ typedef struct
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
@@ -906,8 +967,8 @@ typedef struct
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
@@ -917,18 +978,18 @@ typedef struct
#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -951,40 +1012,46 @@ typedef struct
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
-#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
@@ -1002,10 +1069,10 @@ typedef struct
/** @brief Force or release AHB peripheral reset.
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F030x6) || defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
@@ -1013,18 +1080,18 @@ typedef struct
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
@@ -1043,10 +1110,10 @@ typedef struct
/** @brief Force or release APB1 peripheral reset.
*/
#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -1054,10 +1121,10 @@ typedef struct
#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F031x6) || defined(STM32F038xx) || \
defined(STM32F042x6) || defined(STM32F048xx) || \
@@ -1077,8 +1144,8 @@ typedef struct
#if defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
@@ -1088,8 +1155,8 @@ typedef struct
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
@@ -1117,8 +1184,8 @@ typedef struct
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
@@ -1128,18 +1195,18 @@ typedef struct
#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -1163,38 +1230,44 @@ typedef struct
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
-#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/** @brief Force or release APB2 peripheral reset.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
-#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
@@ -1250,13 +1323,14 @@ typedef struct
/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F070x6) || defined(STM32F070xB)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
* This parameter can be one of the following values:
- * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
*/
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
@@ -1264,13 +1338,14 @@ typedef struct
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F072xB || STM32F078xx */
+ /* STM32F072xB || STM32F078xx || */
+ /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
@@ -1299,9 +1374,9 @@ typedef struct
/* STM32F091xC || defined(STM32F098xx) */
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSource__: specifies the MCO clock source.
@@ -1348,10 +1423,33 @@ typedef struct
#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
-#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || */
- /* STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ * @param __USART2CLKSource__: specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
#if defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the USART3 clock (USART3CLK).
@@ -1374,7 +1472,7 @@ typedef struct
*/
#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
-#endif /*STM32F091xC || STM32F098xx*/
+#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
@@ -1551,7 +1649,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *Pe
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
index ab176e6e87..2783c28b54 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarm A configuration
+ * + RTC Time and Date functions
+ * + RTC Alarm functions
* + Backup Data Registers configuration
* + Interrupts and flags management
*
@@ -31,12 +31,12 @@
(#) PC13 to PC15 I/Os (when available)
[..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
+ to VDD), the following pins are available:
(#) PC14 and PC15 can be used as either GPIO or LSE pins
(#) PC13 can be used as a GPIO or as the RTC_OUT pin
[..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
+ to VBAT because VDD is not present), the following pins are available:
(#) PC14 and PC15 can be used as LSE pins only
(#) PC13 can be used as the RTC_OUT pin
@@ -48,15 +48,13 @@
occurs:
(#) Software reset, triggered by setting the BDRST bit in the
RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
##### Backup Domain Access #####
===================================================================
[..] After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
-
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(#) Enable the Power Controller (PWR) APB1 interface clock using the
__PWR_CLK_ENABLE() function.
@@ -65,7 +63,7 @@
(#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
- ##### How to use RTC Driver #####
+ ##### How to use this driver #####
===================================================================
[..]
(+) Enable the RTC domain access (see description in the section above).
@@ -83,29 +81,26 @@
===========================
[..]
(+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
- HAL_RTC_SetAlarm_IT() function.
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
##### RTC and low power modes #####
===================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarm (Alarm A),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
-
******************************************************************************
* @attention
*
@@ -168,23 +163,23 @@
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This section provide functions allowing to initialize and configure the
+ [..] This section provides functions allowing to initialize and configure the
RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
RTC registers Write protection, enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
(#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 15-bit synchronous prescaler.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
(++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
+ asynchronous prescaler to a high value to minimize power consumption.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter
+ (#) To configure the RTC Calendar, user application should enter
initialization mode. In this mode, the calendar counter is stopped
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
+ initialization, calendar update or after wake-up from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
@@ -197,13 +192,14 @@
/**
* @brief Initializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
/* Check the RTC peripheral state */
- if(hrtc == HAL_NULL)
+ if(hrtc == NULL)
{
return HAL_ERROR;
}
@@ -269,7 +265,8 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/**
* @brief DeInitializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
@@ -345,25 +342,27 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/**
* @brief Initializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implenetd in the user file
+ the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implenetd in the user file
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -387,12 +386,13 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
/**
* @brief Sets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -511,14 +511,16 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Gets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
- * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers.
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -554,12 +556,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Sets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -662,12 +665,16 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
/**
* @brief Gets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN : Binary data format
- * @arg Format_BCD : BCD data format
+ * @arg FORMAT_BIN : Binary data format
+ * @arg FORMAT_BCD : BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -709,19 +716,20 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
##### RTC Alarm functions #####
===============================================================================
- [..] This section provide functions allowing to configure Alarm feature
+ [..] This section provides functions allowing to configure Alarm feature
@endverbatim
* @{
*/
/**
* @brief Sets the specified RTC Alarm.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -823,6 +831,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
@@ -862,12 +871,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use the HAL_RTC_DeactivateAlarm()).
* @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
@@ -1014,10 +1024,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/**
* @brief Deactive the specified RTC Alarm
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A : AlarmA
+ * @arg RTC_ALARM_A: AlarmA
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
@@ -1040,6 +1051,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
@@ -1071,15 +1083,16 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/**
* @brief Gets the RTC Alarm value and masks.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm
+ * @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A: AlarmA
+ * @arg RTC_ALARM_A: AlarmA
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1118,7 +1131,8 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief This function handles Alarm interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1145,7 +1159,8 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
/**
* @brief Alarm A callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1157,7 +1172,8 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles AlarmA Polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -1165,7 +1181,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
@@ -1214,12 +1230,13 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
+ * initialization, calendar update or after wake-up from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
@@ -1229,6 +1246,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
@@ -1262,8 +1280,9 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
* @{
*/
/**
- * @brief Returns the Alarm state.
- * @param hrtc: RTC handle
+ * @brief Returns the RTC state.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
@@ -1287,8 +1306,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: RTC handle
- * @retval An ErrorStatus enumeration value:
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status:
* - HAL_OK : RTC is in Init mode
* - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
*/
@@ -1302,6 +1322,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
@@ -1353,7 +1374,6 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value)
*/
#endif /* HAL_RTC_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
index 40cc9ecfaf..277112e5ff 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
index 889508fc5d..4566192adf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
@@ -2,15 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
- * + TimeStamp configuration
- * + Tampers configuration
- * + WakeUp Timer configuration
- * + RTC Tamper and TimeStamp Pins Selection
+ * + RTC TimeStamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
* + Extension Control functions
* + Extension RTC features functions
*
@@ -23,19 +22,20 @@
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
- *** RTC Wakeup configuration ***
+ *** RTC Wake-up configuration ***
================================
[..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wake-up timer in interrupt mode
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer()
function.
+ (@) Not available on F030x6/x8/xC and F070x6/xB
*** TimeStamp configuration ***
===============================
[..]
- (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
@@ -44,10 +44,10 @@
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
or Level according to the Tamper filter (if equal to 0 Edge else Level)
value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTCEx_SetTamper_IT() function.
*** Backup Data Registers configuration ***
@@ -57,6 +57,7 @@
function.
(+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
+ (@) Not available on F030x6/x8/xC and F070x6/xB
@endverbatim
@@ -115,7 +116,6 @@
* @{
*/
-
/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
* @brief RTC TimeStamp and Tamper functions
*
@@ -124,7 +124,7 @@
##### RTC TimeStamp and Tamper functions #####
===============================================================================
- [..] This section provide functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure TimeStamp feature
@endverbatim
* @{
@@ -133,13 +133,14 @@
/**
* @brief Sets TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -186,14 +187,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
/**
* @brief Sets TimeStamp with Interrupt.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This API must be called before enabling the TimeStamp feature.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -247,7 +249,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
/**
* @brief Deactivates TimeStamp.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -284,13 +287,14 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
/**
* @brief Gets the RTC TimeStamp value.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTimeStamp: Pointer to Time structure
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -340,7 +344,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -388,7 +393,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to RTC Tamper.
* @retval HAL status
*/
@@ -444,7 +450,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/**
* @brief Deactivates Tamper.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Tamper: Selected tamper pin.
* This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
* @retval HAL status
@@ -471,7 +478,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
/**
* @brief This function handles TimeStamp interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -542,7 +550,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/**
* @brief TimeStamp callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -554,7 +563,8 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Tamper 1 callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -566,7 +576,8 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Tamper 2 callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -576,7 +587,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
*/
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Tamper 3 callback.
* @param hrtc: RTC handle
@@ -592,7 +603,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles TimeStamp polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -600,14 +612,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
{
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
- /* Clear the TIMESTAMP OverRun Flag */
+ /* Clear the TIMESTAMP Overrun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
/* Change TIMESTAMP state */
@@ -634,7 +646,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
/**
* @brief This function handles Tamper1 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -642,7 +655,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
@@ -669,7 +682,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
/**
* @brief This function handles Tamper2 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -677,7 +691,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
@@ -705,7 +719,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief This function handles Tamper3 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -713,7 +728,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
@@ -752,7 +767,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
##### RTC Wake-up functions #####
===============================================================================
- [..] This section provide functions allowing to configure Wake-up feature
+ [..] This section provides functions allowing to configure Wake-up feature
@endverbatim
* @{
@@ -760,7 +775,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
/**
* @brief Sets wake up timer.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
* @retval HAL status
@@ -783,6 +799,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -802,16 +819,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
}
}
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -827,9 +844,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/**
* @brief Sets wake up timer with interrupt
- * @param hrtc: RTC handle
- * @param WakeUpCounter: wake up counter
- * @param WakeUpClock: wake up clock
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -850,6 +868,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -869,10 +888,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
}
}
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
@@ -886,7 +905,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -902,7 +921,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/**
* @brief Deactivates wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -917,12 +937,13 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Disable the Wakeup Timer */
+ /* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -955,7 +976,8 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief Gets wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -966,7 +988,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -993,7 +1016,8 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
/**
* @brief Wake Up Timer callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1005,7 +1029,8 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles Wake Up Timer Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -1013,7 +1038,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
{
uint32_t tickstart = 0;
- /* Get Timeout value */
+ /* Get tick */
tickstart = HAL_GetTick();
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
@@ -1052,27 +1077,28 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
===============================================================================
[..]
This subsection provides functions allowing to
- (+) Writes a data in a specified RTC Backup data register
+ (+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Sets the Coarse calibration parameters.
- (+) Deactivates the Coarse calibration parameters
- (+) Sets the Smooth calibration parameters.
- (+) Configures the Synchronization Shift Control Settings.
- (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enables the RTC reference clock detection.
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
(+) Disable the RTC reference clock detection.
- (+) Enables the Bypass Shadow feature.
- (+) Disables the Bypass Shadow feature.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
@endverbatim
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/**
* @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
* specify the register.
@@ -1095,7 +1121,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
* specify the register.
@@ -1114,25 +1141,26 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @brief Sets the Smooth calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
- * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
- * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
- * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
* @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
* @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmouthCalibMinusPulsesValue mut be equal to 0.
+ * SmouthCalibMinusPulsesValue must be equal to 0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
@@ -1155,6 +1183,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo
/* check if a calibration is pending*/
if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
{
+ /* Get tick */
tickstart = HAL_GetTick();
/* check if a calibration is pending*/
@@ -1194,7 +1223,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo
/**
* @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
@@ -1219,6 +1249,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait until the shift is completed*/
@@ -1289,7 +1320,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh
/**
* @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CalibOutput : Select the Calibration output Selection .
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
@@ -1331,7 +1363,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32
/**
* @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1360,7 +1393,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
/**
* @brief Enables the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1409,7 +1443,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1458,7 +1493,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Enables the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1490,7 +1526,8 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
/**
* @brief Disables the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
index 16d4f7d66a..9bc612815a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@@ -116,7 +116,7 @@ typedef struct
* @}
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
* @{
*/
@@ -130,7 +130,7 @@ typedef struct
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
* @{
@@ -288,7 +288,7 @@ typedef struct
* @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition
* @{
*/
@@ -310,7 +310,7 @@ typedef struct
/**
* @}
*/
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition
* @{
@@ -393,14 +393,14 @@ typedef struct
* @{
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Enable the RTC TimeStamp peripheral.
@@ -409,14 +409,14 @@ typedef struct
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Disable the RTC WakeUp Timer peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Disable the RTC TimeStamp peripheral.
@@ -463,7 +463,7 @@ typedef struct
*/
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Enable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
@@ -473,7 +473,7 @@ typedef struct
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Disable the RTC TimeStamp interrupt.
@@ -485,7 +485,7 @@ typedef struct
*/
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Disable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
@@ -495,7 +495,7 @@ typedef struct
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
@@ -507,7 +507,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
@@ -517,7 +517,7 @@ typedef struct
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
@@ -540,7 +540,7 @@ typedef struct
*/
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Get the selected RTC WakeUpTimer's flag status.
* @param __HANDLE__: specifies the RTC handle.
@@ -551,7 +551,7 @@ typedef struct
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Get the selected RTC Tamper's flag status.
@@ -593,7 +593,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Clear the RTC Wake Up timer's pending flags.
* @param __HANDLE__: specifies the RTC handle.
@@ -603,7 +603,7 @@ typedef struct
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @}
*/
@@ -630,21 +630,21 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
#endif
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
#endif
/**
* @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/** @addtogroup RTCEx_Exported_Functions_Group2
* @{
*/
@@ -667,10 +667,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
*/
/* Extension Control functions ************************************************/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-#endif
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
index 8c39bc04bc..27cd92a6b9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -134,6 +134,10 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -142,16 +146,13 @@
* @brief HAL SMARTCARD module driver
* @{
*/
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define TEACK_REACK_TIMEOUT 1000
+#define TEACK_REACK_TIMEOUT 1000
#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000
#define SMARTCARD_TIMEOUT_VALUE 22000
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
@@ -258,7 +259,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == HAL_NULL)
+ if(hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -313,7 +314,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == HAL_NULL)
+ if(hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -436,7 +437,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -502,7 +503,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -566,7 +567,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -617,7 +618,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard,
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -673,7 +674,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -736,7 +737,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -995,7 +996,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
- hsmartcard->State= HAL_SMARTCARD_STATE_TIMEOUT;
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@@ -1020,7 +1021,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
- hsmartcard->State= HAL_SMARTCARD_STATE_TIMEOUT;
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@@ -1414,16 +1415,17 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
index 017456f73f..b5d5746f04 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined(STM32F030x4) && !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -106,7 +106,7 @@ typedef struct
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_State */
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
@@ -172,20 +172,6 @@ typedef enum
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
-/**
- * @brief HAL SMARTCARD Error Code structure definition
- */
-typedef enum
-{
- HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
- HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
- HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
- HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */
-}HAL_SMARTCARD_ErrorTypeDef;
-
/**
* @brief SMARTCARD clock sources
*/
@@ -203,33 +189,34 @@ typedef enum
*/
typedef struct
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /* SmartCard advanced features initialization parameters */
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
- uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
- uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
- uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+ HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
- HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code
+ This parameter can be a value of @ref SMARTCARD_Error */
}SMARTCARD_HandleTypeDef;
@@ -242,6 +229,20 @@ typedef struct
* @{
*/
+/** @defgroup SMARTCARD_Error SMARTCARD Error
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020) /*!< Receiver TimeOut error */
+/**
+ * @}
+ */
+
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
@@ -324,7 +325,8 @@ typedef struct
* @}
*/
-/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK)
@@ -741,7 +743,7 @@ typedef struct
* @}
*/
-/* Include SMARTCARD HAL Extension module */
+/* Include SMARTCARD HAL Extended module */
#include "stm32f0xx_hal_smartcard_ex.h"
@@ -804,7 +806,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
* @}
*/
-#endif /* !defined(STM32F030x4) && !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
index 7c17ef578f..80fe713808 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief SMARTCARD HAL module driver.
*
* This file provides extended firmware functions to manage the following
@@ -60,6 +60,10 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -68,10 +72,7 @@
* @brief SMARTCARD Extended HAL module driver
* @{
*/
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -181,15 +182,16 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
index 90a69ba6f1..cc053004dd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
index feb5676476..a3499df665 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief SMBUS HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -12,7 +12,6 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
- *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -237,7 +236,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the SMBUS handle allocation */
- if(hsmbus == HAL_NULL)
+ if(hsmbus == NULL)
{
return HAL_ERROR;
}
@@ -336,7 +335,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the SMBUS handle allocation */
- if(hsmbus == HAL_NULL)
+ if(hsmbus == NULL)
{
return HAL_ERROR;
}
@@ -464,7 +463,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == HAL_NULL)
+ if(hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
@@ -553,7 +552,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == HAL_NULL)
+ if(hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
@@ -680,7 +679,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -771,7 +770,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == HAL_NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1280,7 +1279,7 @@ __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
* @param hsmbus : SMBUS handle
* @retval HAL state
*/
-HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->State;
}
@@ -1462,7 +1461,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
if(hsmbus->XferCount == 0)
{
/* Specific use case for Quick command */
- if(hsmbus->pBuffPtr == HAL_NULL)
+ if(hsmbus->pBuffPtr == NULL)
{
/* Generate a Stop command */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
index 7b55b2132b..35fe420e3d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
@@ -103,42 +103,6 @@ typedef struct
section in Reference manual */
} SMBUS_InitTypeDef;
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */
- HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */
- HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */
- HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
- HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
- HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
- HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
- HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */
- HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */
- /* Aliases for inter STM32 series compatibility */
- HAL_SMBUS_STATE_LISTEN = HAL_SMBUS_STATE_SLAVE_LISTEN
-}HAL_SMBUS_StateTypeDef;
-
-/**
- * @brief HAL SMBUS Error Code structure definition
- */
-typedef enum
-{
- HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */
- HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */
- HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */
- HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */
- HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */
- HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */
- HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */
- HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */
-
-}HAL_SMBUS_ErrorTypeDef;
-
/**
* @brief SMBUS handle Structure definition
*/
@@ -156,13 +120,16 @@ typedef struct
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
- __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state
+ This parameter can be a value of @ref SMBUS_State */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
- __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
+ __IO uint32_t State; /*!< SMBUS communication state
+ This parameter can be a value of @ref SMBUS_State */
- __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code
+ This parameter can be a value of @ref SMBUS_Error */
}SMBUS_HandleTypeDef;
/**
@@ -175,6 +142,43 @@ typedef struct
* @{
*/
+/** @defgroup SMBUS_Error SMBUS Error
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_State SMBUS State
+ * @{
+ */
+
+#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
+ /* Aliases for inter STM32 series compatibility */
+#define HAL_SMBUS_STATE_LISTEN HAL_SMBUS_STATE_SLAVE_LISTEN
+
+/**
+ * @}
+ */
+
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
@@ -584,8 +588,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
*/
/* Peripheral State and Errors functions **************************************************/
-HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
index 301f4e8115..6633ea8aa8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_spi.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SPI peripheral:
@@ -129,6 +129,7 @@
* @{
*/
#define SPI_DEFAULT_TIMEOUT 50
+#define SPI_FIFO_SIZE 4
/**
* @}
*/
@@ -140,10 +141,13 @@
* @{
*/
-static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
@@ -162,7 +166,6 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
/**
* @}
*/
@@ -211,7 +214,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
/**
* @brief Initializes the SPI according to the specified parameters
* in the SPI_InitTypeDef and create the associated handle.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
@@ -219,7 +223,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
uint32_t frxth;
/* Check the SPI handle allocation */
- if(hspi == HAL_NULL)
+ if(hspi == NULL)
{
return HAL_ERROR;
}
@@ -311,22 +315,27 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/**
* @brief DeInitializes the SPI peripheral
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == HAL_NULL)
+ if(hspi == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
hspi->State = HAL_SPI_STATE_BUSY;
+ /* check flag before the SPI disable */
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
+ SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
+
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
@@ -343,8 +352,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief SPI MSP Init
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
@@ -355,8 +365,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief SPI MSP DeInit
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
@@ -397,8 +408,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
(#) Blocking mode APIs are :
(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive() in full duplex mode
-
+ (++) HAL_SPI_TransmitReceive() in full duplex mode
+
(#) Non Blocking mode APIs with Interrupt are :
(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
@@ -409,7 +420,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
-
+
(#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
(++) HAL_SPI_TxCpltCallback()
(++) HAL_SPI_RxCpltCallback()
@@ -422,50 +433,56 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief Transmit an amount of data in blocking mode
- * @param hspi: SPI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
-
- if((pData == HAL_NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
+
/* Process Locked */
__HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = HAL_NULL;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_TX(hspi);
+ }
+
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
__HAL_SPI_RESET_CRC(hspi);
}
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- __HAL_SPI_1LINE_TX(hspi);
- }
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -477,16 +494,25 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 16 Bit mode */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
+ /* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0)
{
/* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
{
- return HAL_TIMEOUT;
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
}
}
/* Transmit data in 8 Bit mode */
@@ -494,108 +520,111 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
while (hspi->TxXferCount > 0)
{
- if(hspi->TxXferCount != 0x1)
+ /* Wait until TXE flag is set to send data */
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ if(hspi->TxXferCount > 1)
{
- return HAL_TIMEOUT;
+ /* write on the data register in packaing mode */
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ else
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
}
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
}
else
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
{
- return HAL_TIMEOUT;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
- *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
}
}
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
}
- /* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- return HAL_ERROR;
- }
- else
- {
- return HAL_OK;
+ errorcode = HAL_ERROR;
}
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Receive an amount of data in blocking mode
- * @param hspi: SPI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
__IO uint16_t tmpreg;
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
-
- if((pData == HAL_NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
/* the receive process is not supported in 2Lines direction master mode */
/* in this case we call the transmitReceive process */
+ /* Process Locked */
return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
}
/* Process Locked */
__HAL_LOCK(hspi);
-
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = HAL_NULL;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
-
+
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
__HAL_SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
}
/* Set the Rx Fido thresold */
@@ -616,91 +645,109 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
__HAL_SPI_1LINE_RX(hspi);
}
- /* Check if the SPI is already enabled */
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
- /* Receive data in 8 Bit mode */
if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
{
- while(hspi->RxXferCount > 1)
+ /* Transfert loop */
+ while(hspi->RxXferCount > 0)
{
- /* Wait until the RXNE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
{
- return HAL_TIMEOUT;
+ /* read the received data */
+ (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout manamgement */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
- (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->RxXferCount--;
}
}
- else /* Receive data in 16 Bit mode */
- {
- while(hspi->RxXferCount > 1 )
+ else
+ {
+ /* Transfert loop */
+ while(hspi->RxXferCount > 0)
{
- /* Wait until RXNE flag is reset to read data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
{
- return HAL_TIMEOUT;
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
}
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
+ else
+ {
+ /* Timeout mamangement */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
}
-
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
- }
- /* Wait until RXNE flag is set */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- }
- /* Receive last data in 8 Bit mode */
- else
- {
- (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
- hspi->RxXferCount--;
-
- /* Read CRC from DR to close CRC calculation process */
+ /* Handle the CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* freeze the CRC before the latest data */
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+
+ /* Read the latest data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
+
+ /* Receive last data in 16 Bit mode */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Flag Error*/
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
{
/* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
}
}
}
@@ -708,65 +755,61 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Check the end of the transaction */
if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
-
- hspi->State = HAL_SPI_STATE_READY;
-
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_ERROR;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
{
- return HAL_OK;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Transmit and Receive an amount of data in blocking mode
- * @param hspi: SPI handle
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer to be
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer to be
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- __IO uint16_t tmpreg = 0;
- uint32_t tickstart = 0;
+__IO uint16_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
-
- if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ assert_param(pTxData != NULL);
- tickstart = HAL_GetTick();
-
/* Process Locked */
- __HAL_LOCK(hspi);
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -807,7 +850,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
{
- /* Wait until TXE flag */
+ /* Check TXE flag */
if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
@@ -817,25 +860,21 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
}
}
- /* Wait until RXNE flag */
+ /* Check RXNE flag */
if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
{
*((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
}
}
@@ -844,10 +883,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
{
- /* check if TXE flag is set to send data */
+ /* check TXE flag */
if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
{
- if(hspi->TxXferCount > 2)
+ if(hspi->TxXferCount > 1)
{
hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
@@ -862,7 +901,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
}
@@ -886,15 +925,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->RxXferCount--;
}
}
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
- }
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
}
@@ -911,10 +946,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
@@ -923,18 +960,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
}
}
}
- /* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
@@ -942,335 +972,331 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
}
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- return HAL_ERROR;
- }
- else
- {
- return HAL_OK;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Transmit an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- if(hspi->State == HAL_SPI_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if((pData == NULL) || (Size == 0))
{
- if((pData == HAL_NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = HAL_NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
-
- /* Set the function for IT treatement */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = HAL_NULL;
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->RxISR = HAL_NULL;
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- __HAL_SPI_1LINE_TX(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- __HAL_SPI_RESET_CRC(hspi);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* prepore the transfer */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+ hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL;
+
+ /* Set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
}
else
{
- return HAL_BUSY;
+ hspi->TxISR = SPI_TxISR_8BIT;
}
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- if((pData == HAL_NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = HAL_NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this we call the transmitReceive process */
- return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
- }
-
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
- else
- {
- hspi->CRCSize = 0;
- }
-
- /* check the data size to adapt Rx threshold and the set the function for IT treatement */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- /* set fiforxthresold according the reception data lenght: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_16BIT;
- hspi->TxISR = HAL_NULL;
- }
- else
- {
- /* set fiforxthresold according the reception data lenght: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_8BIT;
- hspi->TxISR = HAL_NULL;
- }
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- __HAL_SPI_1LINE_RX(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- __HAL_SPI_RESET_CRC(hspi);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this we call the transmitReceive process */
+ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
+ }
+
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
+ hspi->CRCSize = 2;
}
-
- return HAL_OK;
}
else
{
- return HAL_BUSY;
+ hspi->CRCSize = 0;
}
+
+ hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL;
+ /* check the data size to adapt Rx threshold and the set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ /* set fiforxthresold according the reception data lenght: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer to be
- * @param Size: amount of data to be sent
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer to be
+ * @param Size : amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- if((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->CRCSize = 0;
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- return HAL_ERROR;
+ hspi->CRCSize = 2;
}
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- hspi->CRCSize = 0;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
-
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatement */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- __HAL_SPI_RESET_CRC(hspi);
- }
-
- /* check if packing mode is enabled and if there is more than 2 data to receive */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
- {
- /* set fiforxthresold according the reception data lenght: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* set fiforxthresold according the reception data lenght: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ }
+
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
- return HAL_BUSY;
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
}
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* check if packing mode is enabled and if there is more than 2 data to receive */
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+ {
+ /* set fiforxthresold according the reception data lenght: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Transmit an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
-
- if((pData == HAL_NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
/* Process Locked */
__HAL_LOCK(hspi);
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = HAL_NULL;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
@@ -1286,11 +1312,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_RESET_CRC(hspi);
}
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = HAL_SPI_DMATransmitCplt;
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfert complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
/* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
/* packing mode is enabled only if the DMA setting is HALWORD */
@@ -1320,45 +1349,50 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
}
/* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- return HAL_OK;
+ return errorcode;
}
/**
-* @brief Receive an amount of data in no-blocking mode with DMA
-* @param hspi: SPI handle
-* @param pData: pointer to data buffer
-* @param Size: amount of data to be sent
-* @retval HAL status
-*/
+ * @brief Receive an amount of data in no-blocking mode with DMA
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
-
- if((pData == HAL_NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* Process Locked */
__HAL_LOCK(hspi);
-
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = HAL_NULL;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
-
+
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
/* Process Unlocked */
@@ -1383,10 +1417,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* packing mode management is enabled by the DMA settings */
if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
- /* Process Locked */
- __HAL_UNLOCK(hspi);
/* Restriction the DMA data received is not allowed in this mode */
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ goto error;
}
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
@@ -1401,21 +1434,21 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfert complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
/* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
/* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
/* Enable the Rx DMA channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1423,177 +1456,260 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
- return HAL_OK;
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer to be
- * @param Size: amount of data to be sent
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer
+ * @param Size : amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- if((hspi->State == HAL_SPI_STATE_READY) ||
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) ||
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* check if the transmit Receive function is not called by a receive master */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Reset CRC Calculation + increase the rxsize */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- __HAL_SPI_RESET_CRC(hspi);
- }
-
- /* Reset the threshold bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-
- /* the packing mode management is enabled by the DMA settings according the spi data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* set fiforxthreshold according the reception data lenght: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* set fiforxthresold according the reception data lenght: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- if((hspi->TxXferSize & 0x1) == 0x0 )
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
- }
- }
-
- if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- /* set fiforxthresold according the reception data lenght: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- /* Size must include the CRC lenght */
- if((hspi->RxXferCount & 0x1) == 0x0 )
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
- }
- }
- }
-
- /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
- the reception request (RXNE) */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
- }
- else
- {
- hspi->hdmarx->XferCpltCallback = HAL_SPI_DMATransmitReceiveCplt;
- }
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
-
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
- /* Enable the Rx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferCpltCallback = HAL_NULL;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
-
- /* Enable the Tx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* check if the transmit Receive function is not called by a receive master */
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Reset CRC Calculation + increase the rxsize */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* the packing mode management is enabled by the DMA settings according the spi data size */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthreshold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- return HAL_BUSY;
+ /* set fiforxthresold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ if((hspi->TxXferSize & 0x1) == 0x0)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ }
+ }
+
+ if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* set fiforxthresold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if((hspi->RxXferCount & 0x1) == 0x0 )
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+ }
+ }
}
+
+ /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
+ reception request (RXNE) */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Enable the Rx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable the Tx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
/**
* @brief This function handles SPI interrupt request.
- * @param hspi: SPI handle
- * @retval HAL status
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None.
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
/* SPI in mode Receiver ----------------------------------------------------*/
- if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
- (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
/* SPI in mode Tramitter ---------------------------------------------------*/
- if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
/* SPI in Erreur Treatment ---------------------------------------------------*/
- if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
{
/* SPI Overrun error interrupt occured -------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
+ if((itflag & SPI_FLAG_OVR) != RESET)
{
if(hspi->State != HAL_SPI_STATE_BUSY_TX)
{
@@ -1607,19 +1723,19 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/* SPI Mode Fault error interrupt occured -------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
+ if((itflag & SPI_FLAG_MODF) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
/* SPI Frame error interrupt occured ----------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
+ if((itflag & SPI_FLAG_FRE) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
-
+
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
@@ -1628,204 +1744,33 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/**
- * @brief DMA SPI transmit process complete callback
- * @param hdma : DMA handle
- * @retval None
+ * @brief Flush the RX fifo.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
*/
-static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Tx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
- /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ __IO uint32_t tmpreg;
+ uint8_t count = 0;
+ while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
{
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->TxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred or Error code */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if(count == SPI_FIFO_SIZE)
{
- HAL_SPI_TxCpltCallback(hspi);
+ return HAL_TIMEOUT;
}
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- }
-}
-
-/**
- * @brief DMA SPI receive process complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- __IO uint16_t tmpreg;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- tmpreg = hspi->Instance->DR;
- }
- else
- {
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
- {
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- }
- }
- }
-
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- }
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-
-static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- __IO int16_t tmpreg;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
- {
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- }
- else
- {
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- tmpreg = hspi->Instance->DR;
- }
- }
-
- /* Check the end of the transaction */
- SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- }
-}
-
-/**
- * @brief DMA SPI communication error callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
- hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
+ };
+ return HAL_OK;
}
/**
* @brief Tx Transfer completed callbacks
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
@@ -1836,8 +1781,9 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Rx Transfer completed callbacks
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
@@ -1848,8 +1794,9 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Tx and Rx Transfer completed callbacks
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
@@ -1857,11 +1804,51 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
*/
}
-
+
+/**
+ * @brief Tx Half Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
/**
* @brief SPI error callbacks
- * @param hspi: SPI handle
- * @retval None
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
@@ -1884,25 +1871,38 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
[..]
This subsection provides a set of functions allowing to control the SPI.
(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
- (+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter)
- without calling the HAL_SPI_Init() API
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
@endverbatim
* @{
*/
/**
* @brief Return the SPI state
- * @param hspi : SPI handle
- * @retval HAL state
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
return hspi->State;
}
+
+/**
+ * @brief Return the SPI error code
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI Error Code
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ return hspi->ErrorCode;
+}
+
/**
* @}
*/
+
/**
* @}
*/
@@ -1912,9 +1912,233 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* @{
*/
+/**
+ * @brief DMA SPI transmit process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO uint16_t tmpreg;
+
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Check the end of the transaction */
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO int16_t tmpreg;
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Half transmit receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
/**
* @brief Rx Handler for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -1958,13 +2182,14 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Rx Handler for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg;
-
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ UNUSED(tmpreg);
hspi->CRCSize--;
/* check end of the reception */
@@ -1982,7 +2207,9 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Tx Handler for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2019,7 +2246,9 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2048,14 +2277,16 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg;
/* Receive data in 16 Bit mode */
- tmpreg = hspi->Instance->DR;
-
+ __IO uint16_t tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -2064,7 +2295,9 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Tx Handler for Transmit and Receive in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2092,12 +2325,14 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the CRC receive in Interrupt context
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg;
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
+ UNUSED(tmpreg);
hspi->CRCSize--;
if(hspi->CRCSize == 0)
@@ -2108,7 +2343,9 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the recieve in Interrupt context
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2134,13 +2371,16 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the CRC 16bit recieve in Interrupt context
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -2150,7 +2390,9 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the 16Bit recieve in Interrupt context
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2177,7 +2419,9 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Handle the data 8Bit transmit in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2197,7 +2441,9 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Handle the data 16Bit transmit in Interrupt mode
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2219,7 +2465,8 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief This function handles SPI Communication Timeout.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param Flag : SPI flag to check
* @param State : flag state to check
* @param Timeout : Timeout duration
@@ -2233,7 +2480,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2269,9 +2516,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
/**
* @brief This function handles SPI Communication Timeout.
- * @param hspi: SPI handle
- * @param Fifo: Fifo to check
- * @param State: Fifo state to check
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo : Fifo to check
+ * @param State : Fifo state to check
* @param Timeout : Timeout duration
* @retval HAL status
*/
@@ -2285,14 +2533,16 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ UNUSED(tmpreg);
}
+
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
@@ -2324,8 +2574,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
/**
* @brief This function handles the check of the RX transaction complete.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param Timeout : Timeout duration
+ * @retval None.
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
{
@@ -2333,59 +2585,32 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
- }
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
-
+
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ }
return HAL_OK;
}
-/**
- * @brief This function handles the check of the RXTX or TX transaction complete.
- * @param hspi: SPI handle
- * @param Timeout : Timeout duration
- */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
-{
- /* Procedure to check the transaction complete */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- return HAL_OK;
-}
-
/**
* @brief This function handles the close of the RXTX transaction.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
- /* Check the end of the transaction */
- SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
@@ -2419,7 +2644,9 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief This function handles the close of the RX transaction.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
@@ -2453,16 +2680,15 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief This function handles the close of the TX transaction.
- * @param hspi: SPI handle
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- /* Check the end of the transaction */
- SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
index 1cf48569b1..b9ecd1716d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_spi.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@@ -106,6 +106,7 @@ typedef struct
This parameter must 0 or 1 or 2*/
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
@@ -117,68 +118,52 @@ typedef struct
*/
typedef enum
{
- HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_TIMEOUT = 0x06, /*!< Timeout state */
- HAL_SPI_STATE_ERROR = 0x07 /*!< Data Transmission and Reception process is ongoing */
-
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
}HAL_SPI_StateTypeDef;
-/**
- * @brief HAL SPI Error Code structure definition
- */
-typedef enum
-{
- HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
- HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
- HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
- HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
- HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
- HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_SPI_ERROR_FLAG = 0x20, /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
- HAL_SPI_ERROR_UNKNOW = 0x40, /*!< Unknow Error error */
-}HAL_SPI_ErrorTypeDef;
-
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
- SPI_TypeDef *Instance; /* SPI registers base address */
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
- SPI_InitTypeDef Init; /* SPI communication parameters */
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
- uint16_t TxXferSize; /* SPI Tx Transfer size */
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
- uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
- uint16_t RxXferSize; /* SPI Rx Transfer size */
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
- uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
- uint32_t CRCSize; /* SPI CRC size used for the transfer */
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
- DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_SPI_StateTypeDef State; /* SPI communication state */
+ HAL_SPI_StateTypeDef State; /*!< SPI communication state */
- HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
+ __IO uint32_t ErrorCode; /*!< SPI Error code
+ This parameter can be a value of @ref SPI_Error */
}SPI_HandleTypeDef;
@@ -192,10 +177,24 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
+/** @defgroup SPI_Error SPI Error
+ * @{
+ */
+ #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+ #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
+ #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
+ #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
+ #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
+ #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+ #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+ #define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /*!< Unknow Error error */
+/**
+ * @}
+ */
+
/** @defgroup SPI_mode SPI mode
* @{
*/
-
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
@@ -223,23 +222,22 @@ typedef struct __SPI_HandleTypeDef
* @}
*/
-/** @defgroup SPI_data_size SPI data size
+/** @defgroup SPI_data_size SPI Data size
* @{
*/
-
-#define SPI_DATASIZE_4BIT ((uint16_t)0x0300)
-#define SPI_DATASIZE_5BIT ((uint16_t)0x0400)
-#define SPI_DATASIZE_6BIT ((uint16_t)0x0500)
-#define SPI_DATASIZE_7BIT ((uint16_t)0x0600)
-#define SPI_DATASIZE_8BIT ((uint16_t)0x0700)
-#define SPI_DATASIZE_9BIT ((uint16_t)0x0800)
-#define SPI_DATASIZE_10BIT ((uint16_t)0x0900)
-#define SPI_DATASIZE_11BIT ((uint16_t)0x0A00)
-#define SPI_DATASIZE_12BIT ((uint16_t)0x0B00)
-#define SPI_DATASIZE_13BIT ((uint16_t)0x0C00)
-#define SPI_DATASIZE_14BIT ((uint16_t)0x0D00)
-#define SPI_DATASIZE_15BIT ((uint16_t)0x0E00)
-#define SPI_DATASIZE_16BIT ((uint16_t)0x0F00)
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
@@ -261,9 +259,8 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
-
-#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
/**
@@ -273,9 +270,8 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
-
-#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
/**
@@ -285,19 +281,17 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Slave_Select_management SPI Slave Select management
* @{
*/
-
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
-
/**
* @}
*/
-/** @defgroup SPI_NSS_pulse_management SPI NSS pulse management
+/** @defgroup SPI_NSSP_Mode SPI NSS pulse management
* @{
*/
#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
@@ -305,16 +299,13 @@ typedef struct __SPI_HandleTypeDef
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
((NSSP) == SPI_NSS_PULSE_DISABLED))
-
/**
* @}
*/
-
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
-
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
@@ -338,7 +329,6 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
* @{
*/
-
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
@@ -350,7 +340,6 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_TI_mode SPI TI mode
* @{
*/
-
#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
#define SPI_TIMODE_ENABLED SPI_CR2_FRF
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
@@ -362,7 +351,6 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-
#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
@@ -391,11 +379,11 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
* @{
* This parameter can be one of the following values:
- * SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+ * RXNE event is generated if the FIFO
* level is greater or equal to 1/2(16-bits).
- * SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4(8 bits).
- */
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4(8 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
@@ -408,8 +396,8 @@ typedef struct __SPI_HandleTypeDef
* @brief SPI Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
- * @{
- */
+ * @{
+ */
#define SPI_IT_TXE SPI_CR2_TXEIE
#define SPI_IT_RXNE SPI_CR2_RXNEIE
#define SPI_IT_ERR SPI_CR2_ERRIE
@@ -441,12 +429,11 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
* @{
*/
+#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
+#define SPI_FTLVL_FULL ((uint32_t)0x1800)
-#define SPI_FTLVL_EMPTY ((uint16_t)0x0000)
-#define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800)
-#define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000)
-#define SPI_FTLVL_FULL ((uint16_t)0x1800)
-
/**
* @}
*/
@@ -454,11 +441,10 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
* @{
*/
-#define SPI_FRLVL_EMPTY ((uint16_t)0x0000)
-#define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200)
-#define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400)
-#define SPI_FRLVL_FULL ((uint16_t)0x0600)
-
+#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)
/**
* @}
*/
@@ -480,23 +466,22 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
/** @brief Enables or disables the specified SPI interrupts.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@@ -506,9 +491,9 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPI flag is set or not.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ : specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
@@ -517,73 +502,86 @@ typedef struct __SPI_HandleTypeDef
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the SPI CRCERR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clears the SPI MODF pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
*
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE);}while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = (__HANDLE__)->Instance->SR;\
+ UNUSED(tmpreg); \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\
+ }while(0)
/** @brief Clears the SPI OVR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
*
* @retval None
*/
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
- (__HANDLE__)->Instance->SR;}while(0)
-
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clears the SPI FRE pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
*
* @retval None
*/
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
-
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0)
/** @brief Enables the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
/** @brief Disables the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
/** @brief Sets the SPI transmit-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
/** @brief Sets the SPI receive-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_BIDIOE))
+#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
/** @brief Resets the CRC calculation of the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
+ * @param __HANDLE__ : specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
@@ -629,10 +627,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi);
+
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
/**
* @}
@@ -644,6 +650,7 @@ void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
index 620314827f..a6284fd928 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -207,7 +207,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
@@ -475,7 +475,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
{
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
@@ -972,7 +972,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
@@ -1472,7 +1472,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
@@ -1938,7 +1938,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
@@ -2205,7 +2205,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
uint32_t tmpccer = 0;
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h
index f010fc9662..405d26d60a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -290,7 +290,7 @@ typedef struct
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
+ This array is accessed by a @ref TIM_DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
@@ -1117,7 +1117,7 @@ typedef struct
* @}
*/
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
+/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c
index 756b3b1ebd..e8d8543f6d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
@@ -162,7 +162,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
TIM_OC_InitTypeDef OC_Config;
/* Check the TIM handle allocation */
- if(htim == HAL_NULL)
+ if(htim == NULL)
{
return HAL_ERROR;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h
index 6b2b2e08c6..f7f974df5c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c
index 323c073e27..589d6de1b5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and DeInitialization
@@ -111,6 +111,12 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+#ifdef HAL_TSC_MODULE_ENABLED
+
+#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
+ defined(STM32F042x6) || defined(STM32F072xB) || \
+ defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -120,12 +126,6 @@
* @{
*/
-#ifdef HAL_TSC_MODULE_ENABLED
-
-#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
- defined(STM32F042x6) || defined(STM32F072xB) || \
- defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -161,7 +161,7 @@ static uint32_t TSC_extract_groups(uint32_t iomask);
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
{
/* Check TSC handle allocation */
- if (htsc == HAL_NULL)
+ if (htsc == NULL)
{
return HAL_ERROR;
}
@@ -244,7 +244,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
{
/* Check TSC handle allocation */
- if (htsc == HAL_NULL)
+ if (htsc == NULL)
{
return HAL_ERROR;
}
@@ -774,18 +774,18 @@ static uint32_t TSC_extract_groups(uint32_t iomask)
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
/* defined(STM32F042x6) || defined(STM32F072xB) || */
/* defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
#endif /* HAL_TSC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h
index d4c539e1a0..da76cf0eb0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief This file contains all the functions prototypes for the TSC firmware
* library.
******************************************************************************
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c
index 596de810be..4300a4ca3d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_uart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -264,7 +264,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -324,7 +324,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -392,7 +392,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -452,7 +452,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -580,7 +580,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -736,7 +736,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
{
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -787,7 +787,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
{
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -912,7 +912,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
{
- if((pData == HAL_NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1050,12 +1050,12 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
huart->Instance->CR3 &= ~USART_CR3_DMAR;
/* Abort the UART DMA tx channel */
- if(huart->hdmatx != HAL_NULL)
+ if(huart->hdmatx != NULL)
{
HAL_DMA_Abort(huart->hdmatx);
}
/* Abort the UART DMA rx channel */
- if(huart->hdmarx != HAL_NULL)
+ if(huart->hdmarx != NULL)
{
HAL_DMA_Abort(huart->hdmarx);
}
@@ -1477,7 +1477,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
- huart->State = HAL_UART_STATE_TIMEOUT;
+ huart->State = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1502,7 +1502,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
- huart->State = HAL_UART_STATE_TIMEOUT;
+ huart->State = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h
index 8836fc6e99..29bf8761b0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_uart.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -141,22 +141,6 @@ typedef struct
This parameter can be a value of @ref UART_MSB_First */
} UART_AdvFeatureInitTypeDef;
-/**
- * @brief UART wake up from stop mode parameters
- */
-typedef struct
-{
- uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
- This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
- If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
- be filled up. */
-
- uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref UART_WakeUp_Address_Length */
-
- uint8_t Address; /*!< UART/USART node address (7-bit long max) */
-} UART_WakeUpTypeDef;
-
/**
* @brief HAL UART State structures definition
*/
@@ -172,19 +156,6 @@ typedef enum
HAL_UART_STATE_ERROR = 0x04 /*!< Error */
}HAL_UART_StateTypeDef;
-/**
- * @brief HAL UART Error Code structure definition
- */
-typedef enum
-{
- HAL_UART_ERROR_NONE = 0x00, /*!< No error */
- HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_UART_ERROR_FE = 0x04, /*!< frame error */
- HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_UART_ErrorTypeDef;
-
/**
* @brief UART clock sources definition
*/
@@ -202,35 +173,36 @@ typedef enum
*/
typedef struct
{
- USART_TypeDef *Instance; /* UART registers base address */
+ USART_TypeDef *Instance; /*!< UART registers base address */
- UART_InitTypeDef Init; /* UART communication parameters */
+ UART_InitTypeDef Init; /*!< UART communication parameters */
- UART_AdvFeatureInitTypeDef AdvancedInit; /* UART Advanced Features initialization parameters */
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
- uint16_t TxXferSize; /* UART Tx Transfer size */
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /* UART Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
- uint16_t RxXferSize; /* UART Rx Transfer size */
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /* UART Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
- uint16_t Mask; /* UART Rx RDR register mask */
+ uint16_t Mask; /*!< UART Rx RDR register mask */
- DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_UART_StateTypeDef State; /* UART communication state */
+ HAL_UART_StateTypeDef State; /*!< UART communication state */
- HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
+ __IO uint32_t ErrorCode; /*!< UART Error code
+ This parameter can be a value of @ref UART_Error */
}UART_HandleTypeDef;
@@ -243,13 +215,28 @@ typedef struct
* @{
*/
+/** @defgroup UART_Error UART Error
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 ((uint32_t)0x0000)
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
+ ((STOPBITS) == UART_STOPBITS_2) || \
+ ((STOPBITS) == UART_STOPBITS_1_5))
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c
index cbe70d1dae..0a0121e984 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Extended UART HAL module driver.
*
* This file provides firmware functions to manage the following extended
@@ -79,9 +79,9 @@
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
/**
@@ -94,164 +94,39 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
* @{
*/
-/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
- * @brief UART Interrupt handling function
- *
-@verbatim
- ===============================================================================
- ##### IO operation function #####
- ===============================================================================
- This subsection provides functions allowing to manage the UART interrupts
- and to handle Wake up interrupt call-back.
-
- (#) Non-Blocking mode API with Interrupt is :
- (+) HAL_UART_IRQHandler()
-
- (#) Callback provided in No_Blocking mode:
- (+) HAL_UART_WakeupCallback()
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles UART interrupt request.
- * @param huart: uart handle
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- /* UART parity error interrupt occurred -------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* UART frame error interrupt occured --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* UART noise error interrupt occured --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* UART Over-Run interrupt occured -----------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- HAL_UART_ErrorCallback(huart);
- }
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
- /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- HAL_UART_WakeupCallback(huart);
- }
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
-
- /* UART in mode Receiver ---------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
- {
- UART_Receive_IT(huart);
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
- {
- UART_Transmit_IT(huart);
- }
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
- {
- UART_EndTransmit_IT(huart);
- }
-}
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
-/**
- * @brief UART wakeup from Stop mode callback
- * @param huart: uart handle
- * @retval None
- */
- __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_WakeupCallback can be implemented in the user file
- */
-}
-#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)*/
-
-/**
- * @}
- */
-
/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration Functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
- (++) Word Length
+ (++) Word Length (Fixed to 8-bits only for LIN mode)
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
the possible UART frame formats are as listed in the following table:
- |-----------|-----------|---------------------------------------|
+ |-----------|-----------|---------------------------------------|
| M1M0 bits | PCE bit | UART frame |
- |-----------------------|---------------------------------------|
+ |-----------------------|---------------------------------------|
| 00 | 0 | | SB | 8-bit data | STB | |
- |-----------|-----------|---------------------------------------|
+ |-----------|-----------|---------------------------------------|
| 00 | 1 | | SB | 7-bit data | PB | STB | |
- |-----------|-----------|---------------------------------------|
+ |-----------|-----------|---------------------------------------|
| 01 | 0 | | SB | 9-bit data | STB | |
- |-----------|-----------|---------------------------------------|
+ |-----------|-----------|---------------------------------------|
| 01 | 1 | | SB | 8-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ +---------------------------------------------------------------+
| 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ |-----------|-----------|---------------------------------------|
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ +---------------------------------------------------------------+
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
@@ -273,7 +148,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
* @{
*/
-
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
* @brief Initializes the RS485 Driver enable feature according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle .
@@ -298,7 +173,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPo
uint32_t temp = 0x0;
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -353,12 +228,12 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPo
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
* @brief Initializes the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
+ * parameters in the UART_InitTypeDef and creates the associated handle.
* @param huart: uart handle
* @param BreakDetectLength: specifies the LIN break detection length.
* This parameter can be one of the following values:
@@ -369,7 +244,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPo
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -384,6 +259,12 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
return HAL_ERROR;
}
+ /* in LIN mode, data length is limited to 8-bit only */
+ if(huart->Init.WordLength!= UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
@@ -419,11 +300,138 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
*/
+/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
+ * @brief Extended UART Interrupt handling function
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to manage the UART interrupts
+ and to handle Wake up interrupt call-back.
+
+ (#) Non-Blocking mode API with Interrupt is :
+ (++) HAL_UART_IRQHandler()
+
+ (#) Callback provided in No_Blocking mode:
+ (++) HAL_UART_WakeupCallback()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief This function handles UART interrupt request.
+ * @param huart: uart handle
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART frame error interrupt occured --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART noise error interrupt occured --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART Over-Run interrupt occured -----------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ HAL_UART_ErrorCallback(huart);
+ }
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ HAL_UART_WakeupCallback(huart);
+ }
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
+ {
+ UART_Transmit_IT(huart);
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+}
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief UART wakeup from Stop mode callback
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_WakeupCallback can be implemented in the user file
+ */
+}
+#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
+
+/**
+ * @}
+ */
+
+
/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@@ -435,19 +443,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
This subsection provides extended functions allowing to control the UART.
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
detection length to more than 4 bits for multiprocessor address mark wake up.
- (+) HAL_UART_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
+ (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
long as UART clock is HSI or LSE
- (+) HAL_UART_DisableStopMode() API disables the above feature
- (+) HAL_MultiProcessorEx_AddressLength_Set() API configures the address length when the
- wake-up event is the address match feature
- (+) UART_Wakeup_AddressConfig() API sets the reference address used when address
- match feature is carried out
+ (+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ (+) HAL_LIN_SendBreak() API transmits the break characters
@endverbatim
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
* @brief Set Wakeup from Stop mode interrupt flag selection
* @param huart: uart handle,
@@ -551,7 +557,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
return HAL_OK;
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @brief By default in multiprocessor mode, when the wake up method is set
@@ -570,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
{
/* Check the UART handle allocation */
- if(huart == HAL_NULL)
+ if(huart == NULL)
{
return HAL_ERROR;
}
@@ -594,26 +600,34 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
}
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart: uart handle
- * @param WakeUpSelection: UART wake up from stop mode parameters
+ * @brief Transmits break characters.
+ * @param huart: UART handle
* @retval HAL status
- */
-static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
{
- /* Check parmeters */
- assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
- /* Set the USART address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
-
- /* Set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
@@ -656,6 +670,27 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
return HAL_OK;
}
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart: uart handle
+ * @param WakeUpSelection: UART wake up from stop mode parameters
+ * @retval HAL status
+ */
+static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ /* Check parmeters */
+ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h
index ef505f4824..7a941621bd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of UART HAL Extension module.
******************************************************************************
* @attention
@@ -55,6 +55,31 @@
*/
/* Exported types ------------------------------------------------------------*/
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UART_WakeUp_Address_Length */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max) */
+} UART_WakeUpTypeDef;
+/**
+ * @}
+ */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
@@ -63,9 +88,9 @@
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
@@ -77,9 +102,9 @@
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
@@ -87,9 +112,9 @@
/** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
@@ -103,15 +128,15 @@
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode
* @{
*/
@@ -133,7 +158,7 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/** @defgroup UART_Flags UARTEx Status Flags
* Elements values convention: 0xXXXX
@@ -142,24 +167,24 @@
*/
#define UART_FLAG_REACK ((uint32_t)0x00400000)
#define UART_FLAG_TEACK ((uint32_t)0x00200000)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_FLAG_WUF ((uint32_t)0x00100000)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_FLAG_RWU ((uint32_t)0x00080000)
#define UART_FLAG_SBKF ((uint32_t)0x00040000
#define UART_FLAG_CMF ((uint32_t)0x00020000)
#define UART_FLAG_BUSY ((uint32_t)0x00010000)
#define UART_FLAG_ABRF ((uint32_t)0x00008000)
#define UART_FLAG_ABRE ((uint32_t)0x00004000)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)
#define UART_FLAG_EOBF ((uint32_t)0x00001000)
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
#define UART_FLAG_RTOF ((uint32_t)0x00000800)
#define UART_FLAG_CTS ((uint32_t)0x00000400)
#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_FLAG_LBDF ((uint32_t)0x00000100)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_FLAG_TXE ((uint32_t)0x00000080)
#define UART_FLAG_TC ((uint32_t)0x00000040)
#define UART_FLAG_RXNE ((uint32_t)0x00000020)
@@ -173,13 +198,13 @@
*/
/** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * Elements values convention: 0000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
+ * - ZZZZZ : Flag position in the ISR register(5bits)
* @{
*/
#define UART_IT_PE ((uint16_t)0x0028)
@@ -187,14 +212,14 @@
#define UART_IT_TC ((uint16_t)0x0626)
#define UART_IT_RXNE ((uint16_t)0x0525)
#define UART_IT_IDLE ((uint16_t)0x0424)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_IT_LBD ((uint16_t)0x0846)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_IT_CTS ((uint16_t)0x096A)
-#define UART_IT_CM ((uint16_t)0x142E)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#define UART_IT_CM ((uint16_t)0x112E)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_IT_WUF ((uint16_t)0x1476)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
*/
@@ -209,16 +234,16 @@
#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
*/
@@ -247,7 +272,7 @@
* @}
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable
* @{
*/
@@ -271,7 +296,7 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
@@ -312,7 +337,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F030x8) || \
+#elif defined (STM32F030x8) || defined (STM32F070x6) || \
defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -347,6 +372,47 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
+#elif defined(STM32F070xB)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -496,6 +562,55 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
+#elif defined(STM32F030xC)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
@@ -509,9 +624,9 @@
* @param __HANDLE__: specifies the UART Handle
* @retval none
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
@@ -574,9 +689,9 @@
} \
} \
} while(0)
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
@@ -591,23 +706,25 @@
* @{
*/
/* Initialization and de-initialization functions ****************************/
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
- * @brief Extended I/O operation functions
+ * @brief Extended UART Interrupt handling function
* @{
*/
-/* I/O operation functions ***************************************************/
+/* IO operation functions ***************************************************/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
*/
@@ -618,9 +735,13 @@ void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart);
*/
/* Peripheral Control functions **********************************************/
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6) && !defined(STM32F030xC)
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c
index 0278904cba..a5fb466f4b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_usart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -253,7 +253,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == HAL_NULL)
+ if(husart == NULL)
{
return HAL_ERROR;
}
@@ -299,7 +299,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == HAL_NULL)
+ if(husart == NULL)
{
return HAL_ERROR;
}
@@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == HAL_NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -573,7 +573,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -703,7 +703,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == HAL_NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -762,7 +762,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == HAL_NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -945,7 +945,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1095,12 +1095,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
husart->Instance->CR3 &= ~USART_CR3_DMAR;
/* Abort the USART DMA tx Channel */
- if(husart->hdmatx != HAL_NULL)
+ if(husart->hdmatx != NULL)
{
HAL_DMA_Abort(husart->hdmatx);
}
/* Abort the USART DMA rx Channel */
- if(husart->hdmarx != HAL_NULL)
+ if(husart->hdmarx != NULL)
{
HAL_DMA_Abort(husart->hdmarx);
}
@@ -1466,7 +1466,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
- husart->State= HAL_USART_STATE_TIMEOUT;
+ husart->State= HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1491,7 +1491,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
- husart->State= HAL_USART_STATE_TIMEOUT;
+ husart->State= HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h
index 6750aa8718..cabbd30263 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_usart.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
@@ -111,19 +111,6 @@ typedef enum
HAL_USART_STATE_ERROR = 0x04 /*!< Error */
}HAL_USART_StateTypeDef;
-/**
- * @brief HAL USART Error Code structure definition
- */
-typedef enum
-{
- HAL_USART_ERROR_NONE = 0x00, /*!< No error */
- HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_USART_ERROR_FE = 0x04, /*!< frame error */
- HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_USART_ErrorTypeDef;
-
/**
* @brief USART clock sources definitions
*/
@@ -163,11 +150,12 @@ typedef struct
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_USART_StateTypeDef State; /*!< USART communication state */
+ HAL_USART_StateTypeDef State; /*!< USART communication state */
- HAL_USART_ErrorTypeDef ErrorCode; /*!< USART Error code */
+ __IO uint32_t ErrorCode; /*!< USART Error code
+ This parameter can be a value of @ref USART_Error */
}USART_HandleTypeDef;
@@ -180,15 +168,26 @@ typedef struct
* @{
*/
+/** @defgroup USART_Error USART Error
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x0000)
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
((STOPBITS) == USART_STOPBITS_1_5) || \
((STOPBITS) == USART_STOPBITS_2))
/**
@@ -525,7 +524,6 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-void HAL_USART_SetConfig(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
/**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h
index 1e6efe46f7..9f244f9298 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of USART HAL Extension module.
******************************************************************************
* @attention
@@ -63,9 +63,9 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
@@ -77,9 +77,9 @@
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
((LENGTH) == USART_WORDLENGTH_9B))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
@@ -121,7 +121,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F030x8) || \
+#elif defined (STM32F030x8) || defined (STM32F070x6) || \
defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -156,6 +156,47 @@
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
+#elif defined (STM32F070xB)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -304,7 +345,56 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
+#elif defined(STM32F030xC)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
@@ -317,9 +407,9 @@
* @param __HANDLE__: specifies the USART Handle
* @retval none
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
@@ -382,9 +472,9 @@
} \
} \
} while(0)
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) */
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c
index 2e44dc759e..946ecad9f4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -38,7 +38,6 @@
(+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms
- ===============================================================================
##### How to use this driver #####
===============================================================================
[..]
@@ -118,7 +117,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
@@ -153,7 +152,7 @@
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
- if(hwwdg == HAL_NULL)
+ if(hwwdg == NULL)
{
return HAL_ERROR;
}
@@ -311,7 +310,7 @@ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Enable the Early Wakeup Interrupt */
- __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
/* Enable the peripheral */
__HAL_WWDG_ENABLE(hwwdg);
@@ -355,7 +354,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
* @brief Handles WWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
+ * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function.
* When the downcounter reaches the value 0x40, and EWI interrupt is
* generated and the corresponding Interrupt Service Routine (ISR) can
* be used to trigger specific actions (such as communications or data
@@ -366,22 +365,26 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
- /* WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
- /* Early Wakeup callback */
- HAL_WWDG_WakeupCallback(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Clear the WWDG Data Ready flag */
- __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
-}
+ /* Wheck if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Early Wakeup callback */
+ HAL_WWDG_WakeupCallback(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+ }
}
+}
/**
* @brief Early Wakeup WWDG callback.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h
index 1e452c887e..155f5448d5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 03-Oct-2014
+ * @version V1.2.0
+ * @date 11-December-2014
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
@@ -81,10 +81,10 @@ typedef struct
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number lower than Max_Data = 0x80 */
+ This parameter must be a number lower than Max_Data = 0x80 */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
} WWDG_InitTypeDef;
@@ -113,24 +113,10 @@ typedef struct
* @{
*/
-/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion
- * @brief WWDG registers bit address in the alias region
- * @{
- */
-
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
-
-/**
- * @}
- */
-
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
-#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
-
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
@@ -139,8 +125,7 @@ typedef struct
* @brief WWDG Flag definition
* @{
*/
-#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */
-
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
@@ -148,16 +133,15 @@ typedef struct
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
/**
* @}
*/
@@ -165,8 +149,7 @@ typedef struct
/** @defgroup WWDG_Window WWDG Window
* @{
*/
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
/**
* @}
*/
@@ -174,8 +157,7 @@ typedef struct
/** @defgroup WWDG_Counter WWDG Counter
* @{
*/
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
-
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
/**
* @}
*/
@@ -194,14 +176,65 @@ typedef struct
* @param __HANDLE__: WWDG handle
* @retval None
*/
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
/**
* @brief Enables the WWDG peripheral.
* @param __HANDLE__: WWDG handle
* @retval None
*/
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
+
+/**
+ * @brief Disables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
+
+/**
+ * @brief Gets the selected WWDG's it status.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Clear the WWDG's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Gets the selected WWDG's flag status.
@@ -211,7 +244,7 @@ typedef struct
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the WWDG's pending flags.
@@ -221,26 +254,16 @@ typedef struct
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/**
- * @brief Enables the WWDG early wakeup interrupt.
- * @param __INTERRUPT__: specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __HANDLE__: WWDG Handle.
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
-
-/** @brief Clear the WWDG's interrupt pending bits
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralNames.h
new file mode 100644
index 0000000000..08f32ca262
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralNames.h
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)USART4_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_14 = (int)TIM14_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.c
new file mode 100644
index 0000000000..c275c03915
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.c
@@ -0,0 +1,184 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C2)},
+ {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C2)},
+ {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM1 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15)}, // TIM15_CH1N
+ {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15)}, // TIM15_CH1
+ {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15)}, // TIM15_CH2
+ {PA_4, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14)}, // TIM14_CH1
+// {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH1
+ {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16)}, // TIM16_CH1
+// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH2
+// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1N
+// {PA_7, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14)}, // TIM14_CH1
+ {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17)}, // TIM17_CH1
+// {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1
+// {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2
+// {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3
+// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4
+
+ {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH3
+// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2N
+ {PB_1, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14)}, // TIM14_CH1
+// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH4
+// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3N
+ {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3)}, // TIM3_CH2
+ {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16)}, // TIM16_CH1N
+ {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17)}, // TIM17_CH1N
+ {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16)}, // TIM16_CH1
+ {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17)}, // TIM17_CH1
+// {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1N
+ {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1
+// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2N
+ {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2
+// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3N
+// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM15)}, // TIM15_CH1N
+
+ {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Warning: SWCLK is also on this pin
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)},
+ {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART3)},
+// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART4)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART3)},
+// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART4)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART3)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+ {NC, NC, 0}
+};
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h
new file mode 100644
index 0000000000..383d022e69
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+//*** ADC ***
+
+extern const PinMap PinMap_ADC[];
+
+//*** I2C ***
+
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+//*** PWM ***
+
+extern const PinMap PinMap_PWM[];
+
+//*** SERIAL ***
+
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+
+//*** SPI ***
+
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PinNames.h
new file mode 100644
index 0000000000..c521ed5ad2
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PinNames.h
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f0xx_hal_gpio.h and stm32f0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ USER_BUTTON = PC_13,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ USBTX = PA_2,
+ USBRX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PortNames.h
new file mode 100644
index 0000000000..b1d7307ed0
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PortNames.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c
new file mode 100644
index 0000000000..69401dd2d2
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+ADC_HandleTypeDef AdcHandle;
+
+int adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_ADC);
+
+ // Save pin number for the read function
+ obj->pin = pin;
+
+ // The ADC initialization is done once
+ if (adc_inited == 0) {
+ adc_inited = 1;
+
+ // Enable ADC clock
+ __ADC1_CLK_ENABLE();
+
+ // Configure ADC
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+ AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+ AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
+ AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ AdcHandle.Init.ScanConvMode = DISABLE;
+ AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV;
+ AdcHandle.Init.LowPowerAutoWait = DISABLE;
+ AdcHandle.Init.LowPowerAutoPowerOff = DISABLE;
+ AdcHandle.Init.ContinuousConvMode = DISABLE;
+ AdcHandle.Init.DiscontinuousConvMode = DISABLE;
+ AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ AdcHandle.Init.DMAContinuousRequests = DISABLE;
+ AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ HAL_ADC_Init(&AdcHandle);
+
+ // Run the ADC calibration
+ HAL_ADCEx_Calibration_Start(&AdcHandle);
+ }
+}
+
+static inline uint16_t adc_read(analogin_t *obj)
+{
+ ADC_ChannelConfTypeDef sConfig;
+
+ AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+
+ // Configure ADC channel
+ sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
+
+ switch (obj->pin) {
+ case PA_0:
+ sConfig.Channel = ADC_CHANNEL_0;
+ break;
+ case PA_1:
+ sConfig.Channel = ADC_CHANNEL_1;
+ break;
+ case PA_2:
+ sConfig.Channel = ADC_CHANNEL_2;
+ break;
+ case PA_3:
+ sConfig.Channel = ADC_CHANNEL_3;
+ break;
+ case PA_4:
+ sConfig.Channel = ADC_CHANNEL_4;
+ break;
+ case PA_5:
+ sConfig.Channel = ADC_CHANNEL_5;
+ break;
+ case PA_6:
+ sConfig.Channel = ADC_CHANNEL_6;
+ break;
+ case PA_7:
+ sConfig.Channel = ADC_CHANNEL_7;
+ break;
+ case PB_0:
+ sConfig.Channel = ADC_CHANNEL_8;
+ break;
+ case PB_1:
+ sConfig.Channel = ADC_CHANNEL_9;
+ break;
+ case PC_0:
+ sConfig.Channel = ADC_CHANNEL_10;
+ break;
+ case PC_1:
+ sConfig.Channel = ADC_CHANNEL_11;
+ break;
+ case PC_2:
+ sConfig.Channel = ADC_CHANNEL_12;
+ break;
+ case PC_3:
+ sConfig.Channel = ADC_CHANNEL_13;
+ break;
+ case PC_4:
+ sConfig.Channel = ADC_CHANNEL_14;
+ break;
+ case PC_5:
+ sConfig.Channel = ADC_CHANNEL_15;
+ break;
+ default:
+ return 0;
+ }
+
+ // Clear all channels as it is not done in HAL_ADC_ConfigChannel()
+ AdcHandle.Instance->CHSELR = 0;
+
+ HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+
+ HAL_ADC_Start(&AdcHandle); // Start conversion
+
+ // Wait end of conversion and get value
+ if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&AdcHandle));
+ } else {
+ return 0;
+ }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ // 12-bit to 16-bit conversion
+ value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+ return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/device.h
new file mode 100644
index 0000000000..57a7aa227d
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/device.h
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN 1
+#define DEVICE_PORTOUT 1
+#define DEVICE_PORTINOUT 1
+
+#define DEVICE_INTERRUPTIN 1
+
+#define DEVICE_ANALOGIN 1
+#define DEVICE_ANALOGOUT 0 // Not present on this device
+
+#define DEVICE_SERIAL 1
+
+#define DEVICE_I2C 1
+#define DEVICE_I2CSLAVE 1
+
+#define DEVICE_SPI 1
+#define DEVICE_SPISLAVE 1
+
+#define DEVICE_RTC 1
+
+#define DEVICE_PWMOUT 1
+
+#define DEVICE_SLEEP 1
+
+//=======================================
+
+#define DEVICE_SEMIHOST 0
+#define DEVICE_LOCALFILESYSTEM 0
+#define DEVICE_ID_LENGTH 24
+
+#define DEVICE_DEBUG_AWARENESS 0
+
+#define DEVICE_STDIO_MESSAGES 1
+
+#define DEVICE_ERROR_RED 0
+
+#include "objects.h"
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c
new file mode 100644
index 0000000000..9d395df29c
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ obj->pin = pin;
+ if (pin == (PinName)NC) {
+ return;
+ }
+
+ uint32_t port_index = STM_PORT(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill GPIO object structure for future use
+ obj->mask = gpio_set(pin);
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set = &gpio->BSRR;
+ obj->reg_clr = &gpio->BRR;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (direction == PIN_OUTPUT) {
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c
new file mode 100644
index 0000000000..2f08bb5506
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c
@@ -0,0 +1,267 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15)
+#define CHANNEL_NUM (3)
+
+// Max pins for one line (max with EXTI4_15)
+#define MAX_PIN_LINE (12)
+
+typedef struct gpio_channel {
+ uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
+ uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
+ uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+ uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
+} gpio_channel_t;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+ {.pin_mask = 0},
+ {.pin_mask = 0},
+ {.pin_mask = 0}
+};
+
+// Used to return the index for channels array.
+static uint32_t pin_base_nr[16] = {
+ // EXTI0_1
+ 0, // pin 0
+ 1, // pin 1
+ // EXTI2_3
+ 0, // pin 2
+ 1, // pin 3
+ // EXTI4_15
+ 0, // pin 4
+ 1, // pin 5
+ 2, // pin 6
+ 3, // pin 7
+ 4, // pin 8
+ 5, // pin 9
+ 6, // pin 10
+ 7, // pin 11
+ 8, // pin 12
+ 9, // pin 13
+ 10, // pin 14
+ 11 // pin 15
+};
+
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+ gpio_channel_t *gpio_channel = &channels[irq_index];
+ uint32_t gpio_idx;
+
+ for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+ uint32_t current_mask = (1 << gpio_idx);
+
+ if (gpio_channel->pin_mask & current_mask) {
+ // Retrieve the gpio and pin that generate the irq
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+ uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
+
+ // Clear interrupt flag
+ if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+ __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+
+ if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
+
+ // Check which edge has generated the irq
+ if ((gpio->IDR & pin) == 0) {
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
+ } else {
+ irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
+ }
+ }
+ }
+ }
+}
+
+// EXTI lines 0 to 1
+static void gpio_irq0(void)
+{
+ handle_interrupt_in(0, 2);
+}
+
+// EXTI lines 2 to 3
+static void gpio_irq1(void)
+{
+ handle_interrupt_in(1, 2);
+}
+
+// EXTI lines 4 to 15
+static void gpio_irq2(void)
+{
+ handle_interrupt_in(2, 12);
+}
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ uint32_t irq_index;
+ gpio_channel_t *gpio_channel;
+ uint32_t gpio_idx;
+
+ if (pin == NC) return -1;
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Select irq number and interrupt routine
+ if ((pin_index == 0) || (pin_index == 1)) {
+ irq_n = EXTI0_1_IRQn;
+ vector = (uint32_t)&gpio_irq0;
+ irq_index = 0;
+ } else if ((pin_index == 2) || (pin_index == 3)) {
+ irq_n = EXTI2_3_IRQn;
+ vector = (uint32_t)&gpio_irq1;
+ irq_index = 1;
+ } else if ((pin_index > 3) && (pin_index < 16)) {
+ irq_n = EXTI4_15_IRQn;
+ vector = (uint32_t)&gpio_irq2;
+ irq_index = 2;
+ } else {
+ error("InterruptIn error: pin not supported.\n");
+ return -1;
+ }
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+
+ // Configure GPIO
+ pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
+
+ // Enable EXTI interrupt
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ // Save informations for future use
+ obj->irq_n = irq_n;
+ obj->irq_index = irq_index;
+ obj->event = EDGE_NONE;
+ obj->pin = pin;
+
+ gpio_channel = &channels[irq_index];
+ gpio_idx = pin_base_nr[pin_index];
+ gpio_channel->pin_mask |= (1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = id;
+ gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+ gpio_channel->channel_pin[gpio_idx] = pin_index;
+
+ irq_handler = handler;
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+ uint32_t pin_index = STM_PIN(obj->pin);
+ uint32_t gpio_idx = pin_base_nr[pin_index];
+
+ gpio_channel->pin_mask &= ~(1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = 0;
+ gpio_channel->channel_gpio[gpio_idx] = 0;
+ gpio_channel->channel_pin[gpio_idx] = 0;
+
+ // Disable EXTI line
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ obj->event = EDGE_NONE;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ uint32_t mode = STM_MODE_IT_EVT_RESET;
+ uint32_t pull = GPIO_NOPULL;
+
+ if (enable) {
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING_FALLING;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or RISE
+ mode = STM_MODE_IT_RISING;
+ obj->event = EDGE_RISE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING_FALLING;
+ obj->event = EDGE_BOTH;
+ } else { // NONE or FALL
+ mode = STM_MODE_IT_FALLING;
+ obj->event = EDGE_FALL;
+ }
+ }
+ } else { // Disable
+ if (event == IRQ_RISE) {
+ if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_FALLING;
+ obj->event = EDGE_FALL;
+ } else { // NONE or RISE
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+ mode = STM_MODE_IT_RISING;
+ obj->event = EDGE_RISE;
+ } else { // NONE or FALL
+ mode = STM_MODE_IT_EVT_RESET;
+ obj->event = EDGE_NONE;
+ }
+ }
+ }
+
+ pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ NVIC_DisableIRQ(obj->irq_n);
+ obj->event = EDGE_NONE;
+}
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h
new file mode 100644
index 0000000000..fdc6112cb6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c
new file mode 100644
index 0000000000..25ac0303ec
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c
@@ -0,0 +1,390 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+/* Timeout values for flags and events waiting loops. These timeouts are
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
+#define FLAG_TIMEOUT ((int)0x1000)
+#define LONG_TIMEOUT ((int)0x8000)
+
+I2C_HandleTypeDef I2cHandle;
+
+int i2c1_inited = 0;
+int i2c2_inited = 0;
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ // Determine the I2C to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+
+ obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT(obj->i2c != (I2CName)NC);
+
+ // Enable I2C1 clock and pinout if not done
+ if ((obj->i2c == I2C_1) && !i2c1_inited) {
+ i2c1_inited = 1;
+ __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK);
+ __I2C1_CLK_ENABLE();
+ // Configure I2C pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
+
+ // Enable I2C2 clock and pinout if not done
+ if ((obj->i2c == I2C_2) && !i2c2_inited) {
+ i2c2_inited = 1;
+ __I2C2_CLK_ENABLE();
+ // Configure I2C pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+ }
+
+ // Reset to clear pending flags if any
+ i2c_reset(obj);
+
+ // I2C configuration
+ i2c_frequency(obj, 100000); // 100 kHz per default
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // wait before init
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
+
+ // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
+ switch (hz) {
+ case 100000:
+ I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
+ break;
+ case 400000:
+ I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
+ break;
+ case 1000000:
+ I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
+ break;
+ default:
+ break;
+ }
+
+ // I2C configuration
+ I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
+ I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
+ I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
+ I2cHandle.Init.OwnAddress1 = 0;
+ I2cHandle.Init.OwnAddress2 = 0;
+ I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ HAL_I2C_Init(&I2cHandle);
+}
+
+inline int i2c_start(i2c_t *obj)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+ // Clear Acknowledge failure flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+ // Generate the START condition
+ i2c->CR2 |= I2C_CR2_START;
+
+ // Wait the START condition has been correctly sent
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) {
+ if ((timeout--) == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+inline int i2c_stop(i2c_t *obj)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+
+ // Generate the STOP condition
+ i2c->CR2 |= I2C_CR2_STOP;
+
+ return 0;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+ int value;
+
+ // Update CR2 register
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ);
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ value = i2c_byte_read(obj, 0);
+ data[count] = (char)value;
+ }
+
+ // Wait transfer complete
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ // Wait until STOPF flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ // Clear STOP Flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+
+ // Update CR2 register
+ i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
+ | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE);
+
+ for (count = 0; count < length; count++) {
+ i2c_byte_write(obj, data[count]);
+ }
+
+ // Wait transfer complete
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
+
+ // If not repeated start, send stop
+ if (stop) {
+ i2c_stop(obj);
+ // Wait until STOPF flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return -1;
+ }
+ }
+ // Clear STOP Flag
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
+ }
+
+ return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Wait until the byte is received
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+ if ((timeout--) == 0) {
+ return -1;
+ }
+ }
+
+ return (int)i2c->RXDR;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+
+ // Wait until the previous byte is transmitted
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) {
+ if ((timeout--) == 0) {
+ return 0;
+ }
+ }
+
+ i2c->TXDR = (uint8_t)data;
+
+ return 1;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ int timeout;
+
+ // Wait before reset
+ timeout = LONG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
+
+ if (obj->i2c == I2C_1) {
+ __I2C1_FORCE_RESET();
+ __I2C1_RELEASE_RESET();
+ }
+ if (obj->i2c == I2C_2) {
+ __I2C2_FORCE_RESET();
+ __I2C2_RELEASE_RESET();
+ }
+}
+
+#if DEVICE_I2CSLAVE
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg = 0;
+
+ // disable
+ i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN);
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+ // Reset address bits
+ tmpreg &= 0xFC00;
+ // Set new address
+ tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
+ // Store the new register value
+ i2c->OAR1 = tmpreg;
+ // enable
+ i2c->OAR1 |= I2C_OAR1_OA1EN;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+
+ // Enable / disable slave
+ if (enable_slave == 1) {
+ tmpreg |= I2C_OAR1_OA1EN;
+ } else {
+ tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN);
+ }
+
+ // Set new mode
+ i2c->OAR1 = tmpreg;
+}
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+int i2c_slave_receive(i2c_t *obj)
+{
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int retValue = NoData;
+
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1)
+ retValue = ReadAddressed;
+ else
+ retValue = WriteAddressed;
+
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
+ }
+ }
+
+ return (retValue);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ char size = 0;
+
+ while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
+
+ return size;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ char size = 0;
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+ do {
+ i2c_byte_write(obj, data[size]);
+ size++;
+ } while (size < length);
+
+ return size;
+}
+
+
+#endif // DEVICE_I2CSLAVE
+
+#endif // DEVICE_I2C
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c
new file mode 100644
index 0000000000..74ce0cf19d
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+}
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/objects.h
new file mode 100644
index 0000000000..162117e03d
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/objects.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c
new file mode 100644
index 0000000000..84600c5ecd
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+// GPIO mode look-up table
+static const uint32_t gpio_mode[13] = {
+ 0x00000000, // 0 = GPIO_MODE_INPUT
+ 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP
+ 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD
+ 0x00000002, // 3 = GPIO_MODE_AF_PP
+ 0x00000012, // 4 = GPIO_MODE_AF_OD
+ 0x00000003, // 5 = GPIO_MODE_ANALOG
+ 0x10110000, // 6 = GPIO_MODE_IT_RISING
+ 0x10210000, // 7 = GPIO_MODE_IT_FALLING
+ 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING
+ 0x10120000, // 9 = GPIO_MODE_EVT_RISING
+ 0x10220000, // 10 = GPIO_MODE_EVT_FALLING
+ 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
+ 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL)
+};
+
+// Enable GPIO clock and return GPIO base address
+uint32_t Set_GPIO_Clock(uint32_t port_idx)
+{
+ uint32_t gpio_add = 0;
+ switch (port_idx) {
+ case PortA:
+ gpio_add = GPIOA_BASE;
+ __GPIOA_CLK_ENABLE();
+ break;
+ case PortB:
+ gpio_add = GPIOB_BASE;
+ __GPIOB_CLK_ENABLE();
+ break;
+ case PortC:
+ gpio_add = GPIOC_BASE;
+ __GPIOC_CLK_ENABLE();
+ break;
+ case PortD:
+ gpio_add = GPIOD_BASE;
+ __GPIOD_CLK_ENABLE();
+ break;
+ case PortF:
+ gpio_add = GPIOF_BASE;
+ __GPIOF_CLK_ENABLE();
+ break;
+ default:
+ error("Pinmap error: wrong port number.");
+ break;
+ }
+ return gpio_add;
+}
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ // Get the pin informations
+ uint32_t mode = STM_PIN_MODE(data);
+ uint32_t pupd = STM_PIN_PUPD(data);
+ uint32_t afnum = STM_PIN_AFNUM(data);
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure GPIO
+ GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
+ GPIO_InitStructure.Mode = gpio_mode[mode];
+ GPIO_InitStructure.Pull = pupd;
+ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+ GPIO_InitStructure.Alternate = afnum;
+ HAL_GPIO_Init(gpio, &GPIO_InitStructure);
+
+ // [TODO] Disconnect SWDIO and SWCLK signals ?
+ // Warning: For debugging it is necessary to reconnect under reset if this is done.
+ //if ((pin == PA_13) || (pin == PA_14)) {
+ //
+ //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure pull-up/pull-down resistors
+ uint32_t pupd = (uint32_t)mode;
+ if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down
+ gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
+ gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
+
+}
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c
new file mode 100644
index 0000000000..e982858665
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble = pin number
+PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ uint32_t port_index = (uint32_t)port;
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill PORT object structure for future use
+ obj->port = port;
+ obj->mask = mask;
+ obj->direction = dir;
+ obj->reg_in = &gpio->IDR;
+ obj->reg_out = &gpio->ODR;
+
+ port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ if (dir == PIN_OUTPUT) {
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint32_t i;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+ if (obj->direction == PIN_OUTPUT) {
+ return (*obj->reg_out & obj->mask);
+ } else { // PIN_INPUT
+ return (*obj->reg_in & obj->mask);
+ }
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c
new file mode 100644
index 0000000000..f459b43670
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c
@@ -0,0 +1,211 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+static TIM_HandleTypeDef TimHandle;
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
+ obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+
+ if (obj->pwm == (PWMName)NC) {
+ error("PWM error: pinout mapping failed.");
+ }
+
+ // Enable TIM clock
+ if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
+ if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+ if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE();
+ if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE();
+ if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE();
+ if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE();
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_PWM);
+
+ obj->pin = pin;
+ obj->period = 0;
+ obj->pulse = 0;
+
+ pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+ // Configure GPIO
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+ TIM_OC_InitTypeDef sConfig;
+ int channel = 0;
+ int complementary_channel = 0;
+
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+ if (value < (float)0.0) {
+ value = 0.0;
+ } else if (value > (float)1.0) {
+ value = 1.0;
+ }
+
+ obj->pulse = (uint32_t)((float)obj->period * value);
+
+ // Configure channels
+ sConfig.OCMode = TIM_OCMODE_PWM1;
+ sConfig.Pulse = obj->pulse;
+ sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
+ sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ sConfig.OCFastMode = TIM_OCFAST_DISABLE;
+ sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
+ sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+
+ switch (obj->pin) {
+ // Channels 1
+ case PA_2:
+ case PA_4:
+ case PA_6:
+ case PA_7:
+ case PB_1:
+ case PB_4:
+ case PB_8:
+ case PB_9:
+ case PB_14:
+ case PC_6:
+ channel = TIM_CHANNEL_1;
+ break;
+ // Channels 1N
+ case PA_1:
+ case PB_6:
+ case PB_7:
+ case PB_13:
+ channel = TIM_CHANNEL_1;
+ complementary_channel = 1;
+ break;
+ // Channels 2
+ case PA_3:
+ case PB_5:
+ case PB_15:
+ case PC_7:
+ channel = TIM_CHANNEL_2;
+ break;
+ // Channels 3
+ case PB_0:
+ case PC_8:
+ channel = TIM_CHANNEL_3;
+ break;
+ // Channels 4
+ case PC_9:
+ channel = TIM_CHANNEL_4;
+ break;
+ default:
+ return;
+ }
+
+ HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
+
+ if (complementary_channel) {
+ HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+ } else {
+ HAL_TIM_PWM_Start(&TimHandle, channel);
+ }
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+ float value = 0;
+ if (obj->period > 0) {
+ value = (float)(obj->pulse) / (float)(obj->period);
+ }
+ return ((value > (float)1.0) ? (float)(1.0) : (value));
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+ float dc = pwmout_read(obj);
+
+ __HAL_TIM_DISABLE(&TimHandle);
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ TimHandle.Init.Period = us - 1;
+ TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_PWM_Init(&TimHandle);
+
+ // Set duty cycle again
+ pwmout_write(obj, dc);
+
+ // Save for future use
+ obj->period = us;
+
+ __HAL_TIM_ENABLE(&TimHandle);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ float value = (float)us / (float)obj->period;
+ pwmout_write(obj, value);
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c
new file mode 100644
index 0000000000..09372b9c32
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c
@@ -0,0 +1,201 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_error.h"
+
+static int rtc_inited = 0;
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ uint32_t rtc_freq = 0;
+
+ if (rtc_inited) return;
+ rtc_inited = 1;
+
+ RtcHandle.Instance = RTC;
+
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ rtc_freq = LSE_VALUE;
+ } else {
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("RTC error: LSI clock initialization failed.");
+ }
+ // Connect LSI to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // This value is LSI typical value. To be measured precisely using a timer input capture for example.
+ rtc_freq = LSI_VALUE;
+ }
+
+ // Enable RTC
+ __HAL_RCC_RTC_ENABLE();
+
+ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
+ RtcHandle.Init.AsynchPrediv = 127;
+ RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
+ RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+ error("RTC error: RTC initialization failed.");
+ }
+}
+
+void rtc_free(void)
+{
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Disable access to Backup domain
+ HAL_PWR_DisableBkUpAccess();
+
+ // Disable LSI and LSE clocks
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ rtc_inited = 0;
+}
+
+int rtc_isenabled(void)
+{
+ return rtc_inited;
+}
+
+/*
+ RTC Registers
+ RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+ RTC_Month 1=january, 2=february, ..., 12=december
+ RTC_Date day of the month 1-31
+ RTC_Year year 0-99
+ struct tm
+ tm_sec seconds after the minute 0-61
+ tm_min minutes after the hour 0-59
+ tm_hour hours since midnight 0-23
+ tm_mday day of the month 1-31
+ tm_mon months since January 0-11
+ tm_year years since 1900
+ tm_wday days since Sunday 0-6
+ tm_yday days since January 1 0-365
+ tm_isdst Daylight Saving Time flag
+*/
+time_t rtc_read(void)
+{
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+ struct tm timeinfo;
+
+ RtcHandle.Instance = RTC;
+
+ // Read actual date and time
+ // Warning: the time must be read first!
+ HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+ HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+
+ // Setup a tm structure based on the RTC
+ timeinfo.tm_wday = dateStruct.WeekDay;
+ timeinfo.tm_mon = dateStruct.Month - 1;
+ timeinfo.tm_mday = dateStruct.Date;
+ timeinfo.tm_year = dateStruct.Year + 100;
+ timeinfo.tm_hour = timeStruct.Hours;
+ timeinfo.tm_min = timeStruct.Minutes;
+ timeinfo.tm_sec = timeStruct.Seconds;
+
+ // Convert to timestamp
+ time_t t = mktime(&timeinfo);
+
+ return t;
+}
+
+void rtc_write(time_t t)
+{
+ RTC_DateTypeDef dateStruct;
+ RTC_TimeTypeDef timeStruct;
+
+ RtcHandle.Instance = RTC;
+
+ // Convert the time into a tm
+ struct tm *timeinfo = localtime(&t);
+
+ // Fill RTC structures
+ dateStruct.WeekDay = timeinfo->tm_wday;
+ dateStruct.Month = timeinfo->tm_mon + 1;
+ dateStruct.Date = timeinfo->tm_mday;
+ dateStruct.Year = timeinfo->tm_year - 100;
+ timeStruct.Hours = timeinfo->tm_hour;
+ timeStruct.Minutes = timeinfo->tm_min;
+ timeStruct.Seconds = timeinfo->tm_sec;
+ timeStruct.TimeFormat = RTC_HOURFORMAT12_PM;
+ timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+ timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+
+ // Change the RTC current date/time
+ HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+ HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c
new file mode 100644
index 0000000000..8e8b303ce1
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c
@@ -0,0 +1,366 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include
+#include "PeripheralPins.h"
+
+#define UART_NUM (4)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0};
+
+static uart_irq_handler irq_handler;
+
+UART_HandleTypeDef UartHandle;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void init_uart(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+ UartHandle.Init.BaudRate = obj->baudrate;
+ UartHandle.Init.WordLength = obj->databits;
+ UartHandle.Init.StopBits = obj->stopbits;
+ UartHandle.Init.Parity = obj->parity;
+ UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+
+ if (obj->pin_rx == NC) {
+ UartHandle.Init.Mode = UART_MODE_TX;
+ } else if (obj->pin_tx == NC) {
+ UartHandle.Init.Mode = UART_MODE_RX;
+ } else {
+ UartHandle.Init.Mode = UART_MODE_TX_RX;
+ }
+
+ // Disable the reception overrun detection
+ UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
+ UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+
+ HAL_UART_Init(&UartHandle);
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ // Determine the UART to use (UART_1, UART_2, ...)
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+ // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+ obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT(obj->uart != (UARTName)NC);
+
+ // Enable USART clock
+ if (obj->uart == UART_1) {
+ __USART1_CLK_ENABLE();
+ obj->index = 0;
+ }
+
+ if (obj->uart == UART_2) {
+ __USART2_CLK_ENABLE();
+ obj->index = 1;
+ }
+
+ if (obj->uart == UART_3) {
+ __USART3_CLK_ENABLE();
+ obj->index = 2;
+ }
+
+ if (obj->uart == UART_4) {
+ __USART4_CLK_ENABLE();
+ obj->index = 3;
+ }
+
+ // Configure the UART pins
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+ if (tx != NC) {
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ pin_mode(rx, PullUp);
+ }
+
+ // Configure UART
+ obj->baudrate = 9600;
+ obj->databits = UART_WORDLENGTH_8B;
+ obj->stopbits = UART_STOPBITS_1;
+ obj->parity = UART_PARITY_NONE;
+
+ obj->pin_tx = tx;
+ obj->pin_rx = rx;
+
+ init_uart(obj);
+
+ // For stdio management
+ if (obj->uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ // Reset UART and disable clock
+ if (obj->uart == UART_1) {
+ __USART1_FORCE_RESET();
+ __USART1_RELEASE_RESET();
+ __USART1_CLK_DISABLE();
+ }
+
+ if (obj->uart == UART_2) {
+ __USART2_FORCE_RESET();
+ __USART2_RELEASE_RESET();
+ __USART2_CLK_DISABLE();
+ }
+
+ if (obj->uart == UART_3) {
+ __USART3_FORCE_RESET();
+ __USART3_RELEASE_RESET();
+ __USART3_CLK_DISABLE();
+ }
+
+ if (obj->uart == UART_4) {
+ __USART4_FORCE_RESET();
+ __USART4_RELEASE_RESET();
+ __USART4_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ obj->baudrate = baudrate;
+ init_uart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
+ } else {
+ obj->databits = UART_WORDLENGTH_8B;
+ }
+
+ switch (parity) {
+ case ParityOdd:
+ case ParityForced0:
+ obj->parity = UART_PARITY_ODD;
+ break;
+ case ParityEven:
+ case ParityForced1:
+ obj->parity = UART_PARITY_EVEN;
+ break;
+ default: // ParityNone
+ obj->parity = UART_PARITY_NONE;
+ break;
+ }
+
+ if (stop_bits == 2) {
+ obj->stopbits = UART_STOPBITS_2;
+ } else {
+ obj->stopbits = UART_STOPBITS_1;
+ }
+
+ init_uart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(UARTName name, int id)
+{
+ UartHandle.Instance = (USART_TypeDef *)name;
+ if (serial_irq_ids[id] != 0) {
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
+ irq_handler(serial_irq_ids[id], TxIrq);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
+ }
+ if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
+ irq_handler(serial_irq_ids[id], RxIrq);
+ volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit
+ }
+ }
+}
+
+static void uart1_irq(void)
+{
+ uart_irq(UART_1, 0);
+}
+
+static void uart2_irq(void)
+{
+ uart_irq(UART_2, 1);
+}
+
+static void uart3_irq(void)
+{
+ uart_irq(UART_3, 2);
+}
+
+static void uart4_irq(void)
+{
+ uart_irq(UART_4, 3);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+ if (obj->uart == UART_1) {
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
+ }
+
+ if (obj->uart == UART_2) {
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
+ }
+
+ if (obj->uart == UART_3) {
+ irq_n = USART3_4_IRQn;
+ vector = (uint32_t)&uart3_irq;
+ }
+
+ if (obj->uart == UART_4) {
+ irq_n = USART3_4_IRQn;
+ vector = (uint32_t)&uart4_irq;
+ }
+
+ if (enable) {
+
+ if (irq == RxIrq) {
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+ } else { // TxIrq
+ __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+ }
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+
+ int all_disabled = 0;
+
+ if (irq == RxIrq) {
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+ // Check if TxIrq is disabled too
+ if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
+ } else { // TxIrq
+ __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
+ // Check if RxIrq is disabled too
+ if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ }
+
+ if (all_disabled) NVIC_DisableIRQ(irq_n);
+
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+ while (!serial_readable(obj));
+ return (int)(uart->RDR & (uint16_t)0xFF);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+ while (!serial_writable(obj));
+ uart->TDR = (uint32_t)(c & (uint16_t)0xFF);
+}
+
+int serial_readable(serial_t *obj)
+{
+ int status;
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ // Check if data is received
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+int serial_writable(serial_t *obj)
+{
+ int status;
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ // Check if data is transmitted
+ status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+void serial_clear(serial_t *obj)
+{
+ UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+ __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
+ __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
+}
+
+void serial_pinout_tx(PinName tx)
+{
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+ // [TODO]
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ // [TODO]
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c
new file mode 100644
index 0000000000..aadbc29e6a
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+
+void sleep(void)
+{
+ TIM_HandleTypeDef TimMasterHandle;
+
+ TimMasterHandle.Instance = TIM1;
+
+ // Disable HAL tick and us_ticker update interrupts
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
+
+ // Request to enter SLEEP mode
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+ // Enable HAL tick and us_ticker update interrupts
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
+}
+
+void deepsleep(void)
+{
+ // Request to enter STOP mode with regulator in low power mode
+ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+ // After wake-up from STOP reconfigure the PLL
+ SetSysClock();
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c
new file mode 100644
index 0000000000..e979892e77
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c
@@ -0,0 +1,298 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+static SPI_HandleTypeDef SpiHandle;
+
+static void init_spi(spi_t *obj)
+{
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+
+ __HAL_SPI_DISABLE(&SpiHandle);
+
+ SpiHandle.Init.Mode = obj->mode;
+ SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
+ SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
+ SpiHandle.Init.CLKPhase = obj->cpha;
+ SpiHandle.Init.CLKPolarity = obj->cpol;
+ SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ SpiHandle.Init.CRCPolynomial = 7;
+ SpiHandle.Init.DataSize = obj->bits;
+ SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ SpiHandle.Init.NSS = obj->nss;
+ SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
+
+ HAL_SPI_Init(&SpiHandle);
+
+ __HAL_SPI_ENABLE(&SpiHandle);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ // Determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT(obj->spi != (SPIName)NC);
+
+ // Enable SPI clock
+ if (obj->spi == SPI_1) {
+ __SPI1_CLK_ENABLE();
+ }
+ if (obj->spi == SPI_2) {
+ __SPI2_CLK_ENABLE();
+ }
+
+ // Configure the SPI pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+ // Save new values
+ obj->bits = SPI_DATASIZE_8BIT;
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256;
+
+ obj->pin_miso = miso;
+ obj->pin_mosi = mosi;
+ obj->pin_sclk = sclk;
+ obj->pin_ssel = ssel;
+
+ if (ssel == NC) { // SW NSS Master mode
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
+ } else { // Slave
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
+ }
+
+ init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+ // Reset SPI and disable clock
+ if (obj->spi == SPI_1) {
+ __SPI1_FORCE_RESET();
+ __SPI1_RELEASE_RESET();
+ __SPI1_CLK_DISABLE();
+ }
+
+ if (obj->spi == SPI_2) {
+ __SPI2_FORCE_RESET();
+ __SPI2_RELEASE_RESET();
+ __SPI2_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ // Save new values
+ if (bits == 16) {
+ obj->bits = SPI_DATASIZE_16BIT;
+ } else {
+ obj->bits = SPI_DATASIZE_8BIT;
+ }
+
+ switch (mode) {
+ case 0:
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_1EDGE;
+ break;
+ case 1:
+ obj->cpol = SPI_POLARITY_LOW;
+ obj->cpha = SPI_PHASE_2EDGE;
+ break;
+ case 2:
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_1EDGE;
+ break;
+ default:
+ obj->cpol = SPI_POLARITY_HIGH;
+ obj->cpha = SPI_PHASE_2EDGE;
+ break;
+ }
+
+ if (slave == 0) {
+ obj->mode = SPI_MODE_MASTER;
+ obj->nss = SPI_NSS_SOFT;
+ } else {
+ obj->mode = SPI_MODE_SLAVE;
+ obj->nss = SPI_NSS_HARD_INPUT;
+ }
+
+ init_spi(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock)
+ if (hz < 375000) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz
+ } else if ((hz >= 375000) && (hz < 750000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz
+ } else if ((hz >= 750000) && (hz < 1000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz
+ } else if ((hz >= 1000000) && (hz < 3000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz
+ } else if ((hz >= 3000000) && (hz < 6000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz
+ } else if ((hz >= 6000000) && (hz < 12000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz
+ } else if ((hz >= 12000000) && (hz < 24000000)) {
+ obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz
+ } else { // >= 24000000
+ obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz
+ }
+
+ init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ // Check if data is received
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ // Check if data is transmitted
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
+ }
+}
+
+static inline int ssp_read(spi_t *obj)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
+ }
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+ int status;
+ SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+ status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+ return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+ return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ return (int)(*p_spi_dr);
+ } else {
+ return (int)spi->DR;
+ }
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
+ if (obj->bits == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
+ }
+}
+
+int spi_busy(spi_t *obj)
+{
+ return ssp_busy(obj);
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c
new file mode 100644
index 0000000000..8afe6a9392
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+// Timer selection
+#define TIM_MST TIM1
+
+static TIM_HandleTypeDef TimMasterHandle;
+static int us_ticker_inited = 0;
+
+volatile uint32_t SlaveCounter = 0;
+volatile uint32_t oc_int_part = 0;
+volatile uint16_t oc_rem_part = 0;
+
+void set_compare(uint16_t count)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ // Set new output compare value
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
+ // Enable IT
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ HAL_InitTick(0); // The passed value is not used
+}
+
+uint32_t us_ticker_read()
+{
+ uint32_t counter, counter2;
+ if (!us_ticker_inited) us_ticker_init();
+ // A situation might appear when Master overflows right after Slave is read and before the
+ // new (overflowed) value of Master is read. Which would make the code below consider the
+ // previous (incorrect) value of Slave and the new value of Master, which would return a
+ // value in the past. Avoid this by computing consecutive values of the timer until they
+ // are properly ordered.
+ counter = (uint32_t)(SlaveCounter << 16);
+ counter += TIM_MST->CNT;
+ while (1) {
+ counter2 = (uint32_t)(SlaveCounter << 16);
+ counter2 += TIM_MST->CNT;
+ if (counter2 > counter) {
+ break;
+ }
+ counter = counter2;
+ }
+ return counter2;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ int delta = (int)((uint32_t)timestamp - us_ticker_read());
+ uint16_t cval = TIM_MST->CNT;
+
+ if (delta <= 0) { // This event was in the past
+ us_ticker_irq_handler();
+ } else {
+ oc_int_part = (uint32_t)(delta >> 16);
+ oc_rem_part = (uint16_t)(delta & 0xFFFF);
+ if (oc_rem_part <= (0xFFFF - cval)) {
+ set_compare(cval + oc_rem_part);
+ oc_rem_part = 0;
+ } else {
+ set_compare(0xFFFF);
+ oc_rem_part = oc_rem_part - (0xFFFF - cval);
+ }
+ }
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ }
+}
diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py
index 4ff58ef593..88588f8172 100755
--- a/workspace_tools/build_release.py
+++ b/workspace_tools/build_release.py
@@ -54,6 +54,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('K20D50M', ('ARM', 'GCC_ARM' , 'IAR')),
('NUCLEO_F030R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
+ ('NUCLEO_F070RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
('NUCLEO_F072RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
('NUCLEO_F091RC', ('ARM', 'uARM', 'IAR')),
('NUCLEO_F103RB', ('ARM', 'uARM', 'IAR')),
diff --git a/workspace_tools/export/gcc_arm_nucleo_f070rb.tmpl b/workspace_tools/export/gcc_arm_nucleo_f070rb.tmpl
new file mode 100644
index 0000000000..4c4286f2ea
--- /dev/null
+++ b/workspace_tools/export/gcc_arm_nucleo_f070rb.tmpl
@@ -0,0 +1,71 @@
+# This file was automagically generated by mbed.org. For more information,
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+GCC_BIN =
+PROJECT = {{name}}
+OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
+SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
+INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
+LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
+LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
+LINKER_SCRIPT = {{linker_script}}
+
+###############################################################################
+AS = $(GCC_BIN)arm-none-eabi-as
+CC = $(GCC_BIN)arm-none-eabi-gcc
+CPP = $(GCC_BIN)arm-none-eabi-g++
+LD = $(GCC_BIN)arm-none-eabi-gcc
+OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
+OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
+SIZE = $(GCC_BIN)arm-none-eabi-size
+
+CPU = -mcpu=cortex-m0 -mthumb
+CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections
+CC_FLAGS += -MMD -MP
+CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
+
+LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main
+LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
+LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+
+ifeq ($(DEBUG), 1)
+ CC_FLAGS += -DDEBUG -O0
+else
+ CC_FLAGS += -DNDEBUG -Os
+endif
+
+all: $(PROJECT).bin $(PROJECT).hex size
+
+clean:
+ rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
+
+.s.o:
+ $(AS) $(CPU) -o $@ $<
+
+.c.o:
+ $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+ $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
+ $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
+
+$(PROJECT).bin: $(PROJECT).elf
+ @$(OBJCOPY) -O binary $< $@
+
+$(PROJECT).hex: $(PROJECT).elf
+ @$(OBJCOPY) -O ihex $< $@
+
+$(PROJECT).lst: $(PROJECT).elf
+ @$(OBJDUMP) -Sdh $< > $@
+
+lst: $(PROJECT).lst
+
+size:
+ $(SIZE) $(PROJECT).elf
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+
diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py
index 0ddb511914..bb0d2413d4 100644
--- a/workspace_tools/export/gccarm.py
+++ b/workspace_tools/export/gccarm.py
@@ -57,6 +57,7 @@ class GccArm(Exporter):
'ARCH_MAX',
'DISCO_F429ZI',
'NUCLEO_F030R8',
+ 'NUCLEO_F070RB',
'NUCLEO_F072RB',
'NUCLEO_F302R8',
'NUCLEO_F334R8',
diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py
index 28dddd3316..e1aa752576 100644
--- a/workspace_tools/export/iar.py
+++ b/workspace_tools/export/iar.py
@@ -41,6 +41,7 @@ class IAREmbeddedWorkbench(Exporter):
'K22F',
'K64F',
'NUCLEO_F030R8',
+ 'NUCLEO_F070RB',
'NUCLEO_F072RB',
'NUCLEO_F091RC',
'NUCLEO_F103RB',
diff --git a/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl b/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl
new file mode 100644
index 0000000000..85fe012717
--- /dev/null
+++ b/workspace_tools/export/iar_nucleo_f070rb.ewp.tmpl
@@ -0,0 +1,1903 @@
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diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index 193d030992..6592bbfaa7 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -39,6 +39,7 @@ class Uvision4(Exporter):
'LPC4337',
'LPC812',
'NUCLEO_F030R8',
+ 'NUCLEO_F070RB',
'NUCLEO_F072RB',
'NUCLEO_F091RC',
'NUCLEO_F103RB',
@@ -72,6 +73,7 @@ class Uvision4(Exporter):
'LPC11C24',
'LPC812',
'NUCLEO_F030R8',
+ 'NUCLEO_F070RB',
'NUCLEO_F072RB',
'NUCLEO_F091RC',
'NUCLEO_F103RB',
diff --git a/workspace_tools/export/uvision4_nucleo_f070rb.uvopt.tmpl b/workspace_tools/export/uvision4_nucleo_f070rb.uvopt.tmpl
new file mode 100644
index 0000000000..93bb1e6e08
--- /dev/null
+++ b/workspace_tools/export/uvision4_nucleo_f070rb.uvopt.tmpl
@@ -0,0 +1,218 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+
+
+
+ 0
+ 0
+
+
+
+ mbed NUCLEO_F070RB
+ 0x4
+ ARM-ADS
+
+ 48000000
+
+ 1
+ 1
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+
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+ STLink\ST-LINKIII-KEIL_SWO.dll
+
+
+
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+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+
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+ DLGUARM
+ (105=-1,-1,-1,-1,0)
+
+
+ 0
+ ST-LINKIII-KEIL_SWO
+ -U-O207 -O207 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F05x_128 -FS08000000 -FL020000
+
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+
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+ -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_48MHZ -FS00 -FL020000
+
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+ main.cpp
+ main.cpp
+ 0
+ 0
+
+
+
+
diff --git a/workspace_tools/export/uvision4_nucleo_f070rb.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f070rb.uvproj.tmpl
new file mode 100644
index 0000000000..cab2b4dd93
--- /dev/null
+++ b/workspace_tools/export/uvision4_nucleo_f070rb.uvproj.tmpl
@@ -0,0 +1,438 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ mbed NUCLEO_F070RB
+ 0x4
+ ARM-ADS
+
+
+ STM32F070RB
+ STMicroelectronics
+ IRAM(0x20000000-0x20003FFF) IROM(0x08000000-0x0801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0")
+ "Startup\ST\STM32F0xx\startup_stm32f070.s" ("STM32F070 Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F0xx_128 -FS08000000 -FL020000)
+ 7471
+ stm32f0xx.h
+ SFD\ST\STM32F0xx\STM32F070x.SFR
+ 0
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+
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+ {{name}}
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+ 0
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+
+
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+ STLink\ST-LINKIII-KEIL_SWO.dll
+ "" ()
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+
+ {% for flag in flags %}{{flag}} {% endfor %}
+ {% for s in symbols %} {{s}}, {% endfor %}
+ {% for path in include_paths %} {{path}}; {% endfor %}
+
+
+
+ 1
+ 0
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+ 0x10000000
+ {{scatter_file}}
+
+ {% for file in object_files %}
+ {{file}}
+ {% endfor %}
+
+
+
+
+
+ {% for group,files in source_files %}
+
+ {{group}}
+
+ {% for file in files %}
+
+ {{file.name}}
+ {{file.type}}
+ {{file.path}}
+
+
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+ {% endfor %}
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+
+
+
diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py
index 0aef94b35d..c6106caffb 100755
--- a/workspace_tools/export_test.py
+++ b/workspace_tools/export_test.py
@@ -116,6 +116,7 @@ if __name__ == '__main__':
('uvision', 'HRM1017'),
('uvision', 'NUCLEO_F030R8'),
+ ('uvision', 'NUCLEO_F070RB'),
('uvision', 'NUCLEO_F072RB'),
('uvision', 'NUCLEO_F091RC'),
('uvision', 'NUCLEO_F103RB'),
@@ -170,6 +171,7 @@ if __name__ == '__main__':
('iar', 'LPC1347'),
('iar', 'NUCLEO_F030R8'),
+ ('iar', 'NUCLEO_F070RB'),
('iar', 'NUCLEO_F072RB'),
('iar', 'NUCLEO_F091RC'),
('iar', 'NUCLEO_F302R8'),
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index bc25a78060..7f19c5def7 100644
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -431,6 +431,16 @@ class NUCLEO_F030R8(Target):
self.supported_form_factors = ["ARDUINO", "MORPHO"]
self.detect_code = ["0725"]
+class NUCLEO_F070RB(Target):
+ def __init__(self):
+ Target.__init__(self)
+ self.core = "Cortex-M0"
+ self.extra_labels = ['STM', 'STM32F0', 'STM32F070RB']
+ self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
+ self.default_toolchain = "uARM"
+ self.supported_form_factors = ["ARDUINO", "MORPHO"]
+ self.detect_code = ["0755"]
+
class NUCLEO_F072RB(Target):
def __init__(self):
Target.__init__(self)
@@ -855,6 +865,7 @@ TARGETS = [
### STMicro ###
NUCLEO_F030R8(),
+ NUCLEO_F070RB(),
NUCLEO_F072RB(),
NUCLEO_F091RC(),
NUCLEO_F103RB(),