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K64F, K66F: Update the ENET PHY driver 

PHY init and autonegotation is split into own functions.
pull/7375/head
Mika Leppänen 2018-06-15 10:40:51 +03:00 committed by adbridge
parent f1416c76fa
commit 787ea51bad
6 changed files with 119 additions and 149 deletions
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78
features/netsocket/emac-drivers/TARGET_Freescale_EMAC/kinetis_emac.cpp
View File

@ -66,8 +66,6 @@ uint32_t *rx_ptr[ENET_RX_RING_LEN];
#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1))) #define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1)))
extern "C" void kinetis_init_eth_hardware(void); extern "C" void kinetis_init_eth_hardware(void);
extern "C" uint32_t ENET_GetInstance(ENET_Type *base);
extern "C" clock_ip_name_t s_enetClock[];
/* \brief Flags for worker thread */ /* \brief Flags for worker thread */
#define FLAG_TX 1 #define FLAG_TX 1
@ -232,7 +230,7 @@ bool Kinetis_EMAC::low_level_init_successful()
ENET_GetDefaultConfig(&config); ENET_GetDefaultConfig(&config);
if (init_enet_phy(ENET, phyAddr, sysClock) != kStatus_Success) { if (PHY_Init(ENET, phyAddr, sysClock) != kStatus_Success) {
return false; return false;
} }
@ -263,78 +261,6 @@ bool Kinetis_EMAC::low_level_init_successful()
return true; return true;
} }
status_t Kinetis_EMAC::init_enet_phy(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{
status_t result = kStatus_Success;
uint32_t instance = ENET_GetInstance(base);
#if TARGET_K66F
uint32_t counter = 0xFFFFFU;
uint32_t idReg = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, srcClock_Hz, false);
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) {
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter) {
return kStatus_Fail;
}
counter = 0xFFFFFU;
#elif TARGET_K64F
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
ENET_SetSMI(base, srcClock_Hz, false);
#else
#error invalid target!
#endif
/* Reset PHY. */
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
return result;
}
status_t Kinetis_EMAC::auto_negotiation(ENET_Type *base, uint32_t phyAddr)
{
uint32_t bssReg;
status_t result;
uint32_t counter = 0xFFFFFFU;
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success) {
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (result == kStatus_Success) {
/* Check auto negotiation complete. */
while (counter --) {
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if (result == kStatus_Success) {
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) {
break;
}
}
if (!counter) {
return kStatus_PHY_AutoNegotiateFail;
}
}
}
}
return result;
}
/** \brief Allocates a emac_mem_buf_t and returns the data from the incoming packet. /** \brief Allocates a emac_mem_buf_t and returns the data from the incoming packet.
* *
* \param[in] idx index of packet to be read * \param[in] idx index of packet to be read
@ -544,7 +470,7 @@ void Kinetis_EMAC::phy_task()
if (crt_state.connected == STATE_LINK_UP) { if (crt_state.connected == STATE_LINK_UP) {
if (prev_state.connected != STATE_LINK_UP) { if (prev_state.connected != STATE_LINK_UP) {
auto_negotiation(ENET, phyAddr); PHY_AutoNegotiation(ENET, phyAddr);
} }
PHY_GetLinkSpeedDuplex(ENET, phyAddr, &crt_state.speed, &crt_state.duplex); PHY_GetLinkSpeedDuplex(ENET, phyAddr, &crt_state.speed, &crt_state.duplex);

2
features/netsocket/emac-drivers/TARGET_Freescale_EMAC/kinetis_emac.h
View File

@ -138,8 +138,6 @@ public:
private: private:
bool low_level_init_successful(); bool low_level_init_successful();
status_t init_enet_phy(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
status_t auto_negotiation(ENET_Type *base, uint32_t phyAddr);
void rx_isr(); void rx_isr();
void tx_isr(); void tx_isr();
void packet_rx(); void packet_rx();

47
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c
View File

@ -64,7 +64,6 @@ extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{ {
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT; uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t idReg = 0; uint32_t idReg = 0;
status_t result = kStatus_Success; status_t result = kStatus_Success;
@ -89,36 +88,42 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
} }
/* Reset PHY. */ /* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
return result;
}
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
{
status_t result = kStatus_Success;
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success) if (result == kStatus_Success)
{ {
/* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success) if (result == kStatus_Success)
{ {
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, /* Check auto negotiation complete. */
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); while (counter --)
if (result == kStatus_Success)
{ {
/* Check auto negotiation complete. */ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
while (counter --) if ( result == kStatus_Success)
{ {
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
if ( result == kStatus_Success)
{ {
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) break;
{
break;
}
} }
}
if (!counter) if (!counter)
{ {
return kStatus_PHY_AutoNegotiateFail; return kStatus_PHY_AutoNegotiateFail;
}
} }
} }
} }

11
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h
View File

@ -136,10 +136,19 @@ extern "C" {
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success * @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/ */
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief Initiates auto negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @retval kStatus_Success PHY auto negotiation success
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr);
/*! /*!
* @brief PHY Write function. This function write data over the SMI to * @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces. * the specified PHY register. This function is called by all PHY interfaces.

119
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/fsl_phy.c
View File

@ -1,32 +1,32 @@
/* /*
* Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved. * Copyright 2016-2017 NXP
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* *
* o Redistributions of source code must retain the above copyright notice, this list * o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer. * of conditions and the following disclaimer.
* *
* o Redistributions in binary form must reproduce the above copyright notice, this * o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or * list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution. * other materials provided with the distribution.
* *
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this * contributors may be used to endorse or promote products derived from this
* software without specific prior written permission. * software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "fsl_phy.h" #include "fsl_phy.h"
@ -53,8 +53,10 @@ extern uint32_t ENET_GetInstance(ENET_Type *base);
* Variables * Variables
******************************************************************************/ ******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */ /*! @brief Pointers to enet clocks for each instance. */
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/******************************************************************************* /*******************************************************************************
* Code * Code
@ -62,45 +64,66 @@ extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{ {
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT; uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t idReg = 0;
status_t result = kStatus_Success; status_t result = kStatus_Success;
uint32_t instance = ENET_GetInstance(base); uint32_t instance = ENET_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */ /* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]); CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, srcClock_Hz, false); ENET_SetSMI(base, srcClock_Hz, false);
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter)
{
return kStatus_Fail;
}
/* Reset PHY. */ /* Reset PHY. */
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
return result;
}
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
{
status_t result = kStatus_Success;
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success) if (result == kStatus_Success)
{ {
/* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success) if (result == kStatus_Success)
{ {
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, /* Check auto negotiation complete. */
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); while (counter --)
if (result == kStatus_Success)
{ {
/* Check auto negotiation complete. */ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
while (counter --) if ( result == kStatus_Success)
{ {
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
if ( result == kStatus_Success)
{ {
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) break;
{
break;
}
} }
}
if (!counter) if (!counter)
{ {
return kStatus_PHY_AutoNegotiateFail; return kStatus_PHY_AutoNegotiateFail;
}
} }
} }
} }

11
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/fsl_phy.h
View File

@ -136,10 +136,19 @@ extern "C" {
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success * @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/ */
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief Initiates auto negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @retval kStatus_Success PHY auto negotiation success
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr);
/*! /*!
* @brief PHY Write function. This function write data over the SMI to * @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces. * the specified PHY register. This function is called by all PHY interfaces.