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SystemCoreClock should correspond to current core clock and not D1 clock.

pull/11894/head
Alexandre Bourdiol 2019-09-30 18:34:29 +02:00 committed by adbridge
parent 5418d70813
commit 7846c9fe91
16 changed files with 68 additions and 90 deletions
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41
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c
View File

@ -17,8 +17,8 @@
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variables SystemD1Clock and SystemD2Clock
* be called whenever the core clock is changed * and must be called whenever the core clock is changed
* during program execution. * during program execution.
* *
* *
@ -111,7 +111,14 @@
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 64000000; #if defined(CORE_CM7)
#define SystemCoreClock SystemD1Clock
#elif defined(CORE_CM4)
#define SystemCoreClock SystemD2Clock
#else
#error "Wrong core selection"
#endif
uint32_t SystemD1Clock = 64000000;
uint32_t SystemD2Clock = 64000000; uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
@ -237,7 +244,7 @@ void SystemInit (void)
} }
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemD1Clock and SystemD2Clock variables according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can * The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
@ -250,10 +257,10 @@ void SystemInit (void)
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) * - If SYSCLK source is CSI, SystemD1Clock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) * - If SYSCLK source is HSI, SystemD1Clock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * - If SYSCLK source is HSE, SystemD1Clock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), * - If SYSCLK source is PLL, SystemD1Clock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
* *
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
@ -283,16 +290,16 @@ void SystemCoreClockUpdate (void)
switch (RCC->CFGR & RCC_CFGR_SWS) switch (RCC->CFGR & RCC_CFGR_SWS)
{ {
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); SystemD1Clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break; break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE; SystemD1Clock = CSI_VALUE;
break; break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE; SystemD1Clock = HSE_VALUE;
break; break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
@ -329,27 +336,27 @@ void SystemCoreClockUpdate (void)
break; break;
} }
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); SystemD1Clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
} }
else else
{ {
SystemCoreClock = 0U; SystemD1Clock = 0U;
} }
break; break;
default: default:
SystemCoreClock = CSI_VALUE; SystemD1Clock = CSI_VALUE;
break; break;
} }
/* Compute SystemClock frequency --------------------------------------------------*/ /* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* SystemCoreClock frequency : CM7 CPU frequency */ /* SystemD1Clock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp; SystemD1Clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
} }

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c
View File

@ -145,10 +145,10 @@ HAL_StatusTypeDef HAL_Init(void)
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Update the SystemCoreClock global variable */ /* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); SystemD1Clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
/* Update the SystemD2Clock global variable */ /* Update the SystemD2Clock global variable */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
@ -251,32 +251,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
return HAL_ERROR; return HAL_ERROR;
} }
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Cortex-M7 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/ /* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
}
else
{
/* Cortex-M4 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
#endif
/* Configure the SysTick IRQ priority */ /* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS)) if (TickPriority < (1UL << __NVIC_PRIO_BITS))

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c
View File

@ -500,7 +500,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */ /* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */ /* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
while (wait_loop_index != 0UL) while (wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;
@ -2804,7 +2804,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */ /* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */ /* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c
View File

@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
/* Wait loop initialization and execution */ /* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */ /* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL))); wait_loop_index = (ADC_STAB_DELAY_US * (SystemD1Clock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;
@ -2122,7 +2122,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */ /* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */ /* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.c
View File

@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles.*/ /* CPU processing cycles.*/
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL))); wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemD1Clock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */ /* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL))); wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;
@ -840,7 +840,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */ /* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL))); wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL) while(wait_loop_index != 0UL)
{ {
wait_loop_index--; wait_loop_index--;

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dcmi.c
View File

@ -643,7 +643,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
*/ */
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{ {
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U); register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */
@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
*/ */
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
{ {
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U); register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma.c
View File

@ -1150,7 +1150,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
uint32_t tmpisr_dma, tmpisr_bdma; uint32_t tmpisr_dma, tmpisr_bdma;
uint32_t ccr_reg; uint32_t ccr_reg;
__IO uint32_t count = 0U; __IO uint32_t count = 0U;
uint32_t timeout = SystemCoreClock / 9600U; uint32_t timeout = SystemD1Clock / 9600U;
/* calculate DMA base and stream number */ /* calculate DMA base and stream number */
DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mdma.c
View File

@ -1512,7 +1512,7 @@ HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
{ {
__IO uint32_t count = 0; __IO uint32_t count = 0;
uint32_t timeout = SystemCoreClock / 9600U; uint32_t timeout = SystemD1Clock / 9600U;
uint32_t generalIntFlag, errorFlag; uint32_t generalIntFlag, errorFlag;

8
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c
View File

@ -210,8 +210,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset CFGR register */ /* Reset CFGR register */
CLEAR_REG(RCC->CFGR); CLEAR_REG(RCC->CFGR);
/* Update the SystemCoreClock global variable */ /* Update the SystemD1Clock global variable */
SystemCoreClock = HSI_VALUE; SystemD1Clock = HSI_VALUE;
/* Adapt Systick interrupt period */ /* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK) if(HAL_InitTick(uwTickPrio) != HAL_OK)
@ -1044,8 +1044,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
} }
} }
/* Update the SystemCoreClock global variable */ /* Update the SystemD1Clock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); SystemD1Clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
/* Configure the source of time base considering new system clocks settings*/ /* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (uwTickPrio); halstatus = HAL_InitTick (uwTickPrio);

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c
View File

@ -2188,8 +2188,8 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
*/ */
uint32_t HAL_RCCEx_GetD1SysClockFreq(void) uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
{ {
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); SystemD1Clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
return SystemCoreClock; return SystemD1Clock;
} }
/** /**

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sai.c
View File

@ -2427,7 +2427,7 @@ static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef
*/ */
static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
{ {
register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemD1Clock / 7U / 1000U);
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Disable the SAI instance */ /* Disable the SAI instance */

8
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_spdifrx.c
View File

@ -853,7 +853,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin
*/ */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{ {
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemD1Clock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@ -938,7 +938,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
*/ */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{ {
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemD1Clock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
*/ */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{ {
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemD1Clock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@ -1124,7 +1124,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
*/ */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{ {
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemD1Clock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_spi.c
View File

@ -2445,7 +2445,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
/* Initialized local variable */ /* Initialized local variable */
errorcode = HAL_OK; errorcode = HAL_OK;
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); count = SPI_DEFAULT_TIMEOUT * (SystemD1Clock / 24UL / 1000UL);
/* If master communication on going, make sure current frame is done before closing the connection */ /* If master communication on going, make sure current frame is done before closing the connection */
if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
@ -2551,7 +2551,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
/* Initialized local variable */ /* Initialized local variable */
errorcode = HAL_OK; errorcode = HAL_OK;
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); count = SPI_DEFAULT_TIMEOUT * (SystemD1Clock / 24UL / 1000UL);
/* If master communication on going, make sure current frame is done before closing the connection */ /* If master communication on going, make sure current frame is done before closing the connection */
if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))

12
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c
View File

@ -1198,7 +1198,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
{ {
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */ The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); register uint32_t count = SDMMC_CMDTIMEOUT * (SystemD1Clock / 8U /1000U);
do do
{ {
@ -1228,7 +1228,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */ The Timeout is expressed in ms */
register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); register uint32_t count = Timeout * (SystemD1Clock / 8U /1000U);
do do
{ {
@ -1361,7 +1361,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
uint32_t sta_reg; uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */ The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); register uint32_t count = SDMMC_CMDTIMEOUT * (SystemD1Clock / 8U /1000U);
do do
{ {
@ -1405,7 +1405,7 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
uint32_t sta_reg; uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */ The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); register uint32_t count = SDMMC_CMDTIMEOUT * (SystemD1Clock / 8U /1000U);
do do
{ {
@ -1447,7 +1447,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */ The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); register uint32_t count = SDMMC_CMDTIMEOUT * (SystemD1Clock / 8U /1000U);
do do
{ {
@ -1518,7 +1518,7 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
uint32_t sta_reg; uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement. /* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */ The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); register uint32_t count = SDMMC_CMDTIMEOUT * (SystemD1Clock / 8U /1000U);
do do
{ {

13
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_utils.c
View File

@ -287,18 +287,6 @@ void LL_mDelay(uint32_t Delay)
@endinternal @endinternal
* @{ * @{
*/ */
#if defined (DUAL_CORE)
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param CPU_Frequency Core frequency in Hz
* @note CPU_Frequency can be calculated thanks to RCC helper macro or function
* @ref LL_RCC_GetSystemClocksFreq
* LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
* and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
* @retval None
*/
#else
/** /**
* @brief This function sets directly SystemCoreClock CMSIS variable. * @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function. * @note Variable can be calculated also through SystemCoreClockUpdate function.
@ -307,7 +295,6 @@ void LL_mDelay(uint32_t Delay)
* @ref LL_RCC_GetSystemClocksFreq * @ref LL_RCC_GetSystemClocksFreq
* @retval None * @retval None
*/ */
#endif /* DUAL_CORE */
void LL_SetSystemCoreClock(uint32_t CPU_Frequency) void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
{ {
/* HCLK clock frequency */ /* HCLK clock frequency */

7
targets/TARGET_STM/TARGET_STM32H7/device/system_stm32h7xx.h
View File

@ -55,7 +55,12 @@
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */ #if defined(DUAL_CORE) && defined(CORE_CM4)
#define SystemCoreClock SystemD2Clock /*!< System Domain1 Clock Frequency */
#else
#define SystemCoreClock SystemD1Clock
#endif
extern uint32_t SystemD1Clock; /*!< System Domain1 Clock Frequency */
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */ extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */ extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */