diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c old mode 100644 new mode 100755 index c4c420e83b..c5e1a34963 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,11 +4,13 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h old mode 100644 new mode 100755 index 8492a5cae8..2adbac54fc --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,11 +4,13 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,6 +36,7 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" #include "cycfg_routing.h" +#include "cycfg_peripherals.h" #include "cycfg_pins.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 7539ee5748..52d9c5b484 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,11 +4,13 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c old mode 100644 new mode 100755 similarity index 75% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c index 50ff9533f8..7fc8584383 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c @@ -1,14 +1,16 @@ /******************************************************************************* -* File Name: cycfg_routing.c +* File Name: cycfg_connectivity_bt.c * * Description: -* Establishes all necessary connections between hardware elements. +* Connectivity BT configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2801 +* mtb-pdl-cat1 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2021 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,8 +26,5 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_routing.h" +#include "cycfg_connectivity_bt.h" -void init_cycfg_routing(void) -{ -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h new file mode 100755 index 0000000000..22b250c4ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.h +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2801 +* mtb-pdl-cat1 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_BT_H) +#define CYCFG_CONNECTIVITY_BT_H + +#include "cycfg_notices.h" +#if defined(__cplusplus) +extern "C" { +#endif + +#define bt_0_power_0_ENABLED 1U + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_BT_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h old mode 100644 new mode 100755 index 34634762ae..dad34f4ac0 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,11 +5,13 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c new file mode 100755 index 0000000000..f4e07f2fa9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h new file mode 100755 index 0000000000..76446735e9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#if defined(__cplusplus) +extern "C" { +#endif + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c old mode 100644 new mode 100755 index a570f45dec..2d2b125a5c --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,11 +4,13 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h old mode 100644 new mode 100755 index fc29eef18d..8e80ab361a --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,11 +4,13 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,6 +40,96 @@ extern "C" { #endif +#if defined (CY_USING_HAL) + #define CYBSP_USER_BTN (P0_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA0 (P10_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA1 (P10_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA2 (P10_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA3 (P10_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA4 (P10_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIOA5 (P10_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_THERM_VDD (P10_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_THERM_OUT (P10_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USER_LED (P11_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS (P11_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3 (P11_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2 (P11_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1 (P11_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0 (P11_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK (P11_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_IN (P12_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_OUT (P12_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_MOSI (P5_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_MISO (P5_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_CLK (P5_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_CS (P5_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_RX (P5_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_TX (P5_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_RTS (P5_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_CTS (P5_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL (P6_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA (P6_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_UART_RX (P6_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_UART_TX (P6_5) +#endif //defined (CY_USING_HAL) #define CYBSP_SWDIO_ENABLED 1U #define CYBSP_SWDIO_PORT GPIO_PRT6 #define CYBSP_SWDIO_PORT_NUM 6U @@ -92,6 +184,27 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO5 (P8_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO13 (P9_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO12 (P9_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO11 (P9_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO10 (P9_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO9 (P9_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_GPIO6 (P9_7) +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; #if defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h old mode 100644 new mode 100755 index fb7532ce6e..f5c1559160 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,11 +4,13 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,7 +34,7 @@ extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_routing(void); +static inline void init_cycfg_routing(void) {} #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c old mode 100644 new mode 100755 index a84bf36bc8..96803f7440 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,11 +4,13 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -59,6 +61,18 @@ #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 #define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 #define CY_CFG_SYSCLK_PLL0_ENABLED 1 @@ -93,6 +107,38 @@ .channel_num = 0U, }; #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 5U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { @@ -569,7 +615,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ - secure_config->altHFfreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV @@ -649,6 +695,30 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); } #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath3Init() + { + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath4Init() + { + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath5Init() + { + Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __STATIC_INLINE void Cy_SysClk_ClkPeriInit() { @@ -1023,4 +1093,20 @@ void init_cycfg_system(void) #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h old mode 100644 new mode 100755 index 2bbe49e15d..faa127a009 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,11 +4,13 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.6.0.4266 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -57,10 +59,14 @@ extern "C" { #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_pathmux_5_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U #define srss_0_clock_0_pll_0_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U @@ -72,6 +78,18 @@ extern "C" { #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_system(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense deleted file mode 100644 index a31d15e293..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus old mode 100644 new mode 100755 index 93773a77c2..9cc156166e --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,6 +1,6 @@ - - + + @@ -10,8 +10,96 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -38,14 +126,32 @@ - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + @@ -108,17 +214,40 @@ + + + + + + + + + + + + + + + + + + + + - + + + + @@ -145,6 +274,5 @@ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct old mode 100644 new mode 100755 similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 46a4364a8e..439fffbfea --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -75,16 +75,12 @@ #define MBED_RAM_SIZE 0x7F800 #endif -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif ; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -249,7 +245,7 @@ LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. LR_EROM XIP_START XIP_SIZE { - cy_xip +0 + .cy_xip +0 { * (.cy_xip) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld old mode 100644 new mode 100755 similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 4e4605db15..adfe2ea07d --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -72,12 +72,12 @@ ENTRY(Reset_Handler) #define MBED_RAM_SIZE 0x7F800 #endif -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif /* The size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; +STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard @@ -399,11 +399,9 @@ SECTIONS /* Places the code in the Execute in Place (XIP) section. See the smif driver * documentation for details. */ - cy_xip : + .cy_xip : { - __cy_xip_start = .; KEEP(*(.cy_xip)) - __cy_xip_end = .; } > xip diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf old mode 100644 new mode 100755 similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index a83a7dcb39..e05dce36cd --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -73,16 +73,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) { define symbol MBED_RAM_SIZE = 0x7F800; } -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x0400; + define symbol MBED_BOOT_STACK_SIZE = 0x0400; } else { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = __STACK_SIZE; + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; } } -define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; /* The symbols below define the location and size of blocks of memory in the target. * Use these symbols to specify the memory regions available for allocation. @@ -186,8 +186,6 @@ define block HEAP with expanding size, alignment = 8, minimum size = __ICF define block RO {first section .intvec, readonly}; -define block cy_xip { section .cy_xip }; - /*-Initializations-*/ initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; @@ -222,7 +220,7 @@ place at start of IROM1_region { block RO }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; /* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; +".cy_xip" : place at start of EROM1_region { section .cy_xip }; /* RAM */ place at start of IRAM1_region { readwrite section .intvec_ram}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c old mode 100644 new mode 100755 index 1e051ac3b7..1edd111ea9 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c @@ -1,27 +1,27 @@ -/***************************************************************************//** -* \file cybsp.c -* -* Description: -* Provides initialization code for starting up the hardware contained on the -* Cypress board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file cybsp.c + * + * Description: + * Provides initialization code for starting up the hardware contained on the + * Cypress board. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #include #include "cy_syspm.h" @@ -36,15 +36,19 @@ #include "mbed_power_mgmt.h" #endif +// Define the VDDA voltage - this is needed as 'Power' configuration is disabled +// from design.modus for now. +#ifndef CY_CFG_PWR_VDDA_MV + #define CY_CFG_PWR_VDDA_MV (3300) +#endif + #if defined(__cplusplus) extern "C" { #endif -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ +// The sysclk deep sleep callback is recommended to be the last callback that is executed before +// entry into deep sleep mode and the first one upon exit the deep sleep mode. +// Doing so minimizes the time spent on low power mode entry and exit. #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) #endif @@ -52,26 +56,34 @@ extern "C" { #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) static cyhal_sdio_t sdio_obj; +//-------------------------------------------------------------------------------------------------- +// cybsp_get_wifi_sdio_obj +//-------------------------------------------------------------------------------------------------- cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { return &sdio_obj; } -#endif -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ + +#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + +//-------------------------------------------------------------------------------------------------- +// cybsp_register_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- static cy_rslt_t cybsp_register_sysclk_pm_callback(void) { - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL }; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = + { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER }; if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) @@ -81,51 +93,64 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void) return result; } + +//-------------------------------------------------------------------------------------------------- +// cybsp_init +//-------------------------------------------------------------------------------------------------- cy_rslt_t cybsp_init(void) { - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) + // Setup hardware manager to track resource usage then initialize all system (clock/power) board + // configuration + #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); if (CY_RSLT_SUCCESS == result) { result = cyhal_syspm_init(); } -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) + #ifdef CY_CFG_PWR_VDDA_MV + if (CY_RSLT_SUCCESS == result) + { + cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); + } + #endif + + #else // if defined(CY_USING_HAL) + cy_rslt_t result = CY_RSLT_SUCCESS; + #endif // if defined(CY_USING_HAL) + + #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) init_cycfg_all(); -#endif + #endif if (CY_RSLT_SUCCESS == result) { result = cybsp_register_sysclk_pm_callback(); } -#if !defined(CY_CFG_PWR_SYS_IDLE_MODE) -#ifdef __MBED__ - /* Disable deep-sleep. */ + #if !defined(CY_CFG_PWR_SYS_IDLE_MODE) + #ifdef __MBED__ + // Disable deep-sleep sleep_manager_lock_deep_sleep(); -#else + #else cyhal_syspm_lock_deepsleep(); -#endif -#endif + #endif + #endif - /* Reserve clock dividers used by NP. */ + // Reserve clock dividers used by NP cyhal_clock_divider_t clock1; cyhal_hwmgr_allocate_clock(&clock1, CY_SYSCLK_DIV_16_BIT, true); cyhal_clock_divider_t clock2; cyhal_hwmgr_allocate_clock(&clock2, CY_SYSCLK_DIV_16_BIT, true); - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ + // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was + // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP + // reservation list (cyreservedresources.list) to make sure no resources are reserved by both. return result; } + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h old mode 100644 new mode 100755 index 1ec5ff5a60..c60384cf80 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file cybsp.h + * + * \brief + * Basic API for setting up boards containing a Cypress MCU. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once @@ -29,29 +29,35 @@ #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) +#include "cybsp_bt_config.h" +#endif #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_macros Macros -* \{ -*/ + * \addtogroup group_bsp_errors Error Codes + * \{ + * Error codes specific to the board. + */ /** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \ + (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) -/** \} group_bsp_macros */ +/** \} group_bsp_errors */ /** -* \addtogroup group_bsp_functions Functions -* \{ -*/ + * \addtogroup group_bsp_functions Functions + * \{ + * All functions exposed by the board. + */ /** * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is * a problem initializing any hardware it returns an error code specific * to the hardware module that had a problem. */ @@ -64,10 +70,10 @@ cy_rslt_t cybsp_init(void); * \returns The initialized sdio object. */ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ +#endif // defined(CYBSP_WIFI_CAPABLE) /** \} group_bsp_functions */ #ifdef __cplusplus } -#endif /* __cplusplus */ +#endif // __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_doc.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_doc.h new file mode 100755 index 0000000000..997d9fbc8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_doc.h @@ -0,0 +1,838 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_pins Pin Mappings + * \{ + * Macro definitions for common peripheral pins on the board. + */ + +#if defined(CYBSP_USER_LED) +/** + * \addtogroup group_bsp_pins_led LED Pins + * \{ + * Pins connected to user LEDs on the board. + */ + +#ifdef CYBSP_LED_RGB_RED +/** RGB LED - Red \def CYBSP_LED_RGB_RED + */ +#endif +#ifdef CYBSP_LED_RGB_GREEN +/** RGB LED - Green \def CYBSP_LED_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED_RGB_BLUE +/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE + */ +#endif +#ifdef CYBSP_USER_LED +/** User LED \def CYBSP_USER_LED + */ +#endif +#ifdef CYBSP_USER_LED1 +/** User LED1 \def CYBSP_USER_LED1 + */ +#endif +#ifdef CYBSP_USER_LED2 +/** User LED2 \def CYBSP_USER_LED2 + */ +#endif +#ifdef CYBSP_USER_LED3 +/** User LED3 \def CYBSP_USER_LED3 + */ +#endif +#ifdef CYBSP_USER_LED4 +/** User LED 4 \def CYBSP_USER_LED4 + */ +#endif +#ifdef CYBSP_USER_LED5 +/** User LED 5 \def CYBSP_USER_LED5 + */ +#endif +#ifdef CYBSP_USER_LED6 +/** User LED 6 \def CYBSP_USER_LED6 + */ +#endif +#ifdef CYBSP_USER_LED7 +/** User LED 7 \def CYBSP_USER_LED7 + */ +#endif +#ifdef CYBSP_USER_LED8 +/** User LED 8 \def CYBSP_USER_LED8 + */ +#endif +#ifdef CYBSP_USER_LED9 +/** User LED 9 \def CYBSP_USER_LED9 + */ +#endif +#ifdef CYBSP_USER_LED10 +/** User LED 10 \def CYBSP_USER_LED10 + */ +#endif +#ifdef CYBSP_LED1 +/** LED 1 \def CYBSP_LED1 + */ +#endif +#ifdef CYBSP_LED2 +/** LED 2 \def CYBSP_LED2 + */ +#endif +#ifdef CYBSP_LED3 +/** LED 3 \def CYBSP_LED3 + */ +#endif +#ifdef CYBSP_LED3_RGB_RED +/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED + */ +#endif +#ifdef CYBSP_LED3_RGB_GREEN +/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED3_RGB_BLUE +/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE + */ +#endif +#ifdef CYBSP_LED4 +/** LED 4 \def CYBSP_LED4 + */ +#endif +#ifdef CYBSP_LED5 +/** LED 5 \def CYBSP_LED5 + */ +#endif +#ifdef CYBSP_LED6 +/** LED 6 \def CYBSP_LED6 + */ +#endif +#ifdef CYBSP_LED7 +/** LED 7 \def CYBSP_LED7 + */ +#endif +#ifdef CYBSP_LED8 +/** LED 8 \def CYBSP_LED8 + */ +#endif +#ifdef CYBSP_LED9 +/** LED 9 \def CYBSP_LED9 + */ +#endif +#ifdef CYBSP_LED10 +/** LED 10 \def CYBSP_LED10 + */ +#endif +#ifdef CYBSP_LED11 +/** LED 11 \def CYBSP_LED11 + */ +#endif +#ifdef CYBSP_LED12 +/** LED 12 \def CYBSP_LED12 + */ +#endif +#ifdef CYBSP_LED13 +/** LED 13 \def CYBSP_LED13 + */ +#endif +#ifdef CYBSP_LED_SLD0 +/** Slider LED 0 \def CYBSP_LED_SLD0 + */ +#endif +#ifdef CYBSP_LED_SLD1 +/** Slider LED 1 \def CYBSP_LED_SLD1 + */ +#endif +#ifdef CYBSP_LED_SLD2 +/** Slider LED 2 \def CYBSP_LED_SLD2 + */ +#endif +#ifdef CYBSP_LED_SLD3 +/** Slider LED 3 \def CYBSP_LED_SLD3 + */ +#endif +#ifdef CYBSP_LED_SLD4 +/** Slider LED 4 \def CYBSP_LED_SLD4 + */ +#endif +#ifdef CYBSP_LED_SLD5 +/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 + */ +#endif +#ifdef CYBSP_LED_BTN0 +/** Button LED 0 \def CYBSP_LED_BTN0 + */ +#endif +#ifdef CYBSP_LED_BTN1 +/** Button LED 1 \def CYBSP_LED_BTN1 + */ +#endif +#ifdef CYBSP_LED_BTN2 +/** Button LED 2 \def CYBSP_LED_BTN2 + */ +#endif + +/** \} group_bsp_pins_led */ +#endif // defined(CYBSP_USER_LED) + +#if defined(CYBSP_USER_BTN) +/** + * \addtogroup group_bsp_pins_btn Button Pins + * \{ + * Pins connected to user buttons on the board. + */ + +#ifdef CYBSP_SW1 +/** Switch 1 \def CYBSP_SW1 + */ +#endif +#ifdef CYBSP_SW2 +/** Switch 2 \def CYBSP_SW2 + */ +#endif +#ifdef CYBSP_SW3 +/** Switch 3 \def CYBSP_SW3 + */ +#endif +#ifdef CYBSP_SW4 +/** Switch 4 \def CYBSP_SW4 + */ +#endif +#ifdef CYBSP_USER_BTN +/** User Button 1 \def CYBSP_USER_BTN + */ +#endif +#ifdef CYBSP_USER_BTN1 +/** User Button 1 \def CYBSP_USER_BTN1 + */ +#endif +#ifdef CYBSP_USER_BTN2 +/** User Button 2 \def CYBSP_USER_BTN2 + */ +#endif +#ifdef CYBSP_POTENTIOMETER_INPUT +/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT + */ +#endif + +/** \} group_bsp_pins_btn */ +#endif // defined(CYBSP_USER_BTN) + +#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) +/** + * \addtogroup group_bsp_pins_comm Communication Pins + * \{ + * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...) + */ + +#ifdef CYBSP_DEBUG_UART_RX +/** Pin: UART RX \def CYBSP_DEBUG_UART_RX + */ +#endif +#ifdef CYBSP_DEBUG_UART_TX +/** Pin: UART TX \def CYBSP_DEBUG_UART_TX + */ +#endif +#ifdef CYBSP_I2C_SCL +/** Pin: I2C SCL \def CYBSP_I2C_SCL + */ +#endif +#ifdef CYBSP_I2C_SDA +/** Pin: I2C SDA \def CYBSP_I2C_SDA + */ +#endif +#ifdef CYBSP_SWDIO +/** Pin: SWDIO \def CYBSP_SWDIO + */ +#endif +#ifdef CYBSP_SWDCK +/** Pin: SWDCK \def CYBSP_SWDCK + */ +#endif +#ifdef CYBSP_SPI_MOSI +/** Pin: SPI MOSI \def CYBSP_SPI_MOSI + */ +#endif +#ifdef CYBSP_SPI_MISO +/** Pin: SPI MISO \def CYBSP_SPI_MISO + */ +#endif +#ifdef CYBSP_SPI_CLK +/** Pin: SPI CLK \def CYBSP_SPI_CLK + */ +#endif +#ifdef CYBSP_SPI_CS +/** Pin: SPI CS \def CYBSP_SPI_CS + */ +#endif +#ifdef CYBSP_SWO +/** Pin: SWO \def CYBSP_SWO + */ +#endif +#ifdef CYBSP_QSPI_SS +/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS + */ +#endif +#ifdef CYBSP_QSPI_D3 +/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 + */ +#endif +#ifdef CYBSP_QSPI_D2 +/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 + */ +#endif +#ifdef CYBSP_QSPI_D1 +/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 + */ +#endif +#ifdef CYBSP_QSPI_D0 +/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 + */ +#endif +#ifdef CYBSP_QSPI_SCK +/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D0 +/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D1 +/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D2 +/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D3 +/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CMD +/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CLK +/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK + */ +#endif +#ifdef CYBSP_WIFI_WL_REG_ON +/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON + */ +#endif +#ifdef CYBSP_WIFI_HOST_WAKE +/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE + */ + +/** WiFi host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** WiFi host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +#endif +#ifdef CYBSP_BT_UART_RX +/** Pin: BT UART RX \def CYBSP_BT_UART_RX + */ +#endif +#ifdef CYBSP_BT_UART_TX +/** Pin: BT UART TX \def CYBSP_BT_UART_TX + */ +#endif +#ifdef CYBSP_BT_UART_RTS +/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS + */ +#endif +#ifdef CYBSP_BT_UART_CTS +/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS + */ +#endif +#ifdef CYBSP_BT_POWER +/** Pin: BT Power \def CYBSP_BT_POWER + */ +#endif +#ifdef CYBSP_BT_HOST_WAKE +/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE + */ +/** BT host-wake GPIO drive mode */ +#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) +/** BT host wake IRQ event */ +#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) +#endif +#ifdef CYBSP_BT_DEVICE_WAKE +/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE + */ +/** BT device wakeup GPIO drive mode */ +#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) +/** BT device wakeup polarity */ +#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) +#endif +#ifdef CYBSP_PDM_CLK +/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK + */ +#endif +#ifdef CYBSP_PDM_DATA +/** Pin PDM PCM DATA \def CYBSP_PDM_DATA + */ +#endif +#ifdef CYBSP_I2S_MCLK +/** Pin: I2S MCLK \def CYBSP_I2S_MCLK + */ +#endif +#ifdef CYBSP_I2S_TX_SCK +/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK + */ +#endif +#ifdef CYBSP_I2S_TX_WS +/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS + */ +#endif +#ifdef CYBSP_I2S_TX_DATA +/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA + */ +#endif +#ifdef CYBSP_I2S_RX_SCK +/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK + */ +#endif +#ifdef CYBSP_I2S_RX_WS +/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS + */ +#endif +#ifdef CYBSP_I2S_RX_DATA +/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA + */ +#endif +#ifdef CYBSP_DEBUG_UART_RTS +/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS + */ +#endif +#ifdef CYBSP_DEBUG_UART_CTS +/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS + */ +#endif +#ifdef CYBSP_UART_RX +/** Pin: UART RX \def CYBSP_UART_RX + */ +#endif +#ifdef CYBSP_UART_TX +/** Pin: UART TX \def CYBSP_UART_TX + */ +#endif +#ifdef CYBSP_TDO_SWO +/** Pin: \def CYBSP_TDO_SWO + */ +#endif +#ifdef CYBSP_TMS_SWDIO +/** Pin: \def CYBSP_TMS_SWDIO + */ +#endif +#ifdef CYBSP_SWCLK +/** Pin: \def CYBSP_SWCLK + */ +#endif + +/** \} group_bsp_pins_comm */ +#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) + +#if defined(CYBSP_A0) +/** + * \addtogroup group_bsp_pins_arduino Arduino Header Pins + * \{ + * Pins mapped to the Arduino header on the board. + */ + +#ifdef CYBSP_A0 +/** Arduino A0 \def CYBSP_A0 + */ +#endif +#ifdef CYBSP_A1 +/** Arduino A1 \def CYBSP_A1 + */ +#endif +#ifdef CYBSP_A2 +/** Arduino A2 \def CYBSP_A2 + */ +#endif +#ifdef CYBSP_A3 +/** Arduino A3 \def CYBSP_A3 + */ +#endif +#ifdef CYBSP_A4 +/** Arduino A4 \def CYBSP_A4 + */ +#endif +#ifdef CYBSP_A5 +/** Arduino A5 \def CYBSP_A5 + */ +#endif +#ifdef CYBSP_D0 +/** Arduino D0 \def CYBSP_D0 + */ +#endif +#ifdef CYBSP_D1 +/** Arduino D1 \def CYBSP_D1 + */ +#endif +#ifdef CYBSP_D2 +/** Arduino D2 \def CYBSP_D2 + */ +#endif +#ifdef CYBSP_D3 +/** Arduino D3 \def CYBSP_D3 + */ +#endif +#ifdef CYBSP_D4 +/** Arduino D4 \def CYBSP_D4 + */ +#endif +#ifdef CYBSP_D5 +/** Arduino D5 \def CYBSP_D5 + */ +#endif +#ifdef CYBSP_D6 +/** Arduino D6 \def CYBSP_D6 + */ +#endif +#ifdef CYBSP_D7 +/** Arduino D7 \def CYBSP_D7 + */ +#endif +#ifdef CYBSP_D8 +/** Arduino D8 \def CYBSP_D8 + */ +#endif +#ifdef CYBSP_D9 +/** Arduino D9 \def CYBSP_D9 + */ +#endif +#ifdef CYBSP_D10 +/** Arduino D10 \def CYBSP_D10 + */ +#endif +#ifdef CYBSP_D11 +/** Arduino D11 \def CYBSP_D11 + */ +#endif +#ifdef CYBSP_D12 +/** Arduino D12 \def CYBSP_D12 + */ +#endif +#ifdef CYBSP_D13 +/** Arduino D13 \def CYBSP_D13 + */ +#endif +#ifdef CYBSP_D14 +/** Arduino D14 \def CYBSP_D14 + */ +#endif +#ifdef CYBSP_D15 +/** Arduino D15 \def CYBSP_D15 + */ +#endif + +/** \} group_bsp_pins_arduino */ +#endif // defined(CYBSP_A0) + +#if defined(CYBSP_J2_1) +/** + * \addtogroup group_bsp_pins_j2 J2 Header Pins + * \{ + * Pins mapped to the J2 header on the board. + */ + +#ifdef CYBSP_J2_1 +/** Cypress J2 Header pin 1 \def CYBSP_J2_1 + */ +#endif +#ifdef CYBSP_J2_2 +/** Cypress J2 Header pin 2 \def CYBSP_J2_2 + */ +#endif +#ifdef CYBSP_J2_3 +/** Cypress J2 Header pin 3 \def CYBSP_J2_3 + */ +#endif +#ifdef CYBSP_J2_4 +/** Cypress J2 Header pin 4 \def CYBSP_J2_4 + */ +#endif +#ifdef CYBSP_J2_5 +/** Cypress J2 Header pin 5 \def CYBSP_J2_5 + */ +#endif +#ifdef CYBSP_J2_7 +/** Cypress J2 Header pin 7 \def CYBSP_J2_7 + */ +#endif +#ifdef CYBSP_J2_8 +/** Cypress J2 Header pin 8 \def CYBSP_J2_8 + */ +#endif +#ifdef CYBSP_J2_9 +/** Cypress J2 Header pin 9 \def CYBSP_J2_9 + */ +#endif +#ifdef CYBSP_J2_10 +/** Cypress J2 Header pin 10 \def CYBSP_J2_10 + */ +#endif +#ifdef CYBSP_J2_11 +/** Cypress J2 Header pin 11 \def CYBSP_J2_11 + */ +#endif +#ifdef CYBSP_J2_12 +/** Cypress J2 Header pin 12 \def CYBSP_J2_12 + */ +#endif +#ifdef CYBSP_J2_13 +/** Cypress J2 Header pin 13 \def CYBSP_J2_13 + */ +#endif +#ifdef CYBSP_J2_15 +/** Cypress J2 Header pin 15 \def CYBSP_J2_15 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_6 +/** Cypress J2 Header pin 6 \def CYBSP_J2_6 + */ +#endif +#ifdef CYBSP_J2_17 +/** Cypress J2 Header pin 17 \def CYBSP_J2_17 + */ +#endif +#ifdef CYBSP_J2_18 +/** Cypress J2 Header pin 18 \def CYBSP_J2_18 + */ +#endif +#ifdef CYBSP_J2_19 +/** Cypress J2 Header pin 19 \def CYBSP_J2_19 + */ +#endif +#ifdef CYBSP_J2_20 +/** Cypress J2 Header pin 20 \def CYBSP_J2_20 + */ +#endif +#ifdef CYBSP_J2_14 +/** Cypress J2 Header pin 14 \def CYBSP_J2_14 + */ +#endif + +/** \} group_bsp_pins_j2 */ +#endif // defined(CYBSP_J2_1) + +#if defined(CYBSP_J6_1) +/** + * \addtogroup group_bsp_pins_j6 J6 Header Pins + * \{ + * Pins mapped to the J6 header on the board. + */ + +#ifdef CYBSP_J6_1 +/** Cypress J6 Header pin 1 \def CYBSP_J6_1 + */ +#endif +#ifdef CYBSP_J6_2 +/** Cypress J6 Header pin 2 \def CYBSP_J6_2 + */ +#endif +#ifdef CYBSP_J6_3 +/** Cypress J6 Header pin 3 \def CYBSP_J6_3 + */ +#endif +#ifdef CYBSP_J6_4 +/** Cypress J6 Header pin 4 \def CYBSP_J6_4 + */ +#endif +#ifdef CYBSP_J6_5 +/** Cypress J6 Header pin 5 \def CYBSP_J6_5 + */ +#endif +#ifdef CYBSP_J6_6 +/** Cypress J6 Header pin 6 \def CYBSP_J6_6 + */ +#endif +#ifdef CYBSP_J6_7 +/** Cypress J6 Header pin 7 \def CYBSP_J6_7 + */ +#endif +#ifdef CYBSP_J6_8 +/** Cypress J6 Header pin 8 \def CYBSP_J6_8 + */ +#endif +#ifdef CYBSP_J6_9 +/** Cypress J6 Header pin 9 \def CYBSP_J6_9 + */ +#endif +#ifdef CYBSP_J6_10 +/** Cypress J6 Header pin 10 \def CYBSP_J6_10 + */ +#endif +#ifdef CYBSP_J6_11 +/** Cypress J6 Header pin 11 \def CYBSP_J6_11 + */ +#endif +#ifdef CYBSP_J6_12 +/** Cypress J6 Header pin 12 \def CYBSP_J6_12 + */ +#endif +#ifdef CYBSP_J6_13 +/** Cypress J6 Header pin 13 \def CYBSP_J6_13 + */ +#endif +#ifdef CYBSP_J6_14 +/** Cypress J6 Header pin 14 \def CYBSP_J6_14 + */ +#endif +#ifdef CYBSP_J6_15 +/** Cypress J6 Header pin 15 \def CYBSP_J6_15 + */ +#endif +#ifdef CYBSP_J6_16 +/** Cypress J6 Header pin 16 \def CYBSP_J6_16 + */ +#endif + +/** \} group_bsp_pins_j6 */ +#endif // defined(CYBSP_J6_1) + +#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) +/** + * \addtogroup group_bsp_pins_capsense Capsense + * \{ + * Pins connected to CapSense sensors on the board. + */ + +#ifdef CYBSP_CSD_TX +/** Pin: CapSesnse TX \def CYBSP_CSD_TX + */ +#endif +#ifdef CYBSP_CINA +/** Pin: CapSesnse CINA \def CYBSP_CINA + */ +#endif +#ifdef CYBSP_CINTA +/** Pin: CapSesnse CINTA \def CYBSP_CINTA + */ +#endif +#ifdef CYBSP_CINB +/** Pin: CapSesnse CINB \def CYBSP_CINB + */ +#endif +#ifdef CYBSP_CINTB +/** Pin: CapSesnse CINTB \def CYBSP_CINTB + */ +#endif +#ifdef CYBSP_CMOD +/** Pin: CapSesnse CMOD \def CYBSP_CMOD + */ +#endif +#ifdef CYBSP_CSD_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 + */ +#endif +#ifdef CYBSP_CSD_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 + */ +#endif +#ifdef CYBSP_CSD_SLD0 +/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 + */ +#endif +#ifdef CYBSP_CSD_SLD1 +/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 + */ +#endif +#ifdef CYBSP_CSD_SLD2 +/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 + */ +#endif +#ifdef CYBSP_CSD_SLD3 +/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 + */ +#endif +#ifdef CYBSP_CSD_SLD4 +/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4 + */ +#endif +#ifdef CYBSP_CSD_SLD5 +/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5 + */ +#endif +#ifdef CYBSP_CSX_BTN_TX +/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX + */ +#endif +#ifdef CYBSP_CSX_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0 + */ +#endif +#ifdef CYBSP_CSX_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1 + */ +#endif +#ifdef CYBSP_CSX_BTN2 +/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2 + */ +#endif + +/** \} group_bsp_pins_capsense */ +#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) + +#if defined(CYBSP_WCO_IN) +/** + * \addtogroup group_bsp_pins_wco WCO + * \{ + * Pins connected to the WCO on the board. + */ +#ifdef CYBSP_WCO_IN +/** Pin: WCO input \def CYBSP_WCO_IN + */ +#endif +#ifdef CYBSP_WCO_OUT +/** Pin: WCO output \def CYBSP_WCO_OUT + */ +#endif + +/** \} group_bsp_pins_wco */ +#endif // defined(CYBSP_WCO_IN) + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h old mode 100644 new mode 100755 index 9f0ff31dec..4f704a2845 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h @@ -1,73 +1,34 @@ -/***************************************************************************//** -* \file CYSBSYSKIT-01/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CYSBSYSKIT-01 kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif +#include "cybsp_doc.h" #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - + * \addtogroup group_bsp_pin_state Pin States + * \{ + * Macros to abstract out whether the LEDs & Buttons are wired high or active low. + */ /** Pin state for the LED on. */ #ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) @@ -76,7 +37,6 @@ extern "C" { #ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) #endif - /** Pin state for when a button is pressed. */ #ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) @@ -85,229 +45,8 @@ extern "C" { #ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) #endif - /** \} group_bsp_pin_state */ -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** BSP user LED1 reference designator to pin mapping */ -#ifndef CYBSP_USER_LED1 -#define CYBSP_USER_LED1 (P11_1) -#endif - -/** \} group_bsp_pins_led */ - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** BSP user button reference designator to pin mapping */ -#ifndef CYBSP_USER_BTN -#define CYBSP_USER_BTN (P0_4) -#endif - -/** \} group_bsp_pins_btn */ - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: UART RX */ -#ifndef CYBSP_DEBUG_UART_RX -#define CYBSP_DEBUG_UART_RX (P5_4) -#endif -/** Pin: UART TX */ -#ifndef CYBSP_DEBUG_UART_TX -#define CYBSP_DEBUG_UART_TX (P5_5) -#endif -/** Pin: UART_RTS */ -#ifndef CYBSP_DEBUG_UART_RTS -#define CYBSP_DEBUG_UART_RTS (P5_6) -#endif -/** Pin: UART_CTS */ -#ifndef CYBSP_DEBUG_UART_CTS -#define CYBSP_DEBUG_UART_CTS (P5_7) -#endif - -/** Pin: SWDIO */ -#ifndef CYBSP_SWDIO -#define CYBSP_SWDIO (P6_6) -#endif -/** Pin: SWDCK */ -#ifndef CYBSP_SWDCK -#define CYBSP_SWDCK (P6_7) -#endif - -/** Pin: QUAD SPI SS */ -#ifndef CYBSP_QSPI_SS -#define CYBSP_QSPI_SS (P11_2) -#endif -/** Pin: QUAD SPI D3 */ -#ifndef CYBSP_QSPI_D3 -#define CYBSP_QSPI_D3 (P11_3) -#endif -/** Pin: QUAD SPI D2 */ -#ifndef CYBSP_QSPI_D2 -#define CYBSP_QSPI_D2 (P11_4) -#endif -/** Pin: QUAD SPI D1 */ -#ifndef CYBSP_QSPI_D1 -#define CYBSP_QSPI_D1 (P11_5) -#endif -/** Pin: QUAD SPI D0 */ -#ifndef CYBSP_QSPI_D0 -#define CYBSP_QSPI_D0 (P11_6) -#endif -/** Pin: QUAD SPI SCK */ -#ifndef CYBSP_QSPI_SCK -#define CYBSP_QSPI_SCK (P11_7) -#endif - -/** Pin: I2C SCL */ -#ifndef CYBSP_I2C_SCL -#define CYBSP_I2C_SCL (P6_0) -#endif - -/** Pin: I2C SDA */ -#ifndef CYBSP_I2C_SDA -#define CYBSP_I2C_SDA (P6_1) -#endif - -/** Pin: SPI MOSI */ -#ifndef CYBSP_SPI_MOSI -#define CYBSP_SPI_MOSI (P5_0) -#endif -/** Pin: SPI MISO */ -#ifndef CYBSP_SPI_MISO -#define CYBSP_SPI_MISO (P5_1) -#endif -/** Pin: SPI CLK */ -#ifndef CYBSP_SPI_CLK -#define CYBSP_SPI_CLK (P5_2) -#endif -/** Pin: SPI CS */ -#ifndef CYBSP_SPI_CS -#define CYBSP_SPI_CS (P5_3) -#endif - -/** Pin: FEATHER UART RX */ -#ifndef CYBSP_FEATHER_UART_RX -#define CYBSP_FEATHER_UART_RX (P6_4) -#endif -/** Pin: FEATHER UART TX */ -#ifndef CYBSP_FEATHER_UART_TX -#define CYBSP_FEATHER_UART_TX (P6_5) -#endif - -/** \} group_bsp_pins_comm */ - -/** -* \addtogroup group_bsp_pins_therm Thermister Pins -* \{ -*/ - -/** Pin: Thermister VDD */ -#ifndef CYBSP_THERM_VDD -#define CYBSP_THERM_VDD (P10_6) -#endif -/** Pin: Thermister output */ -#ifndef CYBSP_THERM_OUT -#define CYBSP_THERM_OUT (P10_7) -#endif -/** \} group_bsp_pins_therm */ - -/** -* \addtogroup group_bsp_pins_eco ECO Pins -* \{ -*/ - -/** Pin: ECO IN */ -#ifndef CYBSP_ECO_IN -#define CYBSP_ECO_IN (P12_6) -#endif -/** Pin: ECO IN */ -#ifndef CYBSP_ECO_OUT -#define CYBSP_ECO_OUT (P12_7) -#endif - -/** \} group_bsp_pins_eco */ - -/** -* \addtogroup group_bsp_pins_feather Feather Header Pins -* \{ -*/ - -/** GPIOA0 */ -#ifndef CYBSP_GPIOA0 -#define CYBSP_GPIOA0 (P10_0) -#endif -/** GPIOA1 */ -#ifndef CYBSP_GPIOA1 -#define CYBSP_GPIOA1 (P10_1) -#endif -/** GPIOA2 */ -#ifndef CYBSP_GPIOA2 -#define CYBSP_GPIOA2 (P10_2) -#endif -/** GPIOA3 */ -#ifndef CYBSP_GPIOA3 -#define CYBSP_GPIOA3 (P10_3) -#endif -/** GPIOA4 */ -#ifndef CYBSP_GPIOA4 -#define CYBSP_GPIOA4 (P10_4) -#endif -/** GPIOA5 */ -#ifndef CYBSP_GPIOA5 -#define CYBSP_GPIOA5 (P10_5) -#endif -/** GPIO5 */ -#ifndef CYBSP_GPIO5 -#define CYBSP_GPIO5 (P8_4) -#endif -/** GPIO6 */ -#ifndef CYBSP_GPIO6 -#define CYBSP_GPIO6 (P9_7) -#endif -/** GPIO9 */ -#ifndef CYBSP_GPIO9 -#define CYBSP_GPIO9 (P9_4) -#endif -/** GPIO10 */ -#ifndef CYBSP_GPIO10 -#define CYBSP_GPIO10 (P9_3) -#endif -/** GPIO11 */ -#ifndef CYBSP_GPIO11 -#define CYBSP_GPIO11 (P9_2) -#endif -/** GPIO12 */ -#ifndef CYBSP_GPIO12 -#define CYBSP_GPIO12 (P9_1) -#endif -/** GPIO13 */ -#ifndef CYBSP_GPIO13 -#define CYBSP_GPIO13 (P9_0) -#endif - -/** \} group_bsp_pins_feather */ - -/** \} group_bsp_pins */ - -#endif /* defined(CY_USING_HAL) */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c deleted file mode 100644 index 0a18f50a4d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ /dev/null @@ -1,552 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm4.c -* \version 2.60 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default SlowClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) - -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ - -/* SCB->CPACR */ -#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) -#define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; - -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* \cond -* Initializes the system: -* - Restores FLL registers to the default state for single core devices. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* \endcond -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - - Cy_SystemInit(); - SystemCoreClockUpdate(); - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Allocate and initialize semaphores for the system operations. */ - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - #else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); - #endif /* (__CM0P_PRESENT) */ -#else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); -#endif /* __CM0P_PRESENT */ - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 - }; - - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) - { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } - } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitFpuEnable -****************************************************************************//** -* -* Enables the FPU if it is used. The function is called from the startup file. -* -*******************************************************************************/ -void Cy_SystemInitFpuEnable(void) -{ - #if defined (__FPU_USED) && (__FPU_USED == 1U) - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; - __DSB(); - __ISB(); - Cy_SysLib_ExitCriticalSection(interruptState); - #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ -} - - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm4 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm4(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h deleted file mode 100644 index 423361f58a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h +++ /dev/null @@ -1,680 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6.h -* \version 2.60 -* -* \brief Device system header file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef _SYSTEM_PSOC6_H_ -#define _SYSTEM_PSOC6_H_ - -/** -* \addtogroup group_system_config -* \{ -* Provides device startup, system configuration, and linker script files. -* The system startup provides the followings features: -* - See \ref group_system_config_device_initialization for the: -* * \ref group_system_config_dual_core_device_initialization -* * \ref group_system_config_single_core_device_initialization -* - \ref group_system_config_device_memory_definition -* - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps -* - \ref group_system_config_default_handlers -* - \ref group_system_config_device_vector_table -* - \ref group_system_config_cm4_functions -* -* \section group_system_config_configuration Configuration Considerations -* -* \subsection group_system_config_device_memory_definition Device Memory Definition -* The flash and RAM allocation for each CPU is defined by the linker scripts. -* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. -* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. -* For Single-Core devices the system reserves additional 80 bytes of RAM. -* Using the reserved memory area for other purposes will lead to unexpected behavior. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see warnings during the build process. To eliminate build -* warnings in your project, you can simply comment out or remove the relevant -* code in the linker file. -* -* ARM GCC\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 -* \endcode -* - 'xx_cm4_dual.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* ARM MDK\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see the warnings during the build process: -* L6314W (no section matches pattern) and/or L6329W -* (pattern only matches removed unused sections). In your project, you can -* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -* the linker. You can also comment out or remove the relevant code in the linker -* file. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 -* \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* IAR\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; -* \endcode -* - 'xx_cm4_dual.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* \subsection group_system_config_device_initialization Device Initialization -* After a power-on-reset (POR), the boot process is handled by the boot code -* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot -* code passes the control to the Cortex-M0+ startup code located in flash. -* -* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices -* The Cortex-M0+ startup code performs the device initialization by a call to -* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled -* by default. Enable the core using the \ref Cy_SysEnableCM4() function. -* See \ref group_system_config_cm4_functions for more details. -* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. -* The function has a separate implementation on each core. -* Both function implementations unlock and disable the WDT. -* Therefore enable the WDT after both cores have been initialized. -* -* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices -* The Cortex-M0+ core is not user-accessible on these devices. In this case the -* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. -* -* \subsection group_system_config_heap_stack_config Heap and Stack Configuration -* There are two ways to adjust heap and stack configurations: -* -# Editing source code files -* -# Specifying via command line -* -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. -* -* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* Change the heap and stack sizes by modifying the following lines:\n -* \code .equ Stack_Size, 0x00001000 \endcode -* \code .equ Heap_Size, 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode -* -* \subsubsection group_system_config_heap_stack_config_iar IAR -* - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the -* linker (including quotation marks):\n -* \code --define_symbol __STACK_SIZE=0x000000400 \endcode -* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode -* -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* -* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition -* The default interrupt handler functions are defined as weak functions to a dummy -* handler in the startup file. The naming convention for the interrupt handler names -* is \_IRQHandler. A default interrupt handler can be overwritten in -* user code by defining the handler function using the same name. For example: -* \code -* void scb_0_interrupt_IRQHandler(void) -*{ -* ... -*} -* \endcode -* -* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM -* This process uses memory sections defined in the linker script. The startup -* code actually defines the contents of the vector table and performs the copy. -* \subsubsection group_system_config_device_vector_table_gcc ARM GCC -* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* It defines sections and locations in memory.\n -* Copy interrupt vectors from flash to RAM: \n -* From: \code LONG (__Vectors) \endcode -* To: \code LONG (__ram_vectors_start__) \endcode -* Size: \code LONG (__Vectors_End - __Vectors) \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table -* (RESET_RAM) shall be first in the RAM section.\n -* RESET_RAM represents the vector table. It is defined in the assembler startup -* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \subsubsection group_system_config_device_vector_table_iar IAR -* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* This file defines the .intvec_ram section and its location. -* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* -* \section group_system_config_MISRA MISRA Compliance -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
-* -* \section group_system_config_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n -* Removed $Sub$$main symbol for ARM MDK compiler. -* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n -* Added note about WDT disabling by SystemInit() function. -* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. -* Single core device support. -*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n -* Renamed 'wflash' memory region to 'em_eeprom'. -* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
-* -* -* \defgroup group_system_config_macro Macro -* \{ -* \defgroup group_system_config_system_macro System -* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status -* \defgroup group_system_config_user_settings_macro User Settings -* \} -* \defgroup group_system_config_functions Functions -* \{ -* \defgroup group_system_config_system_functions System -* \defgroup group_system_config_cm4_functions Cortex-M4 Control -* \} -* \defgroup group_system_config_globals Global Variables -* -* \} -*/ - -/** -* \addtogroup group_system_config_system_functions -* \{ -* \details -* The following system functions implement CMSIS Core functions. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* \} -*/ - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* -* Include files -*******************************************************************************/ -#include - - -/******************************************************************************* -* Global preprocessor symbols/macros ('define') -*******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) - #define CY_SYSTEM_CPU_CM0P 1UL -#else - #define CY_SYSTEM_CPU_CM0P 0UL -#endif - -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - - -/******************************************************************************* -* -* START OF USER SETTINGS HERE -* =========================== -* -* All lines with '<<<' can be set by user. -* -*******************************************************************************/ - -/** -* \addtogroup group_system_config_user_settings_macro -* \{ -*/ - -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - - -/***************************************************************************//** -* \brief Start address of the Cortex-M4 application ([address]UL) -* (USER SETTING) -*******************************************************************************/ -#if !defined (CY_CORTEX_M4_APPL_ADDR) - #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ -#endif /* (CY_CORTEX_M4_APPL_ADDR) */ - - -/***************************************************************************//** -* \brief IPC Semaphores allocation ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ - - -/***************************************************************************//** -* \brief IPC Pipe definitions ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ - - -/******************************************************************************* -* -* END OF USER SETTINGS HERE -* ========================= -* -*******************************************************************************/ - -/** \} group_system_config_user_settings_macro */ - - -/** -* \addtogroup group_system_config_system_macro -* \{ -*/ - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M0+ startup driver identifier */ - #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - -#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M4 startup driver identifier */ - #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ - -/** \} group_system_config_system_macro */ - - -/** -* \addtogroup group_system_config_system_functions -* \{ -*/ -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); -/** \} group_system_config_system_functions */ - - -/** -* \addtogroup group_system_config_cm4_functions -* \{ -*/ -extern uint32_t Cy_SysGetCM4Status(void); -extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); -extern void Cy_SysDisableCM4(void); -extern void Cy_SysRetainCM4(void); -extern void Cy_SysResetCM4(void); -/** \} group_system_config_cm4_functions */ - - -/** \cond */ -extern void Default_Handler (void); - -void Cy_SysIpcPipeIsrCm0(void); -void Cy_SysIpcPipeIsrCm4(void); - -extern void Cy_SystemInit(void); -extern void Cy_SystemInitFpuEnable(void); - -extern uint32_t cy_delayFreqHz; -extern uint32_t cy_delayFreqKhz; -extern uint8_t cy_delayFreqMhz; -extern uint32_t cy_delay32kMs; -/** \endcond */ - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/** -* \addtogroup group_system_config_cm4_status_macro -* \{ -*/ -#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ -#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ -#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ -#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ -/** \} group_system_config_cm4_status_macro */ - -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - - -/******************************************************************************* -* IPC Configuration -* ========================= -*******************************************************************************/ -/* IPC CY_PIPE default configuration */ -#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) - -#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ - -#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) - - -/******************************************************************************/ -/* - * The System pipe configuration defines the IPC channel number, interrupt - * number, and the pipe interrupt mask for the endpoint. - * - * The format of the endPoint configuration - * Bits[31:16] Interrupt Mask - * Bits[15:8 ] IPC interrupt - * Bits[ 7:0 ] IPC channel - */ - -/* System Pipe addresses */ -/* CyPipe defines */ - -#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) - -#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) - -/******************************************************************************/ - - -/** \addtogroup group_system_config_globals -* \{ -*/ - -extern uint32_t SystemCoreClock; -extern uint32_t cy_BleEcoClockFreqHz; -extern uint32_t cy_Hfclk0FreqHz; -extern uint32_t cy_PeriClkFreqHz; - -/** \} group_system_config_globals */ - - - -/** \cond INTERNAL */ -/******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must -* not be used in new projects -*******************************************************************************/ - -/* BWC defines for functions related to enter/exit critical section */ -#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection -#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection -#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) -#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) - -/** \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_PSOC6_H_ */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/version.xml new file mode 100755 index 0000000000..247f9c06c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/version.xml @@ -0,0 +1 @@ +2.1.0.21729