diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct index b3c7d855db..ce41a9ad0e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data + RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct index b3c7d855db..ce41a9ad0e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data + RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld index a354adedea..e1c8092a46 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld @@ -30,8 +30,8 @@ MEMORY } /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG */ -__vector_size = 0xDC; + * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 4(8-byte aligned) bytes for EFM32GG */ +__vector_size = 0xE0; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -119,7 +119,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -137,7 +137,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -160,23 +160,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -184,7 +184,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -206,11 +206,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf index f60b984a8c..e57dada035 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf @@ -11,8 +11,8 @@ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000DB; -define symbol __ICFEDIT_region_RAM_start__ = 0x200000DC; +define symbol __NVIC_end__ = 0x200000DF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000E0; define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld index 86bfde4851..699f40b12a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -151,23 +151,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct index 8eed05311d..b31dbbe37f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x20000094 0x00001F6C { ; RW data + RW_IRAM1 0x20000098 0x00001F68 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld index e11addfa54..ffca89e369 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld @@ -25,8 +25,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+21) * sizeof(uint32_t) = 148 bytes for EFM32HG */ -__vector_size = 0x94; + * 0x20000000. We need (16+21) * sizeof(uint32_t) = 148+4(8-byte aligned) bytes for EFM32HG */ +__vector_size = 0x98; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -152,23 +152,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -176,7 +176,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -184,11 +184,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf index 18add8aec9..22c8439dfe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf @@ -11,8 +11,8 @@ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000093; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000094; +define symbol __NVIC_end__ = 0x20000097; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000098; define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld index 910d54a82a..3ccec3d81f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld @@ -112,7 +112,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -130,7 +130,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -151,23 +151,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld index c8b31ea93b..cc78895a91 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -151,23 +151,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct index aa5994119b..b06400e44d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data + RW_IRAM1 0x20000110 0x0003FEF0 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld index 5cf15baf95..6ddce74288 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld @@ -25,8 +25,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ -__vector_size = 0x10C; + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 + 4 (8-byte aligned) bytes for EFM32PG */ +__vector_size = 0x110; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -154,20 +154,20 @@ SECTIONS . = ALIGN (4); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf index 77502fddeb..2a914564f2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf @@ -12,8 +12,8 @@ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000010B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __NVIC_end__ = 0x2000010F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000110; define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00040000-1); /*-Sizes-*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld index e3467258ac..61dd3871f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -152,23 +152,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -176,7 +176,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -184,11 +184,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct index 0178711436..e3d88fc389 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x2000008C 0x00000F74 { ; RW data + RW_IRAM1 0x20000090 0x00000F70 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld index 1d10c10fd4..22568ec19d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld @@ -25,8 +25,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+19) * sizeof(uint32_t) = 140 bytes for EFM32ZG */ -__vector_size = 0x8C; + * 0x20000000. We need (16+19) * sizeof(uint32_t) = 140 + 4(8-byte aligned) bytes for EFM32ZG */ +__vector_size = 0x90; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -152,23 +152,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -176,7 +176,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -184,11 +184,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf index 5cabed38b6..2ece65a90e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf @@ -11,8 +11,8 @@ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000008B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000008C; +define symbol __NVIC_end__ = 0x2000008F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000090; define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld index 3532c44646..ad8928f16d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -151,23 +151,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct index aa5994119b..b06400e44d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct @@ -17,7 +17,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data + RW_IRAM1 0x20000110 0x0003FEF0 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld index 4444a7ea10..8ab03636c6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld @@ -25,8 +25,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ -__vector_size = 0x10C; + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 + 4(8-byte aligned) bytes for EFM32PG */ +__vector_size = 0x110; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -113,7 +113,7 @@ SECTIONS /* .copy.table : { - . = ALIGN(4); + . = ALIGN(8); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) @@ -131,7 +131,7 @@ SECTIONS /* .zero.table : { - . = ALIGN(4); + . = ALIGN(8); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) @@ -151,23 +151,23 @@ SECTIONS PROVIDE( __end_vector_table__ = .); *(vtable) *(.data*) - . = ALIGN (4); + . = ALIGN (8); *(.ram) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -175,7 +175,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; @@ -183,11 +183,11 @@ SECTIONS .bss : { - . = ALIGN(4); + . = ALIGN(8); __bss_start__ = .; *(.bss*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end__ = .; } > RAM diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf index b13edd25a8..fd26aeb572 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf @@ -11,8 +11,8 @@ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000010B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __NVIC_end__ = 0x2000010F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000110; define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/