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Merge pull request #8602 from artokin/sync_rf_drivers 

Sync 802.15.4 RF drivers
pull/8681/head
Cruz Monrreal 2018-11-08 10:06:27 -06:00 committed by GitHub
parent 937d68f0fd d5df64299a
commit 760b0740a9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 902 additions and 1046 deletions
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4
components/802.15.4_RF/atmel-rf-driver/mbed_lib.json
View File

@ -24,6 +24,10 @@
"provide-default": {
"help": "Provide default NanostackRfpy. [true/false]",
"value": false
},
"irq-thread-stack-size": {
"help": "The stack size of the Thread serving the Atmel RF interrupts",
"value": 1024
}
},
"target_overrides": {

432
components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp
View File

@ -50,25 +50,22 @@
#define RFF_TX 0x04
#define RFF_CCA 0x08
typedef enum
{
typedef enum {
RF_MODE_NORMAL = 0,
RF_MODE_SNIFFER = 1,
RF_MODE_ED = 2
}rf_mode_t;
} rf_mode_t;
/*Atmel RF Part Type*/
typedef enum
{
typedef enum {
ATMEL_UNKNOW_DEV = 0,
ATMEL_AT86RF212,
ATMEL_AT86RF231, // No longer supported (doesn't give ED+status on frame read)
ATMEL_AT86RF233
}rf_trx_part_e;
} rf_trx_part_e;
/*Atmel RF states*/
typedef enum
{
typedef enum {
NOP = 0x00,
BUSY_RX = 0x01,
BUSY_TX = 0x02,
@ -83,7 +80,7 @@ typedef enum
RX_AACK_ON = 0x16,
TX_ARET_ON = 0x19,
STATE_TRANSITION_IN_PROGRESS = 0x1F
}rf_trx_states_t;
} rf_trx_states_t;
static const uint8_t *rf_tx_data; // Points to Nanostack's buffer
static uint8_t rf_tx_length;
@ -156,7 +153,7 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state);
static void rf_init(void);
static int8_t rf_device_register(const uint8_t *mac_addr);
static void rf_device_unregister(void);
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol);
static void rf_cca_abort(void);
static void rf_calibration_cb(void);
static void rf_init_phy_mode(void);
@ -168,8 +165,8 @@ static void rf_cca_timer_start(uint32_t slots);
static uint8_t rf_scale_lqi(int8_t rssi);
static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr);
static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr);
static void rf_if_cca_timer_start(uint32_t slots);
static void rf_if_enable_promiscuous_mode(void);
@ -214,7 +211,7 @@ static void rf_if_spi_exchange_n(const void *tx, size_t tx_len, void *rx, size_t
static inline rf_trx_states_t rf_if_trx_status_from_full(uint8_t full_trx_status)
{
return (rf_trx_states_t) (full_trx_status & 0x1F);
return (rf_trx_states_t)(full_trx_status & 0x1F);
}
#ifdef MBED_CONF_RTOS_PRESENT
@ -273,7 +270,7 @@ RFBits::RFBits(PinName spi_mosi, PinName spi_miso,
SLP_TR(spi_slp),
IRQ(spi_irq)
#ifdef MBED_CONF_RTOS_PRESENT
,irq_thread(osPriorityRealtime, 1024)
, irq_thread(osPriorityRealtime, MBED_CONF_ATMEL_RF_IRQ_THREAD_STACK_SIZE, NULL, "atmel_irq_thread")
#endif
{
#ifdef MBED_CONF_RTOS_PRESENT
@ -313,7 +310,7 @@ static void rf_if_ack_timer_signal(void)
}
#endif
// *INDENT-OFF*
/* Delay functions for RF Chip SPI access */
#ifdef __CC_ARM
__asm static void delay_loop(uint32_t count)
@ -359,6 +356,7 @@ static void delay_loop(uint32_t count)
);
}
#endif
// *INDENT-ON*
static void delay_ns(uint32_t ns)
{
@ -379,7 +377,7 @@ static void delay_ns(uint32_t ns)
// t1 = 180ns, SEL falling edge to MISO active [SPI setup assumed slow enough to not need manual delay]
#define CS_SELECT() {rf->CS = 0; /* delay_ns(180); */}
// t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access
// t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access
#define CS_RELEASE() {delay_ns(250); rf->CS = 1; delay_ns(250);}
/*
@ -393,8 +391,7 @@ static rf_trx_part_e rf_radio_type_read(void)
{
rf_trx_part_e ret_val = ATMEL_UNKNOW_DEV;
switch (rf_part_num)
{
switch (rf_part_num) {
case PART_AT86RF212:
ret_val = ATMEL_AT86RF212;
break;
@ -419,9 +416,9 @@ static rf_trx_part_e rf_radio_type_read(void)
static void rf_if_ack_wait_timer_start(uint16_t slots)
{
#ifdef MBED_CONF_RTOS_PRESENT
rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots*50);
rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots * 50);
#else
rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots*50);
rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots * 50);
#endif
}
@ -435,9 +432,9 @@ static void rf_if_ack_wait_timer_start(uint16_t slots)
static void rf_if_calibration_timer_start(uint32_t slots)
{
#ifdef MBED_CONF_RTOS_PRESENT
rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots*50);
rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots * 50);
#else
rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots*50);
rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots * 50);
#endif
}
@ -451,9 +448,9 @@ static void rf_if_calibration_timer_start(uint32_t slots)
static void rf_if_cca_timer_start(uint32_t slots)
{
#ifdef MBED_CONF_RTOS_PRESENT
rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots*50);
rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots * 50);
#else
rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots*50);
rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots * 50);
#endif
}
@ -725,7 +722,7 @@ static void rf_if_write_rf_settings(void)
rf_part_num = rf_if_read_part_num();
rf_if_write_register(XAH_CTRL_0,0);
rf_if_write_register(XAH_CTRL_0, 0);
/* Auto CRC on, IRQ status shows unmasked only, TRX_STATUS output on all accesses */
rf_if_write_register(TRX_CTRL_1, TX_AUTO_CRC_ON | SPI_CMD_MODE_TRX_STATUS);
@ -738,18 +735,14 @@ static void rf_if_write_rf_settings(void)
rf_part_num = rf_if_read_register(PART_NUM);
/*Sub-GHz RF settings*/
if(rf_part_num == PART_AT86RF212)
{
if (rf_part_num == PART_AT86RF212) {
/*GC_TX_OFFS mode-dependent setting - OQPSK*/
rf_if_write_register(RF_CTRL_0, 0x32);
if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B)
{
if (rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B) {
/*TX Output Power setting - 0 dBm North American Band*/
rf_if_write_register(PHY_TX_PWR, 0x03);
}
else
{
} else {
/*TX Output Power setting - 0 dBm North American Band*/
rf_if_write_register(PHY_TX_PWR, 0x24);
}
@ -760,13 +753,12 @@ static void rf_if_write_rf_settings(void)
rf_rssi_base_val = -98;
}
/*2.4GHz RF settings*/
else
{
else {
#if 0
/* Disable power saving functions for now - can only impact reliability,
* and don't have any users demanding it. */
/*Set RPC register*/
rf_if_write_register(TRX_RPC, RX_RPC_CTRL|RX_RPC_EN|PLL_RPC_EN|XAH_TX_RPC_EN|IPAN_RPC_EN|TRX_RPC_RSVD_1);
rf_if_write_register(TRX_RPC, RX_RPC_CTRL | RX_RPC_EN | PLL_RPC_EN | XAH_TX_RPC_EN | IPAN_RPC_EN | TRX_RPC_RSVD_1);
#endif
/*PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s*/
rf_if_write_register(TRX_CTRL_2, RX_SAFE_MODE);
@ -836,12 +828,9 @@ static void rf_if_write_short_addr_registers(uint8_t *short_address)
static void rf_if_ack_pending_ctrl(uint8_t state)
{
rf_if_lock();
if(state)
{
if (state) {
rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD));
}
else
{
} else {
rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD));
}
rf_if_unlock();
@ -859,10 +848,11 @@ static uint8_t rf_if_last_acked_pending(void)
uint8_t last_acked_data_pending;
rf_if_lock();
if(rf_if_read_register(CSMA_SEED_1) & (1 << AACK_SET_PD))
if (rf_if_read_register(CSMA_SEED_1) & (1 << AACK_SET_PD)) {
last_acked_data_pending = 1;
else
} else {
last_acked_data_pending = 0;
}
rf_if_unlock();
return last_acked_data_pending;
@ -879,7 +869,7 @@ static void rf_if_calibration(void)
{
rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START);
/*Wait while calibration is running*/
while(rf_if_read_register(FTN_CTRL) & FTN_START);
while (rf_if_read_register(FTN_CTRL) & FTN_START);
}
/*
@ -907,8 +897,9 @@ static void rf_if_write_ieee_addr_registers(uint8_t *address)
uint8_t i;
uint8_t temp = IEEE_ADDR_0;
for(i=0; i<8; i++)
rf_if_write_register(temp++, address[7-i]);
for (i = 0; i < 8; i++) {
rf_if_write_register(temp++, address[7 - i]);
}
}
/*
@ -941,23 +932,23 @@ static uint8_t rf_if_read_rnd(void)
uint8_t temp;
uint8_t tmp_rpc_val = 0;
/*RPC must be disabled while reading the random number*/
if(rf_part_num == PART_AT86RF233)
{
if (rf_part_num == PART_AT86RF233) {
tmp_rpc_val = rf_if_read_register(TRX_RPC);
rf_if_write_register(TRX_RPC, RX_RPC_CTRL|TRX_RPC_RSVD_1);
rf_if_write_register(TRX_RPC, RX_RPC_CTRL | TRX_RPC_RSVD_1);
}
wait_ms(1);
temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6);
temp = ((rf_if_read_register(PHY_RSSI) >> 5) << 6);
wait_ms(1);
temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 4);
temp |= ((rf_if_read_register(PHY_RSSI) >> 5) << 4);
wait_ms(1);
temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 2);
temp |= ((rf_if_read_register(PHY_RSSI) >> 5) << 2);
wait_ms(1);
temp |= ((rf_if_read_register(PHY_RSSI)>>5));
temp |= ((rf_if_read_register(PHY_RSSI) >> 5));
wait_ms(1);
if(rf_part_num == PART_AT86RF233)
if (rf_part_num == PART_AT86RF233) {
rf_if_write_register(TRX_RPC, tmp_rpc_val);
}
return temp;
}
@ -1080,39 +1071,30 @@ static void rf_if_irq_task_process_irq(void)
static void rf_if_interrupt_handler(void)
#endif
{
static uint8_t last_is, last_ts;
uint8_t irq_status, full_trx_status;
uint8_t orig_xah_ctrl_1 = xah_ctrl_1;
/*Read and clear interrupt flag, and pick up trx_status*/
irq_status = rf_if_read_register_with_status(IRQ_STATUS, &full_trx_status);
uint8_t orig_flags = rf_flags;
/*Frame end interrupt (RX and TX)*/
if(irq_status & TRX_END)
{
if (irq_status & TRX_END) {
/*TX done interrupt*/
rf_trx_states_t trx_status = rf_if_trx_status_from_full(full_trx_status);
if(trx_status == PLL_ON || trx_status == TX_ARET_ON)
{
if (trx_status == PLL_ON || trx_status == TX_ARET_ON) {
rf_handle_tx_end(trx_status);
}
/*Frame received interrupt*/
else
{
else {
rf_handle_rx_end(trx_status);
}
}
if(irq_status & CCA_ED_DONE)
{
if (irq_status & CCA_ED_DONE) {
rf_handle_cca_ed_done(full_trx_status);
}
if (irq_status & TRX_UR)
{
tr_error("Radio underrun is %x->%x ts %x->%x fl %x->%x x1 %x", last_is, irq_status, last_ts, full_trx_status, orig_flags, rf_flags, orig_xah_ctrl_1);
if (irq_status & TRX_UR) {
// Here some counter could be used to monitor the underrun occurancy count.
// Do not print anything here!
}
last_is = irq_status;
last_ts = full_trx_status;
}
/*
@ -1205,18 +1187,14 @@ static int8_t rf_device_register(const uint8_t *mac_addr)
rf_init();
radio_type = rf_radio_type_read();
if(radio_type != ATMEL_UNKNOW_DEV)
{
if (radio_type != ATMEL_UNKNOW_DEV) {
/*Set pointer to MAC address*/
device_driver.PHY_MAC = (uint8_t *)mac_addr;
device_driver.driver_description = (char*)"ATMEL_MAC";
device_driver.driver_description = (char *)"ATMEL_MAC";
//Create setup Used Radio chips
if(radio_type == ATMEL_AT86RF212)
{
if (radio_type == ATMEL_AT86RF212) {
device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
}
else
{
} else {
device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
}
device_driver.phy_channel_pages = phy_channel_pages;
@ -1364,8 +1342,9 @@ static void rf_write_settings(void)
/*Set output power*/
rf_if_write_set_tx_power_register(radio_tx_power);
/*Initialise Antenna Diversity*/
if(rf_use_antenna_diversity)
if (rf_use_antenna_diversity) {
rf_if_write_antenna_diversity_settings();
}
rf_if_unlock();
}
@ -1376,20 +1355,18 @@ static void rf_write_settings(void)
*
* \return none
*/
static void rf_set_short_adr(uint8_t * short_address)
static void rf_set_short_adr(uint8_t *short_address)
{
rf_if_lock();
/*Wake up RF if sleeping*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_disable_slptr();
rf_poll_trx_state_change(TRX_OFF);
}
/*Write address filter registers*/
rf_if_write_short_addr_registers(short_address);
/*RF back to sleep*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_enable_slptr();
}
rf_if_unlock();
@ -1406,16 +1383,14 @@ static void rf_set_pan_id(uint8_t *pan_id)
{
rf_if_lock();
/*Wake up RF if sleeping*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_disable_slptr();
rf_poll_trx_state_change(TRX_OFF);
}
/*Write address filter registers*/
rf_if_write_pan_id_registers(pan_id);
/*RF back to sleep*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_enable_slptr();
}
rf_if_unlock();
@ -1432,16 +1407,14 @@ static void rf_set_address(uint8_t *address)
{
rf_if_lock();
/*Wake up RF if sleeping*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_disable_slptr();
rf_poll_trx_state_change(TRX_OFF);
}
/*Write address filter registers*/
rf_if_write_ieee_addr_registers(address);
/*RF back to sleep*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_enable_slptr();
}
rf_if_unlock();
@ -1458,8 +1431,9 @@ static void rf_channel_set(uint8_t ch)
{
rf_if_lock();
rf_phy_channel = ch;
if(ch < 0x1f)
if (ch < 0x1f) {
rf_if_set_channel_register(ch);
}
rf_if_unlock();
}
@ -1504,29 +1478,28 @@ static void rf_init(void)
*/
static void rf_off(void)
{
if(rf_flags_check(RFF_ON))
{
if (rf_flags_check(RFF_ON)) {
rf_if_lock();
rf_cca_abort();
uint16_t while_counter = 0;
/*Wait while receiving*/
while(rf_if_read_trx_state() == BUSY_RX_AACK)
{
while (rf_if_read_trx_state() == BUSY_RX_AACK) {
while_counter++;
if(while_counter == 0xffff)
if (while_counter == 0xffff) {
break;
}
}
/*RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP*/
if(rf_if_read_trx_state() == RX_AACK_ON)
{
if (rf_if_read_trx_state() == RX_AACK_ON) {
rf_if_change_trx_state(PLL_ON);
}
rf_if_change_trx_state(TRX_OFF);
rf_if_enable_slptr();
/*Disable Antenna Diversity*/
if(rf_use_antenna_diversity)
if (rf_use_antenna_diversity) {
rf_if_disable_ant_div();
}
rf_if_unlock();
}
@ -1545,18 +1518,19 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state)
{
uint16_t while_counter = 0;
if(trx_state == FORCE_PLL_ON)
if (trx_state == FORCE_PLL_ON) {
trx_state = PLL_ON;
else if(trx_state == FORCE_TRX_OFF)
} else if (trx_state == FORCE_TRX_OFF) {
trx_state = TRX_OFF;
}
rf_trx_states_t state_out;
while((state_out = rf_if_read_trx_state()) != trx_state)
{
while ((state_out = rf_if_read_trx_state()) != trx_state) {
while_counter++;
if(while_counter == 0x1ff)
if (while_counter == 0x1ff) {
break;
}
}
return state_out;
}
@ -1571,8 +1545,7 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state)
static rf_trx_states_t rf_poll_for_state(void)
{
rf_trx_states_t state_out;
while((state_out = rf_if_read_trx_state()) == STATE_TRANSITION_IN_PROGRESS)
{
while ((state_out = rf_if_read_trx_state()) == STATE_TRANSITION_IN_PROGRESS) {
}
return state_out;
@ -1587,20 +1560,17 @@ static rf_trx_states_t rf_poll_for_state(void)
* \return 0 Success
* \return -1 Busy
*/
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol)
{
(void)data_protocol;
rf_if_lock();
/*Check if transmitter is busy*/
rf_trx_states_t trx_state = rf_if_read_trx_state();
if(trx_state == BUSY_RX || trx_state == BUSY_RX_AACK || data_length > RF_MTU - 2)
{
if (trx_state == BUSY_RX || trx_state == BUSY_RX_AACK || data_length > RF_MTU - 2) {
rf_if_unlock();
/*Return busy*/
return -1;
}
else
{
} else {
rf_give_up_on_ack();
/*Nanostack has a static TX buffer, which will remain valid until we*/
@ -1660,7 +1630,6 @@ static bool rf_start_tx()
rf_flags_clear(RFF_RX);
// Check whether we saw any delay in the PLL_ON transition.
if (poll_count > 0) {
tr_warning("PLL_ON delayed, retry count: %d", poll_count);
// let's get back to the receiving state.
rf_receive(state);
return false;
@ -1686,42 +1655,32 @@ static bool rf_start_tx()
static void rf_receive(rf_trx_states_t trx_status)
{
uint16_t while_counter = 0;
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_on();
rf_channel_set(rf_phy_channel);
trx_status = TRX_OFF;
}
/*If not yet in RX state set it*/
if(rf_flags_check(RFF_RX) == 0)
{
if (rf_flags_check(RFF_RX) == 0) {
/*Wait while receiving data. Just making sure, usually this shouldn't happen. */
while(trx_status == BUSY_RX || trx_status == BUSY_RX_AACK || trx_status == STATE_TRANSITION_IN_PROGRESS)
{
while (trx_status == BUSY_RX || trx_status == BUSY_RX_AACK || trx_status == STATE_TRANSITION_IN_PROGRESS) {
while_counter++;
if(while_counter == 0xffff)
{
if (while_counter == 0xffff) {
break;
}
trx_status = rf_if_read_trx_state();
}
if((rf_mode == RF_MODE_SNIFFER) || (rf_mode == RF_MODE_ED))
{
if ((rf_mode == RF_MODE_SNIFFER) || (rf_mode == RF_MODE_ED)) {
if (trx_status != RX_ON) {
trx_status = rf_if_change_trx_state(RX_ON);
}
}
else
{
} else {
/*ACK is always received in promiscuous mode to bypass address filters*/
if(rf_rx_mode)
{
if (rf_rx_mode) {
rf_rx_mode = 0;
rf_if_enable_promiscuous_mode();
}
else
{
} else {
rf_if_disable_promiscuous_mode();
}
if (trx_status != RX_AACK_ON) {
@ -1729,8 +1688,7 @@ static void rf_receive(rf_trx_states_t trx_status)
}
}
/*If calibration timer was unable to calibrate the RF, run calibration now*/
if(!rf_tuned)
{
if (!rf_tuned) {
/*Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state*/
rf_if_calibration();
/*RF is tuned now*/
@ -1753,8 +1711,7 @@ static void rf_calibration_cb(void)
/*clear tuned flag to start tuning in rf_receive*/
rf_tuned = 0;
/*If RF is in default receive state, start calibration*/
if(rf_if_read_trx_state() == RX_AACK_ON)
{
if (rf_if_read_trx_state() == RX_AACK_ON) {
rf_if_lock();
/*Set RF in PLL_ON state*/
rf_if_change_trx_state(PLL_ON);
@ -1783,14 +1740,15 @@ static void rf_calibration_cb(void)
static void rf_on(void)
{
/*Set RFF_ON flag*/
if(rf_flags_check(RFF_ON) == 0)
{
if (rf_flags_check(RFF_ON) == 0) {
rf_if_lock();
rf_flags_set(RFF_ON);
/*Enable Antenna diversity*/
if(rf_use_antenna_diversity)
if (rf_use_antenna_diversity)
/*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/
{
rf_if_enable_ant_div();
}
/*Wake up from sleep state*/
rf_if_disable_slptr();
@ -1814,7 +1772,7 @@ static void rf_give_up_on_ack(void)
rf_if_ack_wait_timer_stop();
expected_ack_sequence = -1;
if(device_driver.phy_tx_done_cb){
if (device_driver.phy_tx_done_cb) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_FAIL, 0, 0);
}
}
@ -1831,20 +1789,20 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
{
phy_link_tx_status_e phy_status;
/*Received ACK sequence must be equal with transmitted packet sequence*/
if(expected_ack_sequence == seq_number)
{
if (expected_ack_sequence == seq_number) {
rf_if_disable_promiscuous_mode();
rf_if_ack_wait_timer_stop();
expected_ack_sequence = -1;
/*When data pending bit in ACK frame is set, inform NET library*/
if(data_pending)
if (data_pending) {
phy_status = PHY_LINK_TX_DONE_PENDING;
else
} else {
phy_status = PHY_LINK_TX_DONE;
}
/*Call PHY TX Done API*/
if(device_driver.phy_tx_done_cb){
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle,phy_status, 0, 0);
if (device_driver.phy_tx_done_cb) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, phy_status, 0, 0);
}
} else {
rf_give_up_on_ack();
@ -1861,7 +1819,7 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
static void rf_handle_rx_end(rf_trx_states_t trx_status)
{
/*Frame received interrupt*/
if(!rf_flags_check(RFF_RX)) {
if (!rf_flags_check(RFF_RX)) {
return;
}
@ -1886,8 +1844,7 @@ static void rf_handle_rx_end(rf_trx_states_t trx_status)
rf_lqi = rf_scale_lqi(rf_rssi);
/*Handle received ACK*/
if((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER)
{
if ((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER) {
/*Check if data is pending*/
bool pending = (rf_buffer[0] & 0x10);
@ -1895,7 +1852,7 @@ static void rf_handle_rx_end(rf_trx_states_t trx_status)
rf_handle_ack(rf_buffer[2], pending);
} else {
rf_give_up_on_ack();
if( device_driver.phy_rx_cb ){
if (device_driver.phy_rx_cb) {
device_driver.phy_rx_cb(rf_buffer, len - 2, rf_lqi, rf_rssi, rf_radio_driver_id);
}
}
@ -1925,8 +1882,7 @@ static void rf_handle_tx_end(rf_trx_states_t trx_status)
{
rf_rx_mode = 0;
/*If ACK is needed for this transmission*/
if((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX))
{
if ((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX)) {
expected_ack_sequence = rf_tx_data[2];
rf_ack_wait_timer_start(rf_ack_wait_duration);
rf_rx_mode = 1;
@ -1936,7 +1892,7 @@ static void rf_handle_tx_end(rf_trx_states_t trx_status)
rf_receive(trx_status);
/*Call PHY TX Done API*/
if(device_driver.phy_tx_done_cb){
if (device_driver.phy_tx_done_cb) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0);
}
}
@ -1958,15 +1914,13 @@ static void rf_handle_cca_ed_done(uint8_t full_trx_status)
bool success = false;
/*Check the result of CCA process*/
if((full_trx_status & CCA_STATUS) && rf_if_trx_status_from_full(full_trx_status) == RX_AACK_ON)
{
if ((full_trx_status & CCA_STATUS) && rf_if_trx_status_from_full(full_trx_status) == RX_AACK_ON) {
success = rf_start_tx();
}
if (!success)
{
if (!success) {
/*Send CCA fail notification*/
if(device_driver.phy_tx_done_cb){
if (device_driver.phy_tx_done_cb) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
}
}
@ -1983,8 +1937,7 @@ static void rf_handle_cca_ed_done(uint8_t full_trx_status)
static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
{
int8_t ret_val = 0;
switch (new_state)
{
switch (new_state) {
/*Reset PHY driver and set to idle*/
case PHY_INTERFACE_RESET:
break;
@ -2033,16 +1986,12 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
*/
static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
{
switch (extension_type)
{
switch (extension_type) {
/*Control MAC pending bit for Indirect data transmission*/
case PHY_EXTENSION_CTRL_PENDING_BIT:
if(*data_ptr)
{
if (*data_ptr) {
rf_if_ack_pending_ctrl(1);
}
else
{
} else {
rf_if_ack_pending_ctrl(0);
}
break;
@ -2084,8 +2033,7 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
{
int8_t ret_val = 0;
switch (address_type)
{
switch (address_type) {
/*Set 48-bit address*/
case PHY_MAC_48BIT:
break;
@ -2119,137 +2067,93 @@ static void rf_init_phy_mode(void)
/*Read used PHY Mode*/
tmp = rf_if_read_register(TRX_CTRL_2);
/*Set ACK wait time for used data rate*/
if(part == PART_AT86RF212)
{
if((tmp & 0x1f) == 0x00)
{
if (part == PART_AT86RF212) {
if ((tmp & 0x1f) == 0x00) {
rf_sensitivity = -110;
rf_ack_wait_duration = 938;
tmp = BPSK_20;
}
else if((tmp & 0x1f) == 0x04)
{
} else if ((tmp & 0x1f) == 0x04) {
rf_sensitivity = -108;
rf_ack_wait_duration = 469;
tmp = BPSK_40;
}
else if((tmp & 0x1f) == 0x14)
{
} else if ((tmp & 0x1f) == 0x14) {
rf_sensitivity = -108;
rf_ack_wait_duration = 469;
tmp = BPSK_40_ALT;
}
else if((tmp & 0x1f) == 0x08)
{
} else if ((tmp & 0x1f) == 0x08) {
rf_sensitivity = -101;
rf_ack_wait_duration = 50;
tmp = OQPSK_SIN_RC_100;
}
else if((tmp & 0x1f) == 0x09)
{
} else if ((tmp & 0x1f) == 0x09) {
rf_sensitivity = -99;
rf_ack_wait_duration = 30;
tmp = OQPSK_SIN_RC_200;
}
else if((tmp & 0x1f) == 0x18)
{
} else if ((tmp & 0x1f) == 0x18) {
rf_sensitivity = -102;
rf_ack_wait_duration = 50;
tmp = OQPSK_RC_100;
}
else if((tmp & 0x1f) == 0x19)
{
} else if ((tmp & 0x1f) == 0x19) {
rf_sensitivity = -100;
rf_ack_wait_duration = 30;
tmp = OQPSK_RC_200;
}
else if((tmp & 0x1f) == 0x0c)
{
} else if ((tmp & 0x1f) == 0x0c) {
rf_sensitivity = -100;
rf_ack_wait_duration = 20;
tmp = OQPSK_SIN_250;
}
else if((tmp & 0x1f) == 0x0d)
{
} else if ((tmp & 0x1f) == 0x0d) {
rf_sensitivity = -98;
rf_ack_wait_duration = 25;
tmp = OQPSK_SIN_500;
}
else if((tmp & 0x1f) == 0x0f)
{
} else if ((tmp & 0x1f) == 0x0f) {
rf_sensitivity = -98;
rf_ack_wait_duration = 25;
tmp = OQPSK_SIN_500_ALT;
}
else if((tmp & 0x1f) == 0x1c)
{
} else if ((tmp & 0x1f) == 0x1c) {
rf_sensitivity = -101;
rf_ack_wait_duration = 20;
tmp = OQPSK_RC_250;
}
else if((tmp & 0x1f) == 0x1d)
{
} else if ((tmp & 0x1f) == 0x1d) {
rf_sensitivity = -99;
rf_ack_wait_duration = 25;
tmp = OQPSK_RC_500;
}
else if((tmp & 0x1f) == 0x1f)
{
} else if ((tmp & 0x1f) == 0x1f) {
rf_sensitivity = -99;
rf_ack_wait_duration = 25;
tmp = OQPSK_RC_500_ALT;
}
else if((tmp & 0x3f) == 0x2A)
{
} else if ((tmp & 0x3f) == 0x2A) {
rf_sensitivity = -91;
rf_ack_wait_duration = 25;
tmp = OQPSK_SIN_RC_400_SCR_ON;
}
else if((tmp & 0x3f) == 0x0A)
{
} else if ((tmp & 0x3f) == 0x0A) {
rf_sensitivity = -91;
rf_ack_wait_duration = 25;
tmp = OQPSK_SIN_RC_400_SCR_OFF;
}
else if((tmp & 0x3f) == 0x3A)
{
} else if ((tmp & 0x3f) == 0x3A) {
rf_sensitivity = -97;
rf_ack_wait_duration = 25;
tmp = OQPSK_RC_400_SCR_ON;
}
else if((tmp & 0x3f) == 0x1A)
{
} else if ((tmp & 0x3f) == 0x1A) {
rf_sensitivity = -97;
rf_ack_wait_duration = 25;
tmp = OQPSK_RC_400_SCR_OFF;
}
else if((tmp & 0x3f) == 0x2E)
{
} else if ((tmp & 0x3f) == 0x2E) {
rf_sensitivity = -93;
rf_ack_wait_duration = 13;
tmp = OQPSK_SIN_1000_SCR_ON;
}
else if((tmp & 0x3f) == 0x0E)
{
} else if ((tmp & 0x3f) == 0x0E) {
rf_sensitivity = -93;
rf_ack_wait_duration = 13;
tmp = OQPSK_SIN_1000_SCR_OFF;
}
else if((tmp & 0x3f) == 0x3E)
{
} else if ((tmp & 0x3f) == 0x3E) {
rf_sensitivity = -95;
rf_ack_wait_duration = 13;
tmp = OQPSK_RC_1000_SCR_ON;
}
else if((tmp & 0x3f) == 0x1E)
{
} else if ((tmp & 0x3f) == 0x1E) {
rf_sensitivity = -95;
rf_ack_wait_duration = 13;
tmp = OQPSK_RC_1000_SCR_OFF;
}
}
else
{
} else {
rf_sensitivity = -101;
rf_ack_wait_duration = 20;
}
@ -2263,43 +2167,53 @@ static uint8_t rf_scale_lqi(int8_t rssi)
uint8_t scaled_lqi;
/*rssi < RF sensitivity*/
if(rssi < rf_sensitivity)
scaled_lqi=0;
if (rssi < rf_sensitivity) {
scaled_lqi = 0;
}
/*-91 dBm < rssi < -81 dBm (AT86RF233 XPro)*/
/*-90 dBm < rssi < -80 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 10))
scaled_lqi=31;
else if (rssi < (rf_sensitivity + 10)) {
scaled_lqi = 31;
}
/*-81 dBm < rssi < -71 dBm (AT86RF233 XPro)*/
/*-80 dBm < rssi < -70 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 20))
scaled_lqi=207;
else if (rssi < (rf_sensitivity + 20)) {
scaled_lqi = 207;
}
/*-71 dBm < rssi < -61 dBm (AT86RF233 XPro)*/
/*-70 dBm < rssi < -60 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 30))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 30)) {
scaled_lqi = 255;
}
/*-61 dBm < rssi < -51 dBm (AT86RF233 XPro)*/
/*-60 dBm < rssi < -50 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 40))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 40)) {
scaled_lqi = 255;
}
/*-51 dBm < rssi < -41 dBm (AT86RF233 XPro)*/
/*-50 dBm < rssi < -40 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 50))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 50)) {
scaled_lqi = 255;
}
/*-41 dBm < rssi < -31 dBm (AT86RF233 XPro)*/
/*-40 dBm < rssi < -30 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 60))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 60)) {
scaled_lqi = 255;
}
/*-31 dBm < rssi < -21 dBm (AT86RF233 XPro)*/
/*-30 dBm < rssi < -20 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 70))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 70)) {
scaled_lqi = 255;
}
/*rssi > RF saturation*/
else if(rssi > (rf_sensitivity + 80))
scaled_lqi=111;
else if (rssi > (rf_sensitivity + 80)) {
scaled_lqi = 111;
}
/*-21 dBm < rssi < -11 dBm (AT86RF233 XPro)*/
/*-20 dBm < rssi < -10 dBm (AT86RF212B XPro)*/
else
scaled_lqi=255;
else {
scaled_lqi = 255;
}
return scaled_lqi;
}
@ -2336,7 +2250,7 @@ int8_t NanostackRfPhyAtmel::rf_register()
// Read the mac address if it hasn't been set by a user
rf = _rf;
if (!_mac_set) {
int ret = _mac.read_eui64((void*)_mac_addr);
int ret = _mac.read_eui64((void *)_mac_addr);
if (ret < 0) {
rf = NULL;
rf_if_unlock();
@ -2377,7 +2291,7 @@ void NanostackRfPhyAtmel::get_mac_address(uint8_t *mac)
rf_if_unlock();
return;
}
memcpy((void*)mac, (void*)_mac_addr, sizeof(_mac_addr));
memcpy((void *)mac, (void *)_mac_addr, sizeof(_mac_addr));
rf_if_unlock();
}
@ -2391,7 +2305,7 @@ void NanostackRfPhyAtmel::set_mac_address(uint8_t *mac)
rf_if_unlock();
return;
}
memcpy((void*)_mac_addr, (void*)mac, sizeof(_mac_addr));
memcpy((void *)_mac_addr, (void *)mac, sizeof(_mac_addr));
_mac_set = true;
rf_if_unlock();

17
components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp
View File

@ -33,7 +33,7 @@
using namespace mbed;
AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda , scl)
AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda, scl)
{
// Do nothing
}
@ -41,25 +41,28 @@ AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda , scl)
int AT24Mac::read_serial(void *buf)
{
char offset = AT24MAC_SERIAL_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, SERIAL_LEN);
}
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, SERIAL_LEN);
}
int AT24Mac::read_eui64(void *buf)
{
char offset = AT24MAC_EUI64_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI64_LEN);
}
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI64_LEN);
}
int AT24Mac::read_eui48(void *buf)
{
char offset = AT24MAC_EUI48_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI48_LEN);
}
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI48_LEN);
}
#endif /* DEVICE_I2C */

122
components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c
View File

@ -106,16 +106,16 @@ uint32_t mPhyIrqDisableCnt = 1;
*---------------------------------------------------------------------------*/
void MCR20Drv_Init
(
void
void
)
{
xcvr_spi_init(gXcvrSpiInstance_c);
xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
gXcvrDeassertCS_d();
#if !defined(TARGET_KW24D)
#if !defined(TARGET_KW24D)
MCR20Drv_RST_B_Deassert();
#endif
#endif
RF_IRQ_Init();
RF_IRQ_Disable();
mPhyIrqDisableCnt = 1;
@ -129,8 +129,8 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_DirectAccessSPIWrite
(
uint8_t address,
uint8_t value
uint8_t address,
uint8_t value
)
{
uint16_t txData;
@ -158,15 +158,14 @@ uint8_t value
*---------------------------------------------------------------------------*/
void MCR20Drv_DirectAccessSPIMultiByteWrite
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t startAddress,
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint8_t txData;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return;
}
@ -193,8 +192,8 @@ uint8_t numOfBytes
*---------------------------------------------------------------------------*/
void MCR20Drv_PB_SPIByteWrite
(
uint8_t address,
uint8_t value
uint8_t address,
uint8_t value
)
{
uint32_t txData;
@ -211,7 +210,7 @@ uint8_t value
txData |= (address) << 8;
txData |= (value) << 16;
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, 3);
gXcvrDeassertCS_d();
UnprotectFromMCR20Interrupt();
@ -225,14 +224,13 @@ uint8_t value
*---------------------------------------------------------------------------*/
void MCR20Drv_PB_SPIBurstWrite
(
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint8_t txData;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return;
}
@ -262,7 +260,7 @@ uint8_t numOfBytes
uint8_t MCR20Drv_DirectAccessSPIRead
(
uint8_t address
uint8_t address
)
{
uint8_t txData;
@ -295,16 +293,15 @@ uint8_t address
*---------------------------------------------------------------------------*/
uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t startAddress,
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint8_t txData;
uint8_t phyIRQSTS1;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return 0;
}
@ -334,15 +331,14 @@ uint8_t numOfBytes
*---------------------------------------------------------------------------*/
uint8_t MCR20Drv_PB_SPIBurstRead
(
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint8_t txData;
uint8_t phyIRQSTS1;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return 0;
}
@ -373,8 +369,8 @@ uint8_t numOfBytes
*---------------------------------------------------------------------------*/
void MCR20Drv_IndirectAccessSPIWrite
(
uint8_t address,
uint8_t value
uint8_t address,
uint8_t value
)
{
uint32_t txData;
@ -389,7 +385,7 @@ uint8_t value
txData |= (address) << 8;
txData |= (value) << 16;
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, 3);
gXcvrDeassertCS_d();
UnprotectFromMCR20Interrupt();
@ -403,15 +399,14 @@ uint8_t value
*---------------------------------------------------------------------------*/
void MCR20Drv_IndirectAccessSPIMultiByteWrite
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t startAddress,
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint16_t txData;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return;
}
@ -424,8 +419,8 @@ uint8_t numOfBytes
txData = TransceiverSPI_IARIndexReg;
txData |= (startAddress) << 8;
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)byteArray, 0, numOfBytes);
gXcvrDeassertCS_d();
UnprotectFromMCR20Interrupt();
@ -439,7 +434,7 @@ uint8_t numOfBytes
*---------------------------------------------------------------------------*/
uint8_t MCR20Drv_IndirectAccessSPIRead
(
uint8_t address
uint8_t address
)
{
uint16_t txData;
@ -454,7 +449,7 @@ uint8_t address
txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
txData |= (address) << 8;
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
gXcvrDeassertCS_d();
@ -471,15 +466,14 @@ uint8_t address
*---------------------------------------------------------------------------*/
void MCR20Drv_IndirectAccessSPIMultiByteRead
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t numOfBytes
uint8_t startAddress,
uint8_t *byteArray,
uint8_t numOfBytes
)
{
uint16_t txData;
if( (numOfBytes == 0) || (byteArray == 0) )
{
if ((numOfBytes == 0) || (byteArray == 0)) {
return;
}
@ -492,7 +486,7 @@ uint8_t numOfBytes
txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
txData |= (startAddress) << 8;
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
gXcvrDeassertCS_d();
@ -507,7 +501,7 @@ uint8_t numOfBytes
*---------------------------------------------------------------------------*/
uint32_t MCR20Drv_IsIrqPending
(
void
void
)
{
return RF_isIRQ_Pending();
@ -521,13 +515,12 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_IRQ_Disable
(
void
void
)
{
core_util_critical_section_enter();
if( mPhyIrqDisableCnt == 0 )
{
if (mPhyIrqDisableCnt == 0) {
RF_IRQ_Disable();
}
@ -544,17 +537,15 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_IRQ_Enable
(
void
void
)
{
core_util_critical_section_enter();
if( mPhyIrqDisableCnt )
{
if (mPhyIrqDisableCnt) {
mPhyIrqDisableCnt--;
if( mPhyIrqDisableCnt == 0 )
{
if (mPhyIrqDisableCnt == 0) {
RF_IRQ_Enable();
}
}
@ -570,7 +561,7 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_RST_B_Assert
(
void
void
)
{
RF_RST_Set(0);
@ -584,7 +575,7 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_RST_B_Deassert
(
void
void
)
{
RF_RST_Set(1);
@ -598,7 +589,7 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_SoftRST_Assert
(
void
void
)
{
MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
@ -612,7 +603,7 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_SoftRST_Deassert
(
void
void
)
{
MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
@ -626,7 +617,7 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_Soft_RESET
(
void
void
)
{
//assert SOG_RST
@ -644,19 +635,19 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_RESET
(
void
void
)
{
#if !defined(TARGET_KW24D)
#if !defined(TARGET_KW24D)
volatile uint32_t delay = 1000;
//assert RST_B
MCR20Drv_RST_B_Assert();
while(delay--);
while (delay--);
//deassert RST_B
MCR20Drv_RST_B_Deassert();
#endif
#endif
}
/*---------------------------------------------------------------------------
@ -667,13 +658,12 @@ void
*---------------------------------------------------------------------------*/
void MCR20Drv_Set_CLK_OUT_Freq
(
uint8_t freqDiv
uint8_t freqDiv
)
{
uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
if(freqDiv == gCLK_OUT_FREQ_DISABLE)
{
if (freqDiv == gCLK_OUT_FREQ_DISABLE) {
clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
}

16
components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h
View File

@ -95,7 +95,7 @@ void MCR20Drv_SPI_DMA_Init
*---------------------------------------------------------------------------*/
void MCR20Drv_Start_PB_DMA_SPI_Write
(
uint8_t * srcAddress,
uint8_t *srcAddress,
uint8_t numOfBytes
);
@ -107,7 +107,7 @@ void MCR20Drv_Start_PB_DMA_SPI_Write
*---------------------------------------------------------------------------*/
void MCR20Drv_Start_PB_DMA_SPI_Read
(
uint8_t * dstAddress,
uint8_t *dstAddress,
uint8_t numOfBytes
);
@ -132,7 +132,7 @@ void MCR20Drv_DirectAccessSPIWrite
void MCR20Drv_DirectAccessSPIMultiByteWrite
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);
@ -144,7 +144,7 @@ void MCR20Drv_DirectAccessSPIMultiByteWrite
*---------------------------------------------------------------------------*/
void MCR20Drv_PB_SPIBurstWrite
(
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);
@ -169,7 +169,7 @@ uint8_t MCR20Drv_DirectAccessSPIRead
uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);
@ -193,7 +193,7 @@ void MCR20Drv_PB_SPIByteWrite
*---------------------------------------------------------------------------*/
uint8_t MCR20Drv_PB_SPIBurstRead
(
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);
@ -218,7 +218,7 @@ void MCR20Drv_IndirectAccessSPIWrite
void MCR20Drv_IndirectAccessSPIMultiByteWrite
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);
@ -241,7 +241,7 @@ uint8_t MCR20Drv_IndirectAccessSPIRead
void MCR20Drv_IndirectAccessSPIMultiByteRead
(
uint8_t startAddress,
uint8_t * byteArray,
uint8_t *byteArray,
uint8_t numOfBytes
);

60
components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h
View File

@ -37,7 +37,7 @@
typedef struct overwrites_tag {
char address;
char data;
}overwrites_t;
} overwrites_t;
/*****************************************************************************************************************/
@ -66,37 +66,37 @@ typedef struct overwrites_tag {
//
// Write access to direct space requires only a single address, data pair.
overwrites_t const overwrites_direct[] ={
{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
{0x23, 0x17} //PA_PWR new default Power Step is "23"
overwrites_t const overwrites_direct[] = {
{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
{0x23, 0x17} //PA_PWR new default Power Step is "23"
};
overwrites_t const overwrites_indirect[] ={
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
{0x52, 0x55}, //AGC_THR1 RSSI tune up
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
{0x66, 0x5F}, //ATT_RSSI1 tune up
{0x67, 0x8F}, //ATT_RSSI2 tune up
{0x68, 0x61}, //RSSI_OFFSET
{0x78, 0x03}, //CHF_PMAGAIN
{0x22, 0x50}, //CCA1_THRESH
{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
overwrites_t const overwrites_indirect[] = {
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
{0x52, 0x55}, //AGC_THR1 RSSI tune up
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
{0x66, 0x5F}, //ATT_RSSI1 tune up
{0x67, 0x8F}, //ATT_RSSI2 tune up
{0x68, 0x61}, //RSSI_OFFSET
{0x78, 0x03}, //CHF_PMAGAIN
{0x22, 0x50}, //CCA1_THRESH
{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
};

184
components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h
View File

@ -312,18 +312,18 @@
#define cIRQSTS1_TXIRQ (1<<1)
#define cIRQSTS1_SEQIRQ (1<<0)
typedef union regIRQSTS1_tag{
typedef union regIRQSTS1_tag {
uint8_t byte;
struct{
uint8_t SEQIRQ:1;
uint8_t TXIRQ:1;
uint8_t RXIRQ:1;
uint8_t CCAIRQ:1;
uint8_t RXWTRMRKIRQ:1;
uint8_t FILTERFAIL_IRQ:1;
uint8_t PLL_UNLOCK_IRQ:1;
uint8_t RX_FRM_PEND:1;
}bit;
struct {
uint8_t SEQIRQ: 1;
uint8_t TXIRQ: 1;
uint8_t RXIRQ: 1;
uint8_t CCAIRQ: 1;
uint8_t RXWTRMRKIRQ: 1;
uint8_t FILTERFAIL_IRQ: 1;
uint8_t PLL_UNLOCK_IRQ: 1;
uint8_t RX_FRM_PEND: 1;
} bit;
} regIRQSTS1_t;
// IRQSTS2 bits
@ -336,18 +336,18 @@ typedef union regIRQSTS1_tag{
#define cIRQSTS2_PB_ERR_IRQ (1<<1)
#define cIRQSTS2_WAKE_IRQ (1<<0)
typedef union regIRQSTS2_tag{
typedef union regIRQSTS2_tag {
uint8_t byte;
struct{
uint8_t WAKE_IRQ:1;
uint8_t PB_ERR_IRQ:1;
uint8_t ASM_IRQ:1;
uint8_t TMRSTATUS:1;
uint8_t PI_:1;
uint8_t SRCADDR:1;
uint8_t CCA:1;
uint8_t CRCVALID:1;
}bit;
struct {
uint8_t WAKE_IRQ: 1;
uint8_t PB_ERR_IRQ: 1;
uint8_t ASM_IRQ: 1;
uint8_t TMRSTATUS: 1;
uint8_t PI_: 1;
uint8_t SRCADDR: 1;
uint8_t CCA: 1;
uint8_t CRCVALID: 1;
} bit;
} regIRQSTS2_t;
// IRQSTS3 bits
@ -360,18 +360,18 @@ typedef union regIRQSTS2_tag{
#define cIRQSTS3_TMR2IRQ (1<<1)
#define cIRQSTS3_TMR1IRQ (1<<0)
typedef union regIRQSTS3_tag{
typedef union regIRQSTS3_tag {
uint8_t byte;
struct{
uint8_t TMR1IRQ:1;
uint8_t TMR2IRQ:1;
uint8_t TMR3IRQ:1;
uint8_t TMR4IRQ:1;
uint8_t TMR1MSK:1;
uint8_t TMR2MSK:1;
uint8_t TMR3MSK:1;
uint8_t TMR4MSK:1;
}bit;
struct {
uint8_t TMR1IRQ: 1;
uint8_t TMR2IRQ: 1;
uint8_t TMR3IRQ: 1;
uint8_t TMR4IRQ: 1;
uint8_t TMR1MSK: 1;
uint8_t TMR2MSK: 1;
uint8_t TMR3MSK: 1;
uint8_t TMR4MSK: 1;
} bit;
} regIRQSTS3_t;
// PHY_CTRL1 bits
@ -382,16 +382,16 @@ typedef union regIRQSTS3_tag{
#define cPHY_CTRL1_AUTOACK (1<<3)
#define cPHY_CTRL1_XCVSEQ (7<<0)
typedef union regPHY_CTRL1_tag{
typedef union regPHY_CTRL1_tag {
uint8_t byte;
struct{
uint8_t XCVSEQ:3;
uint8_t AUTOACK:1;
uint8_t RXACKRQD:1;
uint8_t CCABFRTX:1;
uint8_t SLOTTED:1;
uint8_t TMRTRIGEN:1;
}bit;
struct {
uint8_t XCVSEQ: 3;
uint8_t AUTOACK: 1;
uint8_t RXACKRQD: 1;
uint8_t CCABFRTX: 1;
uint8_t SLOTTED: 1;
uint8_t TMRTRIGEN: 1;
} bit;
} regPHY_CTRL1_t;
// PHY_CTRL2 bits
@ -404,18 +404,18 @@ typedef union regPHY_CTRL1_tag{
#define cPHY_CTRL2_TXMSK (1<<1)
#define cPHY_CTRL2_SEQMSK (1<<0)
typedef union regPHY_CTRL2_tag{
typedef union regPHY_CTRL2_tag {
uint8_t byte;
struct{
uint8_t SEQMSK:1;
uint8_t TXMSK:1;
uint8_t RXMSK:1;
uint8_t CCAMSK:1;
uint8_t RX_WMRK_MSK:1;
uint8_t FILTERFAIL_MSK:1;
uint8_t PLL_UNLOCK_MSK:1;
uint8_t CRC_MSK:1;
}bit;
struct {
uint8_t SEQMSK: 1;
uint8_t TXMSK: 1;
uint8_t RXMSK: 1;
uint8_t CCAMSK: 1;
uint8_t RX_WMRK_MSK: 1;
uint8_t FILTERFAIL_MSK: 1;
uint8_t PLL_UNLOCK_MSK: 1;
uint8_t CRC_MSK: 1;
} bit;
} regPHY_CTRL2_t;
// PHY_CTRL3 bits
@ -427,18 +427,18 @@ typedef union regPHY_CTRL2_tag{
#define cPHY_CTRL3_PB_ERR_MSK (1<<1)
#define cPHY_CTRL3_WAKE_MSK (1<<0)
typedef union regPHY_CTRL3_tag{
typedef union regPHY_CTRL3_tag {
uint8_t byte;
struct{
uint8_t WAKE_MSK:1;
uint8_t PB_ERR_MSK:1;
uint8_t ASM_MSK:1;
uint8_t RESERVED:1;
uint8_t TMR1CMP_EN:1;
uint8_t TMR2CMP_EN:1;
uint8_t TMR3CMP_EN:1;
uint8_t TMR4CMP_EN:1;
}bit;
struct {
uint8_t WAKE_MSK: 1;
uint8_t PB_ERR_MSK: 1;
uint8_t ASM_MSK: 1;
uint8_t RESERVED: 1;
uint8_t TMR1CMP_EN: 1;
uint8_t TMR2CMP_EN: 1;
uint8_t TMR3CMP_EN: 1;
uint8_t TMR4CMP_EN: 1;
} bit;
} regPHY_CTRL3_t;
// RX_FRM_LEN bits
@ -454,17 +454,17 @@ typedef union regPHY_CTRL3_tag{
#define cPHY_CTRL4_PROMISCUOUS (1<<1)
#define cPHY_CTRL4_TC2PRIME_EN (1<<0)
typedef union regPHY_CTRL4_tag{
typedef union regPHY_CTRL4_tag {
uint8_t byte;
struct{
uint8_t TC2PRIME_EN:1;
uint8_t PROMISCUOUS:1;
uint8_t TMRLOAD:1;
uint8_t CCATYPE:2;
uint8_t PANCORDNTR0:1;
uint8_t TC3TMOUT:1;
uint8_t TRCV_MSK:1;
}bit;
struct {
uint8_t TC2PRIME_EN: 1;
uint8_t PROMISCUOUS: 1;
uint8_t TMRLOAD: 1;
uint8_t CCATYPE: 2;
uint8_t PANCORDNTR0: 1;
uint8_t TC3TMOUT: 1;
uint8_t TRCV_MSK: 1;
} bit;
} regPHY_CTRL4_t;
// SRC_CTRL bits
@ -475,15 +475,15 @@ typedef union regPHY_CTRL4_tag{
#define cSRC_CTRL_INDEX_EN (1<<1)
#define cSRC_CTRL_INDEX_DISABLE (1<<0)
typedef union regSRC_CTRL_tag{
typedef union regSRC_CTRL_tag {
uint8_t byte;
struct{
uint8_t INDEX_DISABLE:1;
uint8_t INDEX_EN:1;
uint8_t SRCADDR_EN:1;
uint8_t ACK_FRM_PND:1;
uint8_t INDEX:4;
}bit;
struct {
uint8_t INDEX_DISABLE: 1;
uint8_t INDEX_EN: 1;
uint8_t SRCADDR_EN: 1;
uint8_t ACK_FRM_PND: 1;
uint8_t INDEX: 4;
} bit;
} regSRC_CTRL_t;
// ASM_CTRL1 bits
@ -525,17 +525,17 @@ typedef union regSRC_CTRL_tag{
#define cRX_FRAME_FLT_DATA_FT (1<<1)
#define cRX_FRAME_FLT_BEACON_FT (1<<0)
typedef union regRX_FRAME_FILTER_tag{
typedef union regRX_FRAME_FILTER_tag {
uint8_t byte;
struct{
uint8_t FRAME_FLT_BEACON_FT:1;
uint8_t FRAME_FLT_DATA_FT:1;
uint8_t FRAME_FLT_ACK_FT:1;
uint8_t FRAME_FLT_CMD_FT:1;
uint8_t FRAME_FLT_NS_FT:1;
uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
uint8_t FRAME_FLT_FRM_VER:2;
}bit;
struct {
uint8_t FRAME_FLT_BEACON_FT: 1;
uint8_t FRAME_FLT_DATA_FT: 1;
uint8_t FRAME_FLT_ACK_FT: 1;
uint8_t FRAME_FLT_CMD_FT: 1;
uint8_t FRAME_FLT_NS_FT: 1;
uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS: 1;
uint8_t FRAME_FLT_FRM_VER: 2;
} bit;
} regRX_FRAME_FILTER_t;
// DUAL_PAN_CTRL bits

331
components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp
View File

@ -60,40 +60,38 @@ extern "C" {
#define gXcvrRunState_d gXcvrPwrAutodoze_c
#if !defined(TARGET_KW24D)
#define gXcvrLowPowerState_d gXcvrPwrHibernate_c
#define gXcvrLowPowerState_d gXcvrPwrHibernate_c
#else
#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
#endif
/* MCR20A XCVR states */
typedef enum xcvrState_tag{
typedef enum xcvrState_tag {
gIdle_c,
gRX_c,
gTX_c,
gCCA_c,
gTR_c,
gCCCA_c,
}xcvrState_t;
} xcvrState_t;
/* MCR20A XCVR low power states */
typedef enum xcvrPwrMode_tag{
typedef enum xcvrPwrMode_tag {
gXcvrPwrIdle_c,
gXcvrPwrAutodoze_c,
gXcvrPwrDoze_c,
gXcvrPwrHibernate_c
}xcvrPwrMode_t;
} xcvrPwrMode_t;
/*RF Part Type*/
typedef enum
{
typedef enum {
FREESCALE_UNKNOW_DEV = 0,
FREESCALE_MCR20A
}rf_trx_part_e;
} rf_trx_part_e;
/*Atmel RF states*/
typedef enum
{
typedef enum {
NOP = 0x00,
BUSY_RX = 0x01,
RF_TX_START = 0x02,
@ -106,7 +104,7 @@ typedef enum
SLEEP = 0x0F,
RX_AACK_ON = 0x16,
TX_ARET_ON = 0x19
}rf_trx_states_t;
} rf_trx_states_t;
/*RF receive buffer*/
static uint8_t rf_buffer[RF_BUFFER_SIZE];
@ -162,7 +160,7 @@ MBED_UNUSED static void rf_init(void);
MBED_UNUSED static void rf_set_mac_address(const uint8_t *ptr);
MBED_UNUSED static int8_t rf_device_register(void);
MBED_UNUSED static void rf_device_unregister(void);
MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol);
MBED_UNUSED static void rf_cca_abort(void);
MBED_UNUSED static void rf_read_mac_address(uint8_t *ptr);
MBED_UNUSED static int8_t rf_read_random(void);
@ -203,8 +201,8 @@ MBED_UNUSED static uint8_t rf_get_channel_energy(void);
MBED_UNUSED static uint8_t rf_convert_energy_level(uint8_t energyLevel);
MBED_UNUSED static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi);
MBED_UNUSED static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr);
MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr);
static void PHY_InterruptThread(void);
static void handle_interrupt(void);
@ -237,11 +235,10 @@ static int8_t rf_device_register(void)
radio_type = rf_radio_type_read();
if(radio_type == FREESCALE_MCR20A)
{
if (radio_type == FREESCALE_MCR20A) {
/*Set pointer to MAC address*/
device_driver.PHY_MAC = MAC_address;
device_driver.driver_description = (char*)"FREESCALE_MAC";
device_driver.driver_description = (char *)"FREESCALE_MAC";
//Create setup Used Radio chips
/*Type of RF PHY is SubGHz*/
@ -427,7 +424,7 @@ static uint16_t rf_get_phy_mtu_size(void)
*
* \return none
*/
static void rf_set_short_adr(uint8_t * short_address)
static void rf_set_short_adr(uint8_t *short_address)
{
/* Write one register at a time to be accessible from hibernate mode */
MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_MSB, short_address[0]);
@ -501,9 +498,9 @@ static void rf_init(void)
/* Disable Tristate on MISO for SPI reads */
MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02);
/* Set XCVR clock output settings */
#if !defined(TARGET_KW24D)
#if !defined(TARGET_KW24D)
MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
#endif
#endif
/* Set default XCVR power state */
rf_set_power_state(gXcvrRunState_d);
@ -547,13 +544,15 @@ static void rf_init(void)
MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (cRX_FRAME_FLT_FRM_VER | \
cRX_FRAME_FLT_BEACON_FT | \
cRX_FRAME_FLT_DATA_FT | \
cRX_FRAME_FLT_CMD_FT ));
cRX_FRAME_FLT_CMD_FT));
/* Direct register overwrites */
for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++)
for (index = 0; index < sizeof(overwrites_direct) / sizeof(overwrites_t); index++) {
MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data);
}
/* Indirect register overwrites */
for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++)
for (index = 0; index < sizeof(overwrites_indirect) / sizeof(overwrites_t); index++) {
MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data);
}
/* Set the CCA energy threshold value */
MCR20Drv_IndirectAccessSPIWrite(CCA1_THRESH, RF_CCA_THRESHOLD);
@ -608,22 +607,19 @@ static void rf_poll_trx_state_change(rf_trx_states_t trx_state)
* \return 0 Success
* \return -1 Busy
*/
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol)
{
uint8_t ccaMode;
/* Parameter validation */
if( !data_ptr || (data_length > 125) || (PHY_LAYER_PAYLOAD != data_protocol) )
{
if (!data_ptr || (data_length > 125) || (PHY_LAYER_PAYLOAD != data_protocol)) {
return -1;
}
if( mPhySeqState == gRX_c )
{
if (mPhySeqState == gRX_c) {
uint8_t phyReg = MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F;
/* Check for an Rx in progress. */
if((phyReg <= 0x06) || (phyReg == 0x15) || (phyReg == 0x16))
{
if ((phyReg <= 0x06) || (phyReg == 0x15) || (phyReg == 0x16)) {
if (device_driver.phy_tx_done_cb) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
}
@ -633,8 +629,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
}
/*Check if transmitter is busy*/
if( mPhySeqState != gIdle_c )
{
if (mPhySeqState != gIdle_c) {
/*Return busy*/
return -1;
}
@ -649,12 +644,11 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
/* Load data into XCVR */
tx_len = data_length + 2;
MCR20Drv_PB_SPIBurstWrite(data_ptr - 1, data_length + 1);
MCR20Drv_PB_SPIByteWrite(0,tx_len);
MCR20Drv_PB_SPIByteWrite(0, tx_len);
/* Set CCA mode 1 */
ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
if( ccaMode != gCcaCCA_MODE1_c )
{
if (ccaMode != gCcaCCA_MODE1_c) {
mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
mStatusAndControlRegs[PHY_CTRL4] |= gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c;
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
@ -704,13 +698,10 @@ static void rf_cca_abort(void)
static void rf_start_tx(void)
{
/* Perform TxRxAck sequence if required by phyTxMode */
if( need_ack )
{
if (need_ack) {
mStatusAndControlRegs[PHY_CTRL1] |= cPHY_CTRL1_RXACKRQD;
mPhySeqState = gTR_c;
}
else
{
} else {
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_RXACKRQD);
mPhySeqState = gTX_c;
}
@ -724,8 +715,7 @@ static void rf_start_tx(void)
/* Start the sequence immediately */
MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 2);
if( need_ack )
{
if (need_ack) {
rf_ack_wait_timer_start(gPhyWarmUpTime_c + gPhySHRDuration_c + tx_len * gPhySymbolsPerOctet_c + gPhyAckWaitDuration_c);
}
}
@ -742,8 +732,7 @@ static void rf_receive(void)
uint8_t phyRegs[5];
/* RX can start only from Idle state */
if( mPhySeqState != gIdle_c )
{
if (mPhySeqState != gIdle_c) {
return;
}
@ -804,8 +793,7 @@ static void rf_handle_rx_end(void)
rf_receive();
/*Check the length is valid*/
if(len > 1 && len < RF_BUFFER_SIZE)
{
if (len > 1 && len < RF_BUFFER_SIZE) {
rf_lqi = rf_convert_LQI(rf_lqi);
rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi);
/*gcararu: Scale LQI using received RSSI, to match the LQI reported by the ATMEL radio */
@ -851,20 +839,14 @@ static void rf_handle_tx_end(void)
}
/*Call PHY TX Done API*/
if( need_ack )
{
if( rx_frame_pending )
{
if (need_ack) {
if (rx_frame_pending) {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE_PENDING, 1, 1);
}
else
{
} else {
// arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE, 1, 1);
}
}
else
{
} else {
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
}
}
@ -879,12 +861,9 @@ static void rf_handle_tx_end(void)
static void rf_handle_cca_ed_done(void)
{
/*Check the result of CCA process*/
if( !(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA) )
{
if (!(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA)) {
rf_start_tx();
}
else if (device_driver.phy_tx_done_cb)
{
} else if (device_driver.phy_tx_done_cb) {
/*Send CCA fail notification*/
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
}
@ -901,10 +880,9 @@ static void rf_handle_cca_ed_done(void)
static int8_t rf_tx_power_set(uint8_t power)
{
/* gcapraru: Map MCR20A Tx power levels over ATMEL values */
static uint8_t pwrLevelMapping[16] = {25,25,25,24,24,24,23,23,22,22,21,20,19,18,17,14};
static uint8_t pwrLevelMapping[16] = {25, 25, 25, 24, 24, 24, 23, 23, 22, 22, 21, 20, 19, 18, 17, 14};
if( power > 15 )
{
if (power > 15) {
return -1;
}
@ -958,8 +936,7 @@ static int8_t rf_enable_antenna_diversity(void)
static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
{
int8_t ret_val = 0;
switch (new_state)
{
switch (new_state) {
/*Reset PHY driver and set to idle*/
case PHY_INTERFACE_RESET:
break;
@ -996,19 +973,14 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
*/
static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
{
switch (extension_type)
{
switch (extension_type) {
/*Control MAC pending bit for Indirect data transmission*/
case PHY_EXTENSION_CTRL_PENDING_BIT:
{
case PHY_EXTENSION_CTRL_PENDING_BIT: {
uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
if(*data_ptr)
{
if (*data_ptr) {
reg |= cSRC_CTRL_ACK_FRM_PND;
}
else
{
} else {
reg &= ~cSRC_CTRL_ACK_FRM_PND;
}
@ -1026,19 +998,11 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
}
break;
}
/*Set channel*/
case PHY_EXTENSION_SET_CHANNEL:
break;
/*Read energy on the channel*/
case PHY_EXTENSION_READ_CHANNEL_ENERGY:
*data_ptr = rf_get_channel_energy();
break;
/*Read status of the link*/
case PHY_EXTENSION_READ_LINK_STATUS:
break;
case PHY_EXTENSION_CONVERT_SIGNAL_INFO:
break;
case PHY_EXTENSION_ACCEPT_ANY_BEACON:
default:
break;
}
return 0;
@ -1055,8 +1019,7 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
{
int8_t ret_val = 0;
switch (address_type)
{
switch (address_type) {
/*Set 48-bit address*/
case PHY_MAC_48BIT:
break;
@ -1120,11 +1083,9 @@ static void handle_interrupt(void)
xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ;
/* Flter Fail IRQ */
if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) &&
!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK) )
{
if( xcvseqCopy == gRX_c )
{
if ((mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) &&
!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK)) {
if (xcvseqCopy == gRX_c) {
/* Abort current SEQ */
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
@ -1139,17 +1100,15 @@ static void handle_interrupt(void)
}
/* TMR3 IRQ: ACK wait time-out */
if( (mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) &&
!(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK) )
{
if ((mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) &&
!(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK)) {
/* Disable TMR3 IRQ */
mStatusAndControlRegs[IRQSTS3] |= cIRQSTS3_TMR3MSK;
if( xcvseqCopy == gTR_c )
{
if (xcvseqCopy == gTR_c) {
/* Set XCVR to Idle */
mPhySeqState = gIdle_c;
mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
/* Mask interrupts */
mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK;
/* Sync settings with XCVR */
@ -1161,29 +1120,25 @@ static void handle_interrupt(void)
}
/* Sequencer interrupt, the autosequence has completed */
if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) &&
!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK) )
{
if ((mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) &&
!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK)) {
/* Set XCVR to Idle */
mPhySeqState = gIdle_c;
mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
/* Mask interrupts */
mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK;
/* Sync settings with XCVR */
MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
/* PLL unlock, the autosequence has been aborted due to PLL unlock */
if( mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ )
{
if(xcvseqCopy == gRX_c)
{
if (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ) {
if (xcvseqCopy == gRX_c) {
rf_receive();
}
return;
}
switch(xcvseqCopy)
{
switch (xcvseqCopy) {
case gTX_c:
case gTR_c:
rf_handle_tx_end();
@ -1227,8 +1182,7 @@ static void rf_abort(void)
mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_SEQMSK;
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]);
if( (mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c )
{
if ((mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c) {
/* Abort current SEQ */
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
@ -1258,8 +1212,7 @@ static void rf_abort(void)
*/
static void rf_get_timestamp(uint32_t *pRetClk)
{
if(NULL == pRetClk)
{
if (NULL == pRetClk) {
return;
}
@ -1282,8 +1235,7 @@ static void rf_set_timeout(uint32_t *pEndTime)
{
uint8_t phyReg;
if(NULL == pEndTime)
{
if (NULL == pEndTime) {
return;
}
@ -1318,12 +1270,11 @@ static uint8_t rf_if_read_rnd(void)
/* Check if XCVR is idle */
phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
if( (phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c )
{
if ((phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c) {
/* Program a new sequence */
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyReg | gCCA_c);
/* Wait for sequence to finish */
while( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ) );
while (!(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
/* Clear interrupt flag */
MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ);
}
@ -1342,7 +1293,7 @@ static uint8_t rf_if_read_rnd(void)
*/
static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi)
{
int32_t rssi = (50*lqi - 16820) / 163;
int32_t rssi = (50 * lqi - 16820) / 163;
return (int8_t)rssi;
}
@ -1358,20 +1309,15 @@ static uint8_t rf_convert_LQI(uint8_t hwLqi)
uint32_t tmpLQI;
/* LQI Saturation Level */
if (hwLqi >= 230)
{
if (hwLqi >= 230) {
return 0xFF;
}
else if (hwLqi <= 9)
{
} else if (hwLqi <= 9) {
return 0;
}
else
{
} else {
/* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */
/* The LQI value mst be multiplied by ~1.1087 */
/* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/
tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 );
tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123);
/* tmpLQI = (tmpLQI / 2^16) + hwLqi */
tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi;
@ -1393,16 +1339,13 @@ static void rf_promiscuous(uint8_t state)
rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
if( state )
{
if (state) {
/* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */
/* All frame types accepted*/
phyCtrl4Reg |= cPHY_CTRL4_PROMISCUOUS;
rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
rxFrameFltReg |= (cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT);
}
else
{
} else {
phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS;
/* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */
/* Beacon, Data and MAC command frame types accepted */
@ -1427,8 +1370,7 @@ static void rf_set_power_state(xcvrPwrMode_t newState)
uint8_t pwrMode;
uint8_t xtalState;
if( mPwrState == newState )
{
if (mPwrState == newState) {
return;
}
@ -1436,8 +1378,7 @@ static void rf_set_power_state(xcvrPwrMode_t newState)
pwrMode = MCR20Drv_DirectAccessSPIRead(PWR_MODES);
xtalState = pwrMode & cPWR_MODES_XTALEN;
switch( newState )
{
switch (newState) {
case gXcvrPwrIdle_c:
pwrMode &= ~(cPWR_MODES_AUTODOZE);
pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_PMC_MODE);
@ -1459,12 +1400,11 @@ static void rf_set_power_state(xcvrPwrMode_t newState)
mPwrState = newState;
MCR20Drv_DirectAccessSPIWrite(PWR_MODES, pwrMode);
if( !xtalState && (pwrMode & cPWR_MODES_XTALEN))
{
if (!xtalState && (pwrMode & cPWR_MODES_XTALEN)) {
/* wait for crystal oscillator to complet its warmup */
while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY);
while ((MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY) != cPWR_MODES_XTAL_READY);
/* wait for radio wakeup from hibernate interrupt */
while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) );
while ((MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS)) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS));
MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ);
}
@ -1481,8 +1421,7 @@ static uint8_t rf_get_channel_energy(void)
MCR20Drv_IRQ_Disable();
/* RX can start only from Idle state */
if( mPhySeqState != gIdle_c )
{
if (mPhySeqState != gIdle_c) {
MCR20Drv_IRQ_Enable();
return 0;
}
@ -1492,8 +1431,7 @@ static uint8_t rf_get_channel_energy(void)
/* Switch to ED mode */
ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
if( ccaMode != gCcaED_c )
{
if (ccaMode != gCcaED_c) {
mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
mStatusAndControlRegs[PHY_CTRL4] |= gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c;
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
@ -1504,7 +1442,7 @@ static uint8_t rf_get_channel_energy(void)
MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ | cIRQSTS1_SEQIRQ);
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
/* Wait for sequence to finish */
while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
while (!(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
/* Set XCVR to Idle */
mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
@ -1524,18 +1462,13 @@ static uint8_t rf_get_channel_energy(void)
*/
static uint8_t rf_convert_energy_level(uint8_t energyLevel)
{
if(energyLevel >= 90)
{
if (energyLevel >= 90) {
/* ED value is below minimum. Return 0x00. */
energyLevel = 0x00;
}
else if(energyLevel <= 26)
{
} else if (energyLevel <= 26) {
/* ED value is above maximum. Return 0xFF. */
energyLevel = 0xFF;
}
else
{
} else {
/* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */
energyLevel = (90 - energyLevel);
/* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */
@ -1555,43 +1488,53 @@ static uint8_t rf_scale_lqi(int8_t rssi)
const int8_t rf_sensitivity = -98;
/*rssi < RF sensitivity*/
if(rssi < rf_sensitivity)
scaled_lqi=0;
if (rssi < rf_sensitivity) {
scaled_lqi = 0;
}
/*-91 dBm < rssi < -81 dBm (AT86RF233 XPro)*/
/*-90 dBm < rssi < -80 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 10))
scaled_lqi=31;
else if (rssi < (rf_sensitivity + 10)) {
scaled_lqi = 31;
}
/*-81 dBm < rssi < -71 dBm (AT86RF233 XPro)*/
/*-80 dBm < rssi < -70 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 20))
scaled_lqi=207;
else if (rssi < (rf_sensitivity + 20)) {
scaled_lqi = 207;
}
/*-71 dBm < rssi < -61 dBm (AT86RF233 XPro)*/
/*-70 dBm < rssi < -60 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 30))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 30)) {
scaled_lqi = 255;
}
/*-61 dBm < rssi < -51 dBm (AT86RF233 XPro)*/
/*-60 dBm < rssi < -50 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 40))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 40)) {
scaled_lqi = 255;
}
/*-51 dBm < rssi < -41 dBm (AT86RF233 XPro)*/
/*-50 dBm < rssi < -40 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 50))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 50)) {
scaled_lqi = 255;
}
/*-41 dBm < rssi < -31 dBm (AT86RF233 XPro)*/
/*-40 dBm < rssi < -30 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 60))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 60)) {
scaled_lqi = 255;
}
/*-31 dBm < rssi < -21 dBm (AT86RF233 XPro)*/
/*-30 dBm < rssi < -20 dBm (AT86RF212B XPro)*/
else if(rssi < (rf_sensitivity + 70))
scaled_lqi=255;
else if (rssi < (rf_sensitivity + 70)) {
scaled_lqi = 255;
}
/*rssi > RF saturation*/
else if(rssi > (rf_sensitivity + 80))
scaled_lqi=111;
else if (rssi > (rf_sensitivity + 80)) {
scaled_lqi = 111;
}
/*-21 dBm < rssi < -11 dBm (AT86RF233 XPro)*/
/*-20 dBm < rssi < -10 dBm (AT86RF212B XPro)*/
else
scaled_lqi=255;
else {
scaled_lqi = 255;
}
return scaled_lqi;
}
@ -1605,28 +1548,33 @@ extern "C" void xcvr_spi_init(uint32_t instance)
(void)instance;
}
extern "C" void RF_IRQ_Init(void) {
extern "C" void RF_IRQ_Init(void)
{
MBED_ASSERT(irq != NULL);
irq->mode(PullUp);
irq->fall(&PHY_InterruptHandler);
}
extern "C" void RF_IRQ_Enable(void) {
extern "C" void RF_IRQ_Enable(void)
{
MBED_ASSERT(irq != NULL);
irq->enable_irq();
}
extern "C" void RF_IRQ_Disable(void) {
extern "C" void RF_IRQ_Disable(void)
{
MBED_ASSERT(irq != NULL);
irq->disable_irq();
}
extern "C" uint8_t RF_isIRQ_Pending(void) {
extern "C" uint8_t RF_isIRQ_Pending(void)
{
MBED_ASSERT(rf != NULL);
return !irq_pin->read();
}
extern "C" void RF_RST_Set(int state) {
extern "C" void RF_RST_Set(int state)
{
MBED_ASSERT(rst != NULL);
*rst = state;
}
@ -1651,36 +1599,33 @@ extern "C" void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq)
}
extern "C" void xcvr_spi_transfer(uint32_t instance,
uint8_t * sendBuffer,
uint8_t * receiveBuffer,
uint8_t *sendBuffer,
uint8_t *receiveBuffer,
size_t transferByteCount)
{
MBED_ASSERT(spi != NULL);
(void)instance;
volatile uint8_t dummy;
if( !transferByteCount )
if (!transferByteCount) {
return;
}
if( !sendBuffer && !receiveBuffer )
if (!sendBuffer && !receiveBuffer) {
return;
}
while( transferByteCount-- )
{
if( sendBuffer )
{
while (transferByteCount--) {
if (sendBuffer) {
dummy = *sendBuffer;
sendBuffer++;
}
else
{
} else {
dummy = 0xFF;
}
dummy = spi->write(dummy);
if( receiveBuffer )
{
if (receiveBuffer) {
*receiveBuffer = dummy;
receiveBuffer++;
}
@ -1768,7 +1713,7 @@ void NanostackRfPhyMcr20a::get_mac_address(uint8_t *mac)
{
rf_if_lock();
memcpy((void*)mac, (void*)MAC_address, sizeof(MAC_address));
memcpy((void *)mac, (void *)MAC_address, sizeof(MAC_address));
rf_if_unlock();
}
@ -1782,7 +1727,7 @@ void NanostackRfPhyMcr20a::set_mac_address(uint8_t *mac)
rf_if_unlock();
return;
}
memcpy((void*)MAC_address, (void*)mac, sizeof(MAC_address));
memcpy((void *)MAC_address, (void *)mac, sizeof(MAC_address));
rf_if_unlock();
}

4
components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h
View File

@ -78,8 +78,8 @@ void gXcvrDeassertCS_d(void);
void xcvr_spi_init(uint32_t instance);
void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq);
void xcvr_spi_transfer(uint32_t instance,
uint8_t * sendBuffer,
uint8_t * receiveBuffer,
uint8_t *sendBuffer,
uint8_t *receiveBuffer,
uint32_t transferByteCount);
#if defined(__cplusplus)