From 9bc2deb9aa371cfdf7ebe6fbe6f4eda8e21250c9 Mon Sep 17 00:00:00 2001 From: Martin Eckardt Date: Tue, 11 Aug 2020 21:58:56 +0200 Subject: [PATCH 1/9] make G4 target compileable with CAN support --- targets/TARGET_STM/TARGET_STM32G4/objects.h | 2 +- targets/TARGET_STM/can_api.c | 24 ++++++++++++++++++--- targets/targets.json | 3 ++- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h index 5a33295f3c..00f278c9f0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -133,7 +133,7 @@ struct analogin_s { #if DEVICE_CAN struct can_s { - CAN_HandleTypeDef CanHandle; + FDCAN_HandleTypeDef CanHandle; int index; int hz; }; diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 560ca9e321..e80e74171e 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -133,9 +133,12 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz obj->CanHandle.Init.DataSyncJumpWidth = 0x1; // Not used - only in FDCAN obj->CanHandle.Init.DataTimeSeg1 = 0x1; // Not used - only in FDCAN obj->CanHandle.Init.DataTimeSeg2 = 0x1; // Not used - only in FDCAN +#ifndef TARGET_STM32G4 obj->CanHandle.Init.MessageRAMOffset = 0; +#endif obj->CanHandle.Init.StdFiltersNbr = 1; // to be aligned with the handle parameter in can_filter obj->CanHandle.Init.ExtFiltersNbr = 1; // to be aligned with the handle parameter in can_filter +#ifndef TARGET_STM32G4 obj->CanHandle.Init.RxFifo0ElmtsNbr = 8; obj->CanHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; obj->CanHandle.Init.RxFifo1ElmtsNbr = 0; @@ -145,9 +148,11 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz obj->CanHandle.Init.TxEventsNbr = 3; obj->CanHandle.Init.TxBuffersNbr = 0; obj->CanHandle.Init.TxFifoQueueElmtsNbr = 3; +#endif obj->CanHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; +#ifndef TARGET_STM32G4 obj->CanHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_8; - +#endif can_internal_init(obj); } @@ -198,7 +203,9 @@ void can_irq_free(can_t *obj) else { return; } +#ifndef TARGET_STM32G4 HAL_NVIC_DisableIRQ(FDCAN_CAL_IRQn); +#endif can_irq_ids[obj->index] = 0; } @@ -441,14 +448,21 @@ static void can_irq(CANName name, int id) irq_handler(can_irq_ids[id], IRQ_TX); } } - +#ifndef TARGET_STM32G4 if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE); irq_handler(can_irq_ids[id], IRQ_RX); } } - +#else + if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { + if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { + __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE); + irq_handler(can_irq_ids[id], IRQ_RX); + } + } +#endif if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_ERROR_WARNING)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING); @@ -501,7 +515,11 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) interrupts = FDCAN_IT_TX_COMPLETE; break; case IRQ_RX: +#ifndef TARGET_STM32G4 interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE; +#else + interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; +#endif break; case IRQ_ERROR: interrupts = FDCAN_IT_ERROR_WARNING; diff --git a/targets/targets.json b/targets/targets.json index 67b809954a..5226cb9090 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2475,7 +2475,8 @@ "device_has_add": [ "ANALOGOUT", "FLASH", - "MPU" + "MPU", + "CAN" ] }, "NUCLEO_G474RE": { From 988653202991308639983b36701c1a6969992a59 Mon Sep 17 00:00:00 2001 From: Martin Eckardt Date: Mon, 7 Sep 2020 01:22:29 +0200 Subject: [PATCH 2/9] Added support for FDCAN3 --- targets/TARGET_STM/can_api.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index e80e74171e..c134aa5d1e 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -76,6 +76,11 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz else if (pinmap->peripheral == CAN_2) { obj->index = 1; } +#endif +#if defined(FDCAN3_BASE) + else if (pinmap->peripheral == CAN_3) { + obj->index = 2; + } #endif else { error("can_init wrong instance\n"); @@ -199,6 +204,12 @@ void can_irq_free(can_t *obj) HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn); } +#endif +#if defined(FDCAN3_BASE) + else if (can == CAN_3) { + HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); + HAL_NVIC_DisableIRQ(FDCAN3_IT1_IRQn); + } #endif else { return; @@ -505,6 +516,17 @@ void FDCAN2_IT1_IRQHandler(void) can_irq(CAN_2, 1); } +void FDCAN3_IT0_IRQHandler(void) +{ + can_irq(CAN_3, 2); +} + +void FDCAN3_IT1_IRQHandler(void) +{ + can_irq(CAN_3, 2); +} + + // TODO Add other interrupts ? void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { @@ -549,6 +571,12 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) NVIC_SetVector(FDCAN2_IT1_IRQn, (uint32_t)&FDCAN2_IT1_IRQHandler); NVIC_EnableIRQ(FDCAN2_IT1_IRQn); #endif +#if defined(FDCAN3_BASE) + NVIC_SetVector(FDCAN3_IT0_IRQn, (uint32_t)&FDCAN3_IT0_IRQHandler); + NVIC_EnableIRQ(FDCAN3_IT0_IRQn); + NVIC_SetVector(FDCAN3_IT1_IRQn, (uint32_t)&FDCAN3_IT1_IRQHandler); + NVIC_EnableIRQ(FDCAN3_IT1_IRQn); +#endif } #else /* FDCAN1 */ From f32efe4c282778ed6f173b26d8be8b5abed19a26 Mon Sep 17 00:00:00 2001 From: Martin Eckardt Date: Thu, 27 Aug 2020 14:42:12 +0200 Subject: [PATCH 3/9] Changed PLL to 160MHz, PLLQ to 80MHz --- .../TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c index 22bd617fbc..926ef41a1b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c @@ -105,9 +105,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; - RCC_OscInitStruct.PLL.PLLN = 85; + RCC_OscInitStruct.PLL.PLLN = 80; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL From 08ce2f2de8b46f92331afd842980affd0f610bed Mon Sep 17 00:00:00 2001 From: Martin Eckardt Date: Thu, 27 Aug 2020 16:29:53 +0200 Subject: [PATCH 4/9] Calculate FDCAN_clk instead of assuming fix 10MHz - The FDCAN_clk is calculated on runtime from the according RCC-registers --- targets/TARGET_STM/can_api.c | 61 ++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index c134aa5d1e..e24e91fa97 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -57,6 +57,62 @@ int can_internal_init(can_t *obj) return 1; } + +/** Calculate the fdcan-core-clk value for accurate calculation of the quantum timing + * + * !Attention Not all bitrates can be covered with all fdcan-core-clk values. When a clk + * does not work for the desired bitrate, change system_clock settings for PLLQ + * + * !Attention For now, PCLK is not supported (PLLQ is selected always anyways) + * + * @returns + * core_frequency when successful + * -1 when error / not supported + */ +static int _can_get_core_frequency( void ) +{ + int clk_sel = (RCC->CCIPR & RCC_CCIPR_FDCANSEL_Msk) >> RCC_CCIPR_FDCANSEL_Pos; + + switch (clk_sel){ + case 0: //! HSE clock selected as FDCAN clock + { + return HSE_VALUE; + } + case 1: //! PLL "Q" clock selected as FDCAN clock + { + int pll_source_clk; + + int pll_source = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_Msk); + if (pll_source == RCC_PLLCFGR_PLLSRC_HSE){ + pll_source_clk = HSE_VALUE; + } else if (pll_source == RCC_PLLCFGR_PLLSRC_HSI){ + pll_source_clk = HSI_VALUE; + } else { + MBED_ERROR( + MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_CONFIG_UNSUPPORTED), + "PLL source must be HSI or HSE"); + return -1; + } + + int pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM_Msk) >> RCC_PLLCFGR_PLLM_Pos) + 1; + int plln = (RCC->PLLCFGR & RCC_PLLCFGR_PLLN_Msk) >> RCC_PLLCFGR_PLLN_Pos; + int pllq = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ_Msk) >> RCC_PLLCFGR_PLLQ_Pos) + 1; + pllq = pllq * 2; + int fdcan_freq = ((pll_source_clk / pllm) * plln) / pllq; + + return fdcan_freq; + } + case 2: //! PCLK Clk selected as FDCAN clock + case 3: + default: + MBED_ERROR( + MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_CONFIG_UNSUPPORTED), + "Wrong clk_source configuration"); + return -1; + } +} + + #if STATIC_PINMAP_READY #define CAN_INIT_FREQ_DIRECT can_init_freq_direct void can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz) @@ -123,7 +179,8 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz Phase_segment_2 | 30 tq | = - 1 - Synchronization_Jump_width | 30 tq | = */ - int ntq = 10000000 / hz; + + int ntq = _can_get_core_frequency() / hz; obj->CanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC; obj->CanHandle.Init.Mode = FDCAN_MODE_NORMAL; @@ -254,7 +311,7 @@ int can_frequency(can_t *obj, int f) } /* See can_init_freq function for calculation details */ - int ntq = 10000000 / f; + int ntq = _can_get_core_frequency() / f; obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75; // Phase_segment_1 obj->CanHandle.Init.NominalTimeSeg2 = ntq - 1 - obj->CanHandle.Init.NominalTimeSeg1; // Phase_segment_2 obj->CanHandle.Init.NominalSyncJumpWidth = obj->CanHandle.Init.NominalTimeSeg2; // Synchronization_Jump_width From 35c9e7a5adb9a83521dc4c9b533271b9809f3db6 Mon Sep 17 00:00:00 2001 From: Martin Eckardt Date: Mon, 14 Sep 2020 15:24:14 +0200 Subject: [PATCH 5/9] Use HAL function for FDCAN_CLK-calculation - Thanks to @jeromecoutant for showing the HAL funtion - Added #ifdef guard to FDCAN2/3 handler functions --- targets/TARGET_STM/can_api.c | 88 ++++++++++++------------------------ 1 file changed, 29 insertions(+), 59 deletions(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index e24e91fa97..230084aa94 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -57,62 +57,6 @@ int can_internal_init(can_t *obj) return 1; } - -/** Calculate the fdcan-core-clk value for accurate calculation of the quantum timing - * - * !Attention Not all bitrates can be covered with all fdcan-core-clk values. When a clk - * does not work for the desired bitrate, change system_clock settings for PLLQ - * - * !Attention For now, PCLK is not supported (PLLQ is selected always anyways) - * - * @returns - * core_frequency when successful - * -1 when error / not supported - */ -static int _can_get_core_frequency( void ) -{ - int clk_sel = (RCC->CCIPR & RCC_CCIPR_FDCANSEL_Msk) >> RCC_CCIPR_FDCANSEL_Pos; - - switch (clk_sel){ - case 0: //! HSE clock selected as FDCAN clock - { - return HSE_VALUE; - } - case 1: //! PLL "Q" clock selected as FDCAN clock - { - int pll_source_clk; - - int pll_source = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_Msk); - if (pll_source == RCC_PLLCFGR_PLLSRC_HSE){ - pll_source_clk = HSE_VALUE; - } else if (pll_source == RCC_PLLCFGR_PLLSRC_HSI){ - pll_source_clk = HSI_VALUE; - } else { - MBED_ERROR( - MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_CONFIG_UNSUPPORTED), - "PLL source must be HSI or HSE"); - return -1; - } - - int pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM_Msk) >> RCC_PLLCFGR_PLLM_Pos) + 1; - int plln = (RCC->PLLCFGR & RCC_PLLCFGR_PLLN_Msk) >> RCC_PLLCFGR_PLLN_Pos; - int pllq = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ_Msk) >> RCC_PLLCFGR_PLLQ_Pos) + 1; - pllq = pllq * 2; - int fdcan_freq = ((pll_source_clk / pllm) * plln) / pllq; - - return fdcan_freq; - } - case 2: //! PCLK Clk selected as FDCAN clock - case 3: - default: - MBED_ERROR( - MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_CONFIG_UNSUPPORTED), - "Wrong clk_source configuration"); - return -1; - } -} - - #if STATIC_PINMAP_READY #define CAN_INIT_FREQ_DIRECT can_init_freq_direct void can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz) @@ -180,7 +124,16 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz Synchronization_Jump_width | 30 tq | = */ - int ntq = _can_get_core_frequency() / hz; + // !Attention Not all bitrates can be covered with all fdcan-core-clk values. When a clk + // does not work for the desired bitrate, change system_clock settings for FDCAN_CLK + // (default FDCAN_CLK is PLLQ) +#ifdef TARGET_STM32G4 + int ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / hz; +#else + // STM32H7 doesn't support yet HAL_RCCEx_GetPeriphCLKFreq for FDCAN + // Internal ST ticket 92465 + int ntq = 10000000 / hz; +#endif obj->CanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC; obj->CanHandle.Init.Mode = FDCAN_MODE_NORMAL; @@ -310,8 +263,21 @@ int can_frequency(can_t *obj, int f) error("HAL_FDCAN_Stop error\n"); } - /* See can_init_freq function for calculation details */ - int ntq = _can_get_core_frequency() / f; + + /* See can_init_freq function for calculation details + * + * !Attention Not all bitrates can be covered with all fdcan-core-clk values. When a clk + * does not work for the desired bitrate, change system_clock settings for FDCAN_CLK + * (default FDCAN_CLK is PLLQ) + */ +#ifdef TARGET_STM32G4 + int ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / f; +#else + // STM32H7 doesn't support yet HAL_RCCEx_GetPeriphCLKFreq for FDCAN + // Internal ST ticket 92465 + int ntq = 10000000 / hz; +#endif + obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75; // Phase_segment_1 obj->CanHandle.Init.NominalTimeSeg2 = ntq - 1 - obj->CanHandle.Init.NominalTimeSeg1; // Phase_segment_2 obj->CanHandle.Init.NominalSyncJumpWidth = obj->CanHandle.Init.NominalTimeSeg2; // Synchronization_Jump_width @@ -563,6 +529,7 @@ void FDCAN1_IT1_IRQHandler(void) can_irq(CAN_1, 0); } +#if defined(FDCAN2_BASE) void FDCAN2_IT0_IRQHandler(void) { can_irq(CAN_2, 1); @@ -572,7 +539,9 @@ void FDCAN2_IT1_IRQHandler(void) { can_irq(CAN_2, 1); } +#endif //FDCAN2_BASE +#if defined(FDCAN3_BASE) void FDCAN3_IT0_IRQHandler(void) { can_irq(CAN_3, 2); @@ -582,6 +551,7 @@ void FDCAN3_IT1_IRQHandler(void) { can_irq(CAN_3, 2); } +#endif //FDCAN3_BASE // TODO Add other interrupts ? From 13b663397f759d1d31c1bbb82c9beb2239c14703 Mon Sep 17 00:00:00 2001 From: m-ecry Date: Mon, 14 Sep 2020 16:29:12 +0200 Subject: [PATCH 6/9] STM-can-api: Added usage of prescaler - This enables more frequencies, but without regard to the accuracy. May still require manual clock setup, to remain in tolerance window --- targets/TARGET_STM/can_api.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 230084aa94..61903b27dd 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -135,12 +135,24 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz int ntq = 10000000 / hz; #endif + int nominalPrescaler = 1; + // !When the sample point should be lower than 50%, this must be changed to + // !IS_FDCAN_NOMINAL_TSEG2(ntq/nominalPrescaler), since + // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% + while (!IS_FDCAN_NOMINAL_TSEG1(ntq/nominalPrescaler)){ + nominalPrescaler ++; + if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){ + error("Could not determine good nominalPrescaler. Bad clock value\n"); + } + } + ntq = ntq/nominalPrescaler; + obj->CanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC; obj->CanHandle.Init.Mode = FDCAN_MODE_NORMAL; obj->CanHandle.Init.AutoRetransmission = ENABLE; obj->CanHandle.Init.TransmitPause = DISABLE; obj->CanHandle.Init.ProtocolException = ENABLE; - obj->CanHandle.Init.NominalPrescaler = 1; // Prescaler + obj->CanHandle.Init.NominalPrescaler = nominalPrescaler; // Prescaler obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75; // Phase_segment_1 obj->CanHandle.Init.NominalTimeSeg2 = ntq - 1 - obj->CanHandle.Init.NominalTimeSeg1; // Phase_segment_2 obj->CanHandle.Init.NominalSyncJumpWidth = obj->CanHandle.Init.NominalTimeSeg2; // Synchronization_Jump_width @@ -278,6 +290,19 @@ int can_frequency(can_t *obj, int f) int ntq = 10000000 / hz; #endif + int nominalPrescaler = 1; + // !When the sample point should be lower than 50%, this must be changed to + // !IS_FDCAN_DATA_TSEG2(ntq/nominalPrescaler), since + // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% + while (!IS_FDCAN_DATA_TSEG1(ntq/nominalPrescaler)){ + nominalPrescaler ++; + if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){ + error("Could not determine good nominalPrescaler. Bad clock value\n"); + } + } + ntq = ntq/nominalPrescaler; + + obj->CanHandle.Init.NominalPrescaler = nominalPrescaler; obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75; // Phase_segment_1 obj->CanHandle.Init.NominalTimeSeg2 = ntq - 1 - obj->CanHandle.Init.NominalTimeSeg1; // Phase_segment_2 obj->CanHandle.Init.NominalSyncJumpWidth = obj->CanHandle.Init.NominalTimeSeg2; // Synchronization_Jump_width From d0c8ad75e1956c20b359f1a2884e0819cd809f26 Mon Sep 17 00:00:00 2001 From: m-ecry Date: Mon, 14 Sep 2020 18:10:48 +0200 Subject: [PATCH 7/9] STM-can-api: Support reading of remote_msg - Previously a received msg was fixed of data_type --- targets/TARGET_STM/can_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 61903b27dd..29a7c96da5 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -405,7 +405,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) msg->format = CANExtended; } msg->id = RxHeader.Identifier; - msg->type = CANData; + msg->type = (RxHeader.RxFrameType == FDCAN_DATA_FRAME) ? CANData : CANRemote; msg->len = RxHeader.DataLength >> 16; // see FDCAN_data_length_code value return 1; From 2a13fa199dcc9f2a8faef79b7377e12222830d23 Mon Sep 17 00:00:00 2001 From: m-ecry Date: Mon, 14 Sep 2020 18:13:15 +0200 Subject: [PATCH 8/9] STMG4-sys-clk: If can PLLQ=160MHz, else 170MHz - with 170MHz as can-core-frequency, the accuracy for many baudrates is too low. 160MHz is better for a broad range of frequencies --- .../TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c index 926ef41a1b..84a6c01709 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c @@ -105,9 +105,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; +#if DEVICE_CAN RCC_OscInitStruct.PLL.PLLN = 80; +#else + RCC_OscInitStruct.PLL.PLLN = 85; +#endif RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL From 73493b909a442d97f1d208c14620ca8d55636223 Mon Sep 17 00:00:00 2001 From: m-ecry Date: Wed, 16 Sep 2020 17:18:25 +0200 Subject: [PATCH 9/9] STM-can-api: Fixed variable name for H7 - can_frequency uses f instead of hz for can frequency - Also added comment to system_clock --- .../TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c | 3 +++ targets/TARGET_STM/can_api.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c index 84a6c01709..45f82d03da 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c @@ -105,6 +105,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; + //! 170MHz as a core frequency for FDCAN is not suitable for many frequencies, + //! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz + //! should be standard. #if DEVICE_CAN RCC_OscInitStruct.PLL.PLLN = 80; #else diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 29a7c96da5..b264941b81 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -287,7 +287,7 @@ int can_frequency(can_t *obj, int f) #else // STM32H7 doesn't support yet HAL_RCCEx_GetPeriphCLKFreq for FDCAN // Internal ST ticket 92465 - int ntq = 10000000 / hz; + int ntq = 10000000 / f; #endif int nominalPrescaler = 1;