mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #4665 from Archcady/enable_sdram
Enable sdram usage of REALTEK_RTL8195AMpull/5043/merge
Jimmy Brisson
GitHub
commit
7457bbbc5c
Binary file not shown.
|
|
@ -1,51 +1,78 @@
|
||||||
; *************************************************************
|
; Realtek Semiconductor Corp.
|
||||||
; *** Scatter-Loading Description File for RTL8195A ***
|
;
|
||||||
; *************************************************************
|
; RTL8195A ARMCC Scatter File
|
||||||
LR_ROM 0x00000000 0x00030000{
|
;
|
||||||
_ROM_CODE 0x00000000 0x00030000 {
|
; MEMORY
|
||||||
;*.o (RESET, +First)
|
; {
|
||||||
;*(InRoot$$Sections)
|
; SROM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00007000
|
||||||
}
|
; SRAM (rwx) : ORIGIN = 0x10007000, LENGTH = 0x00070000 - 0x00007000
|
||||||
}
|
; TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
|
||||||
|
; DRAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||||
|
; }
|
||||||
|
|
||||||
LR_RAM 0x10006000 0x6FFFF {
|
LR_IRAM 0x10007000 (0x70000 - 0x7000) {
|
||||||
;LR_RAM 0x10000000 0x6FFFF {
|
|
||||||
;ROM_BSS 0x10000000 0x0005FFF{
|
|
||||||
;rtl_console.o(.mon.ram.bss*)
|
|
||||||
;}
|
|
||||||
|
|
||||||
.image2.table 0x10006000 FIXED {
|
IMAGE2_TABLE 0x10007000 FIXED {
|
||||||
rtl8195a_init.o(.image2.ram.data*)
|
*rtl8195a_init.o(.image2.ram.data*, +FIRST)
|
||||||
rtl8195a_init.o(.image2.validate.rodata*)
|
*rtl8195a_init.o(.image2.validate.rodata*)
|
||||||
}
|
}
|
||||||
|
|
||||||
.text +0 FIXED{
|
ER_IRAM +0 FIXED {
|
||||||
rtl8195a_init.o(.infra.ram.start)
|
*rtl8195a_crypto.o (+RO)
|
||||||
;*.o(.mon.ram.text*)
|
* (i.mbedtls*)
|
||||||
;*.o(.hal.flash.text*)
|
*libc.a (+RO)
|
||||||
;*.o(.hal.sdrc.text*)
|
|
||||||
;*.o(.hal.gpio.text*)
|
|
||||||
;*.o(.text*)
|
|
||||||
;*.o(.rodata*)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
|
|
||||||
.data +0 FIXED{
|
*rtx_*.o (+RO)
|
||||||
.ANY (+RW)
|
*Ticker.o (+RO)
|
||||||
|
*Timeout.o (+RO)
|
||||||
|
*rtx_timer.o (+RO)
|
||||||
|
*TimerEvent.o (+RO)
|
||||||
|
*mbed_ticker_api.o (+RO)
|
||||||
|
*mbed_critical.o (+RO)
|
||||||
|
*us_ticker.o (+RO)
|
||||||
|
|
||||||
|
*lib_peripheral_mbed_arm.ar (+RO)
|
||||||
}
|
}
|
||||||
|
|
||||||
RW_IRAM1 +0 UNINIT FIXED {
|
RW_IRAM1 +0 UNINIT FIXED {
|
||||||
.ANY (+ZI)
|
*rtl8195a_crypto.o(+RW)
|
||||||
|
;*mbedtls*.o(+RW)
|
||||||
|
*libc.a (+RW)
|
||||||
|
*(.sdram.data*)
|
||||||
|
*lib_peripheral_mbed_arm.ar (+RW)
|
||||||
}
|
}
|
||||||
|
|
||||||
TCM_OVERLAY 0x1FFF0000 0x10000{
|
RW_IRAM2 +0 UNINIT FIXED {
|
||||||
lwip_mem.o(.bss*)
|
*rtl8195a_crypto.o(+ZI, COMMON)
|
||||||
lwip_memp.o(.bss*)
|
;*mbedtls*.o(+ZI, COMMON)
|
||||||
|
*libc.a (+ZI, COMMON)
|
||||||
|
*(.bss.thread_stack_main)
|
||||||
|
*lib_peripheral_mbed_arm.ar (+ZI, COMMON)
|
||||||
|
}
|
||||||
|
|
||||||
|
ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
LR_TCM 0x1FFF0000 0x10000 {
|
||||||
|
TCM_OVERLAY 0x1FFF0000 0x10000 {
|
||||||
|
*lwip_mem.o(.bss*)
|
||||||
|
*lwip_memp.o(.bss*)
|
||||||
*.o(.tcm.heap*)
|
*.o(.tcm.heap*)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
LR_DRAM 0x30000000 0x1FFFFF{
|
LR_DRAM 0x30000000 0x200000 {
|
||||||
_DRAM_CODE 0x30000000 0x1FFFFF{
|
|
||||||
|
ER_DRAM +0 FIXED {
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
RW_DRAM1 +0 UNINIT FIXED {
|
||||||
|
.ANY (+RW)
|
||||||
|
}
|
||||||
|
|
||||||
|
RW_DRAM2 +0 UNINIT FIXED {
|
||||||
|
.ANY (+ZI)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -1,24 +1,9 @@
|
||||||
/******************************************************************************
|
/* mbed Microcontroller Library - stackheap
|
||||||
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
|
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* mbed Microcontroller Library - stackheap
|
|
||||||
* Setup a fixed single stack/heap memory model,
|
* Setup a fixed single stack/heap memory model,
|
||||||
* between the top of the RW/ZI region and the stackpointer
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
******************************************************************************/
|
*/
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -26,21 +11,14 @@ extern "C" {
|
||||||
#include <rt_misc.h>
|
#include <rt_misc.h>
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
extern char Image$$RW_IRAM2$$ZI$$Limit[];
|
||||||
|
|
||||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM2$$ZI$$Limit;
|
||||||
uint32_t sp_limit = __current_sp();
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
//push down stack pointer to recycle some of the stack space that are not use in future
|
|
||||||
__asm volatile
|
|
||||||
(
|
|
||||||
"MRS IP, MSP \n"
|
|
||||||
"ADD IP, #64 \n"
|
|
||||||
"BIC IP, IP, #7 \n"
|
|
||||||
"MSR MSP, IP \n"
|
|
||||||
);
|
|
||||||
struct __initial_stackheap r;
|
struct __initial_stackheap r;
|
||||||
r.heap_base = zi_limit;
|
r.heap_base = zi_limit;
|
||||||
r.heap_limit = sp_limit;
|
r.heap_limit = sp_limit;
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -0,0 +1,237 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
INCLUDE "rtl8195a_rom.h"
|
||||||
|
/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
|
||||||
|
But we can put .data/.bss of Image2 in this region */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
|
||||||
|
DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100
|
||||||
|
SRAM1 (rwx) : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000
|
||||||
|
SRAM2 (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Stack sizes: */
|
||||||
|
StackSize = 0x1000;
|
||||||
|
|
||||||
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
* with other linker script that defines memory regions FLASH and RAM.
|
||||||
|
* It references following symbols, which must be defined in code:
|
||||||
|
* _reset_init : Entry of reset handler
|
||||||
|
*
|
||||||
|
* It defines following symbols, which code can use without definition:
|
||||||
|
* __exidx_start
|
||||||
|
* __exidx_end
|
||||||
|
* __etext
|
||||||
|
* __data_start__
|
||||||
|
* __preinit_array_start
|
||||||
|
* __preinit_array_end
|
||||||
|
* __init_array_start
|
||||||
|
* __init_array_end
|
||||||
|
* __fini_array_start
|
||||||
|
* __fini_array_end
|
||||||
|
* __data_end__
|
||||||
|
* __bss_start__
|
||||||
|
* __bss_end__
|
||||||
|
* __end__
|
||||||
|
* end
|
||||||
|
* __HeapLimit
|
||||||
|
* __StackLimit
|
||||||
|
* __StackTop
|
||||||
|
* __stack
|
||||||
|
*/
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.image2.table :
|
||||||
|
{
|
||||||
|
KEEP(*(SORT(.image2.ram.data*)))
|
||||||
|
KEEP(*(.image2.validate.rodata*))
|
||||||
|
} > SRAM2
|
||||||
|
|
||||||
|
.text.sram1 :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*rtl8195a_crypto.o (.text* .rodata*)
|
||||||
|
*mbedtls*.o (.text* .rodata*)
|
||||||
|
*libc.a: (.text* .rodata*)
|
||||||
|
*Ticker.o (.text*)
|
||||||
|
*Timeout.o (.text*)
|
||||||
|
*TimerEvent.o (.text*)
|
||||||
|
*mbed_ticker_api.o (.text*)
|
||||||
|
*mbed_critical.o (.text*)
|
||||||
|
*us_ticker.o (.text*)
|
||||||
|
|
||||||
|
*lib_peripheral_mbed_gcc.a: (.text*)
|
||||||
|
|
||||||
|
} > SRAM1
|
||||||
|
|
||||||
|
.text.sram2 :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.mon.ram.text*)
|
||||||
|
*(.hal.flash.text*)
|
||||||
|
*(.hal.sdrc.text*)
|
||||||
|
*(.hal.gpio.text*)
|
||||||
|
*(.text*)
|
||||||
|
|
||||||
|
KEEP(*(.init))
|
||||||
|
KEEP(*(.fini))
|
||||||
|
|
||||||
|
/* .ctors */
|
||||||
|
*crtbegin.o(.ctors)
|
||||||
|
*crtbegin?.o(.ctors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||||
|
*(SORT(.ctors.*))
|
||||||
|
*(.ctors)
|
||||||
|
|
||||||
|
/* .dtors */
|
||||||
|
*crtbegin.o(.dtors)
|
||||||
|
*crtbegin?.o(.dtors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||||
|
*(SORT(.dtors.*))
|
||||||
|
*(.dtors)
|
||||||
|
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
KEEP(*(.eh_frame*))
|
||||||
|
} > SRAM2
|
||||||
|
__etext = .;
|
||||||
|
|
||||||
|
__data_start__ = .;
|
||||||
|
|
||||||
|
.data.sram1 :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__sram_data_start__ = .;
|
||||||
|
*rtl8195a_crypto*.o (.data*)
|
||||||
|
*mbedtls*.o (.data*)
|
||||||
|
__sram_data_end__ = .;
|
||||||
|
} > SRAM1
|
||||||
|
|
||||||
|
.data.sram2 :
|
||||||
|
{
|
||||||
|
__sdram_data_start__ = .;
|
||||||
|
*(vtable)
|
||||||
|
*(.data*)
|
||||||
|
*(.sdram.data*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* preinit data */
|
||||||
|
PROVIDE (__preinit_array_start = .);
|
||||||
|
KEEP(*(.preinit_array))
|
||||||
|
PROVIDE (__preinit_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* init data */
|
||||||
|
PROVIDE (__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE (__init_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* finit data */
|
||||||
|
PROVIDE (__fini_array_start = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE (__fini_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
__sdram_data_end__ = .;
|
||||||
|
/* All data end */
|
||||||
|
} > SRAM2
|
||||||
|
__data_end__ = .;
|
||||||
|
__image2_end__ = .;
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > SRAM2
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} > SRAM2
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
.bss.sram1 (NOLOAD) :
|
||||||
|
{
|
||||||
|
__bss_sram_start__ = .;
|
||||||
|
*rtl8195a_crypto.o (.bss* COMMON)
|
||||||
|
*mbedtls*.o (.bss* COMMON)
|
||||||
|
*(.bss.thread_stack_main)
|
||||||
|
__bss_sram_end__ = .;
|
||||||
|
} > SRAM1
|
||||||
|
|
||||||
|
.bss.sram2 (NOLOAD) :
|
||||||
|
{
|
||||||
|
__bss_start__ = .;
|
||||||
|
__bss_dram_start__ = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
*(.bdsram.data*)
|
||||||
|
__bss_dram_end__ = .;
|
||||||
|
__bss_end__ = .;
|
||||||
|
} > SRAM2
|
||||||
|
|
||||||
|
.bf_data :
|
||||||
|
{
|
||||||
|
__buffer_data_start__ = .;
|
||||||
|
*(.bfsram.data*)
|
||||||
|
__buffer_data_end__ = .;
|
||||||
|
} > SRAM2
|
||||||
|
|
||||||
|
.heap (NOLOAD):
|
||||||
|
{
|
||||||
|
__end__ = .;
|
||||||
|
end = __end__;
|
||||||
|
*(.heap*)
|
||||||
|
. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
|
||||||
|
__HeapLimit = .;
|
||||||
|
} > SRAM1
|
||||||
|
|
||||||
|
.TCM_overlay :
|
||||||
|
{
|
||||||
|
__bss_dtcm_start__ = .;
|
||||||
|
*lwip_mem.o (.bss*)
|
||||||
|
*lwip_memp.o (.bss*)
|
||||||
|
*(.tcm.heap*)
|
||||||
|
__bss_dtcm_end__ = .;
|
||||||
|
} > TCM
|
||||||
|
|
||||||
|
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||||
|
* used for linker to calculate size of stack sections, and assign
|
||||||
|
* values to stack symbols later */
|
||||||
|
.stack_dummy (NOLOAD):
|
||||||
|
{
|
||||||
|
__StackLimit = .;
|
||||||
|
*(.stack)
|
||||||
|
. += StackSize - (. - __StackLimit);
|
||||||
|
} > SRAM1
|
||||||
|
|
||||||
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
|
* size of stack_dummy section */
|
||||||
|
__StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
|
||||||
|
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||||
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
|
/* Check if data + heap + stack exceeds RAM limit */
|
||||||
|
ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
|
||||||
|
}
|
||||||
|
|
@ -13,11 +13,6 @@
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/*INCLUDE "mbed-os/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/export-rom_v02.txt"*/
|
|
||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
__vectors_table = 0x0;
|
__vectors_table = 0x0;
|
||||||
|
|
@ -28,6 +23,7 @@ SECTIONS
|
||||||
BusFault_Handler = 0x125;
|
BusFault_Handler = 0x125;
|
||||||
UsageFault_Handler = 0x129;
|
UsageFault_Handler = 0x129;
|
||||||
HalLogUartInit = 0x201;
|
HalLogUartInit = 0x201;
|
||||||
|
HalSerialPutcRtl8195a = 0x2d9;
|
||||||
HalSerialGetcRtl8195a = 0x309;
|
HalSerialGetcRtl8195a = 0x309;
|
||||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||||
|
|
@ -171,7 +167,7 @@ SECTIONS
|
||||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||||
HalGdamChInitRtl8195a = 0x5e91;
|
HalGdamChInitRtl8195a = 0x5e91;
|
||||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||||
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
HalGdmaChBlockSetingRtl8195a = 0x60dd;
|
||||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||||
|
|
@ -337,20 +333,30 @@ SECTIONS
|
||||||
_memcmp = 0xf429;
|
_memcmp = 0xf429;
|
||||||
_memcpy = 0xf465;
|
_memcpy = 0xf465;
|
||||||
_memset = 0xf511;
|
_memset = 0xf511;
|
||||||
|
__memcmp = 0xf429;
|
||||||
|
__memcpy = 0xf465;
|
||||||
|
__memset = 0xf511;
|
||||||
Rand = 0xf585;
|
Rand = 0xf585;
|
||||||
_strncpy = 0xf60d;
|
_strncpy = 0xf60d;
|
||||||
_strcpy = 0xf629;
|
_strcpy = 0xf629;
|
||||||
|
__strncpy = 0xf60d;
|
||||||
|
__strcpy = 0xf629;
|
||||||
prvStrCpy = 0xf639;
|
prvStrCpy = 0xf639;
|
||||||
_strlen = 0xf651;
|
_strlen = 0xf651;
|
||||||
_strnlen = 0xf669;
|
_strnlen = 0xf669;
|
||||||
|
__strlen = 0xf651;
|
||||||
|
__strnlen = 0xf669;
|
||||||
prvStrLen = 0xf699;
|
prvStrLen = 0xf699;
|
||||||
_strcmp = 0xf6b1;
|
_strcmp = 0xf6b1;
|
||||||
_strncmp = 0xf6d1;
|
_strncmp = 0xf6d1;
|
||||||
|
__strcmp = 0xf6b1;
|
||||||
|
__strncmp = 0xf6d1;
|
||||||
prvStrCmp = 0xf719;
|
prvStrCmp = 0xf719;
|
||||||
StrUpr = 0xf749;
|
StrUpr = 0xf749;
|
||||||
prvAtoi = 0xf769;
|
prvAtoi = 0xf769;
|
||||||
prvStrStr = 0xf7bd;
|
prvStrStr = 0xf7bd;
|
||||||
_strsep = 0xf7d5;
|
_strsep = 0xf7d5;
|
||||||
|
__strsep = 0xf7d5;
|
||||||
skip_spaces = 0xf815;
|
skip_spaces = 0xf815;
|
||||||
skip_atoi = 0xf831;
|
skip_atoi = 0xf831;
|
||||||
_parse_integer_fixup_radix = 0xf869;
|
_parse_integer_fixup_radix = 0xf869;
|
||||||
|
|
@ -365,8 +371,8 @@ SECTIONS
|
||||||
div_s64 = 0xff99;
|
div_s64 = 0xff99;
|
||||||
div_u64_rem = 0xffa1;
|
div_u64_rem = 0xffa1;
|
||||||
div_s64_rem = 0xffb1;
|
div_s64_rem = 0xffb1;
|
||||||
_strpbrk = 0xffc1;
|
__strpbrk = 0xffc1;
|
||||||
_strchr = 0xffed;
|
__strchr = 0xffed;
|
||||||
aes_set_key = 0x10005;
|
aes_set_key = 0x10005;
|
||||||
aes_encrypt = 0x103d1;
|
aes_encrypt = 0x103d1;
|
||||||
aes_decrypt = 0x114a5;
|
aes_decrypt = 0x114a5;
|
||||||
|
|
@ -613,6 +619,11 @@ SECTIONS
|
||||||
__AES_rcon = 0x30e78;
|
__AES_rcon = 0x30e78;
|
||||||
__AES_Te4 = 0x30ea0;
|
__AES_Te4 = 0x30ea0;
|
||||||
I2CDmaChNo = 0x312a0;
|
I2CDmaChNo = 0x312a0;
|
||||||
|
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||||
|
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||||
|
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||||
|
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||||
|
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||||
UartLogRomCmdTable = 0x316a0;
|
UartLogRomCmdTable = 0x316a0;
|
||||||
_HalRuartOp = 0x31700;
|
_HalRuartOp = 0x31700;
|
||||||
_HalGdmaOp = 0x31760;
|
_HalGdmaOp = 0x31760;
|
||||||
|
|
@ -634,6 +645,90 @@ SECTIONS
|
||||||
rom_wps_rcons = 0x35d88;
|
rom_wps_rcons = 0x35d88;
|
||||||
rom_wps_Td4s = 0x35d94;
|
rom_wps_Td4s = 0x35d94;
|
||||||
rom_wps_Td0 = 0x35e94;
|
rom_wps_Td0 = 0x35e94;
|
||||||
|
__rom_b_cut_end__ = 0x4467c;
|
||||||
|
__rom_c_cut_text_start__ = 0x4467c;
|
||||||
|
HalInitPlatformLogUartV02 = 0x4467d;
|
||||||
|
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||||
|
HalInitPlatformTimerV02 = 0x44755;
|
||||||
|
HalShowBuildInfoV02 = 0x447cd;
|
||||||
|
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||||
|
HalSpiInitV02 = 0x4488d;
|
||||||
|
HalBootFlowV02 = 0x44a29;
|
||||||
|
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||||
|
HalResetVsrV02 = 0x44b41;
|
||||||
|
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||||
|
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||||
|
RtkI2CSendV02 = 0x4508d;
|
||||||
|
RtkI2CReceiveV02 = 0x459a1;
|
||||||
|
HalI2COpInitV02 = 0x461ed;
|
||||||
|
I2CISRHandleV02 = 0x463e9;
|
||||||
|
RtkSalI2COpInitV02 = 0x46be1;
|
||||||
|
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||||
|
SpiFlashAppV02 = 0x46c85;
|
||||||
|
SpicInitRtl8195AV02 = 0x46dc5;
|
||||||
|
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||||
|
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||||
|
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||||
|
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||||
|
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||||
|
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||||
|
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||||
|
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||||
|
HalTimerOpInitV02 = 0x472f9;
|
||||||
|
GPIO_LockV02 = 0x47345;
|
||||||
|
GPIO_UnLockV02 = 0x47379;
|
||||||
|
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||||
|
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||||
|
FindElementIndexV02 = 0x47541;
|
||||||
|
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||||
|
DramInit_rom = 0x47619;
|
||||||
|
ChangeRandSeed_rom = 0x47979;
|
||||||
|
Sdr_Rand2_rom = 0x47985;
|
||||||
|
MemTest_rom = 0x479dd;
|
||||||
|
SdrCalibration_rom = 0x47a45;
|
||||||
|
SdrControllerInit_rom = 0x47d99;
|
||||||
|
SDIO_EnterCritical = 0x47e39;
|
||||||
|
SDIO_ExitCritical = 0x47e85;
|
||||||
|
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||||
|
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||||
|
SDIO_Device_Init_Rom = 0x47f81;
|
||||||
|
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||||
|
SDIO_Device_DeInit_Rom = 0x48255;
|
||||||
|
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||||
|
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||||
|
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||||
|
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||||
|
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||||
|
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||||
|
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||||
|
SDIO_RxTask_Rom = 0x4851d;
|
||||||
|
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||||
|
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||||
|
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||||
|
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||||
|
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||||
|
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||||
|
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||||
|
SDIO_ReadMem_Rom = 0x488fd;
|
||||||
|
SDIO_WriteMem_Rom = 0x489a9;
|
||||||
|
SDIO_SetMem_Rom = 0x48a69;
|
||||||
|
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||||
|
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||||
|
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||||
|
SDIO_TxTask_Rom = 0x48e9d;
|
||||||
|
SDIO_TaskUp_Rom = 0x48eed;
|
||||||
|
SDIO_Boot_Up = 0x48f55;
|
||||||
|
__rom_c_cut_text_end__ = 0x49070;
|
||||||
|
__rom_c_cut_rodata_start__ = 0x49070;
|
||||||
|
BAUDRATE_v02 = 0x49070;
|
||||||
|
OVSR_v02 = 0x490fc;
|
||||||
|
DIV_v02 = 0x49188;
|
||||||
|
OVSR_ADJ_v02 = 0x49214;
|
||||||
|
SdrDramInfo_rom = 0x492a0;
|
||||||
|
SdrDramTiming_rom = 0x492b4;
|
||||||
|
SdrDramModeReg_rom = 0x492e8;
|
||||||
|
SdrDramDev_rom = 0x49304;
|
||||||
|
__rom_c_cut_rodata_end__ = 0x49314;
|
||||||
NewVectorTable = 0x10000000;
|
NewVectorTable = 0x10000000;
|
||||||
UserIrqFunTable = 0x10000100;
|
UserIrqFunTable = 0x10000100;
|
||||||
UserIrqDataTable = 0x10000200;
|
UserIrqDataTable = 0x10000200;
|
||||||
|
|
@ -661,193 +756,4 @@ SECTIONS
|
||||||
DM_CfoTrack = 0x10000738;
|
DM_CfoTrack = 0x10000738;
|
||||||
rom_libgloss_ram_map = 0x10000760;
|
rom_libgloss_ram_map = 0x10000760;
|
||||||
__rtl_errno = 0x10000bc4;
|
__rtl_errno = 0x10000bc4;
|
||||||
_rtl_impure_ptr = 0x10001c60;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
|
|
||||||
But we can put .data/.bss of Image2 in this region */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
|
|
||||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 0x10006000-0x10000bc8
|
|
||||||
DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10006000 - 0x10002100
|
|
||||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 0x10070000 - 0x10006000
|
|
||||||
SD_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
|
||||||
* with other linker script that defines memory regions FLASH and RAM.
|
|
||||||
* It references following symbols, which must be defined in code:
|
|
||||||
* _reset_init : Entry of reset handler
|
|
||||||
*
|
|
||||||
* It defines following symbols, which code can use without definition:
|
|
||||||
* __exidx_start
|
|
||||||
* __exidx_end
|
|
||||||
* __etext
|
|
||||||
* __data_start__
|
|
||||||
* __preinit_array_start
|
|
||||||
* __preinit_array_end
|
|
||||||
* __init_array_start
|
|
||||||
* __init_array_end
|
|
||||||
* __fini_array_start
|
|
||||||
* __fini_array_end
|
|
||||||
* __data_end__
|
|
||||||
* __bss_start__
|
|
||||||
* __bss_end__
|
|
||||||
* __end__
|
|
||||||
* end
|
|
||||||
* __HeapLimit
|
|
||||||
* __StackLimit
|
|
||||||
* __StackTop
|
|
||||||
* __stack
|
|
||||||
*/
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__rom_bss_start__ = 0x10000300;
|
|
||||||
__rom_bss_end__ = 0x10000bc8;
|
|
||||||
__ram_table_start__ = 0x10000bc8;
|
|
||||||
/*
|
|
||||||
.ram.start.table :
|
|
||||||
{
|
|
||||||
|
|
||||||
} > ROM_USED_RAM
|
|
||||||
*/
|
|
||||||
.image2.table :
|
|
||||||
{
|
|
||||||
__image2_start__ = .;
|
|
||||||
__image2_entry_func__ = .;
|
|
||||||
KEEP(*(SORT(.image2.ram.data*)))
|
|
||||||
__image2_validate_code__ = .;
|
|
||||||
KEEP(*(.image2.validate.rodata*))
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.infra.ram.start*)
|
|
||||||
*(.mon.ram.text*)
|
|
||||||
*(.hal.flash.text*)
|
|
||||||
*(.hal.sdrc.text*)
|
|
||||||
*(.hal.gpio.text*)
|
|
||||||
*(.text*)
|
|
||||||
|
|
||||||
KEEP(*(.init))
|
|
||||||
KEEP(*(.fini))
|
|
||||||
|
|
||||||
/* .ctors */
|
|
||||||
*crtbegin.o(.ctors)
|
|
||||||
*crtbegin?.o(.ctors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
|
||||||
*(SORT(.ctors.*))
|
|
||||||
*(.ctors)
|
|
||||||
|
|
||||||
/* .dtors */
|
|
||||||
*crtbegin.o(.dtors)
|
|
||||||
*crtbegin?.o(.dtors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
|
||||||
*(SORT(.dtors.*))
|
|
||||||
*(.dtors)
|
|
||||||
*(.rodata*)
|
|
||||||
KEEP(*(.eh_frame*))
|
|
||||||
} > BD_RAM
|
|
||||||
__etext = .;
|
|
||||||
|
|
||||||
|
|
||||||
__data_start__ = .;
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(vtable)
|
|
||||||
*(.data*)
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* preinit data */
|
|
||||||
PROVIDE (__preinit_array_start = .);
|
|
||||||
KEEP(*(.preinit_array))
|
|
||||||
PROVIDE (__preinit_array_end = .);
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* init data */
|
|
||||||
PROVIDE (__init_array_start = .);
|
|
||||||
KEEP(*(SORT(.init_array.*)))
|
|
||||||
KEEP(*(.init_array))
|
|
||||||
PROVIDE (__init_array_end = .);
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* finit data */
|
|
||||||
PROVIDE (__fini_array_start = .);
|
|
||||||
KEEP(*(SORT(.fini_array.*)))
|
|
||||||
KEEP(*(.fini_array))
|
|
||||||
PROVIDE (__fini_array_end = .);
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
/* All data end */
|
|
||||||
} > BD_RAM
|
|
||||||
__data_end__ = .;
|
|
||||||
__image2_end__ = .;
|
|
||||||
|
|
||||||
.ARM.extab :
|
|
||||||
{
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
__exidx_start = .;
|
|
||||||
.ARM.exidx :
|
|
||||||
{
|
|
||||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
|
||||||
} > BD_RAM
|
|
||||||
__exidx_end = .;
|
|
||||||
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
__bss_start__ = .;
|
|
||||||
*(.bss*)
|
|
||||||
*(.bdsram.data*)
|
|
||||||
*(COMMON)
|
|
||||||
__bss_end__ = .;
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
|
|
||||||
.bf_data :
|
|
||||||
{
|
|
||||||
__buffer_data_start__ = .;
|
|
||||||
*(.bfsram.data*)
|
|
||||||
__buffer_data_end__ = .;
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
.heap :
|
|
||||||
{
|
|
||||||
__end__ = .;
|
|
||||||
end = __end__;
|
|
||||||
*(.heap*)
|
|
||||||
__HeapLimit = .;
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
.TCM_overlay :
|
|
||||||
{
|
|
||||||
*lwip_mem.o (.bss*)
|
|
||||||
*lwip_memp.o (.bss*)
|
|
||||||
*(.tcm.heap*)
|
|
||||||
} > TCM
|
|
||||||
|
|
||||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
|
||||||
* used for linker to calculate size of stack sections, and assign
|
|
||||||
* values to stack symbols later */
|
|
||||||
.stack_dummy :
|
|
||||||
{
|
|
||||||
*(.stack)
|
|
||||||
} > BD_RAM
|
|
||||||
|
|
||||||
/* Set stack top to end of RAM, and stack limit move down by
|
|
||||||
* size of stack_dummy section */
|
|
||||||
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
|
|
||||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
|
||||||
PROVIDE(__stack = __StackTop);
|
|
||||||
|
|
||||||
/* Check if data + heap + stack exceeds RAM limit */
|
|
||||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
Binary file not shown.
|
|
@ -16,7 +16,7 @@ define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
|
||||||
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
|
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
|
||||||
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
|
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
|
||||||
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
|
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
|
||||||
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000;
|
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10007000;
|
||||||
}
|
}
|
||||||
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
|
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
|
||||||
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
|
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
|
||||||
|
|
@ -120,6 +120,7 @@ place at start of ROM_USED_RAM_region {
|
||||||
block IMAGE1
|
block IMAGE1
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
keep { section .image2.ram.data* };
|
keep { section .image2.ram.data* };
|
||||||
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
|
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
|
||||||
|
|
||||||
|
|
@ -135,61 +136,161 @@ define block CPP_INIT with alignment = 8, fixed order {
|
||||||
define block FPB_REMAP with alignment = 256,fixed order {
|
define block FPB_REMAP with alignment = 256,fixed order {
|
||||||
section .fpb.remap*
|
section .fpb.remap*
|
||||||
};
|
};
|
||||||
define block .ram_image2.text with fixed order{ section .infra.ram.start*,
|
|
||||||
section .rodata*,
|
define block MBEDTLS_TEXT with alignment = 8, fixed order{
|
||||||
block CPP_INIT,
|
section .text* object aes.o,
|
||||||
|
section .text* object aesni.o,
|
||||||
|
section .text* object arc4.o,
|
||||||
|
section .text* object asn1parse.o,
|
||||||
|
section .text* object asn1write.o,
|
||||||
|
section .text* object base64.o,
|
||||||
|
section .text* object bignum.o,
|
||||||
|
section .text* object blowfish.o,
|
||||||
|
section .text* object camellia.o,
|
||||||
|
section .text* object ccm.o,
|
||||||
|
section .text* object certs.o,
|
||||||
|
section .text* object cipher.o,
|
||||||
|
section .text* object cipher_wrap.o,
|
||||||
|
section .text* object cmac.o,
|
||||||
|
section .text* object ctr_drbg.o,
|
||||||
|
section .text* object debug.o,
|
||||||
|
section .text* object des.o,
|
||||||
|
section .text* object dhm.o,
|
||||||
|
section .text* object ecdh.o,
|
||||||
|
section .text* object ecdsa.o,
|
||||||
|
section .text* object ecjpake.o,
|
||||||
|
section .text* object ecp.o,
|
||||||
|
section .text* object ecp_curves.o,
|
||||||
|
section .text* object entropy.o,
|
||||||
|
section .text* object entropy_poll.o,
|
||||||
|
section .text* object error.o,
|
||||||
|
section .text* object gcm.o,
|
||||||
|
section .text* object havege.o,
|
||||||
|
section .text* object hmac_drbg.o,
|
||||||
|
section .text* object md.o,
|
||||||
|
section .text* object md2.o,
|
||||||
|
section .text* object md4.o,
|
||||||
|
section .text* object md5.o,
|
||||||
|
section .text* object md_wrap.o,
|
||||||
|
section .text* object memory_buffer_alloc.o,
|
||||||
|
section .text* object net_sockets.o,
|
||||||
|
section .text* object oid.o,
|
||||||
|
section .text* object padlock.o,
|
||||||
|
section .text* object pem.o,
|
||||||
|
section .text* object pk.o,
|
||||||
|
section .text* object pk_wrap.o,
|
||||||
|
section .text* object pkcs11.o,
|
||||||
|
section .text* object pkcs12.o,
|
||||||
|
section .text* object pkcs5.o,
|
||||||
|
section .text* object pkparse.o,
|
||||||
|
section .text* object pkwrite.o,
|
||||||
|
section .text* object platform.o,
|
||||||
|
section .text* object ripemd160.o,
|
||||||
|
section .text* object rsa.o,
|
||||||
|
section .text* object sha1.o,
|
||||||
|
section .text* object sha256.o,
|
||||||
|
section .text* object sha512.o,
|
||||||
|
section .text* object ssl_cache.o,
|
||||||
|
section .text* object ssl_ciphersuites.o,
|
||||||
|
section .text* object ssl_cli.o,
|
||||||
|
section .text* object ssl_cookie.o,
|
||||||
|
section .text* object ssl_srv.o,
|
||||||
|
section .text* object ssl_ticket.o,
|
||||||
|
section .text* object ssl_tls.o,
|
||||||
|
section .text* object threading.o,
|
||||||
|
section .text* object timing.o,
|
||||||
|
section .text* object version.o,
|
||||||
|
section .text* object version_features.o,
|
||||||
|
section .text* object x509.o,
|
||||||
|
section .text* object x509_create.o,
|
||||||
|
section .text* object x509_crl.o,
|
||||||
|
section .text* object x509_crt.o,
|
||||||
|
section .text* object x509_csr.o,
|
||||||
|
section .text* object x509write_crt.o,
|
||||||
|
section .text* object x509write_csr.o,
|
||||||
|
section .text* object xtea.o,
|
||||||
|
};
|
||||||
|
|
||||||
|
define block .sram1.text with fixed order {
|
||||||
|
block MBEDTLS_TEXT,
|
||||||
|
section .text* object Ticker.o,
|
||||||
|
section .text* object Timeout.o,
|
||||||
|
section .text* object TimerEvent.o,
|
||||||
|
section .text* object mbed_ticker_api.o,
|
||||||
|
section .text* object mbed_critical.o,
|
||||||
|
section .text* object us_ticker.o,
|
||||||
|
|
||||||
|
section .text* object lib_peripheral_mbed_iar.a,
|
||||||
|
};
|
||||||
|
|
||||||
|
define block .sram2.text with fixed order {
|
||||||
|
block .image2.start.table1,
|
||||||
|
block .image2.start.table2,
|
||||||
section .mon.ram.text*,
|
section .mon.ram.text*,
|
||||||
section .hal.flash.text*,
|
section .hal.flash.text*,
|
||||||
|
section .hal.sdrc.text*,
|
||||||
section .hal.gpio.text*,
|
section .hal.gpio.text*,
|
||||||
section .text* object main.o,
|
|
||||||
section .text*,
|
section .text*,
|
||||||
section .wlan.text,
|
section .infra.ram.start*,
|
||||||
section .wps.text,
|
section .rodata*,
|
||||||
|
};
|
||||||
|
|
||||||
|
define block .sram2.data with fixed order {
|
||||||
|
//section .infra.ram.start*,
|
||||||
|
//section .rodata*,
|
||||||
|
//section .wlan.text,
|
||||||
|
//section .wps.text,
|
||||||
section CODE,
|
section CODE,
|
||||||
section .otg.rom.text,
|
//section .otg.rom.text,
|
||||||
section Veneer object startup.o,
|
section Veneer object startup.o,
|
||||||
section __DLIB_PERTHREAD,
|
section __DLIB_PERTHREAD,
|
||||||
section .iar.dynexit*,
|
section .iar.dynexit*,
|
||||||
|
block CPP_INIT,
|
||||||
//section .mdns.text
|
//section .mdns.text
|
||||||
};
|
};
|
||||||
|
define block .ram.data with fixed order {
|
||||||
define block .ram.data with fixed order{ readwrite, readonly,
|
readwrite, readonly,
|
||||||
section .data*,
|
section .data*,
|
||||||
section .wlan.data,
|
section .wlan.data,
|
||||||
section .wps.data,
|
section .wps.data,
|
||||||
section DATA,
|
section DATA,
|
||||||
section .ram.otg.data.a,
|
section .ram.otg.data.a,
|
||||||
section .iar.init_table,
|
section .iar.init_table,
|
||||||
//section .mdns.data
|
//section .mdns.data,
|
||||||
|
//section .data* object lib_peripheral_mbed_iar.a,
|
||||||
};
|
};
|
||||||
|
|
||||||
define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
|
define block .ram.bss with fixed order {
|
||||||
|
section .bss*,
|
||||||
define block .ram.bss with fixed order{ section .bss*,
|
|
||||||
section .ssl_ram_map,
|
|
||||||
section .hal.flash.data*,
|
|
||||||
section .hal.gpio.data*,
|
|
||||||
section COMMON,
|
section COMMON,
|
||||||
section .bdsram.data*,
|
section .bdsram.data*,
|
||||||
section .bss* object heap_4.o
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
define block IMAGE2 with fixed order {
|
||||||
|
block .sram1.text,
|
||||||
|
block .ram.data,
|
||||||
|
block .ram.bss
|
||||||
|
};
|
||||||
|
|
||||||
define block .bf_data with fixed order{ section .bfsram.data* };
|
define block .bf_data with fixed order{ section .bfsram.data* };
|
||||||
define block .heap with fixed order{ section .heap* };
|
define block .heap with fixed order{ section .heap* };
|
||||||
define block .stack_dummy with fixed order { section .stack };
|
define block .stack_dummy with fixed order { section .stack };
|
||||||
place at start of BD_RAM_region {
|
place at start of BD_RAM_region {
|
||||||
block IMAGE2,
|
block IMAGE2,
|
||||||
//block IMAGE1_DBG,
|
//block IMAGE1_DBG,
|
||||||
block .ram.bss,
|
//block .ram.bss,
|
||||||
//block .bf_data,
|
//block .bf_data,
|
||||||
};
|
};
|
||||||
|
|
||||||
//place at address mem:0x10052b00 { readwrite,
|
|
||||||
place at end of BD_RAM_region {
|
place at end of BD_RAM_region {
|
||||||
block .bf_data,
|
block .bf_data,
|
||||||
block HEAP,
|
block HEAP,
|
||||||
};
|
};
|
||||||
|
|
||||||
define block SDRAM with fixed order{ section .sdram.text*,
|
define block SDRAM with fixed order {
|
||||||
|
block .sram2.text,
|
||||||
|
block .sram2.data,
|
||||||
|
section .sdram.text*,
|
||||||
section .sdram.data*,
|
section .sdram.data*,
|
||||||
section .mdns.text*,
|
section .mdns.text*,
|
||||||
section .mdns.data*,
|
section .mdns.data*,
|
||||||
|
|
|
||||||
|
|
@ -186,7 +186,7 @@
|
||||||
#define CONFIG_UART_LOG_HISTORY 1
|
#define CONFIG_UART_LOG_HISTORY 1
|
||||||
#undef CONFIG_CONSOLE_NORMALL_MODE
|
#undef CONFIG_CONSOLE_NORMALL_MODE
|
||||||
#define CONFIG_CONSOLE_VERIFY_MODE 1
|
#define CONFIG_CONSOLE_VERIFY_MODE 1
|
||||||
#define CONFIG_DEBUG_LOG 1
|
#undef CONFIG_DEBUG_LOG
|
||||||
#define CONFIG_DEBUG_ERR_MSG 1
|
#define CONFIG_DEBUG_ERR_MSG 1
|
||||||
#undef CONFIG_DEBUG_WARN_MSG
|
#undef CONFIG_DEBUG_WARN_MSG
|
||||||
#undef CONFIG_DEBUG_INFO_MSG
|
#undef CONFIG_DEBUG_INFO_MSG
|
||||||
|
|
|
||||||
|
|
@ -14,26 +14,39 @@
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
#include "rtl8195a.h"
|
#include "rtl8195a.h"
|
||||||
#include "system_8195a.h"
|
|
||||||
#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */
|
|
||||||
extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
|
|
||||||
#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
|
|
||||||
extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
|
|
||||||
#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
|
|
||||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */
|
|
||||||
extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
|
|
||||||
#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
|
|
||||||
extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
|
|
||||||
#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
#if defined(__CC_ARM)
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
#else
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__CC_ARM) || \
|
||||||
|
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
|
||||||
|
|
||||||
|
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
|
||||||
|
extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
|
||||||
|
extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
|
||||||
|
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
|
||||||
|
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
|
||||||
|
extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
|
||||||
|
extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
|
||||||
|
#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
|
||||||
|
#define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
|
||||||
|
#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
|
||||||
|
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
|
||||||
|
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
|
||||||
|
#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
|
||||||
|
#define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||||
|
|
||||||
|
#elif defined (__ICCARM__)
|
||||||
|
|
||||||
#pragma section=".ram.bss"
|
#pragma section=".ram.bss"
|
||||||
#pragma section=".rom.bss"
|
|
||||||
#pragma section=".ram.start.table"
|
|
||||||
#pragma section=".ram_image1.bss"
|
|
||||||
#pragma section=".image2.start.table1"
|
|
||||||
#pragma section=".image2.start.table2"
|
|
||||||
|
|
||||||
|
extern uint32_t CSTACK$$Limit;
|
||||||
uint8_t *__bss_start__;
|
uint8_t *__bss_start__;
|
||||||
uint8_t *__bss_end__;
|
uint8_t *__bss_end__;
|
||||||
|
|
||||||
|
|
@ -42,30 +55,34 @@ void __iar_data_init_app(void)
|
||||||
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
|
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
|
||||||
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
|
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
|
||||||
}
|
}
|
||||||
|
#define __stackp CSTACK$$Limit
|
||||||
|
|
||||||
#else
|
#else
|
||||||
extern uint8_t __bss_start__[];
|
|
||||||
extern uint8_t __bss_end__[];
|
extern uint32_t __StackTop;
|
||||||
extern uint8_t __image1_bss_start__[];
|
extern uint32_t __StackLimit;
|
||||||
extern uint8_t __image1_bss_end__[];
|
extern uint8_t __bss_sram_start__[];
|
||||||
extern uint8_t __image2_entry_func__[];
|
extern uint8_t __bss_sram_end__[];
|
||||||
extern uint8_t __image2_validate_code__[];
|
extern uint8_t __bss_dtcm_start__[];
|
||||||
|
extern uint8_t __bss_dtcm_end__[];
|
||||||
|
extern uint8_t __bss_dram_start__[];
|
||||||
|
extern uint8_t __bss_dram_end__[];
|
||||||
|
|
||||||
|
#define __stackp __StackTop
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
extern VECTOR_Func NewVectorTable[];
|
extern VECTOR_Func NewVectorTable[];
|
||||||
extern void SystemCoreClockUpdate(void);
|
extern void SystemCoreClockUpdate(void);
|
||||||
extern void PLAT_Start(void);
|
extern void PLAT_Start(void);
|
||||||
extern void PLAT_Main(void);
|
extern void PLAT_Main(void);
|
||||||
extern HAL_TIMER_OP HalTimerOp;
|
|
||||||
|
|
||||||
IMAGE2_START_RAM_FUN_SECTION const RAM_START_FUNCTION gImage2EntryFun0 = {
|
IMAGE2_START_RAM_FUN_SECTION
|
||||||
|
const RAM_START_FUNCTION gImage2EntryFun0 = {
|
||||||
PLAT_Start
|
PLAT_Start
|
||||||
};
|
};
|
||||||
|
|
||||||
IMAGE1_VALID_PATTEN_SECTION const uint8_t RAM_IMG1_VALID_PATTEN[] = {
|
IMAGE2_VALID_PATTEN_SECTION
|
||||||
0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff
|
const uint8_t IMAGE2_SIGNATURE[20] = {
|
||||||
};
|
|
||||||
|
|
||||||
IMAGE2_VALID_PATTEN_SECTION const uint8_t RAM_IMG2_VALID_PATTEN[20] = {
|
|
||||||
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
|
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
|
||||||
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
|
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
|
||||||
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
|
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
|
||||||
|
|
@ -93,7 +110,7 @@ void TRAP_NMIHandler(void)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined (__ICCARM__)
|
||||||
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
|
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
|
||||||
{
|
{
|
||||||
uint32_t cfsr;
|
uint32_t cfsr;
|
||||||
|
|
@ -154,96 +171,63 @@ void TRAP_HardFaultHandler_Patch(void)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Override original Interrupt Vector Table
|
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
|
||||||
INFRA_START_SECTION void TRAP_OverrideTable(uint32_t stackp)
|
// Image2 Entry Function
|
||||||
{
|
void PLAT_Start(void)
|
||||||
// Override NMI Handler
|
|
||||||
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
INFRA_START_SECTION void PLAT_Init(void)
|
|
||||||
{
|
{
|
||||||
uint32_t val;
|
uint32_t val;
|
||||||
|
|
||||||
//Set SPS lower voltage
|
#if defined (__ICCARM__)
|
||||||
|
__iar_data_init_app();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Clear RAM BSS
|
||||||
|
#if defined (__ICCARM__)
|
||||||
|
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
|
||||||
|
#else
|
||||||
|
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
|
||||||
|
__rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
|
||||||
|
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Set MSP
|
||||||
|
__set_MSP((uint32_t)&__stackp - 0x100);
|
||||||
|
// Overwrite vector table
|
||||||
|
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern HAL_TIMER_OP_EXT HalTimerOpExt;
|
||||||
|
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
|
||||||
|
__rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
|
||||||
|
|
||||||
|
HalTimerOpInit_Patch(&HalTimerOp);
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
// Set SPS lower voltage
|
||||||
val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
|
val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
|
||||||
val &= 0xf0ffffff;
|
val &= 0xf0ffffff;
|
||||||
val |= 0x6000000;
|
val |= 0x6000000;
|
||||||
__RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
|
__RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
|
||||||
|
|
||||||
//xtal buffer driving current
|
// xtal buffer driving current
|
||||||
val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
|
val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
|
||||||
val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
|
val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
|
||||||
val |= BIT_SYS_XTAL_DRV_RF1(1);
|
val |= BIT_SYS_XTAL_DRV_RF1(1);
|
||||||
__RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
|
__RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
|
||||||
}
|
|
||||||
|
|
||||||
//3 Image 2
|
// Initialize SPIC, then disable it for power saving.
|
||||||
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
|
|
||||||
|
|
||||||
//extern uint32_t mbed_stack_isr_start;
|
|
||||||
//extern uint32_t mbed_stack_isr_size;
|
|
||||||
INFRA_START_SECTION void PLAT_Start(void)
|
|
||||||
{
|
|
||||||
u8 isFlashEn;
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
__iar_data_init_app();
|
|
||||||
#endif
|
|
||||||
// Clear RAM BSS
|
|
||||||
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
|
|
||||||
|
|
||||||
TRAP_OverrideTable(0x1FFFFFFC);
|
|
||||||
/* add by Ian --for mbed isr stack address setting */
|
|
||||||
__set_MSP(0x1fffffbc);
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPIC_MODULE
|
|
||||||
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
|
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
|
||||||
isFlashEn = 1;
|
|
||||||
} else {
|
|
||||||
isFlashEn = 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_TIMER_MODULE
|
|
||||||
HalTimerOpInit_Patch(&HalTimerOp);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//DBG_8195A("===== Enter Image 2 ====\n");
|
|
||||||
|
|
||||||
|
|
||||||
SystemCoreClockUpdate();
|
|
||||||
|
|
||||||
if (isFlashEn) {
|
|
||||||
#if CONFIG_SPIC_EN && SPIC_CALIBRATION_IN_NVM
|
|
||||||
SpicNVMCalLoadAll();
|
SpicNVMCalLoadAll();
|
||||||
#endif
|
|
||||||
SpicReadIDRtl8195A();
|
SpicReadIDRtl8195A();
|
||||||
// turn off SPIC for power saving
|
|
||||||
SpicDisableRtl8195A();
|
SpicDisableRtl8195A();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
PLAT_Init();
|
|
||||||
#ifdef CONFIG_TIMER_MODULE
|
#ifdef CONFIG_TIMER_MODULE
|
||||||
Calibration32k();
|
Calibration32k();
|
||||||
|
|
||||||
#ifdef CONFIG_WDG
|
|
||||||
#ifdef CONFIG_WDG_TEST
|
|
||||||
WDGInit();
|
|
||||||
#endif //CONFIG_WDG_TEST
|
|
||||||
#endif //CONFIG_WDG
|
|
||||||
#endif //CONFIG_TIMER_MODULE
|
|
||||||
|
|
||||||
#ifdef CONFIG_SOC_PS_MODULE
|
|
||||||
//InitSoCPM();
|
|
||||||
#endif
|
#endif
|
||||||
/* GPIOA_7 does not pull high at power on. It causes SDIO Device
|
|
||||||
* hardware to enable automatically and occupy GPIOA[7:0] */
|
|
||||||
#ifndef CONFIG_SDIO_DEVICE_EN
|
#ifndef CONFIG_SDIO_DEVICE_EN
|
||||||
SDIO_DEV_Disable();
|
SDIO_DEV_Disable();
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -256,6 +240,7 @@ extern void SVC_Handler(void);
|
||||||
extern void PendSV_Handler(void);
|
extern void PendSV_Handler(void);
|
||||||
extern void SysTick_Handler(void);
|
extern void SysTick_Handler(void);
|
||||||
|
|
||||||
|
// The Main App entry point
|
||||||
#if defined (__CC_ARM)
|
#if defined (__CC_ARM)
|
||||||
__asm void ARM_PLAT_Main(void)
|
__asm void ARM_PLAT_Main(void)
|
||||||
{
|
{
|
||||||
|
|
@ -264,29 +249,32 @@ __asm void ARM_PLAT_Main(void)
|
||||||
BL SystemInit
|
BL SystemInit
|
||||||
BL __main
|
BL __main
|
||||||
}
|
}
|
||||||
|
#elif defined (__ICCARM__)
|
||||||
|
extern void __iar_program_start(void);
|
||||||
|
|
||||||
|
void IAR_PLAT_Main(void)
|
||||||
|
{
|
||||||
|
SystemInit();
|
||||||
|
__iar_program_start();
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
extern void __iar_program_start( void );
|
|
||||||
// The Main App entry point
|
|
||||||
void PLAT_Main(void)
|
void PLAT_Main(void)
|
||||||
{
|
{
|
||||||
TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
|
TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
|
||||||
|
|
||||||
#if defined (__ICCARM__)
|
#if defined (__CC_ARM)
|
||||||
//IAR_PLAT_Main();
|
|
||||||
SystemInit();
|
|
||||||
__iar_program_start();
|
|
||||||
#elif defined (__CC_ARM)
|
|
||||||
ARM_PLAT_Main();
|
ARM_PLAT_Main();
|
||||||
|
#elif defined (__ICCARM__)
|
||||||
#elif defined (__GNUC__)
|
IAR_PLAT_Main();
|
||||||
__asm (
|
#else
|
||||||
"ldr r0, =SystemInit \n"
|
__asm ("ldr r0, =SystemInit \n"
|
||||||
"blx r0 \n"
|
"blx r0 \n"
|
||||||
"ldr r0, =_start \n"
|
"ldr r0, =_start \n"
|
||||||
"bx r0 \n"
|
"bx r0 \n"
|
||||||
);
|
);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Never reached
|
// Never reached
|
||||||
for(;;);
|
for (;;);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -15,7 +15,7 @@
|
||||||
#define _RTL8195A_TIMER_H_
|
#define _RTL8195A_TIMER_H_
|
||||||
|
|
||||||
|
|
||||||
#define TIMER_TICK_US 31
|
#define TIMER_TICK_US 32
|
||||||
|
|
||||||
#define TIMER_LOAD_COUNT_OFF 0x00
|
#define TIMER_LOAD_COUNT_OFF 0x00
|
||||||
#define TIMER_CURRENT_VAL_OFF 0x04
|
#define TIMER_CURRENT_VAL_OFF 0x04
|
||||||
|
|
|
||||||
|
|
@ -113,12 +113,10 @@ void analogin_init (analogin_t *obj, PinName pin)
|
||||||
|
|
||||||
/* Load user setting */
|
/* Load user setting */
|
||||||
if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) {
|
if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) {
|
||||||
DBG_8195A("K\n");
|
|
||||||
pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian;
|
pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) {
|
if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) {
|
||||||
DBG_8195A("O\n");
|
|
||||||
pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn;
|
pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,154 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "mbed_wait_api.h"
|
||||||
|
|
||||||
|
#include "rtl8195a.h"
|
||||||
|
#include "flash_ext.h"
|
||||||
|
|
||||||
|
#define FLASH_TOP 0x200000
|
||||||
|
#define FLASH_SECTOR_SIZE 0x1000
|
||||||
|
#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
|
||||||
|
#define OTA_REGION1 0x0b000
|
||||||
|
#define OTA_REGION2 0xc0000
|
||||||
|
#define TAG_OFS 0xc
|
||||||
|
#define VER_OFS 0x10
|
||||||
|
|
||||||
|
#define TAG_DOWNLOAD 0x81950001
|
||||||
|
#define TAG_VERIFIED 0x81950003
|
||||||
|
|
||||||
|
static flash_t flash_obj;
|
||||||
|
|
||||||
|
typedef struct imginfo_s {
|
||||||
|
uint32_t base;
|
||||||
|
uint32_t tag;
|
||||||
|
uint64_t ver;
|
||||||
|
} imginfo_t;
|
||||||
|
|
||||||
|
|
||||||
|
void OTA_GetImageInfo(imginfo_t *info)
|
||||||
|
{
|
||||||
|
uint32_t ver_hi, ver_lo;
|
||||||
|
|
||||||
|
flash_ext_read_word(&flash_obj, info->base + TAG_OFS, &info->tag);
|
||||||
|
flash_ext_read_word(&flash_obj, info->base + VER_OFS, &ver_lo);
|
||||||
|
flash_ext_read_word(&flash_obj, info->base + VER_OFS + 4, &ver_hi);
|
||||||
|
|
||||||
|
if (info->tag == TAG_DOWNLOAD) {
|
||||||
|
info->ver = ((uint64_t)ver_hi << 32) | (uint64_t) ver_lo;
|
||||||
|
} else {
|
||||||
|
info->ver = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t OTA_GetBase(void)
|
||||||
|
{
|
||||||
|
static uint32_t ota_base = 0;
|
||||||
|
imginfo_t region1, region2;
|
||||||
|
|
||||||
|
if (ota_base == OTA_REGION1 || ota_base == OTA_REGION2) {
|
||||||
|
return ota_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
region1.base = OTA_REGION1;
|
||||||
|
region2.base = OTA_REGION2;
|
||||||
|
|
||||||
|
OTA_GetImageInfo(®ion1);
|
||||||
|
OTA_GetImageInfo(®ion2);
|
||||||
|
|
||||||
|
if (region1.ver >= region2.ver) {
|
||||||
|
ota_base = region2.base;
|
||||||
|
} else {
|
||||||
|
ota_base = region1.base;
|
||||||
|
}
|
||||||
|
return ota_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t OTA_MarkUpdateDone(void)
|
||||||
|
{
|
||||||
|
uint32_t addr = OTA_GetBase() + TAG_OFS;
|
||||||
|
|
||||||
|
return flash_ext_write_word(&flash_obj, addr, TAG_DOWNLOAD);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
|
||||||
|
{
|
||||||
|
uint32_t addr, start, end, count, shift;
|
||||||
|
uint8_t *pdata = data;
|
||||||
|
uint8_t buf[FLASH_SECTOR_SIZE];
|
||||||
|
|
||||||
|
start = OTA_GetBase() + offset;
|
||||||
|
end = start + len;
|
||||||
|
|
||||||
|
if (data == NULL || start > FLASH_TOP || end > FLASH_TOP) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
addr = start & FLASH_SECTOR_MASK;
|
||||||
|
if (addr != start) {
|
||||||
|
shift = start - addr;
|
||||||
|
count = MIN(FLASH_SECTOR_SIZE - shift, len);
|
||||||
|
flash_ext_stream_read(&flash_obj, addr, shift, buf);
|
||||||
|
memcpy((void *)(buf + shift), (void *)pdata, count);
|
||||||
|
|
||||||
|
flash_ext_erase_sector(&flash_obj, addr);
|
||||||
|
flash_ext_stream_write(&flash_obj, addr, FLASH_SECTOR_SIZE, buf);
|
||||||
|
addr += FLASH_SECTOR_SIZE;
|
||||||
|
pdata += count;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (addr < end) {
|
||||||
|
printf("OTA: update addr=0x%lx, len=%ld\r\n", addr, len);
|
||||||
|
count = MIN(FLASH_SECTOR_SIZE, end - addr);
|
||||||
|
flash_ext_erase_sector(&flash_obj, addr);
|
||||||
|
flash_ext_stream_write(&flash_obj, addr, count, pdata);
|
||||||
|
addr += FLASH_SECTOR_SIZE;
|
||||||
|
pdata += count;
|
||||||
|
}
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data)
|
||||||
|
{
|
||||||
|
uint32_t addr, endaddr;
|
||||||
|
|
||||||
|
addr = OTA_GetBase() + offset;
|
||||||
|
endaddr = addr + len;
|
||||||
|
|
||||||
|
if (data == NULL || addr > FLASH_TOP || endaddr > FLASH_TOP) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("OTA: read addr=0x%lx\r\n", addr);
|
||||||
|
return flash_ext_stream_read(&flash_obj, addr, len, data);
|
||||||
|
}
|
||||||
|
|
||||||
|
void OTA_ResetTarget(void)
|
||||||
|
{
|
||||||
|
__RTK_CTRL_WRITE32(0x14, 0x00000021);
|
||||||
|
wait(1);
|
||||||
|
|
||||||
|
// write SCB->AIRCR
|
||||||
|
HAL_WRITE32(0xE000ED00, 0x0C,
|
||||||
|
(0x5FA << 16) | // VECTKEY
|
||||||
|
(HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
|
||||||
|
(1 << 2)); // SYSRESETREQ
|
||||||
|
|
||||||
|
// not reached
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
#ifndef MBED_OTA_API_H
|
||||||
|
#define MBED_OTA_API_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data);
|
||||||
|
extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data);
|
||||||
|
extern uint32_t OTA_MarkUpdateDone(void);
|
||||||
|
extern void OTA_ResetTarget(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* MBED_OTA_API_H */
|
||||||
|
|
||||||
|
|
@ -77,21 +77,22 @@ uint32_t us_ticker_read()
|
||||||
void us_ticker_set_interrupt(timestamp_t timestamp)
|
void us_ticker_set_interrupt(timestamp_t timestamp)
|
||||||
{
|
{
|
||||||
uint32_t cur_time_us;
|
uint32_t cur_time_us;
|
||||||
uint32_t time_def;
|
uint32_t time_dif;
|
||||||
|
|
||||||
|
|
||||||
cur_time_us = us_ticker_read();
|
|
||||||
if ((uint32_t)timestamp >= cur_time_us) {
|
|
||||||
time_def = (uint32_t)timestamp - cur_time_us;
|
|
||||||
} else {
|
|
||||||
time_def = 0xffffffff - cur_time_us + (uint32_t)timestamp;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (time_def < TIMER_TICK_US) {
|
|
||||||
time_def = TIMER_TICK_US; // at least 1 tick
|
|
||||||
}
|
|
||||||
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
|
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
|
||||||
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_def);
|
cur_time_us = us_ticker_read();
|
||||||
|
if ((uint32_t)timestamp > cur_time_us) {
|
||||||
|
time_dif = (uint32_t)timestamp - cur_time_us;
|
||||||
|
} else {
|
||||||
|
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff);
|
||||||
|
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
|
||||||
|
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
|
||||||
|
NVIC_SetPendingIRQ(TIMER2_7_IRQ);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
TimerAdapter.TimerLoadValueUs = time_dif;
|
||||||
|
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_dif / TIMER_TICK_US);
|
||||||
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
|
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
|
||||||
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
|
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -21,16 +21,14 @@
|
||||||
#include "rtl8195a.h"
|
#include "rtl8195a.h"
|
||||||
|
|
||||||
#if defined(__CC_ARM)
|
#if defined(__CC_ARM)
|
||||||
#ifdef CONFIG_RTL8195A
|
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
|
||||||
#define INITIAL_SP 0x10070000
|
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
|
||||||
#define ISR_STACK_START 0x1FFFEFFC
|
#define ISR_STACK_START (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base)
|
||||||
#else
|
#define ISR_STACK_SIZE (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Length)
|
||||||
#ERROR "NOT SUPPORT NOW"
|
#define INITIAL_SP (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Base)
|
||||||
#endif
|
|
||||||
#elif defined(__GNUC__)
|
#elif defined(__GNUC__)
|
||||||
extern uint32_t __StackTop[];
|
extern uint32_t __StackTop[];
|
||||||
extern uint32_t __StackLimit[];
|
extern uint32_t __StackLimit[];
|
||||||
// extern uint32_t __end__[];
|
|
||||||
extern uint32_t __HeapLimit[];
|
extern uint32_t __HeapLimit[];
|
||||||
#define INITIAL_SP (__StackTop)
|
#define INITIAL_SP (__StackTop)
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -54,4 +52,3 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,30 +1,21 @@
|
||||||
"""
|
"""
|
||||||
mbed REALTEK_RTL8195AM elf2bin script
|
Realtek Semiconductor Corp.
|
||||||
Copyright (c) 2011-2016 Realtek Semiconductor Corp.
|
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
RTL8195A elf2bin script
|
||||||
you may not use this file except in compliance with the License.
|
|
||||||
You may obtain a copy of the License at
|
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
See the License for the specific language governing permissions and
|
|
||||||
limitations under the License.
|
|
||||||
|
|
||||||
LIBRARIES BUILD
|
|
||||||
"""
|
"""
|
||||||
|
|
||||||
import sys, array, struct, os, re, subprocess
|
import sys, array, struct, os, re, subprocess
|
||||||
import hashlib
|
import hashlib
|
||||||
|
import shutil
|
||||||
|
|
||||||
from tools.paths import TOOLS_BOOTLOADERS
|
from tools.paths import TOOLS_BOOTLOADERS
|
||||||
from datetime import datetime
|
from datetime import datetime
|
||||||
|
|
||||||
# Constant Variables
|
# Constant Variables
|
||||||
RAM2_RSVD = 0x3131373835393138
|
RAM2_RSVD = 0x00000000
|
||||||
|
RAM2_VER = 0x8195FFFF00000000
|
||||||
|
RAM2_TAG = 0x81950001
|
||||||
|
RAM2_SHA = '0'
|
||||||
|
|
||||||
def write_fixed_width_string(value, width, output):
|
def write_fixed_width_string(value, width, output):
|
||||||
# cut string to list & reverse
|
# cut string to list & reverse
|
||||||
|
|
@ -48,94 +39,238 @@ def append_image_file(image, output):
|
||||||
output.write(input.read())
|
output.write(input.read())
|
||||||
input.close()
|
input.close()
|
||||||
|
|
||||||
def prepend(image, image_prepend, toolchain, info):
|
def write_padding_bytes(output_name, size):
|
||||||
output = open(image_prepend, "wb")
|
current_size = os.stat(output_name).st_size
|
||||||
write_fixed_width_value(info['size'], 8, output)
|
padcount = size - current_size
|
||||||
write_fixed_width_value(info['addr'], 8, output)
|
if padcount < 0:
|
||||||
write_fixed_width_value(RAM2_RSVD, 16, output)
|
print "[ERROR] image is larger than expected size"
|
||||||
with open(image, "rb") as input:
|
sys.exit(-1)
|
||||||
if toolchain == "IAR":
|
output = open(output_name, "ab")
|
||||||
input.seek(info['addr'])
|
output.write('\377' * padcount)
|
||||||
output.write(input.read(info['size']))
|
|
||||||
output.close()
|
output.close()
|
||||||
|
|
||||||
def parse_section(toolchain, elf, section):
|
def sha256_checksum(filename, block_size=65536):
|
||||||
info = {'addr':None, 'size':0};
|
sha256 = hashlib.sha256()
|
||||||
if toolchain not in ["GCC_ARM", "ARM_STD", "ARM", "ARM_MICRO", "IAR"]:
|
with open(filename, 'rb') as f:
|
||||||
print "[ERROR] unsupported toolchain " + toolchain
|
for block in iter(lambda: f.read(block_size), b''):
|
||||||
sys.exit(-1)
|
sha256.update(block)
|
||||||
|
return sha256.hexdigest()
|
||||||
|
|
||||||
mapfile = elf.rsplit(".", 1)[0] + ".map"
|
def get_version_by_time():
|
||||||
|
secs = int((datetime.now()-datetime(2016,11,1)).total_seconds())
|
||||||
with open(mapfile, 'r') as infile:
|
return RAM2_VER + secs
|
||||||
# Search area to parse
|
|
||||||
for line in infile:
|
|
||||||
if toolchain == "GCC_ARM":
|
|
||||||
# .image2.table 0x[00000000]30000000 0x18
|
|
||||||
# 0x[00000000]30000000 __image2_start__ = .
|
|
||||||
# 0x[00000000]30000000 __image2_entry_func__ = .
|
|
||||||
match = re.match(r'^' + section + \
|
|
||||||
r'\s+0x0{,8}(?P<addr>[0-9A-Fa-f]{8})\s+0x(?P<size>[0-9A-Fa-f]+).*$', line)
|
|
||||||
elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
|
|
||||||
# Memory Map of the image
|
|
||||||
# Load Region LR_DRAM (Base: 0x30000000, Size: 0x00006a74, Max: 0x00200000, ABSOLUTE)
|
|
||||||
# Execution Region IMAGE2_TABLE (Base: 0x30000000, Size: 0x00000018, Max: 0xffffffff, ABSOLUTE, FIXED)
|
|
||||||
# Base Addr Size Type Attr Idx E Section Name Object
|
|
||||||
# 0x30000000 0x00000004 Data RO 5257 .image2.ram.data rtl8195a_init.o
|
|
||||||
match = re.match(r'^.*Region\s+' + section + \
|
|
||||||
r'\s+\(Base: 0x(?P<addr>[0-9A-Fa-f]{8}),\s+Size: 0x(?P<size>[0-9A-Fa-f]+), .*\)$', line)
|
|
||||||
elif toolchain == "IAR":
|
|
||||||
# Section Kind Address Size Object
|
|
||||||
# ------- ---- ------- ---- ------
|
|
||||||
# "A3": 0x8470
|
|
||||||
# IMAGE2 0x10006000 0x5d18 <Block>
|
|
||||||
# .ram_image2.text 0x10006000 0x5bbc <Block>
|
|
||||||
# .rodata const 0x10006000 0x14 retarget.o [17]
|
|
||||||
match = re.match(r'^\s+' + section + \
|
|
||||||
r'\s+0x(?P<addr>[0-9A-Fa-f]{8})\s+0x(?P<size>[0-9A-Fa-f]+)\s+.*<Block>$', line)
|
|
||||||
if match:
|
|
||||||
info['addr'] = int(match.group("addr"), 16)
|
|
||||||
try:
|
|
||||||
info['size'] = int(match.group("size"), 16)
|
|
||||||
except IndexError:
|
|
||||||
print "[WARNING] cannot find the size of section " + section
|
|
||||||
return info
|
|
||||||
|
|
||||||
print "[ERROR] cannot find the address of section " + section
|
|
||||||
return info
|
|
||||||
|
|
||||||
# ----------------------------
|
# ----------------------------
|
||||||
# main function
|
# main function
|
||||||
# ----------------------------
|
# ----------------------------
|
||||||
def rtl8195a_elf2bin(toolchain, image_elf, image_bin):
|
def prepend(image, entry, segment, image_ram2, image_ota):
|
||||||
|
|
||||||
|
# parse input arguments
|
||||||
|
output = open(image_ram2, "wb")
|
||||||
|
|
||||||
|
write_fixed_width_value(os.stat(image).st_size, 8, output)
|
||||||
|
write_fixed_width_value(int(entry), 8, output)
|
||||||
|
write_fixed_width_value(int(segment), 8, output)
|
||||||
|
|
||||||
|
RAM2_SHA = sha256_checksum(image)
|
||||||
|
write_fixed_width_value(RAM2_TAG, 8, output)
|
||||||
|
write_fixed_width_value(get_version_by_time(), 16, output)
|
||||||
|
write_fixed_width_string(RAM2_SHA, 64, output)
|
||||||
|
write_fixed_width_value(RAM2_RSVD, 8, output)
|
||||||
|
|
||||||
|
append_image_file(image, output)
|
||||||
|
output.close()
|
||||||
|
|
||||||
|
ota = open(image_ota, "wb")
|
||||||
|
write_fixed_width_value(os.stat(image).st_size, 8, ota)
|
||||||
|
write_fixed_width_value(int(entry), 8, ota)
|
||||||
|
write_fixed_width_value(int(segment), 8, ota)
|
||||||
|
write_fixed_width_value(0xFFFFFFFF, 8, ota)
|
||||||
|
write_fixed_width_value(get_version_by_time(), 16, ota)
|
||||||
|
write_fixed_width_string(RAM2_SHA, 64, ota)
|
||||||
|
write_fixed_width_value(RAM2_RSVD, 8, ota)
|
||||||
|
|
||||||
|
append_image_file(image, ota)
|
||||||
|
ota.close()
|
||||||
|
|
||||||
|
def find_symbol(toolchain, mapfile, symbol):
|
||||||
|
ret = None
|
||||||
|
|
||||||
|
HEX = '0x0{,8}(?P<addr>[0-9A-Fa-f]{8})'
|
||||||
if toolchain == "GCC_ARM":
|
if toolchain == "GCC_ARM":
|
||||||
img2_sections = [".image2.table", ".text", ".data"]
|
SYM = re.compile(r'^\s+' + HEX + r'\s+' + symbol + '\r?$')
|
||||||
elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
|
elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
|
||||||
img2_sections = [".image2.table", ".text", ".data"]
|
SYM = re.compile(r'^\s+' + HEX + r'\s+0x[0-9A-Fa-f]{8}\s+Code.*\s+i\.' + symbol + r'\s+.*$')
|
||||||
elif toolchain == "IAR":
|
elif toolchain == "IAR":
|
||||||
# actually it's block
|
SYM = re.compile(r'^' + symbol + r'\s+' + HEX + '\s+.*$')
|
||||||
img2_sections = ["IMAGE2"]
|
|
||||||
|
with open(mapfile, 'r') as infile:
|
||||||
|
for line in infile:
|
||||||
|
match = re.match(SYM, line)
|
||||||
|
if match:
|
||||||
|
ret = match.group("addr")
|
||||||
|
|
||||||
|
if not ret:
|
||||||
|
print "[ERROR] cannot find the address of symbol " + symbol
|
||||||
|
return 0
|
||||||
|
|
||||||
|
return int(ret,16) | 1
|
||||||
|
|
||||||
|
def parse_load_segment_gcc(image_elf):
|
||||||
|
# Program Headers:
|
||||||
|
# Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
|
||||||
|
# LOAD 0x000034 0x10006000 0x10006000 0x026bc 0x026bc RW 0x8
|
||||||
|
# LOAD 0x0026f0 0x30000000 0x30000000 0x06338 0x06338 RWE 0x4
|
||||||
|
segment_list = []
|
||||||
|
cmd = 'arm-none-eabi-readelf -l ' + image_elf
|
||||||
|
for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
|
||||||
|
if not line.startswith(" LOAD"):
|
||||||
|
continue
|
||||||
|
segment = line.split()
|
||||||
|
if len(segment) != 8:
|
||||||
|
continue
|
||||||
|
offset = int(segment[1][2:], 16)
|
||||||
|
addr = int(segment[2][2:], 16)
|
||||||
|
size = int(segment[4][2:], 16)
|
||||||
|
if addr != 0 and size != 0:
|
||||||
|
segment_list.append((offset, addr, size))
|
||||||
|
return segment_list
|
||||||
|
|
||||||
|
def parse_load_segment_armcc(image_elf):
|
||||||
|
# ====================================
|
||||||
|
#
|
||||||
|
# ** Program header #2
|
||||||
|
#
|
||||||
|
# Type : PT_LOAD (1)
|
||||||
|
# File Offset : 52 (0x34)
|
||||||
|
# Virtual Addr : 0x30000000
|
||||||
|
# Physical Addr : 0x30000000
|
||||||
|
# Size in file : 27260 bytes (0x6a7c)
|
||||||
|
# Size in memory: 42168 bytes (0xa4b8)
|
||||||
|
# Flags : PF_X + PF_W + PF_R + PF_ARM_ENTRY (0x80000007)
|
||||||
|
# Alignment : 8
|
||||||
|
#
|
||||||
|
(offset, addr, size) = (0, 0, 0)
|
||||||
|
segment_list = []
|
||||||
|
in_segment = False
|
||||||
|
cmd = 'fromelf --text -v --only=none ' + image_elf
|
||||||
|
for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
|
||||||
|
if line == "":
|
||||||
|
pass
|
||||||
|
elif line.startswith("** Program header"):
|
||||||
|
in_segment = True
|
||||||
|
elif in_segment == False:
|
||||||
|
pass
|
||||||
|
elif line.startswith("============"):
|
||||||
|
if addr != 0 and size != 0:
|
||||||
|
segment_list.append((offset, addr, size))
|
||||||
|
in_segment = False
|
||||||
|
(offset, addr, size) = (0, 0, 0)
|
||||||
|
elif line.startswith(" Type"):
|
||||||
|
if not re.match(r'\s+Type\s+:\s+PT_LOAD\s.*$', line):
|
||||||
|
in_segment = False
|
||||||
|
elif line.startswith(" File Offset"):
|
||||||
|
match = re.match(r'^\s+File Offset\s+:\s+(?P<offset>\d+).*$', line)
|
||||||
|
if match:
|
||||||
|
offset = int(match.group("offset"))
|
||||||
|
elif line.startswith(" Virtual Addr"):
|
||||||
|
match = re.match(r'^\s+Virtual Addr\s+:\s+0x(?P<addr>[0-9a-f]+).*$', line)
|
||||||
|
if match:
|
||||||
|
addr = int(match.group("addr"), 16)
|
||||||
|
elif line.startswith(" Size in file"):
|
||||||
|
match = re.match(r'^\s+Size in file\s+:.*\(0x(?P<size>[0-9a-f]+)\).*$', line)
|
||||||
|
if match:
|
||||||
|
size = int(match.group("size"), 16)
|
||||||
|
return segment_list
|
||||||
|
|
||||||
|
|
||||||
|
def parse_load_segment_iar(image_elf):
|
||||||
|
# SEGMENTS:
|
||||||
|
#
|
||||||
|
# Type Offset Virtual Physical File Sz Mem Sz Flags Align
|
||||||
|
# ---- ------ ------- -------- ------- ------ ----- -----
|
||||||
|
# 0: load 0x34 0x10006000 0x10006000 0x26bc 0x26bc 0x6 WR 0x8
|
||||||
|
# 1: load 0x26f0 0x30000000 0x30000000 0x6338 0x6338 0x7 XWR 0x4
|
||||||
|
#
|
||||||
|
# SECTIONS:
|
||||||
|
#
|
||||||
|
# Name Type Addr Offset Size Aln Lnk Inf ESz Flags
|
||||||
|
# ---- ---- ---- ------ ---- --- --- --- --- -----
|
||||||
|
# 1: .shstrtab strtab 0xfc4d8 0x60 0x4
|
||||||
|
# 2: .strtab strtab 0xfc538 0xbb3f 0x4
|
||||||
|
|
||||||
|
segment_list = []
|
||||||
|
in_segment = False
|
||||||
|
cmd = 'ielfdumparm ' + image_elf
|
||||||
|
for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
|
||||||
|
if line.startswith(" SEGMENTS:"):
|
||||||
|
in_segment = True
|
||||||
|
elif in_segment == False:
|
||||||
|
pass
|
||||||
|
elif line.startswith(" SECTIONS:"):
|
||||||
|
break
|
||||||
|
elif re.match(r'^\s+\w+:\s+load\s+.*$', line):
|
||||||
|
segment = line.split()
|
||||||
|
offset = int(segment[2][2:], 16)
|
||||||
|
addr = int(segment[3][2:], 16)
|
||||||
|
size = int(segment[5][2:], 16)
|
||||||
|
if addr < 0x10007000:
|
||||||
|
continue
|
||||||
|
if addr != 0 and size != 0:
|
||||||
|
segment_list.append((offset, addr, size))
|
||||||
|
return segment_list
|
||||||
|
|
||||||
|
def parse_load_segment(toolchain, image_elf):
|
||||||
|
if toolchain == "GCC_ARM":
|
||||||
|
return parse_load_segment_gcc(image_elf)
|
||||||
|
elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
|
||||||
|
return parse_load_segment_armcc(image_elf)
|
||||||
|
elif toolchain == "IAR":
|
||||||
|
return parse_load_segment_iar(image_elf)
|
||||||
else:
|
else:
|
||||||
print("[error] unsupported toolchain") + toolchain
|
return []
|
||||||
return
|
|
||||||
ram2_info = {'addr':None, 'size':0}
|
def write_load_segment(image_elf, image_bin, segment):
|
||||||
|
file_elf = open(image_elf, "rb")
|
||||||
|
file_bin = open(image_bin, "wb")
|
||||||
|
for (offset, addr, size) in segment:
|
||||||
|
file_elf.seek(offset)
|
||||||
|
# write image header - size & addr
|
||||||
|
write_fixed_width_value(addr, 8, file_bin)
|
||||||
|
write_fixed_width_value(size, 8, file_bin)
|
||||||
|
# write load segment
|
||||||
|
file_bin.write(file_elf.read(size))
|
||||||
|
delta = size % 4
|
||||||
|
if delta != 0:
|
||||||
|
padding = 4 - delta
|
||||||
|
write_fixed_width_value(0x0, padding * 2, file_bin)
|
||||||
|
file_bin.close()
|
||||||
|
file_elf.close()
|
||||||
|
|
||||||
|
# ----------------------------
|
||||||
|
# main function
|
||||||
|
# ----------------------------
|
||||||
|
def rtl8195a_elf2bin(t_self, image_elf, image_bin):
|
||||||
|
# remove target binary file/path
|
||||||
|
if os.path.isfile(image_bin):
|
||||||
|
os.remove(image_bin)
|
||||||
|
else:
|
||||||
|
shutil.rmtree(image_bin)
|
||||||
|
|
||||||
|
segment = parse_load_segment(t_self.name, image_elf)
|
||||||
|
write_load_segment(image_elf, image_bin, segment)
|
||||||
|
|
||||||
image_name = os.path.splitext(image_elf)[0]
|
image_name = os.path.splitext(image_elf)[0]
|
||||||
|
image_map = image_name + '.map'
|
||||||
|
|
||||||
ram1_prepend_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1_prepend.bin")
|
ram2_ent = find_symbol(t_self.name, image_map, "PLAT_Start")
|
||||||
ram2_prepend_bin = image_name + '-ram_2_prepend.bin'
|
ram1_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1.bin")
|
||||||
|
ram2_bin = image_name + '-ram_2.bin'
|
||||||
|
ota_bin = image_name + '-ota.bin'
|
||||||
|
prepend(image_bin, ram2_ent, len(segment), ram2_bin, ota_bin)
|
||||||
|
|
||||||
old_bin = image_name + '.bin'
|
|
||||||
for section in img2_sections:
|
|
||||||
section_info = parse_section(toolchain, image_elf, section)
|
|
||||||
if ram2_info['addr'] is None or ram2_info['addr'] > section_info['addr']:
|
|
||||||
ram2_info['addr'] = section_info['addr']
|
|
||||||
ram2_info['size'] = ram2_info['size'] + section_info['size']
|
|
||||||
|
|
||||||
prepend(old_bin, ram2_prepend_bin, toolchain, ram2_info)
|
|
||||||
# write output file
|
# write output file
|
||||||
output = open(image_bin, "wb")
|
output = open(image_bin, "wb")
|
||||||
append_image_file(ram1_prepend_bin, output)
|
append_image_file(ram1_bin, output)
|
||||||
append_image_file(ram2_prepend_bin, output)
|
append_image_file(ram2_bin, output)
|
||||||
output.close()
|
output.close()
|
||||||
# post built done
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -523,7 +523,7 @@ class RTL8195ACode:
|
||||||
@staticmethod
|
@staticmethod
|
||||||
def binary_hook(t_self, resources, elf, binf):
|
def binary_hook(t_self, resources, elf, binf):
|
||||||
from tools.targets.REALTEK_RTL8195AM import rtl8195a_elf2bin
|
from tools.targets.REALTEK_RTL8195AM import rtl8195a_elf2bin
|
||||||
rtl8195a_elf2bin(t_self.name, elf, binf)
|
rtl8195a_elf2bin(t_self, elf, binf)
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
# Instantiate all public targets
|
# Instantiate all public targets
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue