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Merge pull request #4696 from pan-/max32630_fix_uart 

Max32630 UART: Fix IRQ dispatching and CTS/RTS line configuration
pull/4803/head
Jimmy Brisson 2017-07-24 10:46:36 -05:00 committed by GitHub
parent 93ae6f99aa bf419ca1b3
commit 742d98a9ed
2 changed files with 23 additions and 16 deletions
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32
targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c
View File

@ -100,26 +100,26 @@ const PinMap PinMap_UART_RX[] = {
}; };
const PinMap PinMap_UART_CTS[] = { const PinMap PinMap_UART_CTS[] = {
{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) }, { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) }, { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) }, { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) }, { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) }, { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) }, { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) }, { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) }, { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
{ NC, NC, 0 } { NC, NC, 0 }
}; };
const PinMap PinMap_UART_RTS[] = { const PinMap PinMap_UART_RTS[] = {
{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) }, { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) }, { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) }, { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) }, { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) }, { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) }, { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) }, { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) }, { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
{ NC, NC, 0 } { NC, NC, 0 }
}; };

7
targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c
View File

@ -180,6 +180,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
//****************************************************************************** //******************************************************************************
void uart_handler(serial_t *obj) void uart_handler(serial_t *obj)
{ {
// clear interrupts
volatile uint32_t flags = obj->uart->intfl;
obj->uart->intfl = flags;
if (obj && obj->id) { if (obj && obj->id) {
irq_handler(obj->id, RxIrq); irq_handler(obj->id, RxIrq);
} }
@ -200,6 +204,9 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
//****************************************************************************** //******************************************************************************
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{ {
MBED_ASSERT(obj->index < MXC_CFG_UART_INSTANCES);
objs[obj->index] = obj;
switch (obj->index) { switch (obj->index) {
case 0: case 0:
NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);