mirror of https://github.com/ARMmbed/mbed-os.git
parent
d042729339
commit
73e1fcb54c
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@ -490,11 +490,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((pData == NULL) && (Length > 0U))
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if ((pData == NULL) && (Length > 0U))
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{
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{
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@ -942,11 +942,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((pData == NULL) && (Length > 0U))
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if ((pData == NULL) && (Length > 0U))
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{
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{
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@ -1521,11 +1521,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((pData == NULL) && (Length > 0U))
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if ((pData == NULL) && (Length > 0U))
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{
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{
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@ -2069,11 +2069,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((pData == NULL) && (Length > 0U))
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if ((pData == NULL) && (Length > 0U))
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{
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{
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@ -2979,11 +2979,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
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if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
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{
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{
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@ -3901,11 +3901,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
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assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
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assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((BurstBuffer == NULL) && (BurstLength > 0U))
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if ((BurstBuffer == NULL) && (BurstLength > 0U))
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{
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{
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@ -4166,11 +4166,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
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assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
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assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if ((BurstBuffer == NULL) && (BurstLength > 0U))
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if ((BurstBuffer == NULL) && (BurstLength > 0U))
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{
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{
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@ -409,11 +409,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
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assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if (((uint32_t)pData == 0U) && (Length > 0U))
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if (((uint32_t)pData == 0U) && (Length > 0U))
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{
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{
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@ -721,11 +721,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if (((uint32_t)pData == 0U) && (Length > 0U))
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if (((uint32_t)pData == 0U) && (Length > 0U))
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{
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{
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@ -1129,11 +1129,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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if ((htim->State == HAL_TIM_STATE_BUSY))
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if (htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if ((htim->State == HAL_TIM_STATE_READY))
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else if (htim->State == HAL_TIM_STATE_READY)
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{
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{
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if (((uint32_t)pData == 0U) && (Length > 0U))
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if (((uint32_t)pData == 0U) && (Length > 0U))
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{
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{
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