[HAL LPC408x] Fix mask bits for SPI clock rate

pull/4869/head
toyowata 2017-08-08 15:58:32 +09:00
parent cb9b2b0456
commit 72e8241ee0
2 changed files with 4 additions and 4 deletions

View File

@ -118,7 +118,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
tmp |= DSS << 0
| FRF << 4
| SPO << 6
@ -153,7 +153,7 @@ void spi_frequency(spi_t *obj, int hz) {
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;

View File

@ -98,7 +98,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
tmp |= DSS << 0
| FRF << 4
| SPO << 6
@ -133,7 +133,7 @@ void spi_frequency(spi_t *obj, int hz) {
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;