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Fix ITM on NRF52 series 

The ITM must be initialized before the SoftDevice, but due to the
lazy initialization in C++ on (at least) GCC the ITM init call
might happen too late.

This commit moves the initialization code into the NRF52 system
startup file.
pull/7631/head
Marcus Chang 2018-06-29 13:33:45 -07:00 committed by Cruz Monrreal II
parent 87aa896e8a
commit 71a2a39445
3 changed files with 69 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c
View File

@ -79,13 +79,13 @@ void SystemInit(void)
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_16()){
@ -154,7 +154,7 @@ void SystemInit(void)
if (errata_108()){
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
}
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_136()){
@ -162,7 +162,7 @@ void SystemInit(void)
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
@ -216,6 +216,29 @@ void SystemInit(void)
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
/**
* Mbed HAL specific code section.
*
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
*/
#if defined (DEVICE_ITM)
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
#endif
}

55
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c
View File

@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
@ -76,7 +76,7 @@ void SystemInit(void)
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_36()){
@ -84,7 +84,7 @@ void SystemInit(void)
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_66()){
@ -106,31 +106,31 @@ void SystemInit(void)
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_136()){
@ -138,7 +138,7 @@ void SystemInit(void)
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
@ -192,6 +192,29 @@ void SystemInit(void)
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
/**
* Mbed HAL specific code section.
*
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
*/
#if defined (DEVICE_ITM)
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
#endif
}
@ -200,7 +223,7 @@ static bool errata_36(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -210,7 +233,7 @@ static bool errata_66(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -220,7 +243,7 @@ static bool errata_98(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -230,7 +253,7 @@ static bool errata_103(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -240,7 +263,7 @@ static bool errata_115(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -250,7 +273,7 @@ static bool errata_120(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
@ -260,7 +283,7 @@ static bool errata_136(void)
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}

22
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c
View File

@ -18,27 +18,11 @@
#include "hal/itm_api.h"
#include "nrf.h"
#include "nrf5x_lf_clk_helper.h"
/* SWO frequency: 4000 kHz */
void itm_init(void)
{
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
/**
* Initialization moved to system_nrf52840.c due to SoftDevice incompatibility.
*/
}
#endif