mirror of https://github.com/ARMmbed/mbed-os.git
parent
5d80f9e98f
commit
7154ac65f2
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@ -390,11 +390,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if((pData == 0 ) && (Length > 0))
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if((pData == 0 ) && (Length > 0))
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{
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{
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@ -784,11 +784,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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{
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@ -1294,11 +1294,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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{
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@ -1777,11 +1777,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if((pData == 0U ) && (Length > 0U))
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if((pData == 0U ) && (Length > 0U))
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{
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{
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@ -2592,11 +2592,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
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if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
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{
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{
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@ -3386,11 +3386,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
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assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if((BurstBuffer == 0U ) && (BurstLength > 0U))
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if((BurstBuffer == 0U ) && (BurstLength > 0U))
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{
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{
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@ -3656,11 +3656,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_LENGTH(BurstLength));
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assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
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assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if((BurstBuffer == 0U ) && (BurstLength > 0U))
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if((BurstBuffer == 0U ) && (BurstLength > 0U))
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{
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{
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@ -388,11 +388,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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{
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@ -693,11 +693,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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{
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@ -1109,11 +1109,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
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if((htim->State == HAL_TIM_STATE_BUSY))
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if(htim->State == HAL_TIM_STATE_BUSY)
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{
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{
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return HAL_BUSY;
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return HAL_BUSY;
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}
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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else if(htim->State == HAL_TIM_STATE_READY)
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{
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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{
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