Fixes typos in SMSC9220 Ethernet driver

Change-Id: I44a12ec1c57a926dadee81df1b84bd531d5cfccb
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
pull/9385/head
Bence Kaposzta 2019-01-15 15:36:35 +01:00
parent aff2bee8a4
commit 709c121a0c
1 changed files with 13 additions and 13 deletions

View File

@ -125,19 +125,19 @@ enum smsc9220_mac_reg_offsets_t{
* *
*/ */
enum phy_reg_offsets_t{ enum phy_reg_offsets_t{
SMSC9220_PHY_REG_OFFSET_BCTRL = 0x0U, SMSC9220_PHY_REG_OFFSET_BCTRL = 0U,
SMSC9220_PHY_REG_OFFSET_BSTATUS = 0x1U, SMSC9220_PHY_REG_OFFSET_BSTATUS = 1U,
SMSC9220_PHY_REG_OFFSET_ID1 = 0x2U, SMSC9220_PHY_REG_OFFSET_ID1 = 2U,
SMSC9220_PHY_REG_OFFSET_ID2 = 0x3U, SMSC9220_PHY_REG_OFFSET_ID2 = 3U,
SMSC9220_PHY_REG_OFFSET_ANEG_ADV = 0x4U, SMSC9220_PHY_REG_OFFSET_ANEG_ADV = 4U,
SMSC9220_PHY_REG_OFFSET_ANEG_LPA = 0x5U, SMSC9220_PHY_REG_OFFSET_ANEG_LPA = 5U,
SMSC9220_PHY_REG_OFFSET_ANEG_EXP = 0x6U, SMSC9220_PHY_REG_OFFSET_ANEG_EXP = 6U,
SMSC9220_PHY_REG_OFFSET_MCONTROL = 0x17U, SMSC9220_PHY_REG_OFFSET_MCONTROL = 17U,
SMSC9220_PHY_REG_OFFSET_MSTATUS = 0x18U, SMSC9220_PHY_REG_OFFSET_MSTATUS = 18U,
SMSC9220_PHY_REG_OFFSET_CSINDICATE = 0x27U, SMSC9220_PHY_REG_OFFSET_CSINDICATE = 27U,
SMSC9220_PHY_REG_OFFSET_INTSRC = 0x29U, SMSC9220_PHY_REG_OFFSET_INTSRC = 29U,
SMSC9220_PHY_REG_OFFSET_INTMASK = 0x30U, SMSC9220_PHY_REG_OFFSET_INTMASK = 30U,
SMSC9220_PHY_REG_OFFSET_CS = 0x31U SMSC9220_PHY_REG_OFFSET_CS = 31U
}; };
/* Bit definitions for PHY Basic Status Register */ /* Bit definitions for PHY Basic Status Register */