From cbe0f73a0e366295f06d1b08f29ff471a4331d78 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Thu, 7 Sep 2023 10:07:15 +0300 Subject: [PATCH] Fix: Do not disable SPI for manual drive mode during transaction setup It has been reported that disabling SPI module causes glitch for manual SS drive mode Signed-off-by: Sadik.Ozer --- .../Libraries/PeriphDrivers/Source/SPI/spi_reva.c | 2 +- .../Libraries/PeriphDrivers/Source/SPI/spi_reva.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index 82a54ee244..05d6ad32a9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) states[spi_num].started = 0; states[spi_num].req_done = 0; // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). - if (states[spi_num].ssDeassert == 1) { + if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1)) { (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index 2726ede611..9b201d5e32 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) states[spi_num].started = 0; states[spi_num].req_done = 0; // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). - if (states[spi_num].ssDeassert == 1) { + if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1) ) { (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); }