mirror of https://github.com/ARMmbed/mbed-os.git
Refactoring PWM driver for RZ/A1
d-kato
parent
bb61ea1433
commit
70217338cb
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@ -90,8 +90,6 @@ static int32_t period_ch2 = 1;
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#endif
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#ifdef FUMC_MTU2_PWM
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#define MTU2_PWM_SIGNAL 2
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typedef enum {
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TIOC0A = 0,
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TIOC0B,
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@ -111,34 +109,25 @@ typedef enum {
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TIOC4D,
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} MTU2_PWMType;
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static const MTU2_PWMType MTU2_PORT[] = {
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TIOC0A, // PWM_TIOC0A
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TIOC0C, // PWM_TIOC0C
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TIOC1A, // PWM_TIOC1A
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TIOC2A, // PWM_TIOC2A
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TIOC3A, // PWM_TIOC3A
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TIOC3C, // PWM_TIOC3C
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TIOC4A, // PWM_TIOC4A
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TIOC4C, // PWM_TIOC4C
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};
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typedef struct {
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MTU2_PWMType port;
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__IO uint16_t * pulse1;
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__IO uint16_t * pulse2;
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__IO uint16_t * period1;
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__IO uint8_t * tcr;
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__IO uint8_t * tmdr;
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int max_period;
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} st_mtu2_ctrl_t;
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static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = {
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{ &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A
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{ &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C
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{ &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A
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{ &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A
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{ &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A
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{ &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C
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{ &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A
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{ &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C
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};
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static __IO uint8_t *TCR_MATCH[] = {
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&MTU2TCR_0,
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&MTU2TCR_1,
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&MTU2TCR_2,
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&MTU2TCR_3,
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&MTU2TCR_4,
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static st_mtu2_ctrl_t mtu2_ctl[] = {
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{ TIOC0A, &MTU2TGRA_0, &MTU2TGRC_0, &MTU2TGRB_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0A
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{ TIOC0C, &MTU2TGRC_0, &MTU2TGRA_0, &MTU2TGRD_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0C
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{ TIOC1A, &MTU2TGRA_1, NULL , &MTU2TGRB_1, &MTU2TCR_1, &MTU2TMDR_1, 503000 }, // PWM_TIOC1A
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{ TIOC2A, &MTU2TGRA_2, NULL , &MTU2TGRB_2, &MTU2TCR_2, &MTU2TMDR_2, 2000000 }, // PWM_TIOC2A
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{ TIOC3A, &MTU2TGRA_3, &MTU2TGRC_3, &MTU2TGRB_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3A
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{ TIOC3C, &MTU2TGRC_3, &MTU2TGRA_3, &MTU2TGRD_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3C
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{ TIOC4A, &MTU2TGRA_4, &MTU2TGRC_4, &MTU2TGRB_4, &MTU2TCR_4, &MTU2TMDR_4, 2000000 }, // PWM_TIOC4A
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{ TIOC4C, &MTU2TGRC_4, &MTU2TGRA_4, &MTU2TGRD_4, &MTU2TCR_4, &MTU2TMDR_4, 2000000 }, // PWM_TIOC4C
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};
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static __IO uint8_t *TIORH_MATCH[] = {
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@ -157,43 +146,6 @@ static __IO uint8_t *TIORL_MATCH[] = {
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&MTU2TIORL_4,
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};
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static __IO uint16_t *TGRA_MATCH[] = {
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&MTU2TGRA_0,
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&MTU2TGRA_1,
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&MTU2TGRA_2,
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&MTU2TGRA_3,
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&MTU2TGRA_4,
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};
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static __IO uint16_t *TGRC_MATCH[] = {
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&MTU2TGRC_0,
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NULL,
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NULL,
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&MTU2TGRC_3,
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&MTU2TGRC_4,
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};
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static __IO uint8_t *TMDR_MATCH[] = {
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&MTU2TMDR_0,
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&MTU2TMDR_1,
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&MTU2TMDR_2,
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&MTU2TMDR_3,
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&MTU2TMDR_4,
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};
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static int MAX_PERIOD[] = {
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125000,
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503000,
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2000000,
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2000000,
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2000000,
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};
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typedef enum {
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MTU2_PULSE = 0,
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MTU2_PERIOD
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} MTU2Signal;
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static uint16_t init_mtu2_period_ch[5] = {0};
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static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
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#endif
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@ -206,26 +158,21 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
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if (pwm >= MTU2_PWM_OFFSET) {
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#ifdef FUMC_MTU2_PWM
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/* PWM by MTU2 */
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int tmp_pwm;
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// power on
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mtu2_init();
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obj->pwm = pwm;
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tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
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obj->ch = 4;
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st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
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obj->ch = (uint8_t)(((uint32_t)p_mtu2_ctl->port & 0x000000F0) >> 4);
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if (obj->ch == 4) {
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MTU2TOER |= 0x36;
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} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
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obj->ch = 3;
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} else if (obj->ch == 3) {
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MTU2TOER |= 0x09;
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} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
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obj->ch = 2;
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} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
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obj->ch = 1;
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} else {
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obj->ch = 0;
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// do nothing
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}
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// Wire pinout
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pinmap_pinout(pin, PinMap_PWM);
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@ -284,7 +231,7 @@ void pwmout_write(pwmout_t* obj, float value) {
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if (obj->pwm >= MTU2_PWM_OFFSET) {
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#ifdef FUMC_MTU2_PWM
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/* PWM by MTU2 */
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int tmp_pwm;
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st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
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if (value < 0.0f) {
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value = 0.0f;
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@ -293,13 +240,13 @@ void pwmout_write(pwmout_t* obj, float value) {
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} else {
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// Do Nothing
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}
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tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
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wk_cycle = (uint32_t)*p_mtu2_ctl->period1;
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// set channel match to percentage
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if (value == 1.0f) {
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*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1);
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*p_mtu2_ctl->pulse1 = (uint16_t)(wk_cycle - 1);
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} else {
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*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
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*p_mtu2_ctl->pulse1 = (uint16_t)((float)wk_cycle * value);
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}
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#endif
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} else {
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@ -336,11 +283,10 @@ float pwmout_read(pwmout_t* obj) {
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#ifdef FUMC_MTU2_PWM
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/* PWM by MTU2 */
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uint32_t wk_pulse;
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int tmp_pwm;
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st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
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tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
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wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
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wk_cycle = (uint32_t)*p_mtu2_ctl->period1;
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wk_pulse = (uint32_t)*p_mtu2_ctl->pulse1;
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value = ((float)wk_pulse / (float)wk_cycle);
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#endif
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} else {
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@ -403,12 +349,11 @@ void pwmout_period_us(pwmout_t* obj, int us) {
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int max_us = 0;
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/* PWM by MTU2 */
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int tmp_pwm;
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st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
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uint8_t tmp_tcr_up;
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uint8_t tmp_tstr_sp;
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uint8_t tmp_tstr_st;
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max_us = MAX_PERIOD[obj->ch];
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max_us = p_mtu2_ctl->max_period;
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if (us > max_us) {
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us = max_us;
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} else if (us < 1) {
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@ -436,37 +381,34 @@ void pwmout_period_us(pwmout_t* obj, int us) {
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}
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wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
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tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
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if (((uint8_t)p_mtu2_ctl->port & 0x0F) == 0x02) {
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tmp_tcr_up = 0xC0;
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} else {
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tmp_tcr_up = 0x40;
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}
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if ((obj->ch == 4) || (obj->ch == 3)) {
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tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
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tmp_tstr_st = (1 << (obj->ch + 3));
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} else {
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tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
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tmp_tstr_st = (1 << obj->ch);
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}
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// Counter Stop
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MTU2TSTR &= tmp_tstr_sp;
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wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
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*TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
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MTU2TSTR &= ~tmp_tstr_st;
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wk_last_cycle = *p_mtu2_ctl->period1;
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*p_mtu2_ctl->tcr = tmp_tcr_up | wk_cks;
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*TIORH_MATCH[obj->ch] = 0x21;
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if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
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*TIORL_MATCH[obj->ch] = 0x21;
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}
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*MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
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// Set duty again(TGRA)
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set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
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if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
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// Set duty again(TGRC)
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set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
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// Set period
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*p_mtu2_ctl->period1 = (uint16_t)wk_cycle;
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// Set duty again
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set_mtu2_duty_again(p_mtu2_ctl->pulse1, wk_last_cycle, wk_cycle);
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if (p_mtu2_ctl->pulse2 != NULL) {
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set_mtu2_duty_again(p_mtu2_ctl->pulse2, wk_last_cycle, wk_cycle);
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}
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*TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
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// Set mode
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*p_mtu2_ctl->tmdr = 0x02; // PWM mode 1
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// Counter Start
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MTU2TSTR |= tmp_tstr_st;
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// Save for future use
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